1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ 2 /* Copyright 2017-2019 NXP */ 3 4 #include <linux/bitops.h> 5 6 #define ENETC_MM_VERIFY_SLEEP_US USEC_PER_MSEC 7 #define ENETC_MM_VERIFY_RETRIES 3 8 9 #define ENETC_NUM_TC 8 10 11 /* ENETC device IDs */ 12 #define ENETC_DEV_ID_PF 0xe100 13 #define ENETC_DEV_ID_VF 0xef00 14 #define ENETC_DEV_ID_PTP 0xee02 15 16 /* ENETC register block BAR */ 17 #define ENETC_BAR_REGS 0 18 19 /** SI regs, offset: 0h */ 20 #define ENETC_SIMR 0 21 #define ENETC_SIMR_EN BIT(31) 22 #define ENETC_SIMR_RSSE BIT(0) 23 #define ENETC_SICTR0 0x18 24 #define ENETC_SICTR1 0x1c 25 #define ENETC_SIPCAPR0 0x20 26 #define ENETC_SIPCAPR0_PSFP BIT(9) 27 #define ENETC_SIPCAPR0_RSS BIT(8) 28 #define ENETC_SIPCAPR0_QBV BIT(4) 29 #define ENETC_SIPCAPR0_QBU BIT(3) 30 #define ENETC_SIPCAPR0_RFS BIT(2) 31 #define ENETC_SIPCAPR1 0x24 32 #define ENETC_SITGTGR 0x30 33 #define ENETC_SIRBGCR 0x38 34 /* cache attribute registers for transactions initiated by ENETC */ 35 #define ENETC_SICAR0 0x40 36 #define ENETC_SICAR1 0x44 37 #define ENETC_SICAR2 0x48 38 /* rd snoop, no alloc 39 * wr snoop, no alloc, partial cache line update for BDs and full cache line 40 * update for data 41 */ 42 #define ENETC_SICAR_RD_COHERENT 0x2b2b0000 43 #define ENETC_SICAR_WR_COHERENT 0x00006727 44 #define ENETC_SICAR_MSI 0x00300030 /* rd/wr device, no snoop, no alloc */ 45 46 #define ENETC_SIPMAR0 0x80 47 #define ENETC_SIPMAR1 0x84 48 49 /* VF-PF Message passing */ 50 #define ENETC_DEFAULT_MSG_SIZE 1024 /* and max size */ 51 /* msg size encoding: default and max msg value of 1024B encoded as 0 */ 52 static inline u32 enetc_vsi_set_msize(u32 size) 53 { 54 return size < ENETC_DEFAULT_MSG_SIZE ? size >> 5 : 0; 55 } 56 57 #define ENETC_PSIMSGRR 0x204 58 #define ENETC_PSIMSGRR_MR_MASK GENMASK(2, 1) 59 #define ENETC_PSIMSGRR_MR(n) BIT((n) + 1) /* n = VSI index */ 60 #define ENETC_PSIVMSGRCVAR0(n) (0x210 + (n) * 0x8) /* n = VSI index */ 61 #define ENETC_PSIVMSGRCVAR1(n) (0x214 + (n) * 0x8) 62 63 #define ENETC_VSIMSGSR 0x204 /* RO */ 64 #define ENETC_VSIMSGSR_MB BIT(0) 65 #define ENETC_VSIMSGSR_MS BIT(1) 66 #define ENETC_VSIMSGSNDAR0 0x210 67 #define ENETC_VSIMSGSNDAR1 0x214 68 69 #define ENETC_SIMSGSR_SET_MC(val) ((val) << 16) 70 #define ENETC_SIMSGSR_GET_MC(val) ((val) >> 16) 71 72 /* SI statistics */ 73 #define ENETC_SIROCT 0x300 74 #define ENETC_SIRFRM 0x308 75 #define ENETC_SIRUCA 0x310 76 #define ENETC_SIRMCA 0x318 77 #define ENETC_SITOCT 0x320 78 #define ENETC_SITFRM 0x328 79 #define ENETC_SITUCA 0x330 80 #define ENETC_SITMCA 0x338 81 #define ENETC_RBDCR(n) (0x8180 + (n) * 0x200) 82 83 /* Control BDR regs */ 84 #define ENETC_SICBDRMR 0x800 85 #define ENETC_SICBDRSR 0x804 /* RO */ 86 #define ENETC_SICBDRBAR0 0x810 87 #define ENETC_SICBDRBAR1 0x814 88 #define ENETC_SICBDRPIR 0x818 89 #define ENETC_SICBDRCIR 0x81c 90 #define ENETC_SICBDRLENR 0x820 91 92 #define ENETC_SICAPR0 0x900 93 #define ENETC_SICAPR1 0x904 94 95 #define ENETC_PSIIER 0xa00 96 #define ENETC_PSIIER_MR_MASK GENMASK(2, 1) 97 #define ENETC_PSIIDR 0xa08 98 #define ENETC_SITXIDR 0xa18 99 #define ENETC_SIRXIDR 0xa28 100 #define ENETC_SIMSIVR 0xa30 101 102 #define ENETC_SIMSITRV(n) (0xB00 + (n) * 0x4) 103 #define ENETC_SIMSIRRV(n) (0xB80 + (n) * 0x4) 104 105 #define ENETC_SIUEFDCR 0xe28 106 107 #define ENETC_SIRFSCAPR 0x1200 108 #define ENETC_SIRFSCAPR_GET_NUM_RFS(val) ((val) & 0x7f) 109 #define ENETC_SIRSSCAPR 0x1600 110 #define ENETC_SIRSSCAPR_GET_NUM_RSS(val) (BIT((val) & 0xf) * 32) 111 112 /** SI BDR sub-blocks, n = 0..7 */ 113 enum enetc_bdr_type {TX, RX}; 114 #define ENETC_BDR_OFF(i) ((i) * 0x200) 115 #define ENETC_BDR(t, i, r) (0x8000 + (t) * 0x100 + ENETC_BDR_OFF(i) + (r)) 116 /* RX BDR reg offsets */ 117 #define ENETC_RBMR 0 118 #define ENETC_RBMR_BDS BIT(2) 119 #define ENETC_RBMR_CM BIT(4) 120 #define ENETC_RBMR_VTE BIT(5) 121 #define ENETC_RBMR_EN BIT(31) 122 #define ENETC_RBSR 0x4 123 #define ENETC_RBBSR 0x8 124 #define ENETC_RBCIR 0xc 125 #define ENETC_RBBAR0 0x10 126 #define ENETC_RBBAR1 0x14 127 #define ENETC_RBPIR 0x18 128 #define ENETC_RBLENR 0x20 129 #define ENETC_RBIER 0xa0 130 #define ENETC_RBIER_RXTIE BIT(0) 131 #define ENETC_RBIDR 0xa4 132 #define ENETC_RBICR0 0xa8 133 #define ENETC_RBICR0_ICEN BIT(31) 134 #define ENETC_RBICR0_ICPT_MASK 0x1ff 135 #define ENETC_RBICR0_SET_ICPT(n) ((n) & ENETC_RBICR0_ICPT_MASK) 136 #define ENETC_RBICR1 0xac 137 138 /* TX BDR reg offsets */ 139 #define ENETC_TBMR 0 140 #define ENETC_TBSR_BUSY BIT(0) 141 #define ENETC_TBMR_VIH BIT(9) 142 #define ENETC_TBMR_PRIO_MASK GENMASK(2, 0) 143 #define ENETC_TBMR_SET_PRIO(val) ((val) & ENETC_TBMR_PRIO_MASK) 144 #define ENETC_TBMR_EN BIT(31) 145 #define ENETC_TBSR 0x4 146 #define ENETC_TBBAR0 0x10 147 #define ENETC_TBBAR1 0x14 148 #define ENETC_TBPIR 0x18 149 #define ENETC_TBCIR 0x1c 150 #define ENETC_TBCIR_IDX_MASK 0xffff 151 #define ENETC_TBLENR 0x20 152 #define ENETC_TBIER 0xa0 153 #define ENETC_TBIER_TXTIE BIT(0) 154 #define ENETC_TBIDR 0xa4 155 #define ENETC_TBICR0 0xa8 156 #define ENETC_TBICR0_ICEN BIT(31) 157 #define ENETC_TBICR0_ICPT_MASK 0xf 158 #define ENETC_TBICR0_SET_ICPT(n) ((ilog2(n) + 1) & ENETC_TBICR0_ICPT_MASK) 159 #define ENETC_TBICR1 0xac 160 161 #define ENETC_RTBLENR_LEN(n) ((n) & ~0x7) 162 163 /* Port regs, offset: 1_0000h */ 164 #define ENETC_PORT_BASE 0x10000 165 #define ENETC_PMR 0x0000 166 #define ENETC_PMR_EN GENMASK(18, 16) 167 #define ENETC_PMR_PSPEED_MASK GENMASK(11, 8) 168 #define ENETC_PMR_PSPEED_10M 0 169 #define ENETC_PMR_PSPEED_100M BIT(8) 170 #define ENETC_PMR_PSPEED_1000M BIT(9) 171 #define ENETC_PMR_PSPEED_2500M BIT(10) 172 #define ENETC_PSR 0x0004 /* RO */ 173 #define ENETC_PSIPMR 0x0018 174 #define ENETC_PSIPMR_SET_UP(n) BIT(n) /* n = SI index */ 175 #define ENETC_PSIPMR_SET_MP(n) BIT((n) + 16) 176 #define ENETC_PSIPVMR 0x001c 177 #define ENETC_VLAN_PROMISC_MAP_ALL 0x7 178 #define ENETC_PSIPVMR_SET_VP(simap) ((simap) & 0x7) 179 #define ENETC_PSIPVMR_SET_VUTA(simap) (((simap) & 0x7) << 16) 180 #define ENETC_PSIPMAR0(n) (0x0100 + (n) * 0x8) /* n = SI index */ 181 #define ENETC_PSIPMAR1(n) (0x0104 + (n) * 0x8) 182 #define ENETC_PVCLCTR 0x0208 183 #define ENETC_PCVLANR1 0x0210 184 #define ENETC_PCVLANR2 0x0214 185 #define ENETC_VLAN_TYPE_C BIT(0) 186 #define ENETC_VLAN_TYPE_S BIT(1) 187 #define ENETC_PVCLCTR_OVTPIDL(bmp) ((bmp) & 0xff) /* VLAN_TYPE */ 188 #define ENETC_PSIVLANR(n) (0x0240 + (n) * 4) /* n = SI index */ 189 #define ENETC_PSIVLAN_EN BIT(31) 190 #define ENETC_PSIVLAN_SET_QOS(val) ((u32)(val) << 12) 191 #define ENETC_PPAUONTR 0x0410 192 #define ENETC_PPAUOFFTR 0x0414 193 #define ENETC_PTXMBAR 0x0608 194 #define ENETC_PCAPR0 0x0900 195 #define ENETC_PCAPR0_RXBDR(val) ((val) >> 24) 196 #define ENETC_PCAPR0_TXBDR(val) (((val) >> 16) & 0xff) 197 #define ENETC_PCAPR1 0x0904 198 #define ENETC_PSICFGR0(n) (0x0940 + (n) * 0xc) /* n = SI index */ 199 #define ENETC_PSICFGR0_SET_TXBDR(val) ((val) & 0xff) 200 #define ENETC_PSICFGR0_SET_RXBDR(val) (((val) & 0xff) << 16) 201 #define ENETC_PSICFGR0_VTE BIT(12) 202 #define ENETC_PSICFGR0_SIVIE BIT(14) 203 #define ENETC_PSICFGR0_ASE BIT(15) 204 #define ENETC_PSICFGR0_SIVC(bmp) (((bmp) & 0xff) << 24) /* VLAN_TYPE */ 205 206 #define ENETC_PTCCBSR0(n) (0x1110 + (n) * 8) /* n = 0 to 7*/ 207 #define ENETC_CBSE BIT(31) 208 #define ENETC_CBS_BW_MASK GENMASK(6, 0) 209 #define ENETC_PTCCBSR1(n) (0x1114 + (n) * 8) /* n = 0 to 7*/ 210 #define ENETC_RSSHASH_KEY_SIZE 40 211 #define ENETC_PRSSCAPR 0x1404 212 #define ENETC_PRSSCAPR_GET_NUM_RSS(val) (BIT((val) & 0xf) * 32) 213 #define ENETC_PRSSK(n) (0x1410 + (n) * 4) /* n = [0..9] */ 214 #define ENETC_PSIVLANFMR 0x1700 215 #define ENETC_PSIVLANFMR_VS BIT(0) 216 #define ENETC_PRFSMR 0x1800 217 #define ENETC_PRFSMR_RFSE BIT(31) 218 #define ENETC_PRFSCAPR 0x1804 219 #define ENETC_PRFSCAPR_GET_NUM_RFS(val) ((((val) & 0xf) + 1) * 16) 220 #define ENETC_PSIRFSCFGR(n) (0x1814 + (n) * 4) /* n = SI index */ 221 #define ENETC_PFPMR 0x1900 222 #define ENETC_PFPMR_PMACE BIT(1) 223 #define ENETC_EMDIO_BASE 0x1c00 224 #define ENETC_PSIUMHFR0(n, err) (((err) ? 0x1d08 : 0x1d00) + (n) * 0x10) 225 #define ENETC_PSIUMHFR1(n) (0x1d04 + (n) * 0x10) 226 #define ENETC_PSIMMHFR0(n, err) (((err) ? 0x1d00 : 0x1d08) + (n) * 0x10) 227 #define ENETC_PSIMMHFR1(n) (0x1d0c + (n) * 0x10) 228 #define ENETC_PSIVHFR0(n) (0x1e00 + (n) * 8) /* n = SI index */ 229 #define ENETC_PSIVHFR1(n) (0x1e04 + (n) * 8) /* n = SI index */ 230 #define ENETC_MMCSR 0x1f00 231 #define ENETC_MMCSR_LINK_FAIL BIT(31) 232 #define ENETC_MMCSR_VT_MASK GENMASK(29, 23) /* Verify Time */ 233 #define ENETC_MMCSR_VT(x) (((x) << 23) & ENETC_MMCSR_VT_MASK) 234 #define ENETC_MMCSR_GET_VT(x) (((x) & ENETC_MMCSR_VT_MASK) >> 23) 235 #define ENETC_MMCSR_TXSTS_MASK GENMASK(22, 21) /* Merge Status */ 236 #define ENETC_MMCSR_GET_TXSTS(x) (((x) & ENETC_MMCSR_TXSTS_MASK) >> 21) 237 #define ENETC_MMCSR_VSTS_MASK GENMASK(20, 18) /* Verify Status */ 238 #define ENETC_MMCSR_GET_VSTS(x) (((x) & ENETC_MMCSR_VSTS_MASK) >> 18) 239 #define ENETC_MMCSR_VDIS BIT(17) /* Verify Disabled */ 240 #define ENETC_MMCSR_ME BIT(16) /* Merge Enabled */ 241 #define ENETC_MMCSR_RAFS_MASK GENMASK(9, 8) /* Remote Additional Fragment Size */ 242 #define ENETC_MMCSR_RAFS(x) (((x) << 8) & ENETC_MMCSR_RAFS_MASK) 243 #define ENETC_MMCSR_GET_RAFS(x) (((x) & ENETC_MMCSR_RAFS_MASK) >> 8) 244 #define ENETC_MMCSR_LAFS_MASK GENMASK(4, 3) /* Local Additional Fragment Size */ 245 #define ENETC_MMCSR_GET_LAFS(x) (((x) & ENETC_MMCSR_LAFS_MASK) >> 3) 246 #define ENETC_MMCSR_LPA BIT(2) /* Local Preemption Active */ 247 #define ENETC_MMCSR_LPE BIT(1) /* Local Preemption Enabled */ 248 #define ENETC_MMCSR_LPS BIT(0) /* Local Preemption Supported */ 249 #define ENETC_MMFAECR 0x1f08 250 #define ENETC_MMFSECR 0x1f0c 251 #define ENETC_MMFAOCR 0x1f10 252 #define ENETC_MMFCRXR 0x1f14 253 #define ENETC_MMFCTXR 0x1f18 254 #define ENETC_MMHCR 0x1f1c 255 #define ENETC_PTCMSDUR(n) (0x2020 + (n) * 4) /* n = TC index [0..7] */ 256 257 #define ENETC_PMAC_OFFSET 0x1000 258 259 #define ENETC_PM0_CMD_CFG 0x8008 260 #define ENETC_PM0_TX_EN BIT(0) 261 #define ENETC_PM0_RX_EN BIT(1) 262 #define ENETC_PM0_PROMISC BIT(4) 263 #define ENETC_PM0_PAUSE_IGN BIT(8) 264 #define ENETC_PM0_CMD_XGLP BIT(10) 265 #define ENETC_PM0_CMD_TXP BIT(11) 266 #define ENETC_PM0_CMD_PHY_TX_EN BIT(15) 267 #define ENETC_PM0_CMD_SFD BIT(21) 268 #define ENETC_PM0_MAXFRM 0x8014 269 #define ENETC_SET_TX_MTU(val) ((val) << 16) 270 #define ENETC_SET_MAXFRM(val) ((val) & 0xffff) 271 #define ENETC_PM0_RX_FIFO 0x801c 272 #define ENETC_PM0_RX_FIFO_VAL 1 273 274 #define ENETC_PM_IMDIO_BASE 0x8030 275 276 #define ENETC_PM0_PAUSE_QUANTA 0x8054 277 #define ENETC_PM0_PAUSE_THRESH 0x8064 278 279 #define ENETC_PM0_SINGLE_STEP 0x80c0 280 #define ENETC_PM0_SINGLE_STEP_CH BIT(7) 281 #define ENETC_PM0_SINGLE_STEP_EN BIT(31) 282 #define ENETC_SET_SINGLE_STEP_OFFSET(v) (((v) & 0xff) << 8) 283 284 #define ENETC_PM0_IF_MODE 0x8300 285 #define ENETC_PM0_IFM_RG BIT(2) 286 #define ENETC_PM0_IFM_RLP (BIT(5) | BIT(11)) 287 #define ENETC_PM0_IFM_EN_AUTO BIT(15) 288 #define ENETC_PM0_IFM_SSP_MASK GENMASK(14, 13) 289 #define ENETC_PM0_IFM_SSP_1000 (2 << 13) 290 #define ENETC_PM0_IFM_SSP_100 (0 << 13) 291 #define ENETC_PM0_IFM_SSP_10 (1 << 13) 292 #define ENETC_PM0_IFM_FULL_DPX BIT(12) 293 #define ENETC_PM0_IFM_IFMODE_MASK GENMASK(1, 0) 294 #define ENETC_PM0_IFM_IFMODE_XGMII 0 295 #define ENETC_PM0_IFM_IFMODE_GMII 2 296 #define ENETC_PSIDCAPR 0x1b08 297 #define ENETC_PSIDCAPR_MSK GENMASK(15, 0) 298 #define ENETC_PSFCAPR 0x1b18 299 #define ENETC_PSFCAPR_MSK GENMASK(15, 0) 300 #define ENETC_PSGCAPR 0x1b28 301 #define ENETC_PSGCAPR_GCL_MSK GENMASK(18, 16) 302 #define ENETC_PSGCAPR_SGIT_MSK GENMASK(15, 0) 303 #define ENETC_PFMCAPR 0x1b38 304 #define ENETC_PFMCAPR_MSK GENMASK(15, 0) 305 306 /* Port MAC counters: Port MAC 0 corresponds to the eMAC and 307 * Port MAC 1 to the pMAC. 308 */ 309 #define ENETC_PM_REOCT(mac) (0x8100 + ENETC_PMAC_OFFSET * (mac)) 310 #define ENETC_PM_RALN(mac) (0x8110 + ENETC_PMAC_OFFSET * (mac)) 311 #define ENETC_PM_RXPF(mac) (0x8118 + ENETC_PMAC_OFFSET * (mac)) 312 #define ENETC_PM_RFRM(mac) (0x8120 + ENETC_PMAC_OFFSET * (mac)) 313 #define ENETC_PM_RFCS(mac) (0x8128 + ENETC_PMAC_OFFSET * (mac)) 314 #define ENETC_PM_RVLAN(mac) (0x8130 + ENETC_PMAC_OFFSET * (mac)) 315 #define ENETC_PM_RERR(mac) (0x8138 + ENETC_PMAC_OFFSET * (mac)) 316 #define ENETC_PM_RUCA(mac) (0x8140 + ENETC_PMAC_OFFSET * (mac)) 317 #define ENETC_PM_RMCA(mac) (0x8148 + ENETC_PMAC_OFFSET * (mac)) 318 #define ENETC_PM_RBCA(mac) (0x8150 + ENETC_PMAC_OFFSET * (mac)) 319 #define ENETC_PM_RDRP(mac) (0x8158 + ENETC_PMAC_OFFSET * (mac)) 320 #define ENETC_PM_RPKT(mac) (0x8160 + ENETC_PMAC_OFFSET * (mac)) 321 #define ENETC_PM_RUND(mac) (0x8168 + ENETC_PMAC_OFFSET * (mac)) 322 #define ENETC_PM_R64(mac) (0x8170 + ENETC_PMAC_OFFSET * (mac)) 323 #define ENETC_PM_R127(mac) (0x8178 + ENETC_PMAC_OFFSET * (mac)) 324 #define ENETC_PM_R255(mac) (0x8180 + ENETC_PMAC_OFFSET * (mac)) 325 #define ENETC_PM_R511(mac) (0x8188 + ENETC_PMAC_OFFSET * (mac)) 326 #define ENETC_PM_R1023(mac) (0x8190 + ENETC_PMAC_OFFSET * (mac)) 327 #define ENETC_PM_R1522(mac) (0x8198 + ENETC_PMAC_OFFSET * (mac)) 328 #define ENETC_PM_R1523X(mac) (0x81A0 + ENETC_PMAC_OFFSET * (mac)) 329 #define ENETC_PM_ROVR(mac) (0x81A8 + ENETC_PMAC_OFFSET * (mac)) 330 #define ENETC_PM_RJBR(mac) (0x81B0 + ENETC_PMAC_OFFSET * (mac)) 331 #define ENETC_PM_RFRG(mac) (0x81B8 + ENETC_PMAC_OFFSET * (mac)) 332 #define ENETC_PM_RCNP(mac) (0x81C0 + ENETC_PMAC_OFFSET * (mac)) 333 #define ENETC_PM_RDRNTP(mac) (0x81C8 + ENETC_PMAC_OFFSET * (mac)) 334 #define ENETC_PM_TEOCT(mac) (0x8200 + ENETC_PMAC_OFFSET * (mac)) 335 #define ENETC_PM_TOCT(mac) (0x8208 + ENETC_PMAC_OFFSET * (mac)) 336 #define ENETC_PM_TCRSE(mac) (0x8210 + ENETC_PMAC_OFFSET * (mac)) 337 #define ENETC_PM_TXPF(mac) (0x8218 + ENETC_PMAC_OFFSET * (mac)) 338 #define ENETC_PM_TFRM(mac) (0x8220 + ENETC_PMAC_OFFSET * (mac)) 339 #define ENETC_PM_TFCS(mac) (0x8228 + ENETC_PMAC_OFFSET * (mac)) 340 #define ENETC_PM_TVLAN(mac) (0x8230 + ENETC_PMAC_OFFSET * (mac)) 341 #define ENETC_PM_TERR(mac) (0x8238 + ENETC_PMAC_OFFSET * (mac)) 342 #define ENETC_PM_TUCA(mac) (0x8240 + ENETC_PMAC_OFFSET * (mac)) 343 #define ENETC_PM_TMCA(mac) (0x8248 + ENETC_PMAC_OFFSET * (mac)) 344 #define ENETC_PM_TBCA(mac) (0x8250 + ENETC_PMAC_OFFSET * (mac)) 345 #define ENETC_PM_TPKT(mac) (0x8260 + ENETC_PMAC_OFFSET * (mac)) 346 #define ENETC_PM_TUND(mac) (0x8268 + ENETC_PMAC_OFFSET * (mac)) 347 #define ENETC_PM_T64(mac) (0x8270 + ENETC_PMAC_OFFSET * (mac)) 348 #define ENETC_PM_T127(mac) (0x8278 + ENETC_PMAC_OFFSET * (mac)) 349 #define ENETC_PM_T255(mac) (0x8280 + ENETC_PMAC_OFFSET * (mac)) 350 #define ENETC_PM_T511(mac) (0x8288 + ENETC_PMAC_OFFSET * (mac)) 351 #define ENETC_PM_T1023(mac) (0x8290 + ENETC_PMAC_OFFSET * (mac)) 352 #define ENETC_PM_T1522(mac) (0x8298 + ENETC_PMAC_OFFSET * (mac)) 353 #define ENETC_PM_T1523X(mac) (0x82A0 + ENETC_PMAC_OFFSET * (mac)) 354 #define ENETC_PM_TCNP(mac) (0x82C0 + ENETC_PMAC_OFFSET * (mac)) 355 #define ENETC_PM_TDFR(mac) (0x82D0 + ENETC_PMAC_OFFSET * (mac)) 356 #define ENETC_PM_TMCOL(mac) (0x82D8 + ENETC_PMAC_OFFSET * (mac)) 357 #define ENETC_PM_TSCOL(mac) (0x82E0 + ENETC_PMAC_OFFSET * (mac)) 358 #define ENETC_PM_TLCOL(mac) (0x82E8 + ENETC_PMAC_OFFSET * (mac)) 359 #define ENETC_PM_TECOL(mac) (0x82F0 + ENETC_PMAC_OFFSET * (mac)) 360 361 /* Port counters */ 362 #define ENETC_PICDR(n) (0x0700 + (n) * 8) /* n = [0..3] */ 363 #define ENETC_PBFDSIR 0x0810 364 #define ENETC_PFDMSAPR 0x0814 365 #define ENETC_UFDMF 0x1680 366 #define ENETC_MFDMF 0x1684 367 #define ENETC_PUFDVFR 0x1780 368 #define ENETC_PMFDVFR 0x1784 369 #define ENETC_PBFDVFR 0x1788 370 371 /** Global regs, offset: 2_0000h */ 372 #define ENETC_GLOBAL_BASE 0x20000 373 #define ENETC_G_EIPBRR0 0x0bf8 374 #define EIPBRR0_REVISION GENMASK(15, 0) 375 #define ENETC_REV_1_0 0x0100 376 #define ENETC_REV_4_1 0X0401 377 378 #define ENETC_G_EIPBRR1 0x0bfc 379 #define ENETC_G_EPFBLPR(n) (0xd00 + 4 * (n)) 380 #define ENETC_G_EPFBLPR1_XGMII 0x80000000 381 382 /* PCI device info */ 383 struct enetc_hw { 384 /* SI registers, used by all PCI functions */ 385 void __iomem *reg; 386 /* Port registers, PF only */ 387 void __iomem *port; 388 /* IP global registers, PF only */ 389 void __iomem *global; 390 }; 391 392 /* ENETC register accessors */ 393 394 /* MDIO issue workaround (on LS1028A) - 395 * Due to a hardware issue, an access to MDIO registers 396 * that is concurrent with other ENETC register accesses 397 * may lead to the MDIO access being dropped or corrupted. 398 * To protect the MDIO accesses a readers-writers locking 399 * scheme is used, where the MDIO register accesses are 400 * protected by write locks to insure exclusivity, while 401 * the remaining ENETC registers are accessed under read 402 * locks since they only compete with MDIO accesses. 403 */ 404 extern rwlock_t enetc_mdio_lock; 405 406 DECLARE_STATIC_KEY_FALSE(enetc_has_err050089); 407 408 /* use this locking primitive only on the fast datapath to 409 * group together multiple non-MDIO register accesses to 410 * minimize the overhead of the lock 411 */ 412 static inline void enetc_lock_mdio(void) 413 { 414 if (static_branch_unlikely(&enetc_has_err050089)) 415 read_lock(&enetc_mdio_lock); 416 } 417 418 static inline void enetc_unlock_mdio(void) 419 { 420 if (static_branch_unlikely(&enetc_has_err050089)) 421 read_unlock(&enetc_mdio_lock); 422 } 423 424 /* use these accessors only on the fast datapath under 425 * the enetc_lock_mdio() locking primitive to minimize 426 * the overhead of the lock 427 */ 428 static inline u32 enetc_rd_reg_hot(void __iomem *reg) 429 { 430 if (static_branch_unlikely(&enetc_has_err050089)) 431 lockdep_assert_held(&enetc_mdio_lock); 432 433 return ioread32(reg); 434 } 435 436 static inline void enetc_wr_reg_hot(void __iomem *reg, u32 val) 437 { 438 if (static_branch_unlikely(&enetc_has_err050089)) 439 lockdep_assert_held(&enetc_mdio_lock); 440 441 iowrite32(val, reg); 442 } 443 444 /* internal helpers for the MDIO w/a */ 445 static inline u32 _enetc_rd_reg_wa(void __iomem *reg) 446 { 447 u32 val; 448 449 enetc_lock_mdio(); 450 val = ioread32(reg); 451 enetc_unlock_mdio(); 452 453 return val; 454 } 455 456 static inline void _enetc_wr_reg_wa(void __iomem *reg, u32 val) 457 { 458 enetc_lock_mdio(); 459 iowrite32(val, reg); 460 enetc_unlock_mdio(); 461 } 462 463 static inline u32 _enetc_rd_mdio_reg_wa(void __iomem *reg) 464 { 465 unsigned long flags; 466 u32 val; 467 468 if (static_branch_unlikely(&enetc_has_err050089)) { 469 write_lock_irqsave(&enetc_mdio_lock, flags); 470 val = ioread32(reg); 471 write_unlock_irqrestore(&enetc_mdio_lock, flags); 472 } else { 473 val = ioread32(reg); 474 } 475 476 return val; 477 } 478 479 static inline void _enetc_wr_mdio_reg_wa(void __iomem *reg, u32 val) 480 { 481 unsigned long flags; 482 483 if (static_branch_unlikely(&enetc_has_err050089)) { 484 write_lock_irqsave(&enetc_mdio_lock, flags); 485 iowrite32(val, reg); 486 write_unlock_irqrestore(&enetc_mdio_lock, flags); 487 } else { 488 iowrite32(val, reg); 489 } 490 } 491 492 #ifdef ioread64 493 static inline u64 _enetc_rd_reg64(void __iomem *reg) 494 { 495 return ioread64(reg); 496 } 497 #else 498 /* using this to read out stats on 32b systems */ 499 static inline u64 _enetc_rd_reg64(void __iomem *reg) 500 { 501 u32 low, high, tmp; 502 503 do { 504 high = ioread32(reg + 4); 505 low = ioread32(reg); 506 tmp = ioread32(reg + 4); 507 } while (high != tmp); 508 509 return le64_to_cpu((__le64)high << 32 | low); 510 } 511 #endif 512 513 static inline u64 _enetc_rd_reg64_wa(void __iomem *reg) 514 { 515 u64 val; 516 517 enetc_lock_mdio(); 518 val = _enetc_rd_reg64(reg); 519 enetc_unlock_mdio(); 520 521 return val; 522 } 523 524 /* general register accessors */ 525 #define enetc_rd_reg(reg) _enetc_rd_reg_wa((reg)) 526 #define enetc_wr_reg(reg, val) _enetc_wr_reg_wa((reg), (val)) 527 #define enetc_rd(hw, off) enetc_rd_reg((hw)->reg + (off)) 528 #define enetc_wr(hw, off, val) enetc_wr_reg((hw)->reg + (off), val) 529 #define enetc_rd_hot(hw, off) enetc_rd_reg_hot((hw)->reg + (off)) 530 #define enetc_wr_hot(hw, off, val) enetc_wr_reg_hot((hw)->reg + (off), val) 531 #define enetc_rd64(hw, off) _enetc_rd_reg64_wa((hw)->reg + (off)) 532 /* port register accessors - PF only */ 533 #define enetc_port_rd(hw, off) enetc_rd_reg((hw)->port + (off)) 534 #define enetc_port_wr(hw, off, val) enetc_wr_reg((hw)->port + (off), val) 535 #define enetc_port_rd_mdio(hw, off) _enetc_rd_mdio_reg_wa((hw)->port + (off)) 536 #define enetc_port_wr_mdio(hw, off, val) _enetc_wr_mdio_reg_wa(\ 537 (hw)->port + (off), val) 538 /* global register accessors - PF only */ 539 #define enetc_global_rd(hw, off) enetc_rd_reg((hw)->global + (off)) 540 #define enetc_global_wr(hw, off, val) enetc_wr_reg((hw)->global + (off), val) 541 /* BDR register accessors, see ENETC_BDR() */ 542 #define enetc_bdr_rd(hw, t, n, off) \ 543 enetc_rd(hw, ENETC_BDR(t, n, off)) 544 #define enetc_bdr_wr(hw, t, n, off, val) \ 545 enetc_wr(hw, ENETC_BDR(t, n, off), val) 546 #define enetc_txbdr_rd(hw, n, off) enetc_bdr_rd(hw, TX, n, off) 547 #define enetc_rxbdr_rd(hw, n, off) enetc_bdr_rd(hw, RX, n, off) 548 #define enetc_txbdr_wr(hw, n, off, val) \ 549 enetc_bdr_wr(hw, TX, n, off, val) 550 #define enetc_rxbdr_wr(hw, n, off, val) \ 551 enetc_bdr_wr(hw, RX, n, off, val) 552 553 /* Buffer Descriptors (BD) */ 554 union enetc_tx_bd { 555 struct { 556 __le64 addr; 557 __le16 buf_len; 558 __le16 frm_len; 559 union { 560 struct { 561 u8 reserved[3]; 562 u8 flags; 563 }; /* default layout */ 564 __le32 txstart; 565 __le32 lstatus; 566 }; 567 }; 568 struct { 569 __le32 tstamp; 570 __le16 tpid; 571 __le16 vid; 572 u8 reserved[6]; 573 u8 e_flags; 574 u8 flags; 575 } ext; /* Tx BD extension */ 576 struct { 577 __le32 tstamp; 578 u8 reserved[10]; 579 u8 status; 580 u8 flags; 581 } wb; /* writeback descriptor */ 582 }; 583 584 enum enetc_txbd_flags { 585 ENETC_TXBD_FLAGS_RES0 = BIT(0), /* reserved */ 586 ENETC_TXBD_FLAGS_TSE = BIT(1), 587 ENETC_TXBD_FLAGS_W = BIT(2), 588 ENETC_TXBD_FLAGS_RES3 = BIT(3), /* reserved */ 589 ENETC_TXBD_FLAGS_TXSTART = BIT(4), 590 ENETC_TXBD_FLAGS_EX = BIT(6), 591 ENETC_TXBD_FLAGS_F = BIT(7) 592 }; 593 #define ENETC_TXBD_STATS_WIN BIT(7) 594 #define ENETC_TXBD_TXSTART_MASK GENMASK(24, 0) 595 #define ENETC_TXBD_FLAGS_OFFSET 24 596 597 static inline __le32 enetc_txbd_set_tx_start(u64 tx_start, u8 flags) 598 { 599 u32 temp; 600 601 temp = (tx_start >> 5 & ENETC_TXBD_TXSTART_MASK) | 602 (flags << ENETC_TXBD_FLAGS_OFFSET); 603 604 return cpu_to_le32(temp); 605 } 606 607 static inline void enetc_clear_tx_bd(union enetc_tx_bd *txbd) 608 { 609 memset(txbd, 0, sizeof(*txbd)); 610 } 611 612 /* Extension flags */ 613 #define ENETC_TXBD_E_FLAGS_VLAN_INS BIT(0) 614 #define ENETC_TXBD_E_FLAGS_ONE_STEP_PTP BIT(1) 615 #define ENETC_TXBD_E_FLAGS_TWO_STEP_PTP BIT(2) 616 617 union enetc_rx_bd { 618 struct { 619 __le64 addr; 620 u8 reserved[8]; 621 } w; 622 struct { 623 __le16 inet_csum; 624 __le16 parse_summary; 625 __le32 rss_hash; 626 __le16 buf_len; 627 __le16 vlan_opt; 628 union { 629 struct { 630 __le16 flags; 631 __le16 error; 632 }; 633 __le32 lstatus; 634 }; 635 } r; 636 struct { 637 __le32 tstamp; 638 u8 reserved[12]; 639 } ext; 640 }; 641 642 #define ENETC_RXBD_LSTATUS_R BIT(30) 643 #define ENETC_RXBD_LSTATUS_F BIT(31) 644 #define ENETC_RXBD_ERR_MASK 0xff 645 #define ENETC_RXBD_LSTATUS(flags) ((flags) << 16) 646 #define ENETC_RXBD_FLAG_VLAN BIT(9) 647 #define ENETC_RXBD_FLAG_TSTMP BIT(10) 648 #define ENETC_RXBD_FLAG_TPID GENMASK(1, 0) 649 650 #define ENETC_MAC_ADDR_FILT_CNT 8 /* # of supported entries per port */ 651 #define EMETC_MAC_ADDR_FILT_RES 3 /* # of reserved entries at the beginning */ 652 #define ENETC_MAX_NUM_VFS 2 653 654 #define ENETC_CBD_FLAGS_SF BIT(7) /* short format */ 655 #define ENETC_CBD_STATUS_MASK 0xf 656 657 struct enetc_cmd_rfse { 658 u8 smac_h[6]; 659 u8 smac_m[6]; 660 u8 dmac_h[6]; 661 u8 dmac_m[6]; 662 __be32 sip_h[4]; 663 __be32 sip_m[4]; 664 __be32 dip_h[4]; 665 __be32 dip_m[4]; 666 u16 ethtype_h; 667 u16 ethtype_m; 668 u16 ethtype4_h; 669 u16 ethtype4_m; 670 u16 sport_h; 671 u16 sport_m; 672 u16 dport_h; 673 u16 dport_m; 674 u16 vlan_h; 675 u16 vlan_m; 676 u8 proto_h; 677 u8 proto_m; 678 u16 flags; 679 u16 result; 680 u16 mode; 681 }; 682 683 #define ENETC_RFSE_EN BIT(15) 684 #define ENETC_RFSE_MODE_BD 2 685 686 static inline void enetc_load_primary_mac_addr(struct enetc_hw *hw, 687 struct net_device *ndev) 688 { 689 u8 addr[ETH_ALEN] __aligned(4); 690 691 *(u32 *)addr = __raw_readl(hw->reg + ENETC_SIPMAR0); 692 *(u16 *)(addr + 4) = __raw_readw(hw->reg + ENETC_SIPMAR1); 693 eth_hw_addr_set(ndev, addr); 694 } 695 696 #define ENETC_SI_INT_IDX 0 697 /* base index for Rx/Tx interrupts */ 698 #define ENETC_BDR_INT_BASE_IDX 1 699 700 /* Messaging */ 701 702 /* Command completion status */ 703 enum enetc_msg_cmd_status { 704 ENETC_MSG_CMD_STATUS_OK, 705 ENETC_MSG_CMD_STATUS_FAIL 706 }; 707 708 /* VSI-PSI command message types */ 709 enum enetc_msg_cmd_type { 710 ENETC_MSG_CMD_MNG_MAC = 1, /* manage MAC address */ 711 ENETC_MSG_CMD_MNG_RX_MAC_FILTER,/* manage RX MAC table */ 712 ENETC_MSG_CMD_MNG_RX_VLAN_FILTER /* manage RX VLAN table */ 713 }; 714 715 /* VSI-PSI command action types */ 716 enum enetc_msg_cmd_action_type { 717 ENETC_MSG_CMD_MNG_ADD = 1, 718 ENETC_MSG_CMD_MNG_REMOVE 719 }; 720 721 /* PSI-VSI command header format */ 722 struct enetc_msg_cmd_header { 723 u16 type; /* command class type */ 724 u16 id; /* denotes the specific required action */ 725 }; 726 727 /* Common H/W utility functions */ 728 729 static inline void enetc_bdr_enable_rxvlan(struct enetc_hw *hw, int idx, 730 bool en) 731 { 732 u32 val = enetc_rxbdr_rd(hw, idx, ENETC_RBMR); 733 734 val = (val & ~ENETC_RBMR_VTE) | (en ? ENETC_RBMR_VTE : 0); 735 enetc_rxbdr_wr(hw, idx, ENETC_RBMR, val); 736 } 737 738 static inline void enetc_bdr_enable_txvlan(struct enetc_hw *hw, int idx, 739 bool en) 740 { 741 u32 val = enetc_txbdr_rd(hw, idx, ENETC_TBMR); 742 743 val = (val & ~ENETC_TBMR_VIH) | (en ? ENETC_TBMR_VIH : 0); 744 enetc_txbdr_wr(hw, idx, ENETC_TBMR, val); 745 } 746 747 static inline void enetc_set_bdr_prio(struct enetc_hw *hw, int bdr_idx, 748 int prio) 749 { 750 u32 val = enetc_txbdr_rd(hw, bdr_idx, ENETC_TBMR); 751 752 val &= ~ENETC_TBMR_PRIO_MASK; 753 val |= ENETC_TBMR_SET_PRIO(prio); 754 enetc_txbdr_wr(hw, bdr_idx, ENETC_TBMR, val); 755 } 756 757 enum bdcr_cmd_class { 758 BDCR_CMD_UNSPEC = 0, 759 BDCR_CMD_MAC_FILTER, 760 BDCR_CMD_VLAN_FILTER, 761 BDCR_CMD_RSS, 762 BDCR_CMD_RFS, 763 BDCR_CMD_PORT_GCL, 764 BDCR_CMD_RECV_CLASSIFIER, 765 BDCR_CMD_STREAM_IDENTIFY, 766 BDCR_CMD_STREAM_FILTER, 767 BDCR_CMD_STREAM_GCL, 768 BDCR_CMD_FLOW_METER, 769 __BDCR_CMD_MAX_LEN, 770 BDCR_CMD_MAX_LEN = __BDCR_CMD_MAX_LEN - 1, 771 }; 772 773 /* class 5, command 0 */ 774 struct tgs_gcl_conf { 775 u8 atc; /* init gate value */ 776 u8 res[7]; 777 struct { 778 u8 res1[4]; 779 __le16 acl_len; 780 u8 res2[2]; 781 }; 782 }; 783 784 /* gate control list entry */ 785 struct gce { 786 __le32 period; 787 u8 gate; 788 u8 res[3]; 789 }; 790 791 /* tgs_gcl_conf address point to this data space */ 792 struct tgs_gcl_data { 793 __le32 btl; 794 __le32 bth; 795 __le32 ct; 796 __le32 cte; 797 struct gce entry[]; 798 }; 799 800 /* class 7, command 0, Stream Identity Entry Configuration */ 801 struct streamid_conf { 802 __le32 stream_handle; /* init gate value */ 803 __le32 iports; 804 u8 id_type; 805 u8 oui[3]; 806 u8 res[3]; 807 u8 en; 808 }; 809 810 #define ENETC_CBDR_SID_VID_MASK 0xfff 811 #define ENETC_CBDR_SID_VIDM BIT(12) 812 #define ENETC_CBDR_SID_TG_MASK 0xc000 813 /* streamid_conf address point to this data space */ 814 struct streamid_data { 815 union { 816 u8 dmac[6]; 817 u8 smac[6]; 818 }; 819 u16 vid_vidm_tg; 820 }; 821 822 #define ENETC_CBDR_SFI_PRI_MASK 0x7 823 #define ENETC_CBDR_SFI_PRIM BIT(3) 824 #define ENETC_CBDR_SFI_BLOV BIT(4) 825 #define ENETC_CBDR_SFI_BLEN BIT(5) 826 #define ENETC_CBDR_SFI_MSDUEN BIT(6) 827 #define ENETC_CBDR_SFI_FMITEN BIT(7) 828 #define ENETC_CBDR_SFI_ENABLE BIT(7) 829 /* class 8, command 0, Stream Filter Instance, Short Format */ 830 struct sfi_conf { 831 __le32 stream_handle; 832 u8 multi; 833 u8 res[2]; 834 u8 sthm; 835 /* Max Service Data Unit or Flow Meter Instance Table index. 836 * Depending on the value of FLT this represents either Max 837 * Service Data Unit (max frame size) allowed by the filter 838 * entry or is an index into the Flow Meter Instance table 839 * index identifying the policer which will be used to police 840 * it. 841 */ 842 __le16 fm_inst_table_index; 843 __le16 msdu; 844 __le16 sg_inst_table_index; 845 u8 res1[2]; 846 __le32 input_ports; 847 u8 res2[3]; 848 u8 en; 849 }; 850 851 /* class 8, command 2 stream Filter Instance status query short format 852 * command no need structure define 853 * Stream Filter Instance Query Statistics Response data 854 */ 855 struct sfi_counter_data { 856 u32 matchl; 857 u32 matchh; 858 u32 msdu_dropl; 859 u32 msdu_droph; 860 u32 stream_gate_dropl; 861 u32 stream_gate_droph; 862 u32 flow_meter_dropl; 863 u32 flow_meter_droph; 864 }; 865 866 #define ENETC_CBDR_SGI_OIPV_MASK 0x7 867 #define ENETC_CBDR_SGI_OIPV_EN BIT(3) 868 #define ENETC_CBDR_SGI_CGTST BIT(6) 869 #define ENETC_CBDR_SGI_OGTST BIT(7) 870 #define ENETC_CBDR_SGI_CFG_CHG BIT(1) 871 #define ENETC_CBDR_SGI_CFG_PND BIT(2) 872 #define ENETC_CBDR_SGI_OEX BIT(4) 873 #define ENETC_CBDR_SGI_OEXEN BIT(5) 874 #define ENETC_CBDR_SGI_IRX BIT(6) 875 #define ENETC_CBDR_SGI_IRXEN BIT(7) 876 #define ENETC_CBDR_SGI_ACLLEN_MASK 0x3 877 #define ENETC_CBDR_SGI_OCLLEN_MASK 0xc 878 #define ENETC_CBDR_SGI_EN BIT(7) 879 /* class 9, command 0, Stream Gate Instance Table, Short Format 880 * class 9, command 2, Stream Gate Instance Table entry query write back 881 * Short Format 882 */ 883 struct sgi_table { 884 u8 res[8]; 885 u8 oipv; 886 u8 res0[2]; 887 u8 ocgtst; 888 u8 res1[7]; 889 u8 gset; 890 u8 oacl_len; 891 u8 res2[2]; 892 u8 en; 893 }; 894 895 #define ENETC_CBDR_SGI_AIPV_MASK 0x7 896 #define ENETC_CBDR_SGI_AIPV_EN BIT(3) 897 #define ENETC_CBDR_SGI_AGTST BIT(7) 898 899 /* class 9, command 1, Stream Gate Control List, Long Format */ 900 struct sgcl_conf { 901 u8 aipv; 902 u8 res[2]; 903 u8 agtst; 904 u8 res1[4]; 905 union { 906 struct { 907 u8 res2[4]; 908 u8 acl_len; 909 u8 res3[3]; 910 }; 911 u8 cct[8]; /* Config change time */ 912 }; 913 }; 914 915 #define ENETC_CBDR_SGL_IOMEN BIT(0) 916 #define ENETC_CBDR_SGL_IPVEN BIT(3) 917 #define ENETC_CBDR_SGL_GTST BIT(4) 918 #define ENETC_CBDR_SGL_IPV_MASK 0xe 919 /* Stream Gate Control List Entry */ 920 struct sgce { 921 u32 interval; 922 u8 msdu[3]; 923 u8 multi; 924 }; 925 926 /* stream control list class 9 , cmd 1 data buffer */ 927 struct sgcl_data { 928 u32 btl; 929 u32 bth; 930 u32 ct; 931 u32 cte; 932 struct sgce sgcl[]; 933 }; 934 935 #define ENETC_CBDR_FMI_MR BIT(0) 936 #define ENETC_CBDR_FMI_MREN BIT(1) 937 #define ENETC_CBDR_FMI_DOY BIT(2) 938 #define ENETC_CBDR_FMI_CM BIT(3) 939 #define ENETC_CBDR_FMI_CF BIT(4) 940 #define ENETC_CBDR_FMI_NDOR BIT(5) 941 #define ENETC_CBDR_FMI_OALEN BIT(6) 942 #define ENETC_CBDR_FMI_IRFPP_MASK GENMASK(4, 0) 943 944 /* class 10: command 0/1, Flow Meter Instance Set, short Format */ 945 struct fmi_conf { 946 __le32 cir; 947 __le32 cbs; 948 __le32 eir; 949 __le32 ebs; 950 u8 conf; 951 u8 res1; 952 u8 ir_fpp; 953 u8 res2[4]; 954 u8 en; 955 }; 956 957 struct enetc_cbd { 958 union{ 959 struct sfi_conf sfi_conf; 960 struct sgi_table sgi_table; 961 struct fmi_conf fmi_conf; 962 struct { 963 __le32 addr[2]; 964 union { 965 __le32 opt[4]; 966 struct tgs_gcl_conf gcl_conf; 967 struct streamid_conf sid_set; 968 struct sgcl_conf sgcl_conf; 969 }; 970 }; /* Long format */ 971 __le32 data[6]; 972 }; 973 __le16 index; 974 __le16 length; 975 u8 cmd; 976 u8 cls; 977 u8 _res; 978 u8 status_flags; 979 }; 980 981 #define ENETC_CLK_400M 400000000ULL 982 #define ENETC_CLK_333M 333000000ULL 983 984 static inline u32 enetc_cycles_to_usecs(u32 cycles, u64 clk_freq) 985 { 986 return (u32)div_u64(cycles * 1000000ULL, clk_freq); 987 } 988 989 static inline u32 enetc_usecs_to_cycles(u32 usecs, u64 clk_freq) 990 { 991 return (u32)div_u64(usecs * clk_freq, 1000000ULL); 992 } 993 994 /* Port traffic class frame preemption register */ 995 #define ENETC_PTCFPR(n) (0x1910 + (n) * 4) /* n = [0 ..7] */ 996 #define ENETC_PTCFPR_FPE BIT(31) 997 998 /* port time gating control register */ 999 #define ENETC_PTGCR 0x11a00 1000 #define ENETC_PTGCR_TGE BIT(31) 1001 #define ENETC_PTGCR_TGPE BIT(30) 1002 1003 /* Port time gating capability register */ 1004 #define ENETC_PTGCAPR 0x11a08 1005 #define ENETC_PTGCAPR_MAX_GCL_LEN_MASK GENMASK(15, 0) 1006 1007 /* Port time specific departure */ 1008 #define ENETC_PTCTSDR(n) (0x1210 + 4 * (n)) 1009 #define ENETC_TSDE BIT(31) 1010 1011 /* PSFP setting */ 1012 #define ENETC_PPSFPMR 0x11b00 1013 #define ENETC_PPSFPMR_PSFPEN BIT(0) 1014 #define ENETC_PPSFPMR_VS BIT(1) 1015 #define ENETC_PPSFPMR_PVC BIT(2) 1016 #define ENETC_PPSFPMR_PVZC BIT(3) 1017