1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ 2 /* Copyright 2017-2019 NXP */ 3 4 #include <linux/bitops.h> 5 6 /* ENETC device IDs */ 7 #define ENETC_DEV_ID_PF 0xe100 8 #define ENETC_DEV_ID_VF 0xef00 9 #define ENETC_DEV_ID_PTP 0xee02 10 11 /* ENETC register block BAR */ 12 #define ENETC_BAR_REGS 0 13 14 /** SI regs, offset: 0h */ 15 #define ENETC_SIMR 0 16 #define ENETC_SIMR_EN BIT(31) 17 #define ENETC_SIMR_RSSE BIT(0) 18 #define ENETC_SICTR0 0x18 19 #define ENETC_SICTR1 0x1c 20 #define ENETC_SIPCAPR0 0x20 21 #define ENETC_SIPCAPR0_QBV BIT(4) 22 #define ENETC_SIPCAPR0_PSFP BIT(9) 23 #define ENETC_SIPCAPR0_RSS BIT(8) 24 #define ENETC_SIPCAPR1 0x24 25 #define ENETC_SITGTGR 0x30 26 #define ENETC_SIRBGCR 0x38 27 /* cache attribute registers for transactions initiated by ENETC */ 28 #define ENETC_SICAR0 0x40 29 #define ENETC_SICAR1 0x44 30 #define ENETC_SICAR2 0x48 31 /* rd snoop, no alloc 32 * wr snoop, no alloc, partial cache line update for BDs and full cache line 33 * update for data 34 */ 35 #define ENETC_SICAR_RD_COHERENT 0x2b2b0000 36 #define ENETC_SICAR_WR_COHERENT 0x00006727 37 #define ENETC_SICAR_MSI 0x00300030 /* rd/wr device, no snoop, no alloc */ 38 39 #define ENETC_SIPMAR0 0x80 40 #define ENETC_SIPMAR1 0x84 41 42 /* VF-PF Message passing */ 43 #define ENETC_DEFAULT_MSG_SIZE 1024 /* and max size */ 44 /* msg size encoding: default and max msg value of 1024B encoded as 0 */ 45 static inline u32 enetc_vsi_set_msize(u32 size) 46 { 47 return size < ENETC_DEFAULT_MSG_SIZE ? size >> 5 : 0; 48 } 49 50 #define ENETC_PSIMSGRR 0x204 51 #define ENETC_PSIMSGRR_MR_MASK GENMASK(2, 1) 52 #define ENETC_PSIMSGRR_MR(n) BIT((n) + 1) /* n = VSI index */ 53 #define ENETC_PSIVMSGRCVAR0(n) (0x210 + (n) * 0x8) /* n = VSI index */ 54 #define ENETC_PSIVMSGRCVAR1(n) (0x214 + (n) * 0x8) 55 56 #define ENETC_VSIMSGSR 0x204 /* RO */ 57 #define ENETC_VSIMSGSR_MB BIT(0) 58 #define ENETC_VSIMSGSR_MS BIT(1) 59 #define ENETC_VSIMSGSNDAR0 0x210 60 #define ENETC_VSIMSGSNDAR1 0x214 61 62 #define ENETC_SIMSGSR_SET_MC(val) ((val) << 16) 63 #define ENETC_SIMSGSR_GET_MC(val) ((val) >> 16) 64 65 /* SI statistics */ 66 #define ENETC_SIROCT 0x300 67 #define ENETC_SIRFRM 0x308 68 #define ENETC_SIRUCA 0x310 69 #define ENETC_SIRMCA 0x318 70 #define ENETC_SITOCT 0x320 71 #define ENETC_SITFRM 0x328 72 #define ENETC_SITUCA 0x330 73 #define ENETC_SITMCA 0x338 74 #define ENETC_RBDCR(n) (0x8180 + (n) * 0x200) 75 76 /* Control BDR regs */ 77 #define ENETC_SICBDRMR 0x800 78 #define ENETC_SICBDRSR 0x804 /* RO */ 79 #define ENETC_SICBDRBAR0 0x810 80 #define ENETC_SICBDRBAR1 0x814 81 #define ENETC_SICBDRPIR 0x818 82 #define ENETC_SICBDRCIR 0x81c 83 #define ENETC_SICBDRLENR 0x820 84 85 #define ENETC_SICAPR0 0x900 86 #define ENETC_SICAPR1 0x904 87 88 #define ENETC_PSIIER 0xa00 89 #define ENETC_PSIIER_MR_MASK GENMASK(2, 1) 90 #define ENETC_PSIIDR 0xa08 91 #define ENETC_SITXIDR 0xa18 92 #define ENETC_SIRXIDR 0xa28 93 #define ENETC_SIMSIVR 0xa30 94 95 #define ENETC_SIMSITRV(n) (0xB00 + (n) * 0x4) 96 #define ENETC_SIMSIRRV(n) (0xB80 + (n) * 0x4) 97 98 #define ENETC_SIUEFDCR 0xe28 99 100 #define ENETC_SIRFSCAPR 0x1200 101 #define ENETC_SIRFSCAPR_GET_NUM_RFS(val) ((val) & 0x7f) 102 #define ENETC_SIRSSCAPR 0x1600 103 #define ENETC_SIRSSCAPR_GET_NUM_RSS(val) (BIT((val) & 0xf) * 32) 104 105 /** SI BDR sub-blocks, n = 0..7 */ 106 enum enetc_bdr_type {TX, RX}; 107 #define ENETC_BDR_OFF(i) ((i) * 0x200) 108 #define ENETC_BDR(t, i, r) (0x8000 + (t) * 0x100 + ENETC_BDR_OFF(i) + (r)) 109 /* RX BDR reg offsets */ 110 #define ENETC_RBMR 0 111 #define ENETC_RBMR_BDS BIT(2) 112 #define ENETC_RBMR_VTE BIT(5) 113 #define ENETC_RBMR_EN BIT(31) 114 #define ENETC_RBSR 0x4 115 #define ENETC_RBBSR 0x8 116 #define ENETC_RBCIR 0xc 117 #define ENETC_RBBAR0 0x10 118 #define ENETC_RBBAR1 0x14 119 #define ENETC_RBPIR 0x18 120 #define ENETC_RBLENR 0x20 121 #define ENETC_RBIER 0xa0 122 #define ENETC_RBIER_RXTIE BIT(0) 123 #define ENETC_RBIDR 0xa4 124 #define ENETC_RBICR0 0xa8 125 #define ENETC_RBICR0_ICEN BIT(31) 126 #define ENETC_RBICR0_ICPT_MASK 0x1ff 127 #define ENETC_RBICR0_SET_ICPT(n) ((n) & ENETC_RBICR0_ICPT_MASK) 128 #define ENETC_RBICR1 0xac 129 130 /* TX BDR reg offsets */ 131 #define ENETC_TBMR 0 132 #define ENETC_TBSR_BUSY BIT(0) 133 #define ENETC_TBMR_VIH BIT(9) 134 #define ENETC_TBMR_PRIO_MASK GENMASK(2, 0) 135 #define ENETC_TBMR_SET_PRIO(val) ((val) & ENETC_TBMR_PRIO_MASK) 136 #define ENETC_TBMR_EN BIT(31) 137 #define ENETC_TBSR 0x4 138 #define ENETC_TBBAR0 0x10 139 #define ENETC_TBBAR1 0x14 140 #define ENETC_TBPIR 0x18 141 #define ENETC_TBCIR 0x1c 142 #define ENETC_TBCIR_IDX_MASK 0xffff 143 #define ENETC_TBLENR 0x20 144 #define ENETC_TBIER 0xa0 145 #define ENETC_TBIER_TXTIE BIT(0) 146 #define ENETC_TBIDR 0xa4 147 #define ENETC_TBICR0 0xa8 148 #define ENETC_TBICR0_ICEN BIT(31) 149 #define ENETC_TBICR0_ICPT_MASK 0xf 150 #define ENETC_TBICR0_SET_ICPT(n) ((ilog2(n) + 1) & ENETC_TBICR0_ICPT_MASK) 151 #define ENETC_TBICR1 0xac 152 153 #define ENETC_RTBLENR_LEN(n) ((n) & ~0x7) 154 155 /* Port regs, offset: 1_0000h */ 156 #define ENETC_PORT_BASE 0x10000 157 #define ENETC_PMR 0x0000 158 #define ENETC_PMR_EN GENMASK(18, 16) 159 #define ENETC_PMR_PSPEED_MASK GENMASK(11, 8) 160 #define ENETC_PMR_PSPEED_10M 0 161 #define ENETC_PMR_PSPEED_100M BIT(8) 162 #define ENETC_PMR_PSPEED_1000M BIT(9) 163 #define ENETC_PMR_PSPEED_2500M BIT(10) 164 #define ENETC_PSR 0x0004 /* RO */ 165 #define ENETC_PSIPMR 0x0018 166 #define ENETC_PSIPMR_SET_UP(n) BIT(n) /* n = SI index */ 167 #define ENETC_PSIPMR_SET_MP(n) BIT((n) + 16) 168 #define ENETC_PSIPVMR 0x001c 169 #define ENETC_VLAN_PROMISC_MAP_ALL 0x7 170 #define ENETC_PSIPVMR_SET_VP(simap) ((simap) & 0x7) 171 #define ENETC_PSIPVMR_SET_VUTA(simap) (((simap) & 0x7) << 16) 172 #define ENETC_PSIPMAR0(n) (0x0100 + (n) * 0x8) /* n = SI index */ 173 #define ENETC_PSIPMAR1(n) (0x0104 + (n) * 0x8) 174 #define ENETC_PVCLCTR 0x0208 175 #define ENETC_VLAN_TYPE_C BIT(0) 176 #define ENETC_VLAN_TYPE_S BIT(1) 177 #define ENETC_PVCLCTR_OVTPIDL(bmp) ((bmp) & 0xff) /* VLAN_TYPE */ 178 #define ENETC_PSIVLANR(n) (0x0240 + (n) * 4) /* n = SI index */ 179 #define ENETC_PSIVLAN_EN BIT(31) 180 #define ENETC_PSIVLAN_SET_QOS(val) ((u32)(val) << 12) 181 #define ENETC_PTXMBAR 0x0608 182 #define ENETC_PCAPR0 0x0900 183 #define ENETC_PCAPR0_RXBDR(val) ((val) >> 24) 184 #define ENETC_PCAPR0_TXBDR(val) (((val) >> 16) & 0xff) 185 #define ENETC_PCAPR1 0x0904 186 #define ENETC_PSICFGR0(n) (0x0940 + (n) * 0xc) /* n = SI index */ 187 #define ENETC_PSICFGR0_SET_TXBDR(val) ((val) & 0xff) 188 #define ENETC_PSICFGR0_SET_RXBDR(val) (((val) & 0xff) << 16) 189 #define ENETC_PSICFGR0_VTE BIT(12) 190 #define ENETC_PSICFGR0_SIVIE BIT(14) 191 #define ENETC_PSICFGR0_ASE BIT(15) 192 #define ENETC_PSICFGR0_SIVC(bmp) (((bmp) & 0xff) << 24) /* VLAN_TYPE */ 193 194 #define ENETC_PTCCBSR0(n) (0x1110 + (n) * 8) /* n = 0 to 7*/ 195 #define ENETC_CBSE BIT(31) 196 #define ENETC_CBS_BW_MASK GENMASK(6, 0) 197 #define ENETC_PTCCBSR1(n) (0x1114 + (n) * 8) /* n = 0 to 7*/ 198 #define ENETC_RSSHASH_KEY_SIZE 40 199 #define ENETC_PRSSK(n) (0x1410 + (n) * 4) /* n = [0..9] */ 200 #define ENETC_PSIVLANFMR 0x1700 201 #define ENETC_PSIVLANFMR_VS BIT(0) 202 #define ENETC_PRFSMR 0x1800 203 #define ENETC_PRFSMR_RFSE BIT(31) 204 #define ENETC_PRFSCAPR 0x1804 205 #define ENETC_PRFSCAPR_GET_NUM_RFS(val) ((((val) & 0xf) + 1) * 16) 206 #define ENETC_PSIRFSCFGR(n) (0x1814 + (n) * 4) /* n = SI index */ 207 #define ENETC_PFPMR 0x1900 208 #define ENETC_PFPMR_PMACE BIT(1) 209 #define ENETC_PFPMR_MWLM BIT(0) 210 #define ENETC_EMDIO_BASE 0x1c00 211 #define ENETC_PSIUMHFR0(n, err) (((err) ? 0x1d08 : 0x1d00) + (n) * 0x10) 212 #define ENETC_PSIUMHFR1(n) (0x1d04 + (n) * 0x10) 213 #define ENETC_PSIMMHFR0(n, err) (((err) ? 0x1d00 : 0x1d08) + (n) * 0x10) 214 #define ENETC_PSIMMHFR1(n) (0x1d0c + (n) * 0x10) 215 #define ENETC_PSIVHFR0(n) (0x1e00 + (n) * 8) /* n = SI index */ 216 #define ENETC_PSIVHFR1(n) (0x1e04 + (n) * 8) /* n = SI index */ 217 #define ENETC_MMCSR 0x1f00 218 #define ENETC_MMCSR_ME BIT(16) 219 #define ENETC_PTCMSDUR(n) (0x2020 + (n) * 4) /* n = TC index [0..7] */ 220 221 #define ENETC_PM0_CMD_CFG 0x8008 222 #define ENETC_PM1_CMD_CFG 0x9008 223 #define ENETC_PM0_TX_EN BIT(0) 224 #define ENETC_PM0_RX_EN BIT(1) 225 #define ENETC_PM0_PROMISC BIT(4) 226 #define ENETC_PM0_CMD_XGLP BIT(10) 227 #define ENETC_PM0_CMD_TXP BIT(11) 228 #define ENETC_PM0_CMD_PHY_TX_EN BIT(15) 229 #define ENETC_PM0_CMD_SFD BIT(21) 230 #define ENETC_PM0_MAXFRM 0x8014 231 #define ENETC_SET_TX_MTU(val) ((val) << 16) 232 #define ENETC_SET_MAXFRM(val) ((val) & 0xffff) 233 234 #define ENETC_PM_IMDIO_BASE 0x8030 235 236 #define ENETC_PM0_IF_MODE 0x8300 237 #define ENETC_PMO_IFM_RG BIT(2) 238 #define ENETC_PM0_IFM_RLP (BIT(5) | BIT(11)) 239 #define ENETC_PM0_IFM_RGAUTO (BIT(15) | ENETC_PMO_IFM_RG | BIT(1)) 240 #define ENETC_PM0_IFM_XGMII BIT(12) 241 #define ENETC_PSIDCAPR 0x1b08 242 #define ENETC_PSIDCAPR_MSK GENMASK(15, 0) 243 #define ENETC_PSFCAPR 0x1b18 244 #define ENETC_PSFCAPR_MSK GENMASK(15, 0) 245 #define ENETC_PSGCAPR 0x1b28 246 #define ENETC_PSGCAPR_GCL_MSK GENMASK(18, 16) 247 #define ENETC_PSGCAPR_SGIT_MSK GENMASK(15, 0) 248 #define ENETC_PFMCAPR 0x1b38 249 #define ENETC_PFMCAPR_MSK GENMASK(15, 0) 250 251 /* MAC counters */ 252 #define ENETC_PM0_REOCT 0x8100 253 #define ENETC_PM0_RALN 0x8110 254 #define ENETC_PM0_RXPF 0x8118 255 #define ENETC_PM0_RFRM 0x8120 256 #define ENETC_PM0_RFCS 0x8128 257 #define ENETC_PM0_RVLAN 0x8130 258 #define ENETC_PM0_RERR 0x8138 259 #define ENETC_PM0_RUCA 0x8140 260 #define ENETC_PM0_RMCA 0x8148 261 #define ENETC_PM0_RBCA 0x8150 262 #define ENETC_PM0_RDRP 0x8158 263 #define ENETC_PM0_RPKT 0x8160 264 #define ENETC_PM0_RUND 0x8168 265 #define ENETC_PM0_R64 0x8170 266 #define ENETC_PM0_R127 0x8178 267 #define ENETC_PM0_R255 0x8180 268 #define ENETC_PM0_R511 0x8188 269 #define ENETC_PM0_R1023 0x8190 270 #define ENETC_PM0_R1518 0x8198 271 #define ENETC_PM0_R1519X 0x81A0 272 #define ENETC_PM0_ROVR 0x81A8 273 #define ENETC_PM0_RJBR 0x81B0 274 #define ENETC_PM0_RFRG 0x81B8 275 #define ENETC_PM0_RCNP 0x81C0 276 #define ENETC_PM0_RDRNTP 0x81C8 277 #define ENETC_PM0_TEOCT 0x8200 278 #define ENETC_PM0_TOCT 0x8208 279 #define ENETC_PM0_TCRSE 0x8210 280 #define ENETC_PM0_TXPF 0x8218 281 #define ENETC_PM0_TFRM 0x8220 282 #define ENETC_PM0_TFCS 0x8228 283 #define ENETC_PM0_TVLAN 0x8230 284 #define ENETC_PM0_TERR 0x8238 285 #define ENETC_PM0_TUCA 0x8240 286 #define ENETC_PM0_TMCA 0x8248 287 #define ENETC_PM0_TBCA 0x8250 288 #define ENETC_PM0_TPKT 0x8260 289 #define ENETC_PM0_TUND 0x8268 290 #define ENETC_PM0_T127 0x8278 291 #define ENETC_PM0_T1023 0x8290 292 #define ENETC_PM0_T1518 0x8298 293 #define ENETC_PM0_TCNP 0x82C0 294 #define ENETC_PM0_TDFR 0x82D0 295 #define ENETC_PM0_TMCOL 0x82D8 296 #define ENETC_PM0_TSCOL 0x82E0 297 #define ENETC_PM0_TLCOL 0x82E8 298 #define ENETC_PM0_TECOL 0x82F0 299 300 /* Port counters */ 301 #define ENETC_PICDR(n) (0x0700 + (n) * 8) /* n = [0..3] */ 302 #define ENETC_PBFDSIR 0x0810 303 #define ENETC_PFDMSAPR 0x0814 304 #define ENETC_UFDMF 0x1680 305 #define ENETC_MFDMF 0x1684 306 #define ENETC_PUFDVFR 0x1780 307 #define ENETC_PMFDVFR 0x1784 308 #define ENETC_PBFDVFR 0x1788 309 310 /** Global regs, offset: 2_0000h */ 311 #define ENETC_GLOBAL_BASE 0x20000 312 #define ENETC_G_EIPBRR0 0x0bf8 313 #define ENETC_G_EIPBRR1 0x0bfc 314 #define ENETC_G_EPFBLPR(n) (0xd00 + 4 * (n)) 315 #define ENETC_G_EPFBLPR1_XGMII 0x80000000 316 317 /* PCI device info */ 318 struct enetc_hw { 319 /* SI registers, used by all PCI functions */ 320 void __iomem *reg; 321 /* Port registers, PF only */ 322 void __iomem *port; 323 /* IP global registers, PF only */ 324 void __iomem *global; 325 }; 326 327 /* ENETC register accessors */ 328 329 /* MDIO issue workaround (on LS1028A) - 330 * Due to a hardware issue, an access to MDIO registers 331 * that is concurrent with other ENETC register accesses 332 * may lead to the MDIO access being dropped or corrupted. 333 * To protect the MDIO accesses a readers-writers locking 334 * scheme is used, where the MDIO register accesses are 335 * protected by write locks to insure exclusivity, while 336 * the remaining ENETC registers are accessed under read 337 * locks since they only compete with MDIO accesses. 338 */ 339 extern rwlock_t enetc_mdio_lock; 340 341 /* use this locking primitive only on the fast datapath to 342 * group together multiple non-MDIO register accesses to 343 * minimize the overhead of the lock 344 */ 345 static inline void enetc_lock_mdio(void) 346 { 347 read_lock(&enetc_mdio_lock); 348 } 349 350 static inline void enetc_unlock_mdio(void) 351 { 352 read_unlock(&enetc_mdio_lock); 353 } 354 355 /* use these accessors only on the fast datapath under 356 * the enetc_lock_mdio() locking primitive to minimize 357 * the overhead of the lock 358 */ 359 static inline u32 enetc_rd_reg_hot(void __iomem *reg) 360 { 361 lockdep_assert_held(&enetc_mdio_lock); 362 363 return ioread32(reg); 364 } 365 366 static inline void enetc_wr_reg_hot(void __iomem *reg, u32 val) 367 { 368 lockdep_assert_held(&enetc_mdio_lock); 369 370 iowrite32(val, reg); 371 } 372 373 /* internal helpers for the MDIO w/a */ 374 static inline u32 _enetc_rd_reg_wa(void __iomem *reg) 375 { 376 u32 val; 377 378 enetc_lock_mdio(); 379 val = ioread32(reg); 380 enetc_unlock_mdio(); 381 382 return val; 383 } 384 385 static inline void _enetc_wr_reg_wa(void __iomem *reg, u32 val) 386 { 387 enetc_lock_mdio(); 388 iowrite32(val, reg); 389 enetc_unlock_mdio(); 390 } 391 392 static inline u32 _enetc_rd_mdio_reg_wa(void __iomem *reg) 393 { 394 unsigned long flags; 395 u32 val; 396 397 write_lock_irqsave(&enetc_mdio_lock, flags); 398 val = ioread32(reg); 399 write_unlock_irqrestore(&enetc_mdio_lock, flags); 400 401 return val; 402 } 403 404 static inline void _enetc_wr_mdio_reg_wa(void __iomem *reg, u32 val) 405 { 406 unsigned long flags; 407 408 write_lock_irqsave(&enetc_mdio_lock, flags); 409 iowrite32(val, reg); 410 write_unlock_irqrestore(&enetc_mdio_lock, flags); 411 } 412 413 #ifdef ioread64 414 static inline u64 _enetc_rd_reg64(void __iomem *reg) 415 { 416 return ioread64(reg); 417 } 418 #else 419 /* using this to read out stats on 32b systems */ 420 static inline u64 _enetc_rd_reg64(void __iomem *reg) 421 { 422 u32 low, high, tmp; 423 424 do { 425 high = ioread32(reg + 4); 426 low = ioread32(reg); 427 tmp = ioread32(reg + 4); 428 } while (high != tmp); 429 430 return le64_to_cpu((__le64)high << 32 | low); 431 } 432 #endif 433 434 static inline u64 _enetc_rd_reg64_wa(void __iomem *reg) 435 { 436 u64 val; 437 438 enetc_lock_mdio(); 439 val = _enetc_rd_reg64(reg); 440 enetc_unlock_mdio(); 441 442 return val; 443 } 444 445 /* general register accessors */ 446 #define enetc_rd_reg(reg) _enetc_rd_reg_wa((reg)) 447 #define enetc_wr_reg(reg, val) _enetc_wr_reg_wa((reg), (val)) 448 #define enetc_rd(hw, off) enetc_rd_reg((hw)->reg + (off)) 449 #define enetc_wr(hw, off, val) enetc_wr_reg((hw)->reg + (off), val) 450 #define enetc_rd64(hw, off) _enetc_rd_reg64_wa((hw)->reg + (off)) 451 /* port register accessors - PF only */ 452 #define enetc_port_rd(hw, off) enetc_rd_reg((hw)->port + (off)) 453 #define enetc_port_wr(hw, off, val) enetc_wr_reg((hw)->port + (off), val) 454 #define enetc_port_rd_mdio(hw, off) _enetc_rd_mdio_reg_wa((hw)->port + (off)) 455 #define enetc_port_wr_mdio(hw, off, val) _enetc_wr_mdio_reg_wa(\ 456 (hw)->port + (off), val) 457 /* global register accessors - PF only */ 458 #define enetc_global_rd(hw, off) enetc_rd_reg((hw)->global + (off)) 459 #define enetc_global_wr(hw, off, val) enetc_wr_reg((hw)->global + (off), val) 460 /* BDR register accessors, see ENETC_BDR() */ 461 #define enetc_bdr_rd(hw, t, n, off) \ 462 enetc_rd(hw, ENETC_BDR(t, n, off)) 463 #define enetc_bdr_wr(hw, t, n, off, val) \ 464 enetc_wr(hw, ENETC_BDR(t, n, off), val) 465 #define enetc_txbdr_rd(hw, n, off) enetc_bdr_rd(hw, TX, n, off) 466 #define enetc_rxbdr_rd(hw, n, off) enetc_bdr_rd(hw, RX, n, off) 467 #define enetc_txbdr_wr(hw, n, off, val) \ 468 enetc_bdr_wr(hw, TX, n, off, val) 469 #define enetc_rxbdr_wr(hw, n, off, val) \ 470 enetc_bdr_wr(hw, RX, n, off, val) 471 472 /* Buffer Descriptors (BD) */ 473 union enetc_tx_bd { 474 struct { 475 __le64 addr; 476 __le16 buf_len; 477 __le16 frm_len; 478 union { 479 struct { 480 u8 reserved[3]; 481 u8 flags; 482 }; /* default layout */ 483 __le32 txstart; 484 __le32 lstatus; 485 }; 486 }; 487 struct { 488 __le32 tstamp; 489 __le16 tpid; 490 __le16 vid; 491 u8 reserved[6]; 492 u8 e_flags; 493 u8 flags; 494 } ext; /* Tx BD extension */ 495 struct { 496 __le32 tstamp; 497 u8 reserved[10]; 498 u8 status; 499 u8 flags; 500 } wb; /* writeback descriptor */ 501 }; 502 503 enum enetc_txbd_flags { 504 ENETC_TXBD_FLAGS_RES0 = BIT(0), /* reserved */ 505 ENETC_TXBD_FLAGS_TSE = BIT(1), 506 ENETC_TXBD_FLAGS_W = BIT(2), 507 ENETC_TXBD_FLAGS_RES3 = BIT(3), /* reserved */ 508 ENETC_TXBD_FLAGS_TXSTART = BIT(4), 509 ENETC_TXBD_FLAGS_EX = BIT(6), 510 ENETC_TXBD_FLAGS_F = BIT(7) 511 }; 512 #define ENETC_TXBD_TXSTART_MASK GENMASK(24, 0) 513 #define ENETC_TXBD_FLAGS_OFFSET 24 514 515 static inline __le32 enetc_txbd_set_tx_start(u64 tx_start, u8 flags) 516 { 517 u32 temp; 518 519 temp = (tx_start >> 5 & ENETC_TXBD_TXSTART_MASK) | 520 (flags << ENETC_TXBD_FLAGS_OFFSET); 521 522 return cpu_to_le32(temp); 523 } 524 525 static inline void enetc_clear_tx_bd(union enetc_tx_bd *txbd) 526 { 527 memset(txbd, 0, sizeof(*txbd)); 528 } 529 530 /* Extension flags */ 531 #define ENETC_TXBD_E_FLAGS_VLAN_INS BIT(0) 532 #define ENETC_TXBD_E_FLAGS_TWO_STEP_PTP BIT(2) 533 534 union enetc_rx_bd { 535 struct { 536 __le64 addr; 537 u8 reserved[8]; 538 } w; 539 struct { 540 __le16 inet_csum; 541 __le16 parse_summary; 542 __le32 rss_hash; 543 __le16 buf_len; 544 __le16 vlan_opt; 545 union { 546 struct { 547 __le16 flags; 548 __le16 error; 549 }; 550 __le32 lstatus; 551 }; 552 } r; 553 struct { 554 __le32 tstamp; 555 u8 reserved[12]; 556 } ext; 557 }; 558 559 #define ENETC_RXBD_LSTATUS_R BIT(30) 560 #define ENETC_RXBD_LSTATUS_F BIT(31) 561 #define ENETC_RXBD_ERR_MASK 0xff 562 #define ENETC_RXBD_LSTATUS(flags) ((flags) << 16) 563 #define ENETC_RXBD_FLAG_VLAN BIT(9) 564 #define ENETC_RXBD_FLAG_TSTMP BIT(10) 565 566 #define ENETC_MAC_ADDR_FILT_CNT 8 /* # of supported entries per port */ 567 #define EMETC_MAC_ADDR_FILT_RES 3 /* # of reserved entries at the beginning */ 568 #define ENETC_MAX_NUM_VFS 2 569 570 #define ENETC_CBD_FLAGS_SF BIT(7) /* short format */ 571 #define ENETC_CBD_STATUS_MASK 0xf 572 573 struct enetc_cmd_rfse { 574 u8 smac_h[6]; 575 u8 smac_m[6]; 576 u8 dmac_h[6]; 577 u8 dmac_m[6]; 578 __be32 sip_h[4]; 579 __be32 sip_m[4]; 580 __be32 dip_h[4]; 581 __be32 dip_m[4]; 582 u16 ethtype_h; 583 u16 ethtype_m; 584 u16 ethtype4_h; 585 u16 ethtype4_m; 586 u16 sport_h; 587 u16 sport_m; 588 u16 dport_h; 589 u16 dport_m; 590 u16 vlan_h; 591 u16 vlan_m; 592 u8 proto_h; 593 u8 proto_m; 594 u16 flags; 595 u16 result; 596 u16 mode; 597 }; 598 599 #define ENETC_RFSE_EN BIT(15) 600 #define ENETC_RFSE_MODE_BD 2 601 602 static inline void enetc_get_primary_mac_addr(struct enetc_hw *hw, u8 *addr) 603 { 604 *(u32 *)addr = __raw_readl(hw->reg + ENETC_SIPMAR0); 605 *(u16 *)(addr + 4) = __raw_readw(hw->reg + ENETC_SIPMAR1); 606 } 607 608 #define ENETC_SI_INT_IDX 0 609 /* base index for Rx/Tx interrupts */ 610 #define ENETC_BDR_INT_BASE_IDX 1 611 612 /* Messaging */ 613 614 /* Command completion status */ 615 enum enetc_msg_cmd_status { 616 ENETC_MSG_CMD_STATUS_OK, 617 ENETC_MSG_CMD_STATUS_FAIL 618 }; 619 620 /* VSI-PSI command message types */ 621 enum enetc_msg_cmd_type { 622 ENETC_MSG_CMD_MNG_MAC = 1, /* manage MAC address */ 623 ENETC_MSG_CMD_MNG_RX_MAC_FILTER,/* manage RX MAC table */ 624 ENETC_MSG_CMD_MNG_RX_VLAN_FILTER /* manage RX VLAN table */ 625 }; 626 627 /* VSI-PSI command action types */ 628 enum enetc_msg_cmd_action_type { 629 ENETC_MSG_CMD_MNG_ADD = 1, 630 ENETC_MSG_CMD_MNG_REMOVE 631 }; 632 633 /* PSI-VSI command header format */ 634 struct enetc_msg_cmd_header { 635 u16 type; /* command class type */ 636 u16 id; /* denotes the specific required action */ 637 }; 638 639 /* Common H/W utility functions */ 640 641 static inline void enetc_bdr_enable_rxvlan(struct enetc_hw *hw, int idx, 642 bool en) 643 { 644 u32 val = enetc_rxbdr_rd(hw, idx, ENETC_RBMR); 645 646 val = (val & ~ENETC_RBMR_VTE) | (en ? ENETC_RBMR_VTE : 0); 647 enetc_rxbdr_wr(hw, idx, ENETC_RBMR, val); 648 } 649 650 static inline void enetc_bdr_enable_txvlan(struct enetc_hw *hw, int idx, 651 bool en) 652 { 653 u32 val = enetc_txbdr_rd(hw, idx, ENETC_TBMR); 654 655 val = (val & ~ENETC_TBMR_VIH) | (en ? ENETC_TBMR_VIH : 0); 656 enetc_txbdr_wr(hw, idx, ENETC_TBMR, val); 657 } 658 659 static inline void enetc_set_bdr_prio(struct enetc_hw *hw, int bdr_idx, 660 int prio) 661 { 662 u32 val = enetc_txbdr_rd(hw, bdr_idx, ENETC_TBMR); 663 664 val &= ~ENETC_TBMR_PRIO_MASK; 665 val |= ENETC_TBMR_SET_PRIO(prio); 666 enetc_txbdr_wr(hw, bdr_idx, ENETC_TBMR, val); 667 } 668 669 enum bdcr_cmd_class { 670 BDCR_CMD_UNSPEC = 0, 671 BDCR_CMD_MAC_FILTER, 672 BDCR_CMD_VLAN_FILTER, 673 BDCR_CMD_RSS, 674 BDCR_CMD_RFS, 675 BDCR_CMD_PORT_GCL, 676 BDCR_CMD_RECV_CLASSIFIER, 677 BDCR_CMD_STREAM_IDENTIFY, 678 BDCR_CMD_STREAM_FILTER, 679 BDCR_CMD_STREAM_GCL, 680 BDCR_CMD_FLOW_METER, 681 __BDCR_CMD_MAX_LEN, 682 BDCR_CMD_MAX_LEN = __BDCR_CMD_MAX_LEN - 1, 683 }; 684 685 /* class 5, command 0 */ 686 struct tgs_gcl_conf { 687 u8 atc; /* init gate value */ 688 u8 res[7]; 689 struct { 690 u8 res1[4]; 691 __le16 acl_len; 692 u8 res2[2]; 693 }; 694 }; 695 696 /* gate control list entry */ 697 struct gce { 698 __le32 period; 699 u8 gate; 700 u8 res[3]; 701 }; 702 703 /* tgs_gcl_conf address point to this data space */ 704 struct tgs_gcl_data { 705 __le32 btl; 706 __le32 bth; 707 __le32 ct; 708 __le32 cte; 709 struct gce entry[]; 710 }; 711 712 /* class 7, command 0, Stream Identity Entry Configuration */ 713 struct streamid_conf { 714 __le32 stream_handle; /* init gate value */ 715 __le32 iports; 716 u8 id_type; 717 u8 oui[3]; 718 u8 res[3]; 719 u8 en; 720 }; 721 722 #define ENETC_CBDR_SID_VID_MASK 0xfff 723 #define ENETC_CBDR_SID_VIDM BIT(12) 724 #define ENETC_CBDR_SID_TG_MASK 0xc000 725 /* streamid_conf address point to this data space */ 726 struct streamid_data { 727 union { 728 u8 dmac[6]; 729 u8 smac[6]; 730 }; 731 u16 vid_vidm_tg; 732 }; 733 734 #define ENETC_CBDR_SFI_PRI_MASK 0x7 735 #define ENETC_CBDR_SFI_PRIM BIT(3) 736 #define ENETC_CBDR_SFI_BLOV BIT(4) 737 #define ENETC_CBDR_SFI_BLEN BIT(5) 738 #define ENETC_CBDR_SFI_MSDUEN BIT(6) 739 #define ENETC_CBDR_SFI_FMITEN BIT(7) 740 #define ENETC_CBDR_SFI_ENABLE BIT(7) 741 /* class 8, command 0, Stream Filter Instance, Short Format */ 742 struct sfi_conf { 743 __le32 stream_handle; 744 u8 multi; 745 u8 res[2]; 746 u8 sthm; 747 /* Max Service Data Unit or Flow Meter Instance Table index. 748 * Depending on the value of FLT this represents either Max 749 * Service Data Unit (max frame size) allowed by the filter 750 * entry or is an index into the Flow Meter Instance table 751 * index identifying the policer which will be used to police 752 * it. 753 */ 754 __le16 fm_inst_table_index; 755 __le16 msdu; 756 __le16 sg_inst_table_index; 757 u8 res1[2]; 758 __le32 input_ports; 759 u8 res2[3]; 760 u8 en; 761 }; 762 763 /* class 8, command 2 stream Filter Instance status query short format 764 * command no need structure define 765 * Stream Filter Instance Query Statistics Response data 766 */ 767 struct sfi_counter_data { 768 u32 matchl; 769 u32 matchh; 770 u32 msdu_dropl; 771 u32 msdu_droph; 772 u32 stream_gate_dropl; 773 u32 stream_gate_droph; 774 u32 flow_meter_dropl; 775 u32 flow_meter_droph; 776 }; 777 778 #define ENETC_CBDR_SGI_OIPV_MASK 0x7 779 #define ENETC_CBDR_SGI_OIPV_EN BIT(3) 780 #define ENETC_CBDR_SGI_CGTST BIT(6) 781 #define ENETC_CBDR_SGI_OGTST BIT(7) 782 #define ENETC_CBDR_SGI_CFG_CHG BIT(1) 783 #define ENETC_CBDR_SGI_CFG_PND BIT(2) 784 #define ENETC_CBDR_SGI_OEX BIT(4) 785 #define ENETC_CBDR_SGI_OEXEN BIT(5) 786 #define ENETC_CBDR_SGI_IRX BIT(6) 787 #define ENETC_CBDR_SGI_IRXEN BIT(7) 788 #define ENETC_CBDR_SGI_ACLLEN_MASK 0x3 789 #define ENETC_CBDR_SGI_OCLLEN_MASK 0xc 790 #define ENETC_CBDR_SGI_EN BIT(7) 791 /* class 9, command 0, Stream Gate Instance Table, Short Format 792 * class 9, command 2, Stream Gate Instance Table entry query write back 793 * Short Format 794 */ 795 struct sgi_table { 796 u8 res[8]; 797 u8 oipv; 798 u8 res0[2]; 799 u8 ocgtst; 800 u8 res1[7]; 801 u8 gset; 802 u8 oacl_len; 803 u8 res2[2]; 804 u8 en; 805 }; 806 807 #define ENETC_CBDR_SGI_AIPV_MASK 0x7 808 #define ENETC_CBDR_SGI_AIPV_EN BIT(3) 809 #define ENETC_CBDR_SGI_AGTST BIT(7) 810 811 /* class 9, command 1, Stream Gate Control List, Long Format */ 812 struct sgcl_conf { 813 u8 aipv; 814 u8 res[2]; 815 u8 agtst; 816 u8 res1[4]; 817 union { 818 struct { 819 u8 res2[4]; 820 u8 acl_len; 821 u8 res3[3]; 822 }; 823 u8 cct[8]; /* Config change time */ 824 }; 825 }; 826 827 #define ENETC_CBDR_SGL_IOMEN BIT(0) 828 #define ENETC_CBDR_SGL_IPVEN BIT(3) 829 #define ENETC_CBDR_SGL_GTST BIT(4) 830 #define ENETC_CBDR_SGL_IPV_MASK 0xe 831 /* Stream Gate Control List Entry */ 832 struct sgce { 833 u32 interval; 834 u8 msdu[3]; 835 u8 multi; 836 }; 837 838 /* stream control list class 9 , cmd 1 data buffer */ 839 struct sgcl_data { 840 u32 btl; 841 u32 bth; 842 u32 ct; 843 u32 cte; 844 struct sgce sgcl[0]; 845 }; 846 847 #define ENETC_CBDR_FMI_MR BIT(0) 848 #define ENETC_CBDR_FMI_MREN BIT(1) 849 #define ENETC_CBDR_FMI_DOY BIT(2) 850 #define ENETC_CBDR_FMI_CM BIT(3) 851 #define ENETC_CBDR_FMI_CF BIT(4) 852 #define ENETC_CBDR_FMI_NDOR BIT(5) 853 #define ENETC_CBDR_FMI_OALEN BIT(6) 854 #define ENETC_CBDR_FMI_IRFPP_MASK GENMASK(4, 0) 855 856 /* class 10: command 0/1, Flow Meter Instance Set, short Format */ 857 struct fmi_conf { 858 __le32 cir; 859 __le32 cbs; 860 __le32 eir; 861 __le32 ebs; 862 u8 conf; 863 u8 res1; 864 u8 ir_fpp; 865 u8 res2[4]; 866 u8 en; 867 }; 868 869 struct enetc_cbd { 870 union{ 871 struct sfi_conf sfi_conf; 872 struct sgi_table sgi_table; 873 struct fmi_conf fmi_conf; 874 struct { 875 __le32 addr[2]; 876 union { 877 __le32 opt[4]; 878 struct tgs_gcl_conf gcl_conf; 879 struct streamid_conf sid_set; 880 struct sgcl_conf sgcl_conf; 881 }; 882 }; /* Long format */ 883 __le32 data[6]; 884 }; 885 __le16 index; 886 __le16 length; 887 u8 cmd; 888 u8 cls; 889 u8 _res; 890 u8 status_flags; 891 }; 892 893 #define ENETC_CLK 400000000ULL 894 static inline u32 enetc_cycles_to_usecs(u32 cycles) 895 { 896 return (u32)div_u64(cycles * 1000000ULL, ENETC_CLK); 897 } 898 899 static inline u32 enetc_usecs_to_cycles(u32 usecs) 900 { 901 return (u32)div_u64(usecs * ENETC_CLK, 1000000ULL); 902 } 903 904 /* port time gating control register */ 905 #define ENETC_QBV_PTGCR_OFFSET 0x11a00 906 #define ENETC_QBV_TGE BIT(31) 907 #define ENETC_QBV_TGPE BIT(30) 908 909 /* Port time gating capability register */ 910 #define ENETC_QBV_PTGCAPR_OFFSET 0x11a08 911 #define ENETC_QBV_MAX_GCL_LEN_MASK GENMASK(15, 0) 912 913 /* Port time specific departure */ 914 #define ENETC_PTCTSDR(n) (0x1210 + 4 * (n)) 915 #define ENETC_TSDE BIT(31) 916 917 /* PSFP setting */ 918 #define ENETC_PPSFPMR 0x11b00 919 #define ENETC_PPSFPMR_PSFPEN BIT(0) 920 #define ENETC_PPSFPMR_VS BIT(1) 921 #define ENETC_PPSFPMR_PVC BIT(2) 922 #define ENETC_PPSFPMR_PVZC BIT(3) 923