1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ 2 /* Copyright 2017-2019 NXP */ 3 4 #include <linux/bitops.h> 5 6 #define ENETC_MM_VERIFY_SLEEP_US USEC_PER_MSEC 7 #define ENETC_MM_VERIFY_RETRIES 3 8 9 #define ENETC_NUM_TC 8 10 11 /* ENETC device IDs */ 12 #define ENETC_DEV_ID_PF 0xe100 13 #define ENETC_DEV_ID_VF 0xef00 14 #define ENETC_DEV_ID_PTP 0xee02 15 16 /* ENETC register block BAR */ 17 #define ENETC_BAR_REGS 0 18 19 /** SI regs, offset: 0h */ 20 #define ENETC_SIMR 0 21 #define ENETC_SIMR_EN BIT(31) 22 #define ENETC_SIMR_RSSE BIT(0) 23 #define ENETC_SICTR0 0x18 24 #define ENETC_SICTR1 0x1c 25 #define ENETC_SIPCAPR0 0x20 26 #define ENETC_SIPCAPR0_RSS BIT(8) 27 #define ENETC_SIPCAPR0_RFS BIT(2) 28 #define ENETC_SIPCAPR0_LSO BIT(1) 29 #define ENETC_SIPCAPR1 0x24 30 #define ENETC_SITGTGR 0x30 31 #define ENETC_SIRBGCR 0x38 32 /* cache attribute registers for transactions initiated by ENETC */ 33 #define ENETC_SICAR0 0x40 34 #define ENETC_SICAR1 0x44 35 #define ENETC_SICAR2 0x48 36 /* rd snoop, no alloc 37 * wr snoop, no alloc, partial cache line update for BDs and full cache line 38 * update for data 39 */ 40 #define ENETC_SICAR_RD_COHERENT 0x2b2b0000 41 #define ENETC_SICAR_WR_COHERENT 0x00006727 42 #define ENETC_SICAR_MSI 0x00300030 /* rd/wr device, no snoop, no alloc */ 43 44 #define ENETC_SIPMAR0 0x80 45 #define ENETC_SIPMAR1 0x84 46 47 /* VF-PF Message passing */ 48 #define ENETC_DEFAULT_MSG_SIZE 1024 /* and max size */ 49 /* msg size encoding: default and max msg value of 1024B encoded as 0 */ 50 static inline u32 enetc_vsi_set_msize(u32 size) 51 { 52 return size < ENETC_DEFAULT_MSG_SIZE ? size >> 5 : 0; 53 } 54 55 #define ENETC_PSIMSGRR 0x204 56 #define ENETC_PSIMSGRR_MR_MASK GENMASK(2, 1) 57 #define ENETC_PSIMSGRR_MR(n) BIT((n) + 1) /* n = VSI index */ 58 #define ENETC_PSIVMSGRCVAR0(n) (0x210 + (n) * 0x8) /* n = VSI index */ 59 #define ENETC_PSIVMSGRCVAR1(n) (0x214 + (n) * 0x8) 60 61 #define ENETC_VSIMSGSR 0x204 /* RO */ 62 #define ENETC_VSIMSGSR_MB BIT(0) 63 #define ENETC_VSIMSGSR_MS BIT(1) 64 #define ENETC_VSIMSGSNDAR0 0x210 65 #define ENETC_VSIMSGSNDAR1 0x214 66 67 #define ENETC_SIMSGSR_SET_MC(val) ((val) << 16) 68 #define ENETC_SIMSGSR_GET_MC(val) ((val) >> 16) 69 70 /* SI statistics */ 71 #define ENETC_SIROCT 0x300 72 #define ENETC_SIRFRM 0x308 73 #define ENETC_SIRUCA 0x310 74 #define ENETC_SIRMCA 0x318 75 #define ENETC_SITOCT 0x320 76 #define ENETC_SITFRM 0x328 77 #define ENETC_SITUCA 0x330 78 #define ENETC_SITMCA 0x338 79 #define ENETC_RBDCR(n) (0x8180 + (n) * 0x200) 80 81 /* Control BDR regs */ 82 #define ENETC_SICBDRMR 0x800 83 #define ENETC_SICBDRSR 0x804 /* RO */ 84 #define ENETC_SICBDRBAR0 0x810 85 #define ENETC_SICBDRBAR1 0x814 86 #define ENETC_SICBDRPIR 0x818 87 #define ENETC_SICBDRCIR 0x81c 88 #define ENETC_SICBDRLENR 0x820 89 90 #define ENETC_SICAPR0 0x900 91 #define ENETC_SICAPR1 0x904 92 93 #define ENETC_PSIIER 0xa00 94 #define ENETC_PSIIER_MR_MASK GENMASK(2, 1) 95 #define ENETC_PSIIDR 0xa08 96 #define ENETC_SITXIDR 0xa18 97 #define ENETC_SIRXIDR 0xa28 98 #define ENETC_SIMSIVR 0xa30 99 100 #define ENETC_SIMSITRV(n) (0xB00 + (n) * 0x4) 101 #define ENETC_SIMSIRRV(n) (0xB80 + (n) * 0x4) 102 103 #define ENETC_SIUEFDCR 0xe28 104 105 #define ENETC_SIRFSCAPR 0x1200 106 #define ENETC_SIRFSCAPR_GET_NUM_RFS(val) ((val) & 0x7f) 107 #define ENETC_SIRSSCAPR 0x1600 108 #define ENETC_SIRSSCAPR_GET_NUM_RSS(val) (BIT((val) & 0xf) * 32) 109 110 /** SI BDR sub-blocks, n = 0..7 */ 111 enum enetc_bdr_type {TX, RX}; 112 #define ENETC_BDR_OFF(i) ((i) * 0x200) 113 #define ENETC_BDR(t, i, r) (0x8000 + (t) * 0x100 + ENETC_BDR_OFF(i) + (r)) 114 /* RX BDR reg offsets */ 115 #define ENETC_RBMR 0 116 #define ENETC_RBMR_BDS BIT(2) 117 #define ENETC_RBMR_CM BIT(4) 118 #define ENETC_RBMR_VTE BIT(5) 119 #define ENETC_RBMR_EN BIT(31) 120 #define ENETC_RBSR 0x4 121 #define ENETC_RBBSR 0x8 122 #define ENETC_RBCIR 0xc 123 #define ENETC_RBBAR0 0x10 124 #define ENETC_RBBAR1 0x14 125 #define ENETC_RBPIR 0x18 126 #define ENETC_RBLENR 0x20 127 #define ENETC_RBIER 0xa0 128 #define ENETC_RBIER_RXTIE BIT(0) 129 #define ENETC_RBIDR 0xa4 130 #define ENETC_RBICR0 0xa8 131 #define ENETC_RBICR0_ICEN BIT(31) 132 #define ENETC_RBICR0_ICPT_MASK 0x1ff 133 #define ENETC_RBICR0_SET_ICPT(n) ((n) & ENETC_RBICR0_ICPT_MASK) 134 #define ENETC_RBICR1 0xac 135 136 /* TX BDR reg offsets */ 137 #define ENETC_TBMR 0 138 #define ENETC_TBSR_BUSY BIT(0) 139 #define ENETC_TBMR_VIH BIT(9) 140 #define ENETC_TBMR_PRIO_MASK GENMASK(2, 0) 141 #define ENETC_TBMR_SET_PRIO(val) ((val) & ENETC_TBMR_PRIO_MASK) 142 #define ENETC_TBMR_EN BIT(31) 143 #define ENETC_TBSR 0x4 144 #define ENETC_TBBAR0 0x10 145 #define ENETC_TBBAR1 0x14 146 #define ENETC_TBPIR 0x18 147 #define ENETC_TBCIR 0x1c 148 #define ENETC_TBCIR_IDX_MASK 0xffff 149 #define ENETC_TBLENR 0x20 150 #define ENETC_TBIER 0xa0 151 #define ENETC_TBIER_TXTIE BIT(0) 152 #define ENETC_TBIDR 0xa4 153 #define ENETC_TBICR0 0xa8 154 #define ENETC_TBICR0_ICEN BIT(31) 155 #define ENETC_TBICR0_ICPT_MASK 0xf 156 #define ENETC_TBICR0_SET_ICPT(n) ((ilog2(n) + 1) & ENETC_TBICR0_ICPT_MASK) 157 #define ENETC_TBICR1 0xac 158 159 #define ENETC_RTBLENR_LEN(n) ((n) & ~0x7) 160 161 /* Port regs, offset: 1_0000h */ 162 #define ENETC_PORT_BASE 0x10000 163 #define ENETC_PMR 0x0000 164 #define ENETC_PMR_EN GENMASK(18, 16) 165 #define ENETC_PMR_PSPEED_MASK GENMASK(11, 8) 166 #define ENETC_PMR_PSPEED_10M 0 167 #define ENETC_PMR_PSPEED_100M BIT(8) 168 #define ENETC_PMR_PSPEED_1000M BIT(9) 169 #define ENETC_PMR_PSPEED_2500M BIT(10) 170 #define ENETC_PSR 0x0004 /* RO */ 171 #define ENETC_PSIPMR 0x0018 172 #define ENETC_PSIPMR_SET_UP(n) BIT(n) /* n = SI index */ 173 #define ENETC_PSIPMR_SET_MP(n) BIT((n) + 16) 174 #define ENETC_PSIPVMR 0x001c 175 #define ENETC_VLAN_PROMISC_MAP_ALL 0x7 176 #define ENETC_PSIPVMR_SET_VP(simap) ((simap) & 0x7) 177 #define ENETC_PSIPVMR_SET_VUTA(simap) (((simap) & 0x7) << 16) 178 #define ENETC_PSIPMAR0(n) (0x0100 + (n) * 0x8) /* n = SI index */ 179 #define ENETC_PSIPMAR1(n) (0x0104 + (n) * 0x8) 180 #define ENETC_PVCLCTR 0x0208 181 #define ENETC_PCVLANR1 0x0210 182 #define ENETC_PCVLANR2 0x0214 183 #define ENETC_VLAN_TYPE_C BIT(0) 184 #define ENETC_VLAN_TYPE_S BIT(1) 185 #define ENETC_PVCLCTR_OVTPIDL(bmp) ((bmp) & 0xff) /* VLAN_TYPE */ 186 #define ENETC_PSIVLANR(n) (0x0240 + (n) * 4) /* n = SI index */ 187 #define ENETC_PSIVLAN_EN BIT(31) 188 #define ENETC_PSIVLAN_SET_QOS(val) ((u32)(val) << 12) 189 #define ENETC_PPAUONTR 0x0410 190 #define ENETC_PPAUOFFTR 0x0414 191 #define ENETC_PTXMBAR 0x0608 192 #define ENETC_PCAPR0 0x0900 193 #define ENETC_PCAPR0_RXBDR(val) ((val) >> 24) 194 #define ENETC_PCAPR0_TXBDR(val) (((val) >> 16) & 0xff) 195 #define ENETC_PCAPR0_PSFP BIT(9) 196 #define ENETC_PCAPR0_QBV BIT(4) 197 #define ENETC_PCAPR0_QBU BIT(3) 198 #define ENETC_PCAPR1 0x0904 199 #define ENETC_PSICFGR0(n) (0x0940 + (n) * 0xc) /* n = SI index */ 200 #define ENETC_PSICFGR0_SET_TXBDR(val) ((val) & 0xff) 201 #define ENETC_PSICFGR0_SET_RXBDR(val) (((val) & 0xff) << 16) 202 #define ENETC_PSICFGR0_VTE BIT(12) 203 #define ENETC_PSICFGR0_SIVIE BIT(14) 204 #define ENETC_PSICFGR0_ASE BIT(15) 205 #define ENETC_PSICFGR0_SIVC(bmp) (((bmp) & 0xff) << 24) /* VLAN_TYPE */ 206 207 #define ENETC_PTCCBSR0(n) (0x1110 + (n) * 8) /* n = 0 to 7*/ 208 #define ENETC_CBSE BIT(31) 209 #define ENETC_CBS_BW_MASK GENMASK(6, 0) 210 #define ENETC_PTCCBSR1(n) (0x1114 + (n) * 8) /* n = 0 to 7*/ 211 #define ENETC_RSSHASH_KEY_SIZE 40 212 #define ENETC_PRSSCAPR 0x1404 213 #define ENETC_PRSSCAPR_GET_NUM_RSS(val) (BIT((val) & 0xf) * 32) 214 #define ENETC_PRSSK(n) (0x1410 + (n) * 4) /* n = [0..9] */ 215 #define ENETC_PSIVLANFMR 0x1700 216 #define ENETC_PSIVLANFMR_VS BIT(0) 217 #define ENETC_PRFSMR 0x1800 218 #define ENETC_PRFSMR_RFSE BIT(31) 219 #define ENETC_PRFSCAPR 0x1804 220 #define ENETC_PRFSCAPR_GET_NUM_RFS(val) ((((val) & 0xf) + 1) * 16) 221 #define ENETC_PSIRFSCFGR(n) (0x1814 + (n) * 4) /* n = SI index */ 222 #define ENETC_PFPMR 0x1900 223 #define ENETC_PFPMR_PMACE BIT(1) 224 #define ENETC_EMDIO_BASE 0x1c00 225 #define ENETC_PSIUMHFR0(n, err) (((err) ? 0x1d08 : 0x1d00) + (n) * 0x10) 226 #define ENETC_PSIUMHFR1(n) (0x1d04 + (n) * 0x10) 227 #define ENETC_PSIMMHFR0(n, err) (((err) ? 0x1d00 : 0x1d08) + (n) * 0x10) 228 #define ENETC_PSIMMHFR1(n) (0x1d0c + (n) * 0x10) 229 #define ENETC_PSIVHFR0(n) (0x1e00 + (n) * 8) /* n = SI index */ 230 #define ENETC_PSIVHFR1(n) (0x1e04 + (n) * 8) /* n = SI index */ 231 #define ENETC_MMCSR 0x1f00 232 #define ENETC_MMCSR_LINK_FAIL BIT(31) 233 #define ENETC_MMCSR_VT_MASK GENMASK(29, 23) /* Verify Time */ 234 #define ENETC_MMCSR_VT(x) (((x) << 23) & ENETC_MMCSR_VT_MASK) 235 #define ENETC_MMCSR_GET_VT(x) (((x) & ENETC_MMCSR_VT_MASK) >> 23) 236 #define ENETC_MMCSR_TXSTS_MASK GENMASK(22, 21) /* Merge Status */ 237 #define ENETC_MMCSR_GET_TXSTS(x) (((x) & ENETC_MMCSR_TXSTS_MASK) >> 21) 238 #define ENETC_MMCSR_VSTS_MASK GENMASK(20, 18) /* Verify Status */ 239 #define ENETC_MMCSR_GET_VSTS(x) (((x) & ENETC_MMCSR_VSTS_MASK) >> 18) 240 #define ENETC_MMCSR_VDIS BIT(17) /* Verify Disabled */ 241 #define ENETC_MMCSR_ME BIT(16) /* Merge Enabled */ 242 #define ENETC_MMCSR_RAFS_MASK GENMASK(9, 8) /* Remote Additional Fragment Size */ 243 #define ENETC_MMCSR_RAFS(x) (((x) << 8) & ENETC_MMCSR_RAFS_MASK) 244 #define ENETC_MMCSR_GET_RAFS(x) (((x) & ENETC_MMCSR_RAFS_MASK) >> 8) 245 #define ENETC_MMCSR_LAFS_MASK GENMASK(4, 3) /* Local Additional Fragment Size */ 246 #define ENETC_MMCSR_GET_LAFS(x) (((x) & ENETC_MMCSR_LAFS_MASK) >> 3) 247 #define ENETC_MMCSR_LPA BIT(2) /* Local Preemption Active */ 248 #define ENETC_MMCSR_LPE BIT(1) /* Local Preemption Enabled */ 249 #define ENETC_MMCSR_LPS BIT(0) /* Local Preemption Supported */ 250 #define ENETC_MMFAECR 0x1f08 251 #define ENETC_MMFSECR 0x1f0c 252 #define ENETC_MMFAOCR 0x1f10 253 #define ENETC_MMFCRXR 0x1f14 254 #define ENETC_MMFCTXR 0x1f18 255 #define ENETC_MMHCR 0x1f1c 256 #define ENETC_PTCMSDUR(n) (0x2020 + (n) * 4) /* n = TC index [0..7] */ 257 258 #define ENETC_PMAC_OFFSET 0x1000 259 260 #define ENETC_PM0_CMD_CFG 0x8008 261 #define ENETC_PM0_TX_EN BIT(0) 262 #define ENETC_PM0_RX_EN BIT(1) 263 #define ENETC_PM0_PROMISC BIT(4) 264 #define ENETC_PM0_PAUSE_IGN BIT(8) 265 #define ENETC_PM0_CMD_XGLP BIT(10) 266 #define ENETC_PM0_CMD_TXP BIT(11) 267 #define ENETC_PM0_CMD_PHY_TX_EN BIT(15) 268 #define ENETC_PM0_CMD_SFD BIT(21) 269 #define ENETC_PM0_MAXFRM 0x8014 270 #define ENETC_SET_TX_MTU(val) ((val) << 16) 271 #define ENETC_SET_MAXFRM(val) ((val) & 0xffff) 272 #define ENETC_PM0_RX_FIFO 0x801c 273 #define ENETC_PM0_RX_FIFO_VAL 1 274 275 #define ENETC_PM_IMDIO_BASE 0x8030 276 277 #define ENETC_PM0_PAUSE_QUANTA 0x8054 278 #define ENETC_PM0_PAUSE_THRESH 0x8064 279 280 #define ENETC_PM0_SINGLE_STEP 0x80c0 281 #define ENETC_PM0_SINGLE_STEP_CH BIT(7) 282 #define ENETC_PM0_SINGLE_STEP_EN BIT(31) 283 #define ENETC_SET_SINGLE_STEP_OFFSET(v) (((v) & 0xff) << 8) 284 285 #define ENETC_PM0_IF_MODE 0x8300 286 #define ENETC_PM0_IFM_RG BIT(2) 287 #define ENETC_PM0_IFM_RLP (BIT(5) | BIT(11)) 288 #define ENETC_PM0_IFM_EN_AUTO BIT(15) 289 #define ENETC_PM0_IFM_SSP_MASK GENMASK(14, 13) 290 #define ENETC_PM0_IFM_SSP_1000 (2 << 13) 291 #define ENETC_PM0_IFM_SSP_100 (0 << 13) 292 #define ENETC_PM0_IFM_SSP_10 (1 << 13) 293 #define ENETC_PM0_IFM_FULL_DPX BIT(12) 294 #define ENETC_PM0_IFM_IFMODE_MASK GENMASK(1, 0) 295 #define ENETC_PM0_IFM_IFMODE_XGMII 0 296 #define ENETC_PM0_IFM_IFMODE_GMII 2 297 #define ENETC_PSIDCAPR 0x1b08 298 #define ENETC_PSIDCAPR_MSK GENMASK(15, 0) 299 #define ENETC_PSFCAPR 0x1b18 300 #define ENETC_PSFCAPR_MSK GENMASK(15, 0) 301 #define ENETC_PSGCAPR 0x1b28 302 #define ENETC_PSGCAPR_GCL_MSK GENMASK(18, 16) 303 #define ENETC_PSGCAPR_SGIT_MSK GENMASK(15, 0) 304 #define ENETC_PFMCAPR 0x1b38 305 #define ENETC_PFMCAPR_MSK GENMASK(15, 0) 306 307 /* Port MAC counters: Port MAC 0 corresponds to the eMAC and 308 * Port MAC 1 to the pMAC. 309 */ 310 #define ENETC_PM_REOCT(mac) (0x8100 + ENETC_PMAC_OFFSET * (mac)) 311 #define ENETC_PM_RALN(mac) (0x8110 + ENETC_PMAC_OFFSET * (mac)) 312 #define ENETC_PM_RXPF(mac) (0x8118 + ENETC_PMAC_OFFSET * (mac)) 313 #define ENETC_PM_RFRM(mac) (0x8120 + ENETC_PMAC_OFFSET * (mac)) 314 #define ENETC_PM_RFCS(mac) (0x8128 + ENETC_PMAC_OFFSET * (mac)) 315 #define ENETC_PM_RVLAN(mac) (0x8130 + ENETC_PMAC_OFFSET * (mac)) 316 #define ENETC_PM_RERR(mac) (0x8138 + ENETC_PMAC_OFFSET * (mac)) 317 #define ENETC_PM_RUCA(mac) (0x8140 + ENETC_PMAC_OFFSET * (mac)) 318 #define ENETC_PM_RMCA(mac) (0x8148 + ENETC_PMAC_OFFSET * (mac)) 319 #define ENETC_PM_RBCA(mac) (0x8150 + ENETC_PMAC_OFFSET * (mac)) 320 #define ENETC_PM_RDRP(mac) (0x8158 + ENETC_PMAC_OFFSET * (mac)) 321 #define ENETC_PM_RPKT(mac) (0x8160 + ENETC_PMAC_OFFSET * (mac)) 322 #define ENETC_PM_RUND(mac) (0x8168 + ENETC_PMAC_OFFSET * (mac)) 323 #define ENETC_PM_R64(mac) (0x8170 + ENETC_PMAC_OFFSET * (mac)) 324 #define ENETC_PM_R127(mac) (0x8178 + ENETC_PMAC_OFFSET * (mac)) 325 #define ENETC_PM_R255(mac) (0x8180 + ENETC_PMAC_OFFSET * (mac)) 326 #define ENETC_PM_R511(mac) (0x8188 + ENETC_PMAC_OFFSET * (mac)) 327 #define ENETC_PM_R1023(mac) (0x8190 + ENETC_PMAC_OFFSET * (mac)) 328 #define ENETC_PM_R1522(mac) (0x8198 + ENETC_PMAC_OFFSET * (mac)) 329 #define ENETC_PM_R1523X(mac) (0x81A0 + ENETC_PMAC_OFFSET * (mac)) 330 #define ENETC_PM_ROVR(mac) (0x81A8 + ENETC_PMAC_OFFSET * (mac)) 331 #define ENETC_PM_RJBR(mac) (0x81B0 + ENETC_PMAC_OFFSET * (mac)) 332 #define ENETC_PM_RFRG(mac) (0x81B8 + ENETC_PMAC_OFFSET * (mac)) 333 #define ENETC_PM_RCNP(mac) (0x81C0 + ENETC_PMAC_OFFSET * (mac)) 334 #define ENETC_PM_RDRNTP(mac) (0x81C8 + ENETC_PMAC_OFFSET * (mac)) 335 #define ENETC_PM_TEOCT(mac) (0x8200 + ENETC_PMAC_OFFSET * (mac)) 336 #define ENETC_PM_TOCT(mac) (0x8208 + ENETC_PMAC_OFFSET * (mac)) 337 #define ENETC_PM_TCRSE(mac) (0x8210 + ENETC_PMAC_OFFSET * (mac)) 338 #define ENETC_PM_TXPF(mac) (0x8218 + ENETC_PMAC_OFFSET * (mac)) 339 #define ENETC_PM_TFRM(mac) (0x8220 + ENETC_PMAC_OFFSET * (mac)) 340 #define ENETC_PM_TFCS(mac) (0x8228 + ENETC_PMAC_OFFSET * (mac)) 341 #define ENETC_PM_TVLAN(mac) (0x8230 + ENETC_PMAC_OFFSET * (mac)) 342 #define ENETC_PM_TERR(mac) (0x8238 + ENETC_PMAC_OFFSET * (mac)) 343 #define ENETC_PM_TUCA(mac) (0x8240 + ENETC_PMAC_OFFSET * (mac)) 344 #define ENETC_PM_TMCA(mac) (0x8248 + ENETC_PMAC_OFFSET * (mac)) 345 #define ENETC_PM_TBCA(mac) (0x8250 + ENETC_PMAC_OFFSET * (mac)) 346 #define ENETC_PM_TPKT(mac) (0x8260 + ENETC_PMAC_OFFSET * (mac)) 347 #define ENETC_PM_TUND(mac) (0x8268 + ENETC_PMAC_OFFSET * (mac)) 348 #define ENETC_PM_T64(mac) (0x8270 + ENETC_PMAC_OFFSET * (mac)) 349 #define ENETC_PM_T127(mac) (0x8278 + ENETC_PMAC_OFFSET * (mac)) 350 #define ENETC_PM_T255(mac) (0x8280 + ENETC_PMAC_OFFSET * (mac)) 351 #define ENETC_PM_T511(mac) (0x8288 + ENETC_PMAC_OFFSET * (mac)) 352 #define ENETC_PM_T1023(mac) (0x8290 + ENETC_PMAC_OFFSET * (mac)) 353 #define ENETC_PM_T1522(mac) (0x8298 + ENETC_PMAC_OFFSET * (mac)) 354 #define ENETC_PM_T1523X(mac) (0x82A0 + ENETC_PMAC_OFFSET * (mac)) 355 #define ENETC_PM_TCNP(mac) (0x82C0 + ENETC_PMAC_OFFSET * (mac)) 356 #define ENETC_PM_TDFR(mac) (0x82D0 + ENETC_PMAC_OFFSET * (mac)) 357 #define ENETC_PM_TMCOL(mac) (0x82D8 + ENETC_PMAC_OFFSET * (mac)) 358 #define ENETC_PM_TSCOL(mac) (0x82E0 + ENETC_PMAC_OFFSET * (mac)) 359 #define ENETC_PM_TLCOL(mac) (0x82E8 + ENETC_PMAC_OFFSET * (mac)) 360 #define ENETC_PM_TECOL(mac) (0x82F0 + ENETC_PMAC_OFFSET * (mac)) 361 362 /* Port counters */ 363 #define ENETC_PICDR(n) (0x0700 + (n) * 8) /* n = [0..3] */ 364 #define ENETC_PBFDSIR 0x0810 365 #define ENETC_PFDMSAPR 0x0814 366 #define ENETC_UFDMF 0x1680 367 #define ENETC_MFDMF 0x1684 368 #define ENETC_PUFDVFR 0x1780 369 #define ENETC_PMFDVFR 0x1784 370 #define ENETC_PBFDVFR 0x1788 371 372 /** Global regs, offset: 2_0000h */ 373 #define ENETC_GLOBAL_BASE 0x20000 374 #define ENETC_G_EIPBRR0 0x0bf8 375 #define EIPBRR0_REVISION GENMASK(15, 0) 376 #define ENETC_REV_1_0 0x0100 377 #define ENETC_REV_4_1 0X0401 378 379 #define ENETC_G_EIPBRR1 0x0bfc 380 #define ENETC_G_EPFBLPR(n) (0xd00 + 4 * (n)) 381 #define ENETC_G_EPFBLPR1_XGMII 0x80000000 382 383 /* PCI device info */ 384 struct enetc_hw { 385 /* SI registers, used by all PCI functions */ 386 void __iomem *reg; 387 /* Port registers, PF only */ 388 void __iomem *port; 389 /* IP global registers, PF only */ 390 void __iomem *global; 391 }; 392 393 /* ENETC register accessors */ 394 395 /* MDIO issue workaround (on LS1028A) - 396 * Due to a hardware issue, an access to MDIO registers 397 * that is concurrent with other ENETC register accesses 398 * may lead to the MDIO access being dropped or corrupted. 399 * To protect the MDIO accesses a readers-writers locking 400 * scheme is used, where the MDIO register accesses are 401 * protected by write locks to insure exclusivity, while 402 * the remaining ENETC registers are accessed under read 403 * locks since they only compete with MDIO accesses. 404 */ 405 extern rwlock_t enetc_mdio_lock; 406 407 DECLARE_STATIC_KEY_FALSE(enetc_has_err050089); 408 409 /* use this locking primitive only on the fast datapath to 410 * group together multiple non-MDIO register accesses to 411 * minimize the overhead of the lock 412 */ 413 static inline void enetc_lock_mdio(void) 414 { 415 if (static_branch_unlikely(&enetc_has_err050089)) 416 read_lock(&enetc_mdio_lock); 417 } 418 419 static inline void enetc_unlock_mdio(void) 420 { 421 if (static_branch_unlikely(&enetc_has_err050089)) 422 read_unlock(&enetc_mdio_lock); 423 } 424 425 /* use these accessors only on the fast datapath under 426 * the enetc_lock_mdio() locking primitive to minimize 427 * the overhead of the lock 428 */ 429 static inline u32 enetc_rd_reg_hot(void __iomem *reg) 430 { 431 if (static_branch_unlikely(&enetc_has_err050089)) 432 lockdep_assert_held(&enetc_mdio_lock); 433 434 return ioread32(reg); 435 } 436 437 static inline void enetc_wr_reg_hot(void __iomem *reg, u32 val) 438 { 439 if (static_branch_unlikely(&enetc_has_err050089)) 440 lockdep_assert_held(&enetc_mdio_lock); 441 442 iowrite32(val, reg); 443 } 444 445 /* internal helpers for the MDIO w/a */ 446 static inline u32 _enetc_rd_reg_wa(void __iomem *reg) 447 { 448 u32 val; 449 450 enetc_lock_mdio(); 451 val = ioread32(reg); 452 enetc_unlock_mdio(); 453 454 return val; 455 } 456 457 static inline void _enetc_wr_reg_wa(void __iomem *reg, u32 val) 458 { 459 enetc_lock_mdio(); 460 iowrite32(val, reg); 461 enetc_unlock_mdio(); 462 } 463 464 static inline u32 _enetc_rd_mdio_reg_wa(void __iomem *reg) 465 { 466 unsigned long flags; 467 u32 val; 468 469 if (static_branch_unlikely(&enetc_has_err050089)) { 470 write_lock_irqsave(&enetc_mdio_lock, flags); 471 val = ioread32(reg); 472 write_unlock_irqrestore(&enetc_mdio_lock, flags); 473 } else { 474 val = ioread32(reg); 475 } 476 477 return val; 478 } 479 480 static inline void _enetc_wr_mdio_reg_wa(void __iomem *reg, u32 val) 481 { 482 unsigned long flags; 483 484 if (static_branch_unlikely(&enetc_has_err050089)) { 485 write_lock_irqsave(&enetc_mdio_lock, flags); 486 iowrite32(val, reg); 487 write_unlock_irqrestore(&enetc_mdio_lock, flags); 488 } else { 489 iowrite32(val, reg); 490 } 491 } 492 493 #ifdef ioread64 494 static inline u64 _enetc_rd_reg64(void __iomem *reg) 495 { 496 return ioread64(reg); 497 } 498 #else 499 /* using this to read out stats on 32b systems */ 500 static inline u64 _enetc_rd_reg64(void __iomem *reg) 501 { 502 u32 low, high, tmp; 503 504 do { 505 high = ioread32(reg + 4); 506 low = ioread32(reg); 507 tmp = ioread32(reg + 4); 508 } while (high != tmp); 509 510 return le64_to_cpu((__le64)high << 32 | low); 511 } 512 #endif 513 514 static inline u64 _enetc_rd_reg64_wa(void __iomem *reg) 515 { 516 u64 val; 517 518 enetc_lock_mdio(); 519 val = _enetc_rd_reg64(reg); 520 enetc_unlock_mdio(); 521 522 return val; 523 } 524 525 /* general register accessors */ 526 #define enetc_rd_reg(reg) _enetc_rd_reg_wa((reg)) 527 #define enetc_wr_reg(reg, val) _enetc_wr_reg_wa((reg), (val)) 528 #define enetc_rd(hw, off) enetc_rd_reg((hw)->reg + (off)) 529 #define enetc_wr(hw, off, val) enetc_wr_reg((hw)->reg + (off), val) 530 #define enetc_rd_hot(hw, off) enetc_rd_reg_hot((hw)->reg + (off)) 531 #define enetc_wr_hot(hw, off, val) enetc_wr_reg_hot((hw)->reg + (off), val) 532 #define enetc_rd64(hw, off) _enetc_rd_reg64_wa((hw)->reg + (off)) 533 /* port register accessors - PF only */ 534 #define enetc_port_rd(hw, off) enetc_rd_reg((hw)->port + (off)) 535 #define enetc_port_wr(hw, off, val) enetc_wr_reg((hw)->port + (off), val) 536 #define enetc_port_rd_mdio(hw, off) _enetc_rd_mdio_reg_wa((hw)->port + (off)) 537 #define enetc_port_wr_mdio(hw, off, val) _enetc_wr_mdio_reg_wa(\ 538 (hw)->port + (off), val) 539 /* global register accessors - PF only */ 540 #define enetc_global_rd(hw, off) enetc_rd_reg((hw)->global + (off)) 541 #define enetc_global_wr(hw, off, val) enetc_wr_reg((hw)->global + (off), val) 542 /* BDR register accessors, see ENETC_BDR() */ 543 #define enetc_bdr_rd(hw, t, n, off) \ 544 enetc_rd(hw, ENETC_BDR(t, n, off)) 545 #define enetc_bdr_wr(hw, t, n, off, val) \ 546 enetc_wr(hw, ENETC_BDR(t, n, off), val) 547 #define enetc_txbdr_rd(hw, n, off) enetc_bdr_rd(hw, TX, n, off) 548 #define enetc_rxbdr_rd(hw, n, off) enetc_bdr_rd(hw, RX, n, off) 549 #define enetc_txbdr_wr(hw, n, off, val) \ 550 enetc_bdr_wr(hw, TX, n, off, val) 551 #define enetc_rxbdr_wr(hw, n, off, val) \ 552 enetc_bdr_wr(hw, RX, n, off, val) 553 554 /* Buffer Descriptors (BD) */ 555 union enetc_tx_bd { 556 struct { 557 __le64 addr; 558 union { 559 __le16 buf_len; 560 __le16 hdr_len; /* For LSO, ENETC 4.1 and later */ 561 }; 562 __le16 frm_len; 563 union { 564 struct { 565 u8 l3_aux0; 566 #define ENETC_TX_BD_L3_START GENMASK(6, 0) 567 #define ENETC_TX_BD_IPCS BIT(7) 568 u8 l3_aux1; 569 #define ENETC_TX_BD_L3_HDR_LEN GENMASK(6, 0) 570 #define ENETC_TX_BD_L3T BIT(7) 571 u8 l4_aux; 572 #define ENETC_TX_BD_L4T GENMASK(7, 5) 573 #define ENETC_TXBD_L4T_UDP 1 574 #define ENETC_TXBD_L4T_TCP 2 575 u8 flags; 576 }; /* default layout */ 577 __le32 txstart; 578 __le32 lstatus; 579 }; 580 }; 581 struct { 582 __le32 tstamp; 583 __le16 tpid; 584 __le16 vid; 585 __le16 lso_sg_size; /* For ENETC 4.1 and later */ 586 __le16 frm_len_ext; /* For ENETC 4.1 and later */ 587 u8 reserved[2]; 588 u8 e_flags; 589 u8 flags; 590 } ext; /* Tx BD extension */ 591 struct { 592 __le32 tstamp; 593 u8 reserved[8]; 594 __le16 lso_err_count; /* For ENETC 4.1 and later */ 595 u8 status; 596 u8 flags; 597 } wb; /* writeback descriptor */ 598 }; 599 600 enum enetc_txbd_flags { 601 ENETC_TXBD_FLAGS_L4CS = BIT(0), /* For ENETC 4.1 and later */ 602 ENETC_TXBD_FLAGS_TSE = BIT(1), 603 ENETC_TXBD_FLAGS_LSO = BIT(1), /* For ENETC 4.1 and later */ 604 ENETC_TXBD_FLAGS_W = BIT(2), 605 ENETC_TXBD_FLAGS_CSUM_LSO = BIT(3), /* For ENETC 4.1 and later */ 606 ENETC_TXBD_FLAGS_TXSTART = BIT(4), 607 ENETC_TXBD_FLAGS_EX = BIT(6), 608 ENETC_TXBD_FLAGS_F = BIT(7) 609 }; 610 #define ENETC_TXBD_STATS_WIN BIT(7) 611 #define ENETC_TXBD_TXSTART_MASK GENMASK(24, 0) 612 #define ENETC_TXBD_FLAGS_OFFSET 24 613 614 static inline __le32 enetc_txbd_set_tx_start(u64 tx_start, u8 flags) 615 { 616 u32 temp; 617 618 temp = (tx_start >> 5 & ENETC_TXBD_TXSTART_MASK) | 619 (flags << ENETC_TXBD_FLAGS_OFFSET); 620 621 return cpu_to_le32(temp); 622 } 623 624 static inline void enetc_clear_tx_bd(union enetc_tx_bd *txbd) 625 { 626 memset(txbd, 0, sizeof(*txbd)); 627 } 628 629 /* Extension flags */ 630 #define ENETC_TXBD_E_FLAGS_VLAN_INS BIT(0) 631 #define ENETC_TXBD_E_FLAGS_ONE_STEP_PTP BIT(1) 632 #define ENETC_TXBD_E_FLAGS_TWO_STEP_PTP BIT(2) 633 634 union enetc_rx_bd { 635 struct { 636 __le64 addr; 637 u8 reserved[8]; 638 } w; 639 struct { 640 __le16 inet_csum; 641 __le16 parse_summary; 642 __le32 rss_hash; 643 __le16 buf_len; 644 __le16 vlan_opt; 645 union { 646 struct { 647 __le16 flags; 648 __le16 error; 649 }; 650 __le32 lstatus; 651 }; 652 } r; 653 struct { 654 __le32 tstamp; 655 u8 reserved[12]; 656 } ext; 657 }; 658 659 #define ENETC_RXBD_LSTATUS_R BIT(30) 660 #define ENETC_RXBD_LSTATUS_F BIT(31) 661 #define ENETC_RXBD_ERR_MASK 0xff 662 #define ENETC_RXBD_LSTATUS(flags) ((flags) << 16) 663 #define ENETC_RXBD_FLAG_VLAN BIT(9) 664 #define ENETC_RXBD_FLAG_TSTMP BIT(10) 665 #define ENETC_RXBD_FLAG_TPID GENMASK(1, 0) 666 667 #define ENETC_MAC_ADDR_FILT_CNT 8 /* # of supported entries per port */ 668 #define EMETC_MAC_ADDR_FILT_RES 3 /* # of reserved entries at the beginning */ 669 #define ENETC_MAX_NUM_VFS 2 670 671 #define ENETC_CBD_FLAGS_SF BIT(7) /* short format */ 672 #define ENETC_CBD_STATUS_MASK 0xf 673 674 #define ENETC_TPID_8021Q 0 675 676 struct enetc_cmd_rfse { 677 u8 smac_h[6]; 678 u8 smac_m[6]; 679 u8 dmac_h[6]; 680 u8 dmac_m[6]; 681 __be32 sip_h[4]; 682 __be32 sip_m[4]; 683 __be32 dip_h[4]; 684 __be32 dip_m[4]; 685 u16 ethtype_h; 686 u16 ethtype_m; 687 u16 ethtype4_h; 688 u16 ethtype4_m; 689 u16 sport_h; 690 u16 sport_m; 691 u16 dport_h; 692 u16 dport_m; 693 u16 vlan_h; 694 u16 vlan_m; 695 u8 proto_h; 696 u8 proto_m; 697 u16 flags; 698 u16 result; 699 u16 mode; 700 }; 701 702 #define ENETC_RFSE_EN BIT(15) 703 #define ENETC_RFSE_MODE_BD 2 704 705 static inline void enetc_load_primary_mac_addr(struct enetc_hw *hw, 706 struct net_device *ndev) 707 { 708 u8 addr[ETH_ALEN] __aligned(4); 709 710 *(u32 *)addr = __raw_readl(hw->reg + ENETC_SIPMAR0); 711 *(u16 *)(addr + 4) = __raw_readw(hw->reg + ENETC_SIPMAR1); 712 eth_hw_addr_set(ndev, addr); 713 } 714 715 #define ENETC_SI_INT_IDX 0 716 /* base index for Rx/Tx interrupts */ 717 #define ENETC_BDR_INT_BASE_IDX 1 718 719 /* Messaging */ 720 721 /* Command completion status */ 722 enum enetc_msg_cmd_status { 723 ENETC_MSG_CMD_STATUS_OK, 724 ENETC_MSG_CMD_STATUS_FAIL 725 }; 726 727 /* VSI-PSI command message types */ 728 enum enetc_msg_cmd_type { 729 ENETC_MSG_CMD_MNG_MAC = 1, /* manage MAC address */ 730 ENETC_MSG_CMD_MNG_RX_MAC_FILTER,/* manage RX MAC table */ 731 ENETC_MSG_CMD_MNG_RX_VLAN_FILTER /* manage RX VLAN table */ 732 }; 733 734 /* VSI-PSI command action types */ 735 enum enetc_msg_cmd_action_type { 736 ENETC_MSG_CMD_MNG_ADD = 1, 737 ENETC_MSG_CMD_MNG_REMOVE 738 }; 739 740 /* PSI-VSI command header format */ 741 struct enetc_msg_cmd_header { 742 u16 type; /* command class type */ 743 u16 id; /* denotes the specific required action */ 744 }; 745 746 /* Common H/W utility functions */ 747 748 static inline void enetc_bdr_enable_rxvlan(struct enetc_hw *hw, int idx, 749 bool en) 750 { 751 u32 val = enetc_rxbdr_rd(hw, idx, ENETC_RBMR); 752 753 val = (val & ~ENETC_RBMR_VTE) | (en ? ENETC_RBMR_VTE : 0); 754 enetc_rxbdr_wr(hw, idx, ENETC_RBMR, val); 755 } 756 757 static inline void enetc_bdr_enable_txvlan(struct enetc_hw *hw, int idx, 758 bool en) 759 { 760 u32 val = enetc_txbdr_rd(hw, idx, ENETC_TBMR); 761 762 val = (val & ~ENETC_TBMR_VIH) | (en ? ENETC_TBMR_VIH : 0); 763 enetc_txbdr_wr(hw, idx, ENETC_TBMR, val); 764 } 765 766 static inline void enetc_set_bdr_prio(struct enetc_hw *hw, int bdr_idx, 767 int prio) 768 { 769 u32 val = enetc_txbdr_rd(hw, bdr_idx, ENETC_TBMR); 770 771 val &= ~ENETC_TBMR_PRIO_MASK; 772 val |= ENETC_TBMR_SET_PRIO(prio); 773 enetc_txbdr_wr(hw, bdr_idx, ENETC_TBMR, val); 774 } 775 776 enum bdcr_cmd_class { 777 BDCR_CMD_UNSPEC = 0, 778 BDCR_CMD_MAC_FILTER, 779 BDCR_CMD_VLAN_FILTER, 780 BDCR_CMD_RSS, 781 BDCR_CMD_RFS, 782 BDCR_CMD_PORT_GCL, 783 BDCR_CMD_RECV_CLASSIFIER, 784 BDCR_CMD_STREAM_IDENTIFY, 785 BDCR_CMD_STREAM_FILTER, 786 BDCR_CMD_STREAM_GCL, 787 BDCR_CMD_FLOW_METER, 788 __BDCR_CMD_MAX_LEN, 789 BDCR_CMD_MAX_LEN = __BDCR_CMD_MAX_LEN - 1, 790 }; 791 792 /* class 5, command 0 */ 793 struct tgs_gcl_conf { 794 u8 atc; /* init gate value */ 795 u8 res[7]; 796 struct { 797 u8 res1[4]; 798 __le16 acl_len; 799 u8 res2[2]; 800 }; 801 }; 802 803 /* gate control list entry */ 804 struct gce { 805 __le32 period; 806 u8 gate; 807 u8 res[3]; 808 }; 809 810 /* tgs_gcl_conf address point to this data space */ 811 struct tgs_gcl_data { 812 __le32 btl; 813 __le32 bth; 814 __le32 ct; 815 __le32 cte; 816 struct gce entry[]; 817 }; 818 819 /* class 7, command 0, Stream Identity Entry Configuration */ 820 struct streamid_conf { 821 __le32 stream_handle; /* init gate value */ 822 __le32 iports; 823 u8 id_type; 824 u8 oui[3]; 825 u8 res[3]; 826 u8 en; 827 }; 828 829 #define ENETC_CBDR_SID_VID_MASK 0xfff 830 #define ENETC_CBDR_SID_VIDM BIT(12) 831 #define ENETC_CBDR_SID_TG_MASK 0xc000 832 /* streamid_conf address point to this data space */ 833 struct streamid_data { 834 union { 835 u8 dmac[6]; 836 u8 smac[6]; 837 }; 838 u16 vid_vidm_tg; 839 }; 840 841 #define ENETC_CBDR_SFI_PRI_MASK 0x7 842 #define ENETC_CBDR_SFI_PRIM BIT(3) 843 #define ENETC_CBDR_SFI_BLOV BIT(4) 844 #define ENETC_CBDR_SFI_BLEN BIT(5) 845 #define ENETC_CBDR_SFI_MSDUEN BIT(6) 846 #define ENETC_CBDR_SFI_FMITEN BIT(7) 847 #define ENETC_CBDR_SFI_ENABLE BIT(7) 848 /* class 8, command 0, Stream Filter Instance, Short Format */ 849 struct sfi_conf { 850 __le32 stream_handle; 851 u8 multi; 852 u8 res[2]; 853 u8 sthm; 854 /* Max Service Data Unit or Flow Meter Instance Table index. 855 * Depending on the value of FLT this represents either Max 856 * Service Data Unit (max frame size) allowed by the filter 857 * entry or is an index into the Flow Meter Instance table 858 * index identifying the policer which will be used to police 859 * it. 860 */ 861 __le16 fm_inst_table_index; 862 __le16 msdu; 863 __le16 sg_inst_table_index; 864 u8 res1[2]; 865 __le32 input_ports; 866 u8 res2[3]; 867 u8 en; 868 }; 869 870 /* class 8, command 2 stream Filter Instance status query short format 871 * command no need structure define 872 * Stream Filter Instance Query Statistics Response data 873 */ 874 struct sfi_counter_data { 875 u32 matchl; 876 u32 matchh; 877 u32 msdu_dropl; 878 u32 msdu_droph; 879 u32 stream_gate_dropl; 880 u32 stream_gate_droph; 881 u32 flow_meter_dropl; 882 u32 flow_meter_droph; 883 }; 884 885 #define ENETC_CBDR_SGI_OIPV_MASK 0x7 886 #define ENETC_CBDR_SGI_OIPV_EN BIT(3) 887 #define ENETC_CBDR_SGI_CGTST BIT(6) 888 #define ENETC_CBDR_SGI_OGTST BIT(7) 889 #define ENETC_CBDR_SGI_CFG_CHG BIT(1) 890 #define ENETC_CBDR_SGI_CFG_PND BIT(2) 891 #define ENETC_CBDR_SGI_OEX BIT(4) 892 #define ENETC_CBDR_SGI_OEXEN BIT(5) 893 #define ENETC_CBDR_SGI_IRX BIT(6) 894 #define ENETC_CBDR_SGI_IRXEN BIT(7) 895 #define ENETC_CBDR_SGI_ACLLEN_MASK 0x3 896 #define ENETC_CBDR_SGI_OCLLEN_MASK 0xc 897 #define ENETC_CBDR_SGI_EN BIT(7) 898 /* class 9, command 0, Stream Gate Instance Table, Short Format 899 * class 9, command 2, Stream Gate Instance Table entry query write back 900 * Short Format 901 */ 902 struct sgi_table { 903 u8 res[8]; 904 u8 oipv; 905 u8 res0[2]; 906 u8 ocgtst; 907 u8 res1[7]; 908 u8 gset; 909 u8 oacl_len; 910 u8 res2[2]; 911 u8 en; 912 }; 913 914 #define ENETC_CBDR_SGI_AIPV_MASK 0x7 915 #define ENETC_CBDR_SGI_AIPV_EN BIT(3) 916 #define ENETC_CBDR_SGI_AGTST BIT(7) 917 918 /* class 9, command 1, Stream Gate Control List, Long Format */ 919 struct sgcl_conf { 920 u8 aipv; 921 u8 res[2]; 922 u8 agtst; 923 u8 res1[4]; 924 union { 925 struct { 926 u8 res2[4]; 927 u8 acl_len; 928 u8 res3[3]; 929 }; 930 u8 cct[8]; /* Config change time */ 931 }; 932 }; 933 934 #define ENETC_CBDR_SGL_IOMEN BIT(0) 935 #define ENETC_CBDR_SGL_IPVEN BIT(3) 936 #define ENETC_CBDR_SGL_GTST BIT(4) 937 #define ENETC_CBDR_SGL_IPV_MASK 0xe 938 /* Stream Gate Control List Entry */ 939 struct sgce { 940 u32 interval; 941 u8 msdu[3]; 942 u8 multi; 943 }; 944 945 /* stream control list class 9 , cmd 1 data buffer */ 946 struct sgcl_data { 947 u32 btl; 948 u32 bth; 949 u32 ct; 950 u32 cte; 951 struct sgce sgcl[]; 952 }; 953 954 #define ENETC_CBDR_FMI_MR BIT(0) 955 #define ENETC_CBDR_FMI_MREN BIT(1) 956 #define ENETC_CBDR_FMI_DOY BIT(2) 957 #define ENETC_CBDR_FMI_CM BIT(3) 958 #define ENETC_CBDR_FMI_CF BIT(4) 959 #define ENETC_CBDR_FMI_NDOR BIT(5) 960 #define ENETC_CBDR_FMI_OALEN BIT(6) 961 #define ENETC_CBDR_FMI_IRFPP_MASK GENMASK(4, 0) 962 963 /* class 10: command 0/1, Flow Meter Instance Set, short Format */ 964 struct fmi_conf { 965 __le32 cir; 966 __le32 cbs; 967 __le32 eir; 968 __le32 ebs; 969 u8 conf; 970 u8 res1; 971 u8 ir_fpp; 972 u8 res2[4]; 973 u8 en; 974 }; 975 976 struct enetc_cbd { 977 union{ 978 struct sfi_conf sfi_conf; 979 struct sgi_table sgi_table; 980 struct fmi_conf fmi_conf; 981 struct { 982 __le32 addr[2]; 983 union { 984 __le32 opt[4]; 985 struct tgs_gcl_conf gcl_conf; 986 struct streamid_conf sid_set; 987 struct sgcl_conf sgcl_conf; 988 }; 989 }; /* Long format */ 990 __le32 data[6]; 991 }; 992 __le16 index; 993 __le16 length; 994 u8 cmd; 995 u8 cls; 996 u8 _res; 997 u8 status_flags; 998 }; 999 1000 #define ENETC_CLK_400M 400000000ULL 1001 #define ENETC_CLK_333M 333000000ULL 1002 1003 static inline u32 enetc_cycles_to_usecs(u32 cycles, u64 clk_freq) 1004 { 1005 return (u32)div_u64(cycles * 1000000ULL, clk_freq); 1006 } 1007 1008 static inline u32 enetc_usecs_to_cycles(u32 usecs, u64 clk_freq) 1009 { 1010 return (u32)div_u64(usecs * clk_freq, 1000000ULL); 1011 } 1012 1013 /* Port traffic class frame preemption register */ 1014 #define ENETC_PTCFPR(n) (0x1910 + (n) * 4) /* n = [0 ..7] */ 1015 #define ENETC_PTCFPR_FPE BIT(31) 1016 1017 /* port time gating control register */ 1018 #define ENETC_PTGCR 0x11a00 1019 #define ENETC_PTGCR_TGE BIT(31) 1020 #define ENETC_PTGCR_TGPE BIT(30) 1021 1022 /* Port time gating capability register */ 1023 #define ENETC_PTGCAPR 0x11a08 1024 #define ENETC_PTGCAPR_MAX_GCL_LEN_MASK GENMASK(15, 0) 1025 1026 /* Port time specific departure */ 1027 #define ENETC_PTCTSDR(n) (0x1210 + 4 * (n)) 1028 #define ENETC_TSDE BIT(31) 1029 1030 /* PSFP setting */ 1031 #define ENETC_PPSFPMR 0x11b00 1032 #define ENETC_PPSFPMR_PSFPEN BIT(0) 1033 #define ENETC_PPSFPMR_VS BIT(1) 1034 #define ENETC_PPSFPMR_PVC BIT(2) 1035 #define ENETC_PPSFPMR_PVZC BIT(3) 1036