1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2 /* Copyright 2024 NXP */ 3 4 #include <linux/clk.h> 5 #include <linux/module.h> 6 #include <linux/of_net.h> 7 #include <linux/of_platform.h> 8 #include <linux/unaligned.h> 9 10 #include "enetc_pf_common.h" 11 #include "enetc4_debugfs.h" 12 13 #define ENETC_SI_MAX_RING_NUM 8 14 15 #define ENETC_MAC_FILTER_TYPE_UC BIT(0) 16 #define ENETC_MAC_FILTER_TYPE_MC BIT(1) 17 #define ENETC_MAC_FILTER_TYPE_ALL (ENETC_MAC_FILTER_TYPE_UC | \ 18 ENETC_MAC_FILTER_TYPE_MC) 19 20 struct enetc_mac_addr { 21 u8 addr[ETH_ALEN]; 22 }; 23 24 static void enetc4_get_port_caps(struct enetc_pf *pf) 25 { 26 struct enetc_hw *hw = &pf->si->hw; 27 u32 val; 28 29 val = enetc_port_rd(hw, ENETC4_ECAPR1); 30 pf->caps.num_vsi = (val & ECAPR1_NUM_VSI) >> 24; 31 pf->caps.num_msix = ((val & ECAPR1_NUM_MSIX) >> 12) + 1; 32 33 val = enetc_port_rd(hw, ENETC4_ECAPR2); 34 pf->caps.num_rx_bdr = (val & ECAPR2_NUM_RX_BDR) >> 16; 35 pf->caps.num_tx_bdr = val & ECAPR2_NUM_TX_BDR; 36 37 val = enetc_port_rd(hw, ENETC4_PMCAPR); 38 pf->caps.half_duplex = (val & PMCAPR_HD) ? 1 : 0; 39 40 val = enetc_port_rd(hw, ENETC4_PSIMAFCAPR); 41 pf->caps.mac_filter_num = val & PSIMAFCAPR_NUM_MAC_AFTE; 42 } 43 44 static void enetc4_pf_set_si_primary_mac(struct enetc_hw *hw, int si, 45 const u8 *addr) 46 { 47 u16 lower = get_unaligned_le16(addr + 4); 48 u32 upper = get_unaligned_le32(addr); 49 50 if (si != 0) { 51 __raw_writel(upper, hw->port + ENETC4_PSIPMAR0(si)); 52 __raw_writew(lower, hw->port + ENETC4_PSIPMAR1(si)); 53 } else { 54 __raw_writel(upper, hw->port + ENETC4_PMAR0); 55 __raw_writew(lower, hw->port + ENETC4_PMAR1); 56 } 57 } 58 59 static void enetc4_pf_get_si_primary_mac(struct enetc_hw *hw, int si, 60 u8 *addr) 61 { 62 u32 upper; 63 u16 lower; 64 65 upper = __raw_readl(hw->port + ENETC4_PSIPMAR0(si)); 66 lower = __raw_readw(hw->port + ENETC4_PSIPMAR1(si)); 67 68 put_unaligned_le32(upper, addr); 69 put_unaligned_le16(lower, addr + 4); 70 } 71 72 static void enetc4_pf_set_si_mac_promisc(struct enetc_hw *hw, int si, 73 bool uc_promisc, bool mc_promisc) 74 { 75 u32 val = enetc_port_rd(hw, ENETC4_PSIPMMR); 76 77 if (uc_promisc) 78 val |= PSIPMMR_SI_MAC_UP(si); 79 else 80 val &= ~PSIPMMR_SI_MAC_UP(si); 81 82 if (mc_promisc) 83 val |= PSIPMMR_SI_MAC_MP(si); 84 else 85 val &= ~PSIPMMR_SI_MAC_MP(si); 86 87 enetc_port_wr(hw, ENETC4_PSIPMMR, val); 88 } 89 90 static void enetc4_pf_set_si_uc_hash_filter(struct enetc_hw *hw, int si, 91 u64 hash) 92 { 93 enetc_port_wr(hw, ENETC4_PSIUMHFR0(si), lower_32_bits(hash)); 94 enetc_port_wr(hw, ENETC4_PSIUMHFR1(si), upper_32_bits(hash)); 95 } 96 97 static void enetc4_pf_set_si_mc_hash_filter(struct enetc_hw *hw, int si, 98 u64 hash) 99 { 100 enetc_port_wr(hw, ENETC4_PSIMMHFR0(si), lower_32_bits(hash)); 101 enetc_port_wr(hw, ENETC4_PSIMMHFR1(si), upper_32_bits(hash)); 102 } 103 104 static void enetc4_pf_set_loopback(struct net_device *ndev, bool en) 105 { 106 struct enetc_ndev_priv *priv = netdev_priv(ndev); 107 struct enetc_si *si = priv->si; 108 u32 val; 109 110 val = enetc_port_mac_rd(si, ENETC4_PM_CMD_CFG(0)); 111 val = u32_replace_bits(val, en ? 1 : 0, PM_CMD_CFG_LOOP_EN); 112 /* Default to select MAC level loopback mode if loopback is enabled. */ 113 val = u32_replace_bits(val, en ? LPBCK_MODE_MAC_LEVEL : 0, 114 PM_CMD_CFG_LPBK_MODE); 115 116 enetc_port_mac_wr(si, ENETC4_PM_CMD_CFG(0), val); 117 } 118 119 static void enetc4_pf_clear_maft_entries(struct enetc_pf *pf) 120 { 121 int i; 122 123 for (i = 0; i < pf->num_mfe; i++) 124 ntmp_maft_delete_entry(&pf->si->ntmp_user, i); 125 126 pf->num_mfe = 0; 127 } 128 129 static int enetc4_pf_add_maft_entries(struct enetc_pf *pf, 130 struct enetc_mac_addr *mac, 131 int mac_cnt) 132 { 133 struct maft_entry_data maft = {}; 134 u16 si_bit = BIT(0); 135 int i, err; 136 137 maft.cfge.si_bitmap = cpu_to_le16(si_bit); 138 for (i = 0; i < mac_cnt; i++) { 139 ether_addr_copy(maft.keye.mac_addr, mac[i].addr); 140 err = ntmp_maft_add_entry(&pf->si->ntmp_user, i, &maft); 141 if (unlikely(err)) { 142 pf->num_mfe = i; 143 goto clear_maft_entries; 144 } 145 } 146 147 pf->num_mfe = mac_cnt; 148 149 return 0; 150 151 clear_maft_entries: 152 enetc4_pf_clear_maft_entries(pf); 153 154 return err; 155 } 156 157 static int enetc4_pf_set_uc_exact_filter(struct enetc_pf *pf) 158 { 159 int max_num_mfe = pf->caps.mac_filter_num; 160 struct enetc_mac_filter mac_filter = {}; 161 struct net_device *ndev = pf->si->ndev; 162 struct enetc_hw *hw = &pf->si->hw; 163 struct enetc_mac_addr *mac_tbl; 164 struct netdev_hw_addr *ha; 165 int i = 0, err; 166 int mac_cnt; 167 168 netif_addr_lock_bh(ndev); 169 170 mac_cnt = netdev_uc_count(ndev); 171 if (!mac_cnt) { 172 netif_addr_unlock_bh(ndev); 173 /* clear both MAC hash and exact filters */ 174 enetc4_pf_set_si_uc_hash_filter(hw, 0, 0); 175 enetc4_pf_clear_maft_entries(pf); 176 177 return 0; 178 } 179 180 if (mac_cnt > max_num_mfe) { 181 err = -ENOSPC; 182 goto unlock_netif_addr; 183 } 184 185 mac_tbl = kcalloc(mac_cnt, sizeof(*mac_tbl), GFP_ATOMIC); 186 if (!mac_tbl) { 187 err = -ENOMEM; 188 goto unlock_netif_addr; 189 } 190 191 netdev_for_each_uc_addr(ha, ndev) { 192 enetc_add_mac_addr_ht_filter(&mac_filter, ha->addr); 193 ether_addr_copy(mac_tbl[i++].addr, ha->addr); 194 } 195 196 netif_addr_unlock_bh(ndev); 197 198 /* Set temporary unicast hash filters in case of Rx loss when 199 * updating MAC address filter table 200 */ 201 enetc4_pf_set_si_uc_hash_filter(hw, 0, *mac_filter.mac_hash_table); 202 enetc4_pf_clear_maft_entries(pf); 203 204 if (!enetc4_pf_add_maft_entries(pf, mac_tbl, i)) 205 enetc4_pf_set_si_uc_hash_filter(hw, 0, 0); 206 207 kfree(mac_tbl); 208 209 return 0; 210 211 unlock_netif_addr: 212 netif_addr_unlock_bh(ndev); 213 214 return err; 215 } 216 217 static void enetc4_pf_set_mac_hash_filter(struct enetc_pf *pf, int type) 218 { 219 struct net_device *ndev = pf->si->ndev; 220 struct enetc_mac_filter *mac_filter; 221 struct enetc_hw *hw = &pf->si->hw; 222 struct netdev_hw_addr *ha; 223 224 netif_addr_lock_bh(ndev); 225 if (type & ENETC_MAC_FILTER_TYPE_UC) { 226 mac_filter = &pf->mac_filter[UC]; 227 enetc_reset_mac_addr_filter(mac_filter); 228 netdev_for_each_uc_addr(ha, ndev) 229 enetc_add_mac_addr_ht_filter(mac_filter, ha->addr); 230 231 enetc4_pf_set_si_uc_hash_filter(hw, 0, 232 *mac_filter->mac_hash_table); 233 } 234 235 if (type & ENETC_MAC_FILTER_TYPE_MC) { 236 mac_filter = &pf->mac_filter[MC]; 237 enetc_reset_mac_addr_filter(mac_filter); 238 netdev_for_each_mc_addr(ha, ndev) 239 enetc_add_mac_addr_ht_filter(mac_filter, ha->addr); 240 241 enetc4_pf_set_si_mc_hash_filter(hw, 0, 242 *mac_filter->mac_hash_table); 243 } 244 netif_addr_unlock_bh(ndev); 245 } 246 247 static void enetc4_pf_set_mac_filter(struct enetc_pf *pf, int type) 248 { 249 /* Currently, the MAC address filter table (MAFT) only has 4 entries, 250 * and multiple multicast addresses for filtering will be configured 251 * in the default network configuration, so MAFT is only suitable for 252 * unicast filtering. If the number of unicast addresses exceeds the 253 * table capacity, the MAC hash filter will be used. 254 */ 255 if (type & ENETC_MAC_FILTER_TYPE_UC && enetc4_pf_set_uc_exact_filter(pf)) { 256 /* Fall back to the MAC hash filter */ 257 enetc4_pf_set_mac_hash_filter(pf, ENETC_MAC_FILTER_TYPE_UC); 258 /* Clear the old MAC exact filter */ 259 enetc4_pf_clear_maft_entries(pf); 260 } 261 262 if (type & ENETC_MAC_FILTER_TYPE_MC) 263 enetc4_pf_set_mac_hash_filter(pf, ENETC_MAC_FILTER_TYPE_MC); 264 } 265 266 static const struct enetc_pf_ops enetc4_pf_ops = { 267 .set_si_primary_mac = enetc4_pf_set_si_primary_mac, 268 .get_si_primary_mac = enetc4_pf_get_si_primary_mac, 269 }; 270 271 static int enetc4_pf_struct_init(struct enetc_si *si) 272 { 273 struct enetc_pf *pf = enetc_si_priv(si); 274 275 pf->si = si; 276 pf->total_vfs = pci_sriov_get_totalvfs(si->pdev); 277 pf->ops = &enetc4_pf_ops; 278 279 enetc4_get_port_caps(pf); 280 281 return 0; 282 } 283 284 static u32 enetc4_psicfgr0_val_construct(bool is_vf, u32 num_tx_bdr, u32 num_rx_bdr) 285 { 286 u32 val; 287 288 val = ENETC_PSICFGR0_SET_TXBDR(num_tx_bdr); 289 val |= ENETC_PSICFGR0_SET_RXBDR(num_rx_bdr); 290 val |= ENETC_PSICFGR0_SIVC(ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S); 291 292 if (is_vf) 293 val |= ENETC_PSICFGR0_VTE | ENETC_PSICFGR0_SIVIE; 294 295 return val; 296 } 297 298 static void enetc4_default_rings_allocation(struct enetc_pf *pf) 299 { 300 struct enetc_hw *hw = &pf->si->hw; 301 u32 num_rx_bdr, num_tx_bdr, val; 302 u32 vf_tx_bdr, vf_rx_bdr; 303 int i, rx_rem, tx_rem; 304 305 if (pf->caps.num_rx_bdr < ENETC_SI_MAX_RING_NUM + pf->caps.num_vsi) 306 num_rx_bdr = pf->caps.num_rx_bdr - pf->caps.num_vsi; 307 else 308 num_rx_bdr = ENETC_SI_MAX_RING_NUM; 309 310 if (pf->caps.num_tx_bdr < ENETC_SI_MAX_RING_NUM + pf->caps.num_vsi) 311 num_tx_bdr = pf->caps.num_tx_bdr - pf->caps.num_vsi; 312 else 313 num_tx_bdr = ENETC_SI_MAX_RING_NUM; 314 315 val = enetc4_psicfgr0_val_construct(false, num_tx_bdr, num_rx_bdr); 316 enetc_port_wr(hw, ENETC4_PSICFGR0(0), val); 317 318 num_rx_bdr = pf->caps.num_rx_bdr - num_rx_bdr; 319 rx_rem = num_rx_bdr % pf->caps.num_vsi; 320 num_rx_bdr = num_rx_bdr / pf->caps.num_vsi; 321 322 num_tx_bdr = pf->caps.num_tx_bdr - num_tx_bdr; 323 tx_rem = num_tx_bdr % pf->caps.num_vsi; 324 num_tx_bdr = num_tx_bdr / pf->caps.num_vsi; 325 326 for (i = 0; i < pf->caps.num_vsi; i++) { 327 vf_tx_bdr = (i < tx_rem) ? num_tx_bdr + 1 : num_tx_bdr; 328 vf_rx_bdr = (i < rx_rem) ? num_rx_bdr + 1 : num_rx_bdr; 329 val = enetc4_psicfgr0_val_construct(true, vf_tx_bdr, vf_rx_bdr); 330 enetc_port_wr(hw, ENETC4_PSICFGR0(i + 1), val); 331 } 332 } 333 334 static void enetc4_allocate_si_rings(struct enetc_pf *pf) 335 { 336 enetc4_default_rings_allocation(pf); 337 } 338 339 static void enetc4_pf_set_si_vlan_promisc(struct enetc_hw *hw, int si, bool en) 340 { 341 u32 val = enetc_port_rd(hw, ENETC4_PSIPVMR); 342 343 if (en) 344 val |= BIT(si); 345 else 346 val &= ~BIT(si); 347 348 enetc_port_wr(hw, ENETC4_PSIPVMR, val); 349 } 350 351 static void enetc4_set_default_si_vlan_promisc(struct enetc_pf *pf) 352 { 353 struct enetc_hw *hw = &pf->si->hw; 354 int num_si = pf->caps.num_vsi + 1; 355 int i; 356 357 /* enforce VLAN promiscuous mode for all SIs */ 358 for (i = 0; i < num_si; i++) 359 enetc4_pf_set_si_vlan_promisc(hw, i, true); 360 } 361 362 /* Allocate the number of MSI-X vectors for per SI. */ 363 static void enetc4_set_si_msix_num(struct enetc_pf *pf) 364 { 365 struct enetc_hw *hw = &pf->si->hw; 366 int i, num_msix, total_si; 367 u32 val; 368 369 total_si = pf->caps.num_vsi + 1; 370 371 num_msix = pf->caps.num_msix / total_si + 372 pf->caps.num_msix % total_si - 1; 373 val = num_msix & PSICFGR2_NUM_MSIX; 374 enetc_port_wr(hw, ENETC4_PSICFGR2(0), val); 375 376 num_msix = pf->caps.num_msix / total_si - 1; 377 val = num_msix & PSICFGR2_NUM_MSIX; 378 for (i = 0; i < pf->caps.num_vsi; i++) 379 enetc_port_wr(hw, ENETC4_PSICFGR2(i + 1), val); 380 } 381 382 static void enetc4_enable_all_si(struct enetc_pf *pf) 383 { 384 struct enetc_hw *hw = &pf->si->hw; 385 int num_si = pf->caps.num_vsi + 1; 386 u32 si_bitmap = 0; 387 int i; 388 389 /* Master enable for all SIs */ 390 for (i = 0; i < num_si; i++) 391 si_bitmap |= PMR_SI_EN(i); 392 393 enetc_port_wr(hw, ENETC4_PMR, si_bitmap); 394 } 395 396 static void enetc4_configure_port_si(struct enetc_pf *pf) 397 { 398 struct enetc_hw *hw = &pf->si->hw; 399 400 enetc4_allocate_si_rings(pf); 401 402 /* Outer VLAN tag will be used for VLAN filtering */ 403 enetc_port_wr(hw, ENETC4_PSIVLANFMR, PSIVLANFMR_VS); 404 405 enetc4_set_default_si_vlan_promisc(pf); 406 407 /* Disable SI MAC multicast & unicast promiscuous */ 408 enetc_port_wr(hw, ENETC4_PSIPMMR, 0); 409 410 enetc4_set_si_msix_num(pf); 411 412 enetc4_enable_all_si(pf); 413 } 414 415 static void enetc4_pf_reset_tc_msdu(struct enetc_hw *hw) 416 { 417 u32 val = ENETC_MAC_MAXFRM_SIZE; 418 int tc; 419 420 val = u32_replace_bits(val, SDU_TYPE_MPDU, PTCTMSDUR_SDU_TYPE); 421 422 for (tc = 0; tc < ENETC_NUM_TC; tc++) 423 enetc_port_wr(hw, ENETC4_PTCTMSDUR(tc), val); 424 } 425 426 static void enetc4_set_trx_frame_size(struct enetc_pf *pf) 427 { 428 struct enetc_si *si = pf->si; 429 430 enetc_port_mac_wr(si, ENETC4_PM_MAXFRM(0), 431 ENETC_SET_MAXFRM(ENETC_MAC_MAXFRM_SIZE)); 432 433 enetc4_pf_reset_tc_msdu(&si->hw); 434 } 435 436 static void enetc4_enable_trx(struct enetc_pf *pf) 437 { 438 struct enetc_hw *hw = &pf->si->hw; 439 440 /* Enable port transmit/receive */ 441 enetc_port_wr(hw, ENETC4_POR, 0); 442 } 443 444 static void enetc4_configure_port(struct enetc_pf *pf) 445 { 446 enetc4_configure_port_si(pf); 447 enetc4_set_trx_frame_size(pf); 448 enetc_set_default_rss_key(pf); 449 enetc4_enable_trx(pf); 450 } 451 452 static int enetc4_init_ntmp_user(struct enetc_si *si) 453 { 454 struct ntmp_user *user = &si->ntmp_user; 455 456 /* For ENETC 4.1, all table versions are 0 */ 457 memset(&user->tbl, 0, sizeof(user->tbl)); 458 459 return enetc4_setup_cbdr(si); 460 } 461 462 static void enetc4_free_ntmp_user(struct enetc_si *si) 463 { 464 enetc4_teardown_cbdr(si); 465 } 466 467 static int enetc4_pf_init(struct enetc_pf *pf) 468 { 469 struct device *dev = &pf->si->pdev->dev; 470 int err; 471 472 /* Initialize the MAC address for PF and VFs */ 473 err = enetc_setup_mac_addresses(dev->of_node, pf); 474 if (err) { 475 dev_err(dev, "Failed to set MAC addresses\n"); 476 return err; 477 } 478 479 err = enetc4_init_ntmp_user(pf->si); 480 if (err) { 481 dev_err(dev, "Failed to init CBDR\n"); 482 return err; 483 } 484 485 enetc4_configure_port(pf); 486 487 return 0; 488 } 489 490 static void enetc4_pf_free(struct enetc_pf *pf) 491 { 492 enetc4_free_ntmp_user(pf->si); 493 } 494 495 static void enetc4_psi_do_set_rx_mode(struct work_struct *work) 496 { 497 struct enetc_si *si = container_of(work, struct enetc_si, rx_mode_task); 498 struct enetc_pf *pf = enetc_si_priv(si); 499 struct net_device *ndev = si->ndev; 500 struct enetc_hw *hw = &si->hw; 501 bool uc_promisc = false; 502 bool mc_promisc = false; 503 int type = 0; 504 505 rtnl_lock(); 506 507 if (ndev->flags & IFF_PROMISC) { 508 uc_promisc = true; 509 mc_promisc = true; 510 } else if (ndev->flags & IFF_ALLMULTI) { 511 mc_promisc = true; 512 type = ENETC_MAC_FILTER_TYPE_UC; 513 } else { 514 type = ENETC_MAC_FILTER_TYPE_ALL; 515 } 516 517 enetc4_pf_set_si_mac_promisc(hw, 0, uc_promisc, mc_promisc); 518 519 if (uc_promisc) { 520 enetc4_pf_set_si_uc_hash_filter(hw, 0, 0); 521 enetc4_pf_clear_maft_entries(pf); 522 } 523 524 if (mc_promisc) 525 enetc4_pf_set_si_mc_hash_filter(hw, 0, 0); 526 527 /* Set new MAC filter */ 528 enetc4_pf_set_mac_filter(pf, type); 529 530 rtnl_unlock(); 531 } 532 533 static void enetc4_pf_set_rx_mode(struct net_device *ndev) 534 { 535 struct enetc_ndev_priv *priv = netdev_priv(ndev); 536 struct enetc_si *si = priv->si; 537 538 queue_work(si->workqueue, &si->rx_mode_task); 539 } 540 541 static int enetc4_pf_set_features(struct net_device *ndev, 542 netdev_features_t features) 543 { 544 netdev_features_t changed = ndev->features ^ features; 545 struct enetc_ndev_priv *priv = netdev_priv(ndev); 546 struct enetc_hw *hw = &priv->si->hw; 547 548 if (changed & NETIF_F_HW_VLAN_CTAG_FILTER) { 549 bool promisc_en = !(features & NETIF_F_HW_VLAN_CTAG_FILTER); 550 551 enetc4_pf_set_si_vlan_promisc(hw, 0, promisc_en); 552 } 553 554 if (changed & NETIF_F_LOOPBACK) 555 enetc4_pf_set_loopback(ndev, !!(features & NETIF_F_LOOPBACK)); 556 557 enetc_set_features(ndev, features); 558 559 return 0; 560 } 561 562 static const struct net_device_ops enetc4_ndev_ops = { 563 .ndo_open = enetc_open, 564 .ndo_stop = enetc_close, 565 .ndo_start_xmit = enetc_xmit, 566 .ndo_get_stats = enetc_get_stats, 567 .ndo_set_mac_address = enetc_pf_set_mac_addr, 568 .ndo_set_rx_mode = enetc4_pf_set_rx_mode, 569 .ndo_set_features = enetc4_pf_set_features, 570 .ndo_vlan_rx_add_vid = enetc_vlan_rx_add_vid, 571 .ndo_vlan_rx_kill_vid = enetc_vlan_rx_del_vid, 572 .ndo_eth_ioctl = enetc_ioctl, 573 .ndo_hwtstamp_get = enetc_hwtstamp_get, 574 .ndo_hwtstamp_set = enetc_hwtstamp_set, 575 }; 576 577 static struct phylink_pcs * 578 enetc4_pl_mac_select_pcs(struct phylink_config *config, phy_interface_t iface) 579 { 580 struct enetc_pf *pf = phylink_to_enetc_pf(config); 581 582 return pf->pcs; 583 } 584 585 static void enetc4_mac_config(struct enetc_pf *pf, unsigned int mode, 586 phy_interface_t phy_mode) 587 { 588 struct enetc_ndev_priv *priv = netdev_priv(pf->si->ndev); 589 struct enetc_si *si = pf->si; 590 u32 val; 591 592 val = enetc_port_mac_rd(si, ENETC4_PM_IF_MODE(0)); 593 val &= ~(PM_IF_MODE_IFMODE | PM_IF_MODE_ENA); 594 595 switch (phy_mode) { 596 case PHY_INTERFACE_MODE_RGMII: 597 case PHY_INTERFACE_MODE_RGMII_ID: 598 case PHY_INTERFACE_MODE_RGMII_RXID: 599 case PHY_INTERFACE_MODE_RGMII_TXID: 600 val |= IFMODE_RGMII; 601 /* We need to enable auto-negotiation for the MAC 602 * if its RGMII interface support In-Band status. 603 */ 604 if (phylink_autoneg_inband(mode)) 605 val |= PM_IF_MODE_ENA; 606 break; 607 case PHY_INTERFACE_MODE_RMII: 608 val |= IFMODE_RMII; 609 break; 610 case PHY_INTERFACE_MODE_SGMII: 611 case PHY_INTERFACE_MODE_2500BASEX: 612 val |= IFMODE_SGMII; 613 break; 614 case PHY_INTERFACE_MODE_10GBASER: 615 case PHY_INTERFACE_MODE_XGMII: 616 case PHY_INTERFACE_MODE_USXGMII: 617 val |= IFMODE_XGMII; 618 break; 619 default: 620 dev_err(priv->dev, 621 "Unsupported PHY mode:%d\n", phy_mode); 622 return; 623 } 624 625 enetc_port_mac_wr(si, ENETC4_PM_IF_MODE(0), val); 626 } 627 628 static void enetc4_pl_mac_config(struct phylink_config *config, unsigned int mode, 629 const struct phylink_link_state *state) 630 { 631 struct enetc_pf *pf = phylink_to_enetc_pf(config); 632 633 enetc4_mac_config(pf, mode, state->interface); 634 } 635 636 static void enetc4_set_port_speed(struct enetc_ndev_priv *priv, int speed) 637 { 638 u32 old_speed = priv->speed; 639 u32 val; 640 641 if (speed == old_speed) 642 return; 643 644 val = enetc_port_rd(&priv->si->hw, ENETC4_PCR); 645 val &= ~PCR_PSPEED; 646 647 switch (speed) { 648 case SPEED_100: 649 case SPEED_1000: 650 case SPEED_2500: 651 case SPEED_10000: 652 val |= (PCR_PSPEED & PCR_PSPEED_VAL(speed)); 653 break; 654 case SPEED_10: 655 default: 656 val |= (PCR_PSPEED & PCR_PSPEED_VAL(SPEED_10)); 657 } 658 659 priv->speed = speed; 660 enetc_port_wr(&priv->si->hw, ENETC4_PCR, val); 661 } 662 663 static void enetc4_set_rgmii_mac(struct enetc_pf *pf, int speed, int duplex) 664 { 665 struct enetc_si *si = pf->si; 666 u32 old_val, val; 667 668 old_val = enetc_port_mac_rd(si, ENETC4_PM_IF_MODE(0)); 669 val = old_val & ~(PM_IF_MODE_ENA | PM_IF_MODE_M10 | PM_IF_MODE_REVMII); 670 671 switch (speed) { 672 case SPEED_1000: 673 val = u32_replace_bits(val, SSP_1G, PM_IF_MODE_SSP); 674 break; 675 case SPEED_100: 676 val = u32_replace_bits(val, SSP_100M, PM_IF_MODE_SSP); 677 break; 678 case SPEED_10: 679 val = u32_replace_bits(val, SSP_10M, PM_IF_MODE_SSP); 680 } 681 682 val = u32_replace_bits(val, duplex == DUPLEX_FULL ? 0 : 1, 683 PM_IF_MODE_HD); 684 685 if (val == old_val) 686 return; 687 688 enetc_port_mac_wr(si, ENETC4_PM_IF_MODE(0), val); 689 } 690 691 static void enetc4_set_rmii_mac(struct enetc_pf *pf, int speed, int duplex) 692 { 693 struct enetc_si *si = pf->si; 694 u32 old_val, val; 695 696 old_val = enetc_port_mac_rd(si, ENETC4_PM_IF_MODE(0)); 697 val = old_val & ~(PM_IF_MODE_ENA | PM_IF_MODE_SSP); 698 699 switch (speed) { 700 case SPEED_100: 701 val &= ~PM_IF_MODE_M10; 702 break; 703 case SPEED_10: 704 val |= PM_IF_MODE_M10; 705 } 706 707 val = u32_replace_bits(val, duplex == DUPLEX_FULL ? 0 : 1, 708 PM_IF_MODE_HD); 709 710 if (val == old_val) 711 return; 712 713 enetc_port_mac_wr(si, ENETC4_PM_IF_MODE(0), val); 714 } 715 716 static void enetc4_set_hd_flow_control(struct enetc_pf *pf, bool enable) 717 { 718 struct enetc_si *si = pf->si; 719 u32 old_val, val; 720 721 if (!pf->caps.half_duplex) 722 return; 723 724 old_val = enetc_port_mac_rd(si, ENETC4_PM_CMD_CFG(0)); 725 val = u32_replace_bits(old_val, enable ? 1 : 0, PM_CMD_CFG_HD_FCEN); 726 if (val == old_val) 727 return; 728 729 enetc_port_mac_wr(si, ENETC4_PM_CMD_CFG(0), val); 730 } 731 732 static void enetc4_set_rx_pause(struct enetc_pf *pf, bool rx_pause) 733 { 734 struct enetc_si *si = pf->si; 735 u32 old_val, val; 736 737 old_val = enetc_port_mac_rd(si, ENETC4_PM_CMD_CFG(0)); 738 val = u32_replace_bits(old_val, rx_pause ? 0 : 1, PM_CMD_CFG_PAUSE_IGN); 739 if (val == old_val) 740 return; 741 742 enetc_port_mac_wr(si, ENETC4_PM_CMD_CFG(0), val); 743 } 744 745 static void enetc4_set_tx_pause(struct enetc_pf *pf, int num_rxbdr, bool tx_pause) 746 { 747 u32 pause_off_thresh = 0, pause_on_thresh = 0; 748 u32 init_quanta = 0, refresh_quanta = 0; 749 struct enetc_hw *hw = &pf->si->hw; 750 u32 rbmr, old_rbmr; 751 int i; 752 753 for (i = 0; i < num_rxbdr; i++) { 754 old_rbmr = enetc_rxbdr_rd(hw, i, ENETC_RBMR); 755 rbmr = u32_replace_bits(old_rbmr, tx_pause ? 1 : 0, ENETC_RBMR_CM); 756 if (rbmr == old_rbmr) 757 continue; 758 759 enetc_rxbdr_wr(hw, i, ENETC_RBMR, rbmr); 760 } 761 762 if (tx_pause) { 763 /* When the port first enters congestion, send a PAUSE request 764 * with the maximum number of quanta. When the port exits 765 * congestion, it will automatically send a PAUSE frame with 766 * zero quanta. 767 */ 768 init_quanta = 0xffff; 769 770 /* Also, set up the refresh timer to send follow-up PAUSE 771 * frames at half the quanta value, in case the congestion 772 * condition persists. 773 */ 774 refresh_quanta = 0xffff / 2; 775 776 /* Start emitting PAUSE frames when 3 large frames (or more 777 * smaller frames) have accumulated in the FIFO waiting to be 778 * DMAed to the RX ring. 779 */ 780 pause_on_thresh = 3 * ENETC_MAC_MAXFRM_SIZE; 781 pause_off_thresh = 1 * ENETC_MAC_MAXFRM_SIZE; 782 } 783 784 enetc_port_mac_wr(pf->si, ENETC4_PM_PAUSE_QUANTA(0), init_quanta); 785 enetc_port_mac_wr(pf->si, ENETC4_PM_PAUSE_THRESH(0), refresh_quanta); 786 enetc_port_wr(hw, ENETC4_PPAUONTR, pause_on_thresh); 787 enetc_port_wr(hw, ENETC4_PPAUOFFTR, pause_off_thresh); 788 } 789 790 static void enetc4_enable_mac(struct enetc_pf *pf, bool en) 791 { 792 struct enetc_si *si = pf->si; 793 u32 val; 794 795 val = enetc_port_mac_rd(si, ENETC4_PM_CMD_CFG(0)); 796 val &= ~(PM_CMD_CFG_TX_EN | PM_CMD_CFG_RX_EN); 797 val |= en ? (PM_CMD_CFG_TX_EN | PM_CMD_CFG_RX_EN) : 0; 798 799 enetc_port_mac_wr(si, ENETC4_PM_CMD_CFG(0), val); 800 } 801 802 static void enetc4_pl_mac_link_up(struct phylink_config *config, 803 struct phy_device *phy, unsigned int mode, 804 phy_interface_t interface, int speed, 805 int duplex, bool tx_pause, bool rx_pause) 806 { 807 struct enetc_pf *pf = phylink_to_enetc_pf(config); 808 struct enetc_si *si = pf->si; 809 struct enetc_ndev_priv *priv; 810 bool hd_fc = false; 811 812 priv = netdev_priv(si->ndev); 813 enetc4_set_port_speed(priv, speed); 814 815 if (!phylink_autoneg_inband(mode) && 816 phy_interface_mode_is_rgmii(interface)) 817 enetc4_set_rgmii_mac(pf, speed, duplex); 818 819 if (interface == PHY_INTERFACE_MODE_RMII) 820 enetc4_set_rmii_mac(pf, speed, duplex); 821 822 if (duplex == DUPLEX_FULL) { 823 /* When preemption is enabled, generation of PAUSE frames 824 * must be disabled, as stated in the IEEE 802.3 standard. 825 */ 826 if (priv->active_offloads & ENETC_F_QBU) 827 tx_pause = false; 828 } else { /* DUPLEX_HALF */ 829 if (tx_pause || rx_pause) 830 hd_fc = true; 831 832 /* As per 802.3 annex 31B, PAUSE frames are only supported 833 * when the link is configured for full duplex operation. 834 */ 835 tx_pause = false; 836 rx_pause = false; 837 } 838 839 enetc4_set_hd_flow_control(pf, hd_fc); 840 enetc4_set_tx_pause(pf, priv->num_rx_rings, tx_pause); 841 enetc4_set_rx_pause(pf, rx_pause); 842 enetc4_enable_mac(pf, true); 843 } 844 845 static void enetc4_pl_mac_link_down(struct phylink_config *config, 846 unsigned int mode, 847 phy_interface_t interface) 848 { 849 struct enetc_pf *pf = phylink_to_enetc_pf(config); 850 851 enetc4_enable_mac(pf, false); 852 } 853 854 static const struct phylink_mac_ops enetc_pl_mac_ops = { 855 .mac_select_pcs = enetc4_pl_mac_select_pcs, 856 .mac_config = enetc4_pl_mac_config, 857 .mac_link_up = enetc4_pl_mac_link_up, 858 .mac_link_down = enetc4_pl_mac_link_down, 859 }; 860 861 static void enetc4_pci_remove(void *data) 862 { 863 struct pci_dev *pdev = data; 864 865 enetc_pci_remove(pdev); 866 } 867 868 static int enetc4_link_init(struct enetc_ndev_priv *priv, 869 struct device_node *node) 870 { 871 struct enetc_pf *pf = enetc_si_priv(priv->si); 872 struct device *dev = priv->dev; 873 int err; 874 875 err = of_get_phy_mode(node, &pf->if_mode); 876 if (err) { 877 dev_err(dev, "Failed to get PHY mode\n"); 878 return err; 879 } 880 881 err = enetc_mdiobus_create(pf, node); 882 if (err) { 883 dev_err(dev, "Failed to create MDIO bus\n"); 884 return err; 885 } 886 887 err = enetc_phylink_create(priv, node, &enetc_pl_mac_ops); 888 if (err) { 889 dev_err(dev, "Failed to create phylink\n"); 890 goto err_phylink_create; 891 } 892 893 return 0; 894 895 err_phylink_create: 896 enetc_mdiobus_destroy(pf); 897 898 return err; 899 } 900 901 static void enetc4_link_deinit(struct enetc_ndev_priv *priv) 902 { 903 struct enetc_pf *pf = enetc_si_priv(priv->si); 904 905 enetc_phylink_destroy(priv); 906 enetc_mdiobus_destroy(pf); 907 } 908 909 static int enetc4_psi_wq_task_init(struct enetc_si *si) 910 { 911 char wq_name[24]; 912 913 INIT_WORK(&si->rx_mode_task, enetc4_psi_do_set_rx_mode); 914 snprintf(wq_name, sizeof(wq_name), "enetc-%s", pci_name(si->pdev)); 915 si->workqueue = create_singlethread_workqueue(wq_name); 916 if (!si->workqueue) 917 return -ENOMEM; 918 919 return 0; 920 } 921 922 static int enetc4_pf_netdev_create(struct enetc_si *si) 923 { 924 struct device *dev = &si->pdev->dev; 925 struct enetc_ndev_priv *priv; 926 struct net_device *ndev; 927 int err; 928 929 ndev = alloc_etherdev_mqs(sizeof(struct enetc_ndev_priv), 930 si->num_tx_rings, si->num_rx_rings); 931 if (!ndev) 932 return -ENOMEM; 933 934 priv = netdev_priv(ndev); 935 priv->ref_clk = devm_clk_get_optional(dev, "ref"); 936 if (IS_ERR(priv->ref_clk)) { 937 dev_err(dev, "Get reference clock failed\n"); 938 err = PTR_ERR(priv->ref_clk); 939 goto err_clk_get; 940 } 941 942 enetc_pf_netdev_setup(si, ndev, &enetc4_ndev_ops); 943 944 enetc_init_si_rings_params(priv); 945 946 err = enetc_configure_si(priv); 947 if (err) { 948 dev_err(dev, "Failed to configure SI\n"); 949 goto err_config_si; 950 } 951 952 err = enetc_alloc_msix(priv); 953 if (err) { 954 dev_err(dev, "Failed to alloc MSI-X\n"); 955 goto err_alloc_msix; 956 } 957 958 err = enetc4_link_init(priv, dev->of_node); 959 if (err) 960 goto err_link_init; 961 962 err = enetc4_psi_wq_task_init(si); 963 if (err) { 964 dev_err(dev, "Failed to init workqueue\n"); 965 goto err_wq_init; 966 } 967 968 err = register_netdev(ndev); 969 if (err) { 970 dev_err(dev, "Failed to register netdev\n"); 971 goto err_reg_netdev; 972 } 973 974 return 0; 975 976 err_reg_netdev: 977 destroy_workqueue(si->workqueue); 978 err_wq_init: 979 enetc4_link_deinit(priv); 980 err_link_init: 981 enetc_free_msix(priv); 982 err_alloc_msix: 983 err_config_si: 984 err_clk_get: 985 free_netdev(ndev); 986 987 return err; 988 } 989 990 static void enetc4_pf_netdev_destroy(struct enetc_si *si) 991 { 992 struct enetc_ndev_priv *priv = netdev_priv(si->ndev); 993 struct net_device *ndev = si->ndev; 994 995 unregister_netdev(ndev); 996 cancel_work(&si->rx_mode_task); 997 destroy_workqueue(si->workqueue); 998 enetc4_link_deinit(priv); 999 enetc_free_msix(priv); 1000 free_netdev(ndev); 1001 } 1002 1003 static const struct enetc_si_ops enetc4_psi_ops = { 1004 .get_rss_table = enetc4_get_rss_table, 1005 .set_rss_table = enetc4_set_rss_table, 1006 }; 1007 1008 static int enetc4_pf_probe(struct pci_dev *pdev, 1009 const struct pci_device_id *ent) 1010 { 1011 struct device *dev = &pdev->dev; 1012 struct enetc_si *si; 1013 struct enetc_pf *pf; 1014 int err; 1015 1016 err = enetc_pci_probe(pdev, KBUILD_MODNAME, sizeof(*pf)); 1017 if (err) 1018 return dev_err_probe(dev, err, "PCIe probing failed\n"); 1019 1020 err = devm_add_action_or_reset(dev, enetc4_pci_remove, pdev); 1021 if (err) 1022 return err; 1023 1024 /* si is the private data. */ 1025 si = pci_get_drvdata(pdev); 1026 if (!si->hw.port || !si->hw.global) 1027 return dev_err_probe(dev, -ENODEV, 1028 "Couldn't map PF only space\n"); 1029 1030 si->revision = enetc_get_ip_revision(&si->hw); 1031 si->ops = &enetc4_psi_ops; 1032 err = enetc_get_driver_data(si); 1033 if (err) 1034 return dev_err_probe(dev, err, 1035 "Could not get VF driver data\n"); 1036 1037 err = enetc4_pf_struct_init(si); 1038 if (err) 1039 return err; 1040 1041 pf = enetc_si_priv(si); 1042 err = enetc4_pf_init(pf); 1043 if (err) 1044 return err; 1045 1046 enetc_get_si_caps(si); 1047 1048 err = enetc4_pf_netdev_create(si); 1049 if (err) 1050 goto err_netdev_create; 1051 1052 enetc_create_debugfs(si); 1053 1054 return 0; 1055 1056 err_netdev_create: 1057 enetc4_pf_free(pf); 1058 1059 return err; 1060 } 1061 1062 static void enetc4_pf_remove(struct pci_dev *pdev) 1063 { 1064 struct enetc_si *si = pci_get_drvdata(pdev); 1065 struct enetc_pf *pf = enetc_si_priv(si); 1066 1067 enetc_remove_debugfs(si); 1068 enetc4_pf_netdev_destroy(si); 1069 enetc4_pf_free(pf); 1070 } 1071 1072 static const struct pci_device_id enetc4_pf_id_table[] = { 1073 { PCI_DEVICE(NXP_ENETC_VENDOR_ID, NXP_ENETC_PF_DEV_ID) }, 1074 { 0, } /* End of table. */ 1075 }; 1076 MODULE_DEVICE_TABLE(pci, enetc4_pf_id_table); 1077 1078 static struct pci_driver enetc4_pf_driver = { 1079 .name = KBUILD_MODNAME, 1080 .id_table = enetc4_pf_id_table, 1081 .probe = enetc4_pf_probe, 1082 .remove = enetc4_pf_remove, 1083 }; 1084 module_pci_driver(enetc4_pf_driver); 1085 1086 MODULE_DESCRIPTION("ENETC4 PF Driver"); 1087 MODULE_LICENSE("Dual BSD/GPL"); 1088