1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ 2 /* 3 * This header file defines the register offsets and bit fields 4 * of ENETC4 PF and VFs. Note that the same registers as ENETC 5 * version 1.0 are defined in the enetc_hw.h file. 6 * 7 * Copyright 2024 NXP 8 */ 9 #ifndef __ENETC4_HW_H_ 10 #define __ENETC4_HW_H_ 11 12 #define NXP_ENETC_VENDOR_ID 0x1131 13 #define NXP_ENETC_PF_DEV_ID 0xe101 14 15 /***************************ENETC port registers**************************/ 16 #define ENETC4_ECAPR0 0x0 17 #define ECAPR0_RFS BIT(2) 18 #define ECAPR0_TSD BIT(5) 19 #define ECAPR0_RSS BIT(8) 20 #define ECAPR0_RSC BIT(9) 21 #define ECAPR0_LSO BIT(10) 22 #define ECAPR0_WO BIT(13) 23 24 #define ENETC4_ECAPR1 0x4 25 #define ECAPR1_NUM_TCS GENMASK(6, 4) 26 #define ECAPR1_NUM_MCH GENMASK(9, 8) 27 #define ECAPR1_NUM_UCH GENMASK(11, 10) 28 #define ECAPR1_NUM_MSIX GENMASK(22, 12) 29 #define ECAPR1_NUM_VSI GENMASK(27, 24) 30 #define ECAPR1_NUM_IPV BIT(31) 31 32 #define ENETC4_ECAPR2 0x8 33 #define ECAPR2_NUM_TX_BDR GENMASK(9, 0) 34 #define ECAPR2_NUM_RX_BDR GENMASK(25, 16) 35 36 #define ENETC4_PMR 0x10 37 #define PMR_SI_EN(a) BIT((16 + (a))) 38 39 /* Port Pause ON/OFF threshold register */ 40 #define ENETC4_PPAUONTR 0x108 41 #define ENETC4_PPAUOFFTR 0x10c 42 43 /* Port Station interface promiscuous MAC mode register */ 44 #define ENETC4_PSIPMMR 0x200 45 #define PSIPMMR_SI_MAC_UP(a) BIT(a) /* a = SI index */ 46 #define PSIPMMR_SI_MAC_MP(a) BIT((a) + 16) 47 48 /* Port Station interface promiscuous VLAN mode register */ 49 #define ENETC4_PSIPVMR 0x204 50 51 /* Port RSS key register n. n = 0,1,2,...,9 */ 52 #define ENETC4_PRSSKR(n) ((n) * 0x4 + 0x250) 53 54 /* Port station interface MAC address filtering capability register */ 55 #define ENETC4_PSIMAFCAPR 0x280 56 #define PSIMAFCAPR_NUM_MAC_AFTE GENMASK(11, 0) 57 58 /* Port station interface VLAN filtering capability register */ 59 #define ENETC4_PSIVLANFCAPR 0x2c0 60 #define PSIVLANFCAPR_NUM_VLAN_FTE GENMASK(11, 0) 61 62 /* Port station interface VLAN filtering mode register */ 63 #define ENETC4_PSIVLANFMR 0x2c4 64 #define PSIVLANFMR_VS BIT(0) 65 66 /* Port Station interface a primary MAC address registers */ 67 #define ENETC4_PSIPMAR0(a) ((a) * 0x80 + 0x2000) 68 #define ENETC4_PSIPMAR1(a) ((a) * 0x80 + 0x2004) 69 70 /* Port station interface a configuration register 0/2 */ 71 #define ENETC4_PSICFGR0(a) ((a) * 0x80 + 0x2010) 72 #define PSICFGR0_VASE BIT(13) 73 #define PSICFGR0_ASE BIT(15) 74 #define PSICFGR0_ANTI_SPOOFING (PSICFGR0_VASE | PSICFGR0_ASE) 75 76 #define ENETC4_PSICFGR2(a) ((a) * 0x80 + 0x2018) 77 #define PSICFGR2_NUM_MSIX GENMASK(5, 0) 78 79 #define ENETC4_PMCAPR 0x4004 80 #define PMCAPR_HD BIT(8) 81 #define PMCAPR_FP GENMASK(10, 9) 82 83 /* Port configuration register */ 84 #define ENETC4_PCR 0x4010 85 #define PCR_HDR_FMT BIT(0) 86 #define PCR_L2DOSE BIT(4) 87 #define PCR_TIMER_CS BIT(8) 88 #define PCR_PSPEED GENMASK(29, 16) 89 #define PCR_PSPEED_VAL(speed) (((speed) / 10 - 1) << 16) 90 91 /* Port MAC address register 0/1 */ 92 #define ENETC4_PMAR0 0x4020 93 #define ENETC4_PMAR1 0x4024 94 95 /* Port operational register */ 96 #define ENETC4_POR 0x4100 97 98 /* Port traffic class a transmit maximum SDU register */ 99 #define ENETC4_PTCTMSDUR(a) ((a) * 0x20 + 0x4208) 100 #define PTCTMSDUR_MAXSDU GENMASK(15, 0) 101 #define PTCTMSDUR_SDU_TYPE GENMASK(17, 16) 102 #define SDU_TYPE_PPDU 0 103 #define SDU_TYPE_MPDU 1 104 #define SDU_TYPE_MSDU 2 105 106 #define ENETC4_PMAC_OFFSET 0x400 107 #define ENETC4_PM_CMD_CFG(mac) (0x5008 + (mac) * 0x400) 108 #define PM_CMD_CFG_TX_EN BIT(0) 109 #define PM_CMD_CFG_RX_EN BIT(1) 110 #define PM_CMD_CFG_PAUSE_FWD BIT(7) 111 #define PM_CMD_CFG_PAUSE_IGN BIT(8) 112 #define PM_CMD_CFG_TX_ADDR_INS BIT(9) 113 #define PM_CMD_CFG_LOOP_EN BIT(10) 114 #define PM_CMD_CFG_LPBK_MODE GENMASK(12, 11) 115 #define LPBCK_MODE_EXT_TX_CLK 0 116 #define LPBCK_MODE_MAC_LEVEL 1 117 #define LPBCK_MODE_INT_TX_CLK 2 118 #define PM_CMD_CFG_CNT_FRM_EN BIT(13) 119 #define PM_CMD_CFG_TXP BIT(15) 120 #define PM_CMD_CFG_SEND_IDLE BIT(16) 121 #define PM_CMD_CFG_HD_FCEN BIT(18) 122 #define PM_CMD_CFG_SFD BIT(21) 123 #define PM_CMD_CFG_TX_FLUSH BIT(22) 124 #define PM_CMD_CFG_TX_LOWP_EN BIT(23) 125 #define PM_CMD_CFG_RX_LOWP_EMPTY BIT(24) 126 #define PM_CMD_CFG_SWR BIT(26) 127 #define PM_CMD_CFG_TS_MODE BIT(30) 128 #define PM_CMD_CFG_MG BIT(31) 129 130 /* Port MAC 0/1 Maximum Frame Length Register */ 131 #define ENETC4_PM_MAXFRM(mac) (0x5014 + (mac) * 0x400) 132 133 /* Port MAC 0/1 Pause Quanta Register */ 134 #define ENETC4_PM_PAUSE_QUANTA(mac) (0x5054 + (mac) * 0x400) 135 136 /* Port MAC 0/1 Pause Quanta Threshold Register */ 137 #define ENETC4_PM_PAUSE_THRESH(mac) (0x5064 + (mac) * 0x400) 138 139 /* Port MAC 0 Interface Mode Control Register */ 140 #define ENETC4_PM_IF_MODE(mac) (0x5300 + (mac) * 0x400) 141 #define PM_IF_MODE_IFMODE GENMASK(2, 0) 142 #define IFMODE_XGMII 0 143 #define IFMODE_RMII 3 144 #define IFMODE_RGMII 4 145 #define IFMODE_SGMII 5 146 #define PM_IF_MODE_REVMII BIT(3) 147 #define PM_IF_MODE_M10 BIT(4) 148 #define PM_IF_MODE_HD BIT(6) 149 #define PM_IF_MODE_SSP GENMASK(14, 13) 150 #define SSP_100M 0 151 #define SSP_10M 1 152 #define SSP_1G 2 153 #define PM_IF_MODE_ENA BIT(15) 154 155 #endif 156