1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2 /* Copyright 2017-2019 NXP */ 3 4 #include "enetc.h" 5 #include <linux/bpf_trace.h> 6 #include <linux/clk.h> 7 #include <linux/tcp.h> 8 #include <linux/udp.h> 9 #include <linux/vmalloc.h> 10 #include <linux/ptp_classify.h> 11 #include <net/ip6_checksum.h> 12 #include <net/pkt_sched.h> 13 #include <net/tso.h> 14 15 u32 enetc_port_mac_rd(struct enetc_si *si, u32 reg) 16 { 17 return enetc_port_rd(&si->hw, reg); 18 } 19 EXPORT_SYMBOL_GPL(enetc_port_mac_rd); 20 21 void enetc_port_mac_wr(struct enetc_si *si, u32 reg, u32 val) 22 { 23 enetc_port_wr(&si->hw, reg, val); 24 if (si->hw_features & ENETC_SI_F_QBU) 25 enetc_port_wr(&si->hw, reg + si->drvdata->pmac_offset, val); 26 } 27 EXPORT_SYMBOL_GPL(enetc_port_mac_wr); 28 29 static void enetc_change_preemptible_tcs(struct enetc_ndev_priv *priv, 30 u8 preemptible_tcs) 31 { 32 if (!(priv->si->hw_features & ENETC_SI_F_QBU)) 33 return; 34 35 priv->preemptible_tcs = preemptible_tcs; 36 enetc_mm_commit_preemptible_tcs(priv); 37 } 38 39 static int enetc_mac_addr_hash_idx(const u8 *addr) 40 { 41 u64 fold = __swab64(ether_addr_to_u64(addr)) >> 16; 42 u64 mask = 0; 43 int res = 0; 44 int i; 45 46 for (i = 0; i < 8; i++) 47 mask |= BIT_ULL(i * 6); 48 49 for (i = 0; i < 6; i++) 50 res |= (hweight64(fold & (mask << i)) & 0x1) << i; 51 52 return res; 53 } 54 55 void enetc_add_mac_addr_ht_filter(struct enetc_mac_filter *filter, 56 const unsigned char *addr) 57 { 58 int idx = enetc_mac_addr_hash_idx(addr); 59 60 /* add hash table entry */ 61 __set_bit(idx, filter->mac_hash_table); 62 filter->mac_addr_cnt++; 63 } 64 EXPORT_SYMBOL_GPL(enetc_add_mac_addr_ht_filter); 65 66 void enetc_reset_mac_addr_filter(struct enetc_mac_filter *filter) 67 { 68 filter->mac_addr_cnt = 0; 69 70 bitmap_zero(filter->mac_hash_table, 71 ENETC_MADDR_HASH_TBL_SZ); 72 } 73 EXPORT_SYMBOL_GPL(enetc_reset_mac_addr_filter); 74 75 static int enetc_num_stack_tx_queues(struct enetc_ndev_priv *priv) 76 { 77 int num_tx_rings = priv->num_tx_rings; 78 79 if (priv->xdp_prog) 80 return num_tx_rings - num_possible_cpus(); 81 82 return num_tx_rings; 83 } 84 85 static struct enetc_bdr *enetc_rx_ring_from_xdp_tx_ring(struct enetc_ndev_priv *priv, 86 struct enetc_bdr *tx_ring) 87 { 88 int index = &priv->tx_ring[tx_ring->index] - priv->xdp_tx_ring; 89 90 return priv->rx_ring[index]; 91 } 92 93 static struct sk_buff *enetc_tx_swbd_get_skb(struct enetc_tx_swbd *tx_swbd) 94 { 95 if (tx_swbd->is_xdp_tx || tx_swbd->is_xdp_redirect) 96 return NULL; 97 98 return tx_swbd->skb; 99 } 100 101 static struct xdp_frame * 102 enetc_tx_swbd_get_xdp_frame(struct enetc_tx_swbd *tx_swbd) 103 { 104 if (tx_swbd->is_xdp_redirect) 105 return tx_swbd->xdp_frame; 106 107 return NULL; 108 } 109 110 static void enetc_unmap_tx_buff(struct enetc_bdr *tx_ring, 111 struct enetc_tx_swbd *tx_swbd) 112 { 113 /* For XDP_TX, pages come from RX, whereas for the other contexts where 114 * we have is_dma_page_set, those come from skb_frag_dma_map. We need 115 * to match the DMA mapping length, so we need to differentiate those. 116 */ 117 if (tx_swbd->is_dma_page) 118 dma_unmap_page(tx_ring->dev, tx_swbd->dma, 119 tx_swbd->is_xdp_tx ? PAGE_SIZE : tx_swbd->len, 120 tx_swbd->dir); 121 else 122 dma_unmap_single(tx_ring->dev, tx_swbd->dma, 123 tx_swbd->len, tx_swbd->dir); 124 tx_swbd->dma = 0; 125 } 126 127 static void enetc_free_tx_frame(struct enetc_bdr *tx_ring, 128 struct enetc_tx_swbd *tx_swbd) 129 { 130 struct xdp_frame *xdp_frame = enetc_tx_swbd_get_xdp_frame(tx_swbd); 131 struct sk_buff *skb = enetc_tx_swbd_get_skb(tx_swbd); 132 133 if (tx_swbd->dma) 134 enetc_unmap_tx_buff(tx_ring, tx_swbd); 135 136 if (xdp_frame) { 137 xdp_return_frame(tx_swbd->xdp_frame); 138 tx_swbd->xdp_frame = NULL; 139 } else if (skb) { 140 dev_kfree_skb_any(skb); 141 tx_swbd->skb = NULL; 142 } 143 } 144 145 /* Let H/W know BD ring has been updated */ 146 static void enetc_update_tx_ring_tail(struct enetc_bdr *tx_ring) 147 { 148 /* includes wmb() */ 149 enetc_wr_reg_hot(tx_ring->tpir, tx_ring->next_to_use); 150 } 151 152 static int enetc_ptp_parse(struct sk_buff *skb, u8 *udp, 153 u8 *msgtype, u8 *twostep, 154 u16 *correction_offset, u16 *body_offset) 155 { 156 unsigned int ptp_class; 157 struct ptp_header *hdr; 158 unsigned int type; 159 u8 *base; 160 161 ptp_class = ptp_classify_raw(skb); 162 if (ptp_class == PTP_CLASS_NONE) 163 return -EINVAL; 164 165 hdr = ptp_parse_header(skb, ptp_class); 166 if (!hdr) 167 return -EINVAL; 168 169 type = ptp_class & PTP_CLASS_PMASK; 170 if (type == PTP_CLASS_IPV4 || type == PTP_CLASS_IPV6) 171 *udp = 1; 172 else 173 *udp = 0; 174 175 *msgtype = ptp_get_msgtype(hdr, ptp_class); 176 *twostep = hdr->flag_field[0] & 0x2; 177 178 base = skb_mac_header(skb); 179 *correction_offset = (u8 *)&hdr->correction - base; 180 *body_offset = (u8 *)hdr + sizeof(struct ptp_header) - base; 181 182 return 0; 183 } 184 185 static bool enetc_tx_csum_offload_check(struct sk_buff *skb) 186 { 187 switch (skb->csum_offset) { 188 case offsetof(struct tcphdr, check): 189 case offsetof(struct udphdr, check): 190 return true; 191 default: 192 return false; 193 } 194 } 195 196 static bool enetc_skb_is_ipv6(struct sk_buff *skb) 197 { 198 return vlan_get_protocol(skb) == htons(ETH_P_IPV6); 199 } 200 201 static bool enetc_skb_is_tcp(struct sk_buff *skb) 202 { 203 return skb->csum_offset == offsetof(struct tcphdr, check); 204 } 205 206 /** 207 * enetc_unwind_tx_frame() - Unwind the DMA mappings of a multi-buffer Tx frame 208 * @tx_ring: Pointer to the Tx ring on which the buffer descriptors are located 209 * @count: Number of Tx buffer descriptors which need to be unmapped 210 * @i: Index of the last successfully mapped Tx buffer descriptor 211 */ 212 static void enetc_unwind_tx_frame(struct enetc_bdr *tx_ring, int count, int i) 213 { 214 while (count--) { 215 struct enetc_tx_swbd *tx_swbd = &tx_ring->tx_swbd[i]; 216 217 enetc_free_tx_frame(tx_ring, tx_swbd); 218 if (i == 0) 219 i = tx_ring->bd_count; 220 i--; 221 } 222 } 223 224 static void enetc_set_one_step_ts(struct enetc_si *si, bool udp, int offset) 225 { 226 u32 val = ENETC_PM0_SINGLE_STEP_EN; 227 228 val |= ENETC_SET_SINGLE_STEP_OFFSET(offset); 229 if (udp) 230 val |= ENETC_PM0_SINGLE_STEP_CH; 231 232 /* The "Correction" field of a packet is updated based on the 233 * current time and the timestamp provided 234 */ 235 enetc_port_mac_wr(si, ENETC_PM0_SINGLE_STEP, val); 236 } 237 238 static void enetc4_set_one_step_ts(struct enetc_si *si, bool udp, int offset) 239 { 240 u32 val = PM_SINGLE_STEP_EN; 241 242 val |= PM_SINGLE_STEP_OFFSET_SET(offset); 243 if (udp) 244 val |= PM_SINGLE_STEP_CH; 245 246 enetc_port_mac_wr(si, ENETC4_PM_SINGLE_STEP(0), val); 247 } 248 249 static u32 enetc_update_ptp_sync_msg(struct enetc_ndev_priv *priv, 250 struct sk_buff *skb, bool csum_offload) 251 { 252 struct enetc_skb_cb *enetc_cb = ENETC_SKB_CB(skb); 253 u16 tstamp_off = enetc_cb->origin_tstamp_off; 254 u16 corr_off = enetc_cb->correction_off; 255 struct enetc_si *si = priv->si; 256 struct enetc_hw *hw = &si->hw; 257 __be32 new_sec_l, new_nsec; 258 __be16 new_sec_h; 259 u32 lo, hi, nsec; 260 u8 *data; 261 u64 sec; 262 263 lo = enetc_rd_hot(hw, ENETC_SICTR0); 264 hi = enetc_rd_hot(hw, ENETC_SICTR1); 265 sec = (u64)hi << 32 | lo; 266 nsec = do_div(sec, 1000000000); 267 268 /* Update originTimestamp field of Sync packet 269 * - 48 bits seconds field 270 * - 32 bits nanseconds field 271 * 272 * In addition, if csum_offload is false, the UDP checksum needs 273 * to be updated by software after updating originTimestamp field, 274 * otherwise the hardware will calculate the wrong checksum when 275 * updating the correction field and update it to the packet. 276 */ 277 278 data = skb_mac_header(skb); 279 new_sec_h = htons((sec >> 32) & 0xffff); 280 new_sec_l = htonl(sec & 0xffffffff); 281 new_nsec = htonl(nsec); 282 if (enetc_cb->udp && !csum_offload) { 283 struct udphdr *uh = udp_hdr(skb); 284 __be32 old_sec_l, old_nsec; 285 __be16 old_sec_h; 286 287 old_sec_h = *(__be16 *)(data + tstamp_off); 288 inet_proto_csum_replace2(&uh->check, skb, old_sec_h, 289 new_sec_h, false); 290 291 old_sec_l = *(__be32 *)(data + tstamp_off + 2); 292 inet_proto_csum_replace4(&uh->check, skb, old_sec_l, 293 new_sec_l, false); 294 295 old_nsec = *(__be32 *)(data + tstamp_off + 6); 296 inet_proto_csum_replace4(&uh->check, skb, old_nsec, 297 new_nsec, false); 298 } 299 300 *(__be16 *)(data + tstamp_off) = new_sec_h; 301 *(__be32 *)(data + tstamp_off + 2) = new_sec_l; 302 *(__be32 *)(data + tstamp_off + 6) = new_nsec; 303 304 /* Configure single-step register */ 305 if (is_enetc_rev1(si)) 306 enetc_set_one_step_ts(si, enetc_cb->udp, corr_off); 307 else 308 enetc4_set_one_step_ts(si, enetc_cb->udp, corr_off); 309 310 return lo & ENETC_TXBD_TSTAMP; 311 } 312 313 static int enetc_map_tx_buffs(struct enetc_bdr *tx_ring, struct sk_buff *skb) 314 { 315 bool do_vlan, do_onestep_tstamp = false, do_twostep_tstamp = false; 316 struct enetc_ndev_priv *priv = netdev_priv(tx_ring->ndev); 317 struct enetc_skb_cb *enetc_cb = ENETC_SKB_CB(skb); 318 struct enetc_tx_swbd *tx_swbd; 319 int len = skb_headlen(skb); 320 union enetc_tx_bd temp_bd; 321 bool csum_offload = false; 322 union enetc_tx_bd *txbd; 323 int i, count = 0; 324 skb_frag_t *frag; 325 unsigned int f; 326 dma_addr_t dma; 327 u8 flags = 0; 328 u32 tstamp; 329 330 enetc_clear_tx_bd(&temp_bd); 331 if (skb->ip_summed == CHECKSUM_PARTIAL) { 332 /* Can not support TSD and checksum offload at the same time */ 333 if (priv->active_offloads & ENETC_F_TXCSUM && 334 enetc_tx_csum_offload_check(skb) && !tx_ring->tsd_enable) { 335 temp_bd.l3_aux0 = FIELD_PREP(ENETC_TX_BD_L3_START, 336 skb_network_offset(skb)); 337 temp_bd.l3_aux1 = FIELD_PREP(ENETC_TX_BD_L3_HDR_LEN, 338 skb_network_header_len(skb) / 4); 339 temp_bd.l3_aux1 |= FIELD_PREP(ENETC_TX_BD_L3T, 340 enetc_skb_is_ipv6(skb)); 341 if (enetc_skb_is_tcp(skb)) 342 temp_bd.l4_aux = FIELD_PREP(ENETC_TX_BD_L4T, 343 ENETC_TXBD_L4T_TCP); 344 else 345 temp_bd.l4_aux = FIELD_PREP(ENETC_TX_BD_L4T, 346 ENETC_TXBD_L4T_UDP); 347 flags |= ENETC_TXBD_FLAGS_CSUM_LSO | ENETC_TXBD_FLAGS_L4CS; 348 csum_offload = true; 349 } else if (skb_checksum_help(skb)) { 350 return 0; 351 } 352 } 353 354 if (enetc_cb->flag & ENETC_F_TX_ONESTEP_SYNC_TSTAMP) { 355 do_onestep_tstamp = true; 356 tstamp = enetc_update_ptp_sync_msg(priv, skb, csum_offload); 357 } else if (enetc_cb->flag & ENETC_F_TX_TSTAMP) { 358 do_twostep_tstamp = true; 359 } 360 361 i = tx_ring->next_to_use; 362 txbd = ENETC_TXBD(*tx_ring, i); 363 prefetchw(txbd); 364 365 dma = dma_map_single(tx_ring->dev, skb->data, len, DMA_TO_DEVICE); 366 if (unlikely(dma_mapping_error(tx_ring->dev, dma))) 367 goto dma_err; 368 369 temp_bd.addr = cpu_to_le64(dma); 370 temp_bd.buf_len = cpu_to_le16(len); 371 372 tx_swbd = &tx_ring->tx_swbd[i]; 373 tx_swbd->dma = dma; 374 tx_swbd->len = len; 375 tx_swbd->is_dma_page = 0; 376 tx_swbd->dir = DMA_TO_DEVICE; 377 count++; 378 379 do_vlan = skb_vlan_tag_present(skb); 380 tx_swbd->do_twostep_tstamp = do_twostep_tstamp; 381 tx_swbd->qbv_en = !!(priv->active_offloads & ENETC_F_QBV); 382 tx_swbd->check_wb = tx_swbd->do_twostep_tstamp || tx_swbd->qbv_en; 383 384 if (do_vlan || do_onestep_tstamp || do_twostep_tstamp) 385 flags |= ENETC_TXBD_FLAGS_EX; 386 387 if (tx_ring->tsd_enable) 388 flags |= ENETC_TXBD_FLAGS_TSE | ENETC_TXBD_FLAGS_TXSTART; 389 390 /* first BD needs frm_len and offload flags set */ 391 temp_bd.frm_len = cpu_to_le16(skb->len); 392 temp_bd.flags = flags; 393 394 if (flags & ENETC_TXBD_FLAGS_TSE) 395 temp_bd.txstart = enetc_txbd_set_tx_start(skb->skb_mstamp_ns, 396 flags); 397 398 if (flags & ENETC_TXBD_FLAGS_EX) { 399 u8 e_flags = 0; 400 *txbd = temp_bd; 401 enetc_clear_tx_bd(&temp_bd); 402 403 /* add extension BD for VLAN and/or timestamping */ 404 flags = 0; 405 tx_swbd++; 406 txbd++; 407 i++; 408 if (unlikely(i == tx_ring->bd_count)) { 409 i = 0; 410 tx_swbd = tx_ring->tx_swbd; 411 txbd = ENETC_TXBD(*tx_ring, 0); 412 } 413 prefetchw(txbd); 414 415 if (do_vlan) { 416 temp_bd.ext.vid = cpu_to_le16(skb_vlan_tag_get(skb)); 417 temp_bd.ext.tpid = 0; /* < C-TAG */ 418 e_flags |= ENETC_TXBD_E_FLAGS_VLAN_INS; 419 } 420 421 if (do_onestep_tstamp) { 422 /* Configure extension BD */ 423 temp_bd.ext.tstamp = cpu_to_le32(tstamp); 424 e_flags |= ENETC_TXBD_E_FLAGS_ONE_STEP_PTP; 425 } else if (do_twostep_tstamp) { 426 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 427 e_flags |= ENETC_TXBD_E_FLAGS_TWO_STEP_PTP; 428 } 429 430 temp_bd.ext.e_flags = e_flags; 431 count++; 432 } 433 434 frag = &skb_shinfo(skb)->frags[0]; 435 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++, frag++) { 436 len = skb_frag_size(frag); 437 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, len, 438 DMA_TO_DEVICE); 439 if (dma_mapping_error(tx_ring->dev, dma)) 440 goto dma_err; 441 442 *txbd = temp_bd; 443 enetc_clear_tx_bd(&temp_bd); 444 445 flags = 0; 446 tx_swbd++; 447 txbd++; 448 i++; 449 if (unlikely(i == tx_ring->bd_count)) { 450 i = 0; 451 tx_swbd = tx_ring->tx_swbd; 452 txbd = ENETC_TXBD(*tx_ring, 0); 453 } 454 prefetchw(txbd); 455 456 temp_bd.addr = cpu_to_le64(dma); 457 temp_bd.buf_len = cpu_to_le16(len); 458 459 tx_swbd->dma = dma; 460 tx_swbd->len = len; 461 tx_swbd->is_dma_page = 1; 462 tx_swbd->dir = DMA_TO_DEVICE; 463 count++; 464 } 465 466 /* last BD needs 'F' bit set */ 467 flags |= ENETC_TXBD_FLAGS_F; 468 temp_bd.flags = flags; 469 *txbd = temp_bd; 470 471 tx_ring->tx_swbd[i].is_eof = true; 472 tx_ring->tx_swbd[i].skb = skb; 473 474 enetc_bdr_idx_inc(tx_ring, &i); 475 tx_ring->next_to_use = i; 476 477 skb_tx_timestamp(skb); 478 479 enetc_update_tx_ring_tail(tx_ring); 480 481 return count; 482 483 dma_err: 484 dev_err(tx_ring->dev, "DMA map error"); 485 486 enetc_unwind_tx_frame(tx_ring, count, i); 487 488 return 0; 489 } 490 491 static int enetc_map_tx_tso_hdr(struct enetc_bdr *tx_ring, struct sk_buff *skb, 492 struct enetc_tx_swbd *tx_swbd, 493 union enetc_tx_bd *txbd, int *i, int hdr_len, 494 int data_len) 495 { 496 union enetc_tx_bd txbd_tmp; 497 u8 flags = 0, e_flags = 0; 498 dma_addr_t addr; 499 int count = 1; 500 501 enetc_clear_tx_bd(&txbd_tmp); 502 addr = tx_ring->tso_headers_dma + *i * TSO_HEADER_SIZE; 503 504 if (skb_vlan_tag_present(skb)) 505 flags |= ENETC_TXBD_FLAGS_EX; 506 507 txbd_tmp.addr = cpu_to_le64(addr); 508 txbd_tmp.buf_len = cpu_to_le16(hdr_len); 509 510 /* first BD needs frm_len and offload flags set */ 511 txbd_tmp.frm_len = cpu_to_le16(hdr_len + data_len); 512 txbd_tmp.flags = flags; 513 514 /* For the TSO header we do not set the dma address since we do not 515 * want it unmapped when we do cleanup. We still set len so that we 516 * count the bytes sent. 517 */ 518 tx_swbd->len = hdr_len; 519 tx_swbd->do_twostep_tstamp = false; 520 tx_swbd->check_wb = false; 521 522 /* Actually write the header in the BD */ 523 *txbd = txbd_tmp; 524 525 /* Add extension BD for VLAN */ 526 if (flags & ENETC_TXBD_FLAGS_EX) { 527 /* Get the next BD */ 528 enetc_bdr_idx_inc(tx_ring, i); 529 txbd = ENETC_TXBD(*tx_ring, *i); 530 tx_swbd = &tx_ring->tx_swbd[*i]; 531 prefetchw(txbd); 532 533 /* Setup the VLAN fields */ 534 enetc_clear_tx_bd(&txbd_tmp); 535 txbd_tmp.ext.vid = cpu_to_le16(skb_vlan_tag_get(skb)); 536 txbd_tmp.ext.tpid = 0; /* < C-TAG */ 537 e_flags |= ENETC_TXBD_E_FLAGS_VLAN_INS; 538 539 /* Write the BD */ 540 txbd_tmp.ext.e_flags = e_flags; 541 *txbd = txbd_tmp; 542 count++; 543 } 544 545 return count; 546 } 547 548 static int enetc_map_tx_tso_data(struct enetc_bdr *tx_ring, struct sk_buff *skb, 549 struct enetc_tx_swbd *tx_swbd, 550 union enetc_tx_bd *txbd, char *data, 551 int size, bool last_bd) 552 { 553 union enetc_tx_bd txbd_tmp; 554 dma_addr_t addr; 555 u8 flags = 0; 556 557 enetc_clear_tx_bd(&txbd_tmp); 558 559 addr = dma_map_single(tx_ring->dev, data, size, DMA_TO_DEVICE); 560 if (unlikely(dma_mapping_error(tx_ring->dev, addr))) { 561 netdev_err(tx_ring->ndev, "DMA map error\n"); 562 return -ENOMEM; 563 } 564 565 if (last_bd) { 566 flags |= ENETC_TXBD_FLAGS_F; 567 tx_swbd->is_eof = 1; 568 } 569 570 txbd_tmp.addr = cpu_to_le64(addr); 571 txbd_tmp.buf_len = cpu_to_le16(size); 572 txbd_tmp.flags = flags; 573 574 tx_swbd->dma = addr; 575 tx_swbd->len = size; 576 tx_swbd->dir = DMA_TO_DEVICE; 577 578 *txbd = txbd_tmp; 579 580 return 0; 581 } 582 583 static __wsum enetc_tso_hdr_csum(struct tso_t *tso, struct sk_buff *skb, 584 char *hdr, int hdr_len, int *l4_hdr_len) 585 { 586 char *l4_hdr = hdr + skb_transport_offset(skb); 587 int mac_hdr_len = skb_network_offset(skb); 588 589 if (tso->tlen != sizeof(struct udphdr)) { 590 struct tcphdr *tcph = (struct tcphdr *)(l4_hdr); 591 592 tcph->check = 0; 593 } else { 594 struct udphdr *udph = (struct udphdr *)(l4_hdr); 595 596 udph->check = 0; 597 } 598 599 /* Compute the IP checksum. This is necessary since tso_build_hdr() 600 * already incremented the IP ID field. 601 */ 602 if (!tso->ipv6) { 603 struct iphdr *iph = (void *)(hdr + mac_hdr_len); 604 605 iph->check = 0; 606 iph->check = ip_fast_csum((unsigned char *)iph, iph->ihl); 607 } 608 609 /* Compute the checksum over the L4 header. */ 610 *l4_hdr_len = hdr_len - skb_transport_offset(skb); 611 return csum_partial(l4_hdr, *l4_hdr_len, 0); 612 } 613 614 static void enetc_tso_complete_csum(struct enetc_bdr *tx_ring, struct tso_t *tso, 615 struct sk_buff *skb, char *hdr, int len, 616 __wsum sum) 617 { 618 char *l4_hdr = hdr + skb_transport_offset(skb); 619 __sum16 csum_final; 620 621 /* Complete the L4 checksum by appending the pseudo-header to the 622 * already computed checksum. 623 */ 624 if (!tso->ipv6) 625 csum_final = csum_tcpudp_magic(ip_hdr(skb)->saddr, 626 ip_hdr(skb)->daddr, 627 len, ip_hdr(skb)->protocol, sum); 628 else 629 csum_final = csum_ipv6_magic(&ipv6_hdr(skb)->saddr, 630 &ipv6_hdr(skb)->daddr, 631 len, ipv6_hdr(skb)->nexthdr, sum); 632 633 if (tso->tlen != sizeof(struct udphdr)) { 634 struct tcphdr *tcph = (struct tcphdr *)(l4_hdr); 635 636 tcph->check = csum_final; 637 } else { 638 struct udphdr *udph = (struct udphdr *)(l4_hdr); 639 640 udph->check = csum_final; 641 } 642 } 643 644 static int enetc_lso_count_descs(const struct sk_buff *skb) 645 { 646 /* 4 BDs: 1 BD for LSO header + 1 BD for extended BD + 1 BD 647 * for linear area data but not include LSO header, namely 648 * skb_headlen(skb) - lso_hdr_len (it may be 0, but that's 649 * okay, we only need to consider the worst case). And 1 BD 650 * for gap. 651 */ 652 return skb_shinfo(skb)->nr_frags + 4; 653 } 654 655 static int enetc_lso_get_hdr_len(const struct sk_buff *skb) 656 { 657 int hdr_len, tlen; 658 659 tlen = skb_is_gso_tcp(skb) ? tcp_hdrlen(skb) : sizeof(struct udphdr); 660 hdr_len = skb_transport_offset(skb) + tlen; 661 662 return hdr_len; 663 } 664 665 static void enetc_lso_start(struct sk_buff *skb, struct enetc_lso_t *lso) 666 { 667 lso->lso_seg_size = skb_shinfo(skb)->gso_size; 668 lso->ipv6 = enetc_skb_is_ipv6(skb); 669 lso->tcp = skb_is_gso_tcp(skb); 670 lso->l3_hdr_len = skb_network_header_len(skb); 671 lso->l3_start = skb_network_offset(skb); 672 lso->hdr_len = enetc_lso_get_hdr_len(skb); 673 lso->total_len = skb->len - lso->hdr_len; 674 } 675 676 static void enetc_lso_map_hdr(struct enetc_bdr *tx_ring, struct sk_buff *skb, 677 int *i, struct enetc_lso_t *lso) 678 { 679 union enetc_tx_bd txbd_tmp, *txbd; 680 struct enetc_tx_swbd *tx_swbd; 681 u16 frm_len, frm_len_ext; 682 u8 flags, e_flags = 0; 683 dma_addr_t addr; 684 char *hdr; 685 686 /* Get the first BD of the LSO BDs chain */ 687 txbd = ENETC_TXBD(*tx_ring, *i); 688 tx_swbd = &tx_ring->tx_swbd[*i]; 689 prefetchw(txbd); 690 691 /* Prepare LSO header: MAC + IP + TCP/UDP */ 692 hdr = tx_ring->tso_headers + *i * TSO_HEADER_SIZE; 693 memcpy(hdr, skb->data, lso->hdr_len); 694 addr = tx_ring->tso_headers_dma + *i * TSO_HEADER_SIZE; 695 696 /* {frm_len_ext, frm_len} indicates the total length of 697 * large transmit data unit. frm_len contains the 16 least 698 * significant bits and frm_len_ext contains the 4 most 699 * significant bits. 700 */ 701 frm_len = lso->total_len & 0xffff; 702 frm_len_ext = (lso->total_len >> 16) & 0xf; 703 704 /* Set the flags of the first BD */ 705 flags = ENETC_TXBD_FLAGS_EX | ENETC_TXBD_FLAGS_CSUM_LSO | 706 ENETC_TXBD_FLAGS_LSO | ENETC_TXBD_FLAGS_L4CS; 707 708 enetc_clear_tx_bd(&txbd_tmp); 709 txbd_tmp.addr = cpu_to_le64(addr); 710 txbd_tmp.hdr_len = cpu_to_le16(lso->hdr_len); 711 712 /* first BD needs frm_len and offload flags set */ 713 txbd_tmp.frm_len = cpu_to_le16(frm_len); 714 txbd_tmp.flags = flags; 715 716 txbd_tmp.l3_aux0 = FIELD_PREP(ENETC_TX_BD_L3_START, lso->l3_start); 717 /* l3_hdr_size in 32-bits (4 bytes) */ 718 txbd_tmp.l3_aux1 = FIELD_PREP(ENETC_TX_BD_L3_HDR_LEN, 719 lso->l3_hdr_len / 4); 720 if (lso->ipv6) 721 txbd_tmp.l3_aux1 |= ENETC_TX_BD_L3T; 722 else 723 txbd_tmp.l3_aux0 |= ENETC_TX_BD_IPCS; 724 725 txbd_tmp.l4_aux = FIELD_PREP(ENETC_TX_BD_L4T, lso->tcp ? 726 ENETC_TXBD_L4T_TCP : ENETC_TXBD_L4T_UDP); 727 728 /* For the LSO header we do not set the dma address since 729 * we do not want it unmapped when we do cleanup. We still 730 * set len so that we count the bytes sent. 731 */ 732 tx_swbd->len = lso->hdr_len; 733 tx_swbd->do_twostep_tstamp = false; 734 tx_swbd->check_wb = false; 735 736 /* Actually write the header in the BD */ 737 *txbd = txbd_tmp; 738 739 /* Get the next BD, and the next BD is extended BD */ 740 enetc_bdr_idx_inc(tx_ring, i); 741 txbd = ENETC_TXBD(*tx_ring, *i); 742 tx_swbd = &tx_ring->tx_swbd[*i]; 743 prefetchw(txbd); 744 745 enetc_clear_tx_bd(&txbd_tmp); 746 if (skb_vlan_tag_present(skb)) { 747 /* Setup the VLAN fields */ 748 txbd_tmp.ext.vid = cpu_to_le16(skb_vlan_tag_get(skb)); 749 txbd_tmp.ext.tpid = ENETC_TPID_8021Q; 750 e_flags = ENETC_TXBD_E_FLAGS_VLAN_INS; 751 } 752 753 /* Write the BD */ 754 txbd_tmp.ext.e_flags = e_flags; 755 txbd_tmp.ext.lso_sg_size = cpu_to_le16(lso->lso_seg_size); 756 txbd_tmp.ext.frm_len_ext = cpu_to_le16(frm_len_ext); 757 *txbd = txbd_tmp; 758 } 759 760 static int enetc_lso_map_data(struct enetc_bdr *tx_ring, struct sk_buff *skb, 761 int *i, struct enetc_lso_t *lso, int *count) 762 { 763 union enetc_tx_bd txbd_tmp, *txbd = NULL; 764 struct enetc_tx_swbd *tx_swbd; 765 skb_frag_t *frag; 766 dma_addr_t dma; 767 u8 flags = 0; 768 int len, f; 769 770 len = skb_headlen(skb) - lso->hdr_len; 771 if (len > 0) { 772 dma = dma_map_single(tx_ring->dev, skb->data + lso->hdr_len, 773 len, DMA_TO_DEVICE); 774 if (dma_mapping_error(tx_ring->dev, dma)) 775 return -ENOMEM; 776 777 enetc_bdr_idx_inc(tx_ring, i); 778 txbd = ENETC_TXBD(*tx_ring, *i); 779 tx_swbd = &tx_ring->tx_swbd[*i]; 780 prefetchw(txbd); 781 *count += 1; 782 783 enetc_clear_tx_bd(&txbd_tmp); 784 txbd_tmp.addr = cpu_to_le64(dma); 785 txbd_tmp.buf_len = cpu_to_le16(len); 786 787 tx_swbd->dma = dma; 788 tx_swbd->len = len; 789 tx_swbd->is_dma_page = 0; 790 tx_swbd->dir = DMA_TO_DEVICE; 791 } 792 793 frag = &skb_shinfo(skb)->frags[0]; 794 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++, frag++) { 795 if (txbd) 796 *txbd = txbd_tmp; 797 798 len = skb_frag_size(frag); 799 dma = skb_frag_dma_map(tx_ring->dev, frag); 800 if (dma_mapping_error(tx_ring->dev, dma)) 801 return -ENOMEM; 802 803 /* Get the next BD */ 804 enetc_bdr_idx_inc(tx_ring, i); 805 txbd = ENETC_TXBD(*tx_ring, *i); 806 tx_swbd = &tx_ring->tx_swbd[*i]; 807 prefetchw(txbd); 808 *count += 1; 809 810 enetc_clear_tx_bd(&txbd_tmp); 811 txbd_tmp.addr = cpu_to_le64(dma); 812 txbd_tmp.buf_len = cpu_to_le16(len); 813 814 tx_swbd->dma = dma; 815 tx_swbd->len = len; 816 tx_swbd->is_dma_page = 1; 817 tx_swbd->dir = DMA_TO_DEVICE; 818 } 819 820 /* Last BD needs 'F' bit set */ 821 flags |= ENETC_TXBD_FLAGS_F; 822 txbd_tmp.flags = flags; 823 *txbd = txbd_tmp; 824 825 tx_swbd->is_eof = 1; 826 tx_swbd->skb = skb; 827 828 return 0; 829 } 830 831 static int enetc_lso_hw_offload(struct enetc_bdr *tx_ring, struct sk_buff *skb) 832 { 833 struct enetc_tx_swbd *tx_swbd; 834 struct enetc_lso_t lso = {0}; 835 int err, i, count = 0; 836 837 /* Initialize the LSO handler */ 838 enetc_lso_start(skb, &lso); 839 i = tx_ring->next_to_use; 840 841 enetc_lso_map_hdr(tx_ring, skb, &i, &lso); 842 /* First BD and an extend BD */ 843 count += 2; 844 845 err = enetc_lso_map_data(tx_ring, skb, &i, &lso, &count); 846 if (err) 847 goto dma_err; 848 849 /* Go to the next BD */ 850 enetc_bdr_idx_inc(tx_ring, &i); 851 tx_ring->next_to_use = i; 852 enetc_update_tx_ring_tail(tx_ring); 853 854 return count; 855 856 dma_err: 857 do { 858 tx_swbd = &tx_ring->tx_swbd[i]; 859 enetc_free_tx_frame(tx_ring, tx_swbd); 860 if (i == 0) 861 i = tx_ring->bd_count; 862 i--; 863 } while (--count); 864 865 return 0; 866 } 867 868 static int enetc_map_tx_tso_buffs(struct enetc_bdr *tx_ring, struct sk_buff *skb) 869 { 870 struct enetc_ndev_priv *priv = netdev_priv(tx_ring->ndev); 871 int hdr_len, total_len, data_len; 872 struct enetc_tx_swbd *tx_swbd; 873 union enetc_tx_bd *txbd; 874 struct tso_t tso; 875 __wsum csum, csum2; 876 int count = 0, pos; 877 int err, i, bd_data_num; 878 879 /* Initialize the TSO handler, and prepare the first payload */ 880 hdr_len = tso_start(skb, &tso); 881 total_len = skb->len - hdr_len; 882 i = tx_ring->next_to_use; 883 884 while (total_len > 0) { 885 char *hdr; 886 887 /* Get the BD */ 888 txbd = ENETC_TXBD(*tx_ring, i); 889 tx_swbd = &tx_ring->tx_swbd[i]; 890 prefetchw(txbd); 891 892 /* Determine the length of this packet */ 893 data_len = min_t(int, skb_shinfo(skb)->gso_size, total_len); 894 total_len -= data_len; 895 896 /* prepare packet headers: MAC + IP + TCP */ 897 hdr = tx_ring->tso_headers + i * TSO_HEADER_SIZE; 898 tso_build_hdr(skb, hdr, &tso, data_len, total_len == 0); 899 900 /* compute the csum over the L4 header */ 901 csum = enetc_tso_hdr_csum(&tso, skb, hdr, hdr_len, &pos); 902 count += enetc_map_tx_tso_hdr(tx_ring, skb, tx_swbd, txbd, 903 &i, hdr_len, data_len); 904 bd_data_num = 0; 905 906 while (data_len > 0) { 907 int size; 908 909 size = min_t(int, tso.size, data_len); 910 911 /* Advance the index in the BDR */ 912 enetc_bdr_idx_inc(tx_ring, &i); 913 txbd = ENETC_TXBD(*tx_ring, i); 914 tx_swbd = &tx_ring->tx_swbd[i]; 915 prefetchw(txbd); 916 917 /* Compute the checksum over this segment of data and 918 * add it to the csum already computed (over the L4 919 * header and possible other data segments). 920 */ 921 csum2 = csum_partial(tso.data, size, 0); 922 csum = csum_block_add(csum, csum2, pos); 923 pos += size; 924 925 err = enetc_map_tx_tso_data(tx_ring, skb, tx_swbd, txbd, 926 tso.data, size, 927 size == data_len); 928 if (err) { 929 if (i == 0) 930 i = tx_ring->bd_count; 931 i--; 932 933 goto err_map_data; 934 } 935 936 data_len -= size; 937 count++; 938 bd_data_num++; 939 tso_build_data(skb, &tso, size); 940 941 if (unlikely(bd_data_num >= priv->max_frags && data_len)) 942 goto err_chained_bd; 943 } 944 945 enetc_tso_complete_csum(tx_ring, &tso, skb, hdr, pos, csum); 946 947 if (total_len == 0) 948 tx_swbd->skb = skb; 949 950 /* Go to the next BD */ 951 enetc_bdr_idx_inc(tx_ring, &i); 952 } 953 954 tx_ring->next_to_use = i; 955 enetc_update_tx_ring_tail(tx_ring); 956 957 return count; 958 959 err_map_data: 960 dev_err(tx_ring->dev, "DMA map error"); 961 962 err_chained_bd: 963 enetc_unwind_tx_frame(tx_ring, count, i); 964 965 return 0; 966 } 967 968 static netdev_tx_t enetc_start_xmit(struct sk_buff *skb, 969 struct net_device *ndev) 970 { 971 struct enetc_skb_cb *enetc_cb = ENETC_SKB_CB(skb); 972 struct enetc_ndev_priv *priv = netdev_priv(ndev); 973 struct enetc_bdr *tx_ring; 974 int count; 975 976 /* Queue one-step Sync packet if already locked */ 977 if (enetc_cb->flag & ENETC_F_TX_ONESTEP_SYNC_TSTAMP) { 978 if (test_and_set_bit_lock(ENETC_TX_ONESTEP_TSTAMP_IN_PROGRESS, 979 &priv->flags)) { 980 skb_queue_tail(&priv->tx_skbs, skb); 981 return NETDEV_TX_OK; 982 } 983 } 984 985 tx_ring = priv->tx_ring[skb->queue_mapping]; 986 987 if (skb_is_gso(skb)) { 988 /* LSO data unit lengths of up to 256KB are supported */ 989 if (priv->active_offloads & ENETC_F_LSO && 990 (skb->len - enetc_lso_get_hdr_len(skb)) <= 991 ENETC_LSO_MAX_DATA_LEN) { 992 if (enetc_bd_unused(tx_ring) < enetc_lso_count_descs(skb)) { 993 netif_stop_subqueue(ndev, tx_ring->index); 994 return NETDEV_TX_BUSY; 995 } 996 997 count = enetc_lso_hw_offload(tx_ring, skb); 998 } else { 999 if (enetc_bd_unused(tx_ring) < tso_count_descs(skb)) { 1000 netif_stop_subqueue(ndev, tx_ring->index); 1001 return NETDEV_TX_BUSY; 1002 } 1003 1004 enetc_lock_mdio(); 1005 count = enetc_map_tx_tso_buffs(tx_ring, skb); 1006 enetc_unlock_mdio(); 1007 } 1008 } else { 1009 if (unlikely(skb_shinfo(skb)->nr_frags > priv->max_frags)) 1010 if (unlikely(skb_linearize(skb))) 1011 goto drop_packet_err; 1012 1013 count = skb_shinfo(skb)->nr_frags + 1; /* fragments + head */ 1014 if (enetc_bd_unused(tx_ring) < ENETC_TXBDS_NEEDED(count)) { 1015 netif_stop_subqueue(ndev, tx_ring->index); 1016 return NETDEV_TX_BUSY; 1017 } 1018 1019 enetc_lock_mdio(); 1020 count = enetc_map_tx_buffs(tx_ring, skb); 1021 enetc_unlock_mdio(); 1022 } 1023 1024 if (unlikely(!count)) 1025 goto drop_packet_err; 1026 1027 if (enetc_bd_unused(tx_ring) < ENETC_TXBDS_MAX_NEEDED(priv->max_frags)) 1028 netif_stop_subqueue(ndev, tx_ring->index); 1029 1030 return NETDEV_TX_OK; 1031 1032 drop_packet_err: 1033 dev_kfree_skb_any(skb); 1034 return NETDEV_TX_OK; 1035 } 1036 1037 netdev_tx_t enetc_xmit(struct sk_buff *skb, struct net_device *ndev) 1038 { 1039 struct enetc_skb_cb *enetc_cb = ENETC_SKB_CB(skb); 1040 struct enetc_ndev_priv *priv = netdev_priv(ndev); 1041 u8 udp, msgtype, twostep; 1042 u16 offset1, offset2; 1043 1044 /* Mark tx timestamp type on enetc_cb->flag if requires */ 1045 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 1046 (priv->active_offloads & ENETC_F_TX_TSTAMP_MASK)) 1047 enetc_cb->flag = priv->active_offloads & ENETC_F_TX_TSTAMP_MASK; 1048 else 1049 enetc_cb->flag = 0; 1050 1051 /* Fall back to two-step timestamp if not one-step Sync packet */ 1052 if (enetc_cb->flag & ENETC_F_TX_ONESTEP_SYNC_TSTAMP) { 1053 if (enetc_ptp_parse(skb, &udp, &msgtype, &twostep, 1054 &offset1, &offset2) || 1055 msgtype != PTP_MSGTYPE_SYNC || twostep != 0) { 1056 enetc_cb->flag = ENETC_F_TX_TSTAMP; 1057 } else { 1058 enetc_cb->udp = !!udp; 1059 enetc_cb->correction_off = offset1; 1060 enetc_cb->origin_tstamp_off = offset2; 1061 } 1062 } 1063 1064 return enetc_start_xmit(skb, ndev); 1065 } 1066 EXPORT_SYMBOL_GPL(enetc_xmit); 1067 1068 static irqreturn_t enetc_msix(int irq, void *data) 1069 { 1070 struct enetc_int_vector *v = data; 1071 int i; 1072 1073 enetc_lock_mdio(); 1074 1075 /* disable interrupts */ 1076 enetc_wr_reg_hot(v->rbier, 0); 1077 enetc_wr_reg_hot(v->ricr1, v->rx_ictt); 1078 1079 for_each_set_bit(i, &v->tx_rings_map, ENETC_MAX_NUM_TXQS) 1080 enetc_wr_reg_hot(v->tbier_base + ENETC_BDR_OFF(i), 0); 1081 1082 enetc_unlock_mdio(); 1083 1084 napi_schedule(&v->napi); 1085 1086 return IRQ_HANDLED; 1087 } 1088 1089 static void enetc_rx_dim_work(struct work_struct *w) 1090 { 1091 struct dim *dim = container_of(w, struct dim, work); 1092 struct dim_cq_moder moder = 1093 net_dim_get_rx_moderation(dim->mode, dim->profile_ix); 1094 struct enetc_int_vector *v = 1095 container_of(dim, struct enetc_int_vector, rx_dim); 1096 struct enetc_ndev_priv *priv = netdev_priv(v->rx_ring.ndev); 1097 1098 v->rx_ictt = enetc_usecs_to_cycles(moder.usec, priv->sysclk_freq); 1099 dim->state = DIM_START_MEASURE; 1100 } 1101 1102 static void enetc_rx_net_dim(struct enetc_int_vector *v) 1103 { 1104 struct dim_sample dim_sample = {}; 1105 1106 v->comp_cnt++; 1107 1108 if (!v->rx_napi_work) 1109 return; 1110 1111 dim_update_sample(v->comp_cnt, 1112 v->rx_ring.stats.packets, 1113 v->rx_ring.stats.bytes, 1114 &dim_sample); 1115 net_dim(&v->rx_dim, &dim_sample); 1116 } 1117 1118 static int enetc_bd_ready_count(struct enetc_bdr *tx_ring, int ci) 1119 { 1120 int pi = enetc_rd_reg_hot(tx_ring->tcir) & ENETC_TBCIR_IDX_MASK; 1121 1122 return pi >= ci ? pi - ci : tx_ring->bd_count - ci + pi; 1123 } 1124 1125 static bool enetc_page_reusable(struct page *page) 1126 { 1127 return (!page_is_pfmemalloc(page) && page_ref_count(page) == 1); 1128 } 1129 1130 static void enetc_reuse_page(struct enetc_bdr *rx_ring, 1131 struct enetc_rx_swbd *old) 1132 { 1133 struct enetc_rx_swbd *new; 1134 1135 new = &rx_ring->rx_swbd[rx_ring->next_to_alloc]; 1136 1137 /* next buf that may reuse a page */ 1138 enetc_bdr_idx_inc(rx_ring, &rx_ring->next_to_alloc); 1139 1140 /* copy page reference */ 1141 *new = *old; 1142 } 1143 1144 static void enetc_get_tx_tstamp(struct enetc_hw *hw, union enetc_tx_bd *txbd, 1145 u64 *tstamp) 1146 { 1147 u32 lo, hi, tstamp_lo; 1148 1149 lo = enetc_rd_hot(hw, ENETC_SICTR0); 1150 hi = enetc_rd_hot(hw, ENETC_SICTR1); 1151 tstamp_lo = le32_to_cpu(txbd->wb.tstamp); 1152 if (lo <= tstamp_lo) 1153 hi -= 1; 1154 *tstamp = (u64)hi << 32 | tstamp_lo; 1155 } 1156 1157 static void enetc_tstamp_tx(struct sk_buff *skb, u64 tstamp) 1158 { 1159 struct skb_shared_hwtstamps shhwtstamps; 1160 1161 if (skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) { 1162 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 1163 shhwtstamps.hwtstamp = ns_to_ktime(tstamp); 1164 skb_txtime_consumed(skb); 1165 skb_tstamp_tx(skb, &shhwtstamps); 1166 } 1167 } 1168 1169 static void enetc_recycle_xdp_tx_buff(struct enetc_bdr *tx_ring, 1170 struct enetc_tx_swbd *tx_swbd) 1171 { 1172 struct enetc_ndev_priv *priv = netdev_priv(tx_ring->ndev); 1173 struct enetc_rx_swbd rx_swbd = { 1174 .dma = tx_swbd->dma, 1175 .page = tx_swbd->page, 1176 .page_offset = tx_swbd->page_offset, 1177 .dir = tx_swbd->dir, 1178 .len = tx_swbd->len, 1179 }; 1180 struct enetc_bdr *rx_ring; 1181 1182 rx_ring = enetc_rx_ring_from_xdp_tx_ring(priv, tx_ring); 1183 1184 if (likely(enetc_swbd_unused(rx_ring))) { 1185 enetc_reuse_page(rx_ring, &rx_swbd); 1186 1187 /* sync for use by the device */ 1188 dma_sync_single_range_for_device(rx_ring->dev, rx_swbd.dma, 1189 rx_swbd.page_offset, 1190 ENETC_RXB_DMA_SIZE_XDP, 1191 rx_swbd.dir); 1192 1193 rx_ring->stats.recycles++; 1194 } else { 1195 /* RX ring is already full, we need to unmap and free the 1196 * page, since there's nothing useful we can do with it. 1197 */ 1198 rx_ring->stats.recycle_failures++; 1199 1200 dma_unmap_page(rx_ring->dev, rx_swbd.dma, PAGE_SIZE, 1201 rx_swbd.dir); 1202 __free_page(rx_swbd.page); 1203 } 1204 1205 rx_ring->xdp.xdp_tx_in_flight--; 1206 } 1207 1208 static bool enetc_clean_tx_ring(struct enetc_bdr *tx_ring, int napi_budget) 1209 { 1210 int tx_frm_cnt = 0, tx_byte_cnt = 0, tx_win_drop = 0; 1211 struct net_device *ndev = tx_ring->ndev; 1212 struct enetc_ndev_priv *priv = netdev_priv(ndev); 1213 struct enetc_tx_swbd *tx_swbd; 1214 int i, bds_to_clean; 1215 bool do_twostep_tstamp; 1216 u64 tstamp = 0; 1217 1218 i = tx_ring->next_to_clean; 1219 tx_swbd = &tx_ring->tx_swbd[i]; 1220 1221 bds_to_clean = enetc_bd_ready_count(tx_ring, i); 1222 1223 do_twostep_tstamp = false; 1224 1225 while (bds_to_clean && tx_frm_cnt < ENETC_DEFAULT_TX_WORK) { 1226 struct xdp_frame *xdp_frame = enetc_tx_swbd_get_xdp_frame(tx_swbd); 1227 struct sk_buff *skb = enetc_tx_swbd_get_skb(tx_swbd); 1228 bool is_eof = tx_swbd->is_eof; 1229 1230 if (unlikely(tx_swbd->check_wb)) { 1231 union enetc_tx_bd *txbd = ENETC_TXBD(*tx_ring, i); 1232 1233 if (txbd->flags & ENETC_TXBD_FLAGS_W && 1234 tx_swbd->do_twostep_tstamp) { 1235 enetc_get_tx_tstamp(&priv->si->hw, txbd, 1236 &tstamp); 1237 do_twostep_tstamp = true; 1238 } 1239 1240 if (tx_swbd->qbv_en && 1241 txbd->wb.status & ENETC_TXBD_STATS_WIN) 1242 tx_win_drop++; 1243 } 1244 1245 if (tx_swbd->is_xdp_tx) 1246 enetc_recycle_xdp_tx_buff(tx_ring, tx_swbd); 1247 else if (likely(tx_swbd->dma)) 1248 enetc_unmap_tx_buff(tx_ring, tx_swbd); 1249 1250 if (xdp_frame) { 1251 xdp_return_frame(xdp_frame); 1252 } else if (skb) { 1253 struct enetc_skb_cb *enetc_cb = ENETC_SKB_CB(skb); 1254 1255 if (unlikely(enetc_cb->flag & ENETC_F_TX_ONESTEP_SYNC_TSTAMP)) { 1256 /* Start work to release lock for next one-step 1257 * timestamping packet. And send one skb in 1258 * tx_skbs queue if has. 1259 */ 1260 schedule_work(&priv->tx_onestep_tstamp); 1261 } else if (unlikely(do_twostep_tstamp)) { 1262 enetc_tstamp_tx(skb, tstamp); 1263 do_twostep_tstamp = false; 1264 } 1265 napi_consume_skb(skb, napi_budget); 1266 } 1267 1268 tx_byte_cnt += tx_swbd->len; 1269 /* Scrub the swbd here so we don't have to do that 1270 * when we reuse it during xmit 1271 */ 1272 memset(tx_swbd, 0, sizeof(*tx_swbd)); 1273 1274 bds_to_clean--; 1275 tx_swbd++; 1276 i++; 1277 if (unlikely(i == tx_ring->bd_count)) { 1278 i = 0; 1279 tx_swbd = tx_ring->tx_swbd; 1280 } 1281 1282 /* BD iteration loop end */ 1283 if (is_eof) { 1284 tx_frm_cnt++; 1285 /* re-arm interrupt source */ 1286 enetc_wr_reg_hot(tx_ring->idr, BIT(tx_ring->index) | 1287 BIT(16 + tx_ring->index)); 1288 } 1289 1290 if (unlikely(!bds_to_clean)) 1291 bds_to_clean = enetc_bd_ready_count(tx_ring, i); 1292 } 1293 1294 tx_ring->next_to_clean = i; 1295 tx_ring->stats.packets += tx_frm_cnt; 1296 tx_ring->stats.bytes += tx_byte_cnt; 1297 tx_ring->stats.win_drop += tx_win_drop; 1298 1299 if (unlikely(tx_frm_cnt && netif_carrier_ok(ndev) && 1300 __netif_subqueue_stopped(ndev, tx_ring->index) && 1301 !test_bit(ENETC_TX_DOWN, &priv->flags) && 1302 (enetc_bd_unused(tx_ring) >= 1303 ENETC_TXBDS_MAX_NEEDED(priv->max_frags)))) { 1304 netif_wake_subqueue(ndev, tx_ring->index); 1305 } 1306 1307 return tx_frm_cnt != ENETC_DEFAULT_TX_WORK; 1308 } 1309 1310 static bool enetc_new_page(struct enetc_bdr *rx_ring, 1311 struct enetc_rx_swbd *rx_swbd) 1312 { 1313 bool xdp = !!(rx_ring->xdp.prog); 1314 struct page *page; 1315 dma_addr_t addr; 1316 1317 page = dev_alloc_page(); 1318 if (unlikely(!page)) 1319 return false; 1320 1321 /* For XDP_TX, we forgo dma_unmap -> dma_map */ 1322 rx_swbd->dir = xdp ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE; 1323 1324 addr = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, rx_swbd->dir); 1325 if (unlikely(dma_mapping_error(rx_ring->dev, addr))) { 1326 __free_page(page); 1327 1328 return false; 1329 } 1330 1331 rx_swbd->dma = addr; 1332 rx_swbd->page = page; 1333 rx_swbd->page_offset = rx_ring->buffer_offset; 1334 1335 return true; 1336 } 1337 1338 static int enetc_refill_rx_ring(struct enetc_bdr *rx_ring, const int buff_cnt) 1339 { 1340 struct enetc_rx_swbd *rx_swbd; 1341 union enetc_rx_bd *rxbd; 1342 int i, j; 1343 1344 i = rx_ring->next_to_use; 1345 rx_swbd = &rx_ring->rx_swbd[i]; 1346 rxbd = enetc_rxbd(rx_ring, i); 1347 1348 for (j = 0; j < buff_cnt; j++) { 1349 /* try reuse page */ 1350 if (unlikely(!rx_swbd->page)) { 1351 if (unlikely(!enetc_new_page(rx_ring, rx_swbd))) { 1352 rx_ring->stats.rx_alloc_errs++; 1353 break; 1354 } 1355 } 1356 1357 /* update RxBD */ 1358 rxbd->w.addr = cpu_to_le64(rx_swbd->dma + 1359 rx_swbd->page_offset); 1360 /* clear 'R" as well */ 1361 rxbd->r.lstatus = 0; 1362 1363 enetc_rxbd_next(rx_ring, &rxbd, &i); 1364 rx_swbd = &rx_ring->rx_swbd[i]; 1365 } 1366 1367 if (likely(j)) { 1368 rx_ring->next_to_alloc = i; /* keep track from page reuse */ 1369 rx_ring->next_to_use = i; 1370 1371 /* update ENETC's consumer index */ 1372 enetc_wr_reg_hot(rx_ring->rcir, rx_ring->next_to_use); 1373 } 1374 1375 return j; 1376 } 1377 1378 static void enetc_get_rx_tstamp(struct net_device *ndev, 1379 union enetc_rx_bd *rxbd, 1380 struct sk_buff *skb) 1381 { 1382 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb); 1383 struct enetc_ndev_priv *priv = netdev_priv(ndev); 1384 struct enetc_hw *hw = &priv->si->hw; 1385 u32 lo, hi, tstamp_lo; 1386 u64 tstamp; 1387 1388 if (le16_to_cpu(rxbd->r.flags) & ENETC_RXBD_FLAG_TSTMP) { 1389 lo = enetc_rd_reg_hot(hw->reg + ENETC_SICTR0); 1390 hi = enetc_rd_reg_hot(hw->reg + ENETC_SICTR1); 1391 rxbd = enetc_rxbd_ext(rxbd); 1392 tstamp_lo = le32_to_cpu(rxbd->ext.tstamp); 1393 if (lo <= tstamp_lo) 1394 hi -= 1; 1395 1396 tstamp = (u64)hi << 32 | tstamp_lo; 1397 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 1398 shhwtstamps->hwtstamp = ns_to_ktime(tstamp); 1399 } 1400 } 1401 1402 static void enetc_get_offloads(struct enetc_bdr *rx_ring, 1403 union enetc_rx_bd *rxbd, struct sk_buff *skb) 1404 { 1405 struct enetc_ndev_priv *priv = netdev_priv(rx_ring->ndev); 1406 1407 /* TODO: hashing */ 1408 if (rx_ring->ndev->features & NETIF_F_RXCSUM) { 1409 u16 inet_csum = le16_to_cpu(rxbd->r.inet_csum); 1410 1411 skb->csum = csum_unfold((__force __sum16)~htons(inet_csum)); 1412 skb->ip_summed = CHECKSUM_COMPLETE; 1413 } 1414 1415 if (le16_to_cpu(rxbd->r.flags) & ENETC_RXBD_FLAG_VLAN) { 1416 struct enetc_hw *hw = &priv->si->hw; 1417 __be16 tpid = 0; 1418 1419 switch (le16_to_cpu(rxbd->r.flags) & ENETC_RXBD_FLAG_TPID) { 1420 case 0: 1421 tpid = htons(ETH_P_8021Q); 1422 break; 1423 case 1: 1424 tpid = htons(ETH_P_8021AD); 1425 break; 1426 case 2: 1427 tpid = htons(enetc_rd_hot(hw, ENETC_SICVLANR1) & 1428 SICVLANR_ETYPE); 1429 break; 1430 case 3: 1431 tpid = htons(enetc_rd_hot(hw, ENETC_SICVLANR2) & 1432 SICVLANR_ETYPE); 1433 } 1434 1435 __vlan_hwaccel_put_tag(skb, tpid, le16_to_cpu(rxbd->r.vlan_opt)); 1436 } 1437 1438 if (priv->active_offloads & ENETC_F_RX_TSTAMP) 1439 enetc_get_rx_tstamp(rx_ring->ndev, rxbd, skb); 1440 } 1441 1442 /* This gets called during the non-XDP NAPI poll cycle as well as on XDP_PASS, 1443 * so it needs to work with both DMA_FROM_DEVICE as well as DMA_BIDIRECTIONAL 1444 * mapped buffers. 1445 */ 1446 static struct enetc_rx_swbd *enetc_get_rx_buff(struct enetc_bdr *rx_ring, 1447 int i, u16 size) 1448 { 1449 struct enetc_rx_swbd *rx_swbd = &rx_ring->rx_swbd[i]; 1450 1451 dma_sync_single_range_for_cpu(rx_ring->dev, rx_swbd->dma, 1452 rx_swbd->page_offset, 1453 size, rx_swbd->dir); 1454 return rx_swbd; 1455 } 1456 1457 /* Reuse the current page without performing half-page buffer flipping */ 1458 static void enetc_put_rx_buff(struct enetc_bdr *rx_ring, 1459 struct enetc_rx_swbd *rx_swbd) 1460 { 1461 size_t buffer_size = ENETC_RXB_TRUESIZE - rx_ring->buffer_offset; 1462 1463 enetc_reuse_page(rx_ring, rx_swbd); 1464 1465 dma_sync_single_range_for_device(rx_ring->dev, rx_swbd->dma, 1466 rx_swbd->page_offset, 1467 buffer_size, rx_swbd->dir); 1468 1469 rx_swbd->page = NULL; 1470 } 1471 1472 /* Reuse the current page by performing half-page buffer flipping */ 1473 static void enetc_flip_rx_buff(struct enetc_bdr *rx_ring, 1474 struct enetc_rx_swbd *rx_swbd) 1475 { 1476 if (likely(enetc_page_reusable(rx_swbd->page))) { 1477 rx_swbd->page_offset ^= ENETC_RXB_TRUESIZE; 1478 page_ref_inc(rx_swbd->page); 1479 1480 enetc_put_rx_buff(rx_ring, rx_swbd); 1481 } else { 1482 dma_unmap_page(rx_ring->dev, rx_swbd->dma, PAGE_SIZE, 1483 rx_swbd->dir); 1484 rx_swbd->page = NULL; 1485 } 1486 } 1487 1488 static struct sk_buff *enetc_map_rx_buff_to_skb(struct enetc_bdr *rx_ring, 1489 int i, u16 size) 1490 { 1491 struct enetc_rx_swbd *rx_swbd = enetc_get_rx_buff(rx_ring, i, size); 1492 struct sk_buff *skb; 1493 void *ba; 1494 1495 ba = page_address(rx_swbd->page) + rx_swbd->page_offset; 1496 skb = build_skb(ba - rx_ring->buffer_offset, ENETC_RXB_TRUESIZE); 1497 if (unlikely(!skb)) { 1498 rx_ring->stats.rx_alloc_errs++; 1499 return NULL; 1500 } 1501 1502 skb_reserve(skb, rx_ring->buffer_offset); 1503 __skb_put(skb, size); 1504 1505 enetc_flip_rx_buff(rx_ring, rx_swbd); 1506 1507 return skb; 1508 } 1509 1510 static void enetc_add_rx_buff_to_skb(struct enetc_bdr *rx_ring, int i, 1511 u16 size, struct sk_buff *skb) 1512 { 1513 struct enetc_rx_swbd *rx_swbd = enetc_get_rx_buff(rx_ring, i, size); 1514 1515 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_swbd->page, 1516 rx_swbd->page_offset, size, ENETC_RXB_TRUESIZE); 1517 1518 enetc_flip_rx_buff(rx_ring, rx_swbd); 1519 } 1520 1521 static bool enetc_check_bd_errors_and_consume(struct enetc_bdr *rx_ring, 1522 u32 bd_status, 1523 union enetc_rx_bd **rxbd, int *i) 1524 { 1525 if (likely(!(bd_status & ENETC_RXBD_LSTATUS(ENETC_RXBD_ERR_MASK)))) 1526 return false; 1527 1528 enetc_put_rx_buff(rx_ring, &rx_ring->rx_swbd[*i]); 1529 enetc_rxbd_next(rx_ring, rxbd, i); 1530 1531 while (!(bd_status & ENETC_RXBD_LSTATUS_F)) { 1532 dma_rmb(); 1533 bd_status = le32_to_cpu((*rxbd)->r.lstatus); 1534 1535 enetc_put_rx_buff(rx_ring, &rx_ring->rx_swbd[*i]); 1536 enetc_rxbd_next(rx_ring, rxbd, i); 1537 } 1538 1539 rx_ring->ndev->stats.rx_dropped++; 1540 rx_ring->ndev->stats.rx_errors++; 1541 1542 return true; 1543 } 1544 1545 static struct sk_buff *enetc_build_skb(struct enetc_bdr *rx_ring, 1546 u32 bd_status, union enetc_rx_bd **rxbd, 1547 int *i, int *cleaned_cnt, int buffer_size) 1548 { 1549 struct sk_buff *skb; 1550 u16 size; 1551 1552 size = le16_to_cpu((*rxbd)->r.buf_len); 1553 skb = enetc_map_rx_buff_to_skb(rx_ring, *i, size); 1554 if (!skb) 1555 return NULL; 1556 1557 enetc_get_offloads(rx_ring, *rxbd, skb); 1558 1559 (*cleaned_cnt)++; 1560 1561 enetc_rxbd_next(rx_ring, rxbd, i); 1562 1563 /* not last BD in frame? */ 1564 while (!(bd_status & ENETC_RXBD_LSTATUS_F)) { 1565 bd_status = le32_to_cpu((*rxbd)->r.lstatus); 1566 size = buffer_size; 1567 1568 if (bd_status & ENETC_RXBD_LSTATUS_F) { 1569 dma_rmb(); 1570 size = le16_to_cpu((*rxbd)->r.buf_len); 1571 } 1572 1573 enetc_add_rx_buff_to_skb(rx_ring, *i, size, skb); 1574 1575 (*cleaned_cnt)++; 1576 1577 enetc_rxbd_next(rx_ring, rxbd, i); 1578 } 1579 1580 skb_record_rx_queue(skb, rx_ring->index); 1581 skb->protocol = eth_type_trans(skb, rx_ring->ndev); 1582 1583 return skb; 1584 } 1585 1586 #define ENETC_RXBD_BUNDLE 16 /* # of BDs to update at once */ 1587 1588 static int enetc_clean_rx_ring(struct enetc_bdr *rx_ring, 1589 struct napi_struct *napi, int work_limit) 1590 { 1591 int rx_frm_cnt = 0, rx_byte_cnt = 0; 1592 int cleaned_cnt, i; 1593 1594 cleaned_cnt = enetc_bd_unused(rx_ring); 1595 /* next descriptor to process */ 1596 i = rx_ring->next_to_clean; 1597 1598 while (likely(rx_frm_cnt < work_limit)) { 1599 union enetc_rx_bd *rxbd; 1600 struct sk_buff *skb; 1601 u32 bd_status; 1602 1603 if (cleaned_cnt >= ENETC_RXBD_BUNDLE) 1604 cleaned_cnt -= enetc_refill_rx_ring(rx_ring, 1605 cleaned_cnt); 1606 1607 rxbd = enetc_rxbd(rx_ring, i); 1608 bd_status = le32_to_cpu(rxbd->r.lstatus); 1609 if (!bd_status) 1610 break; 1611 1612 enetc_wr_reg_hot(rx_ring->idr, BIT(rx_ring->index)); 1613 dma_rmb(); /* for reading other rxbd fields */ 1614 1615 if (enetc_check_bd_errors_and_consume(rx_ring, bd_status, 1616 &rxbd, &i)) 1617 break; 1618 1619 skb = enetc_build_skb(rx_ring, bd_status, &rxbd, &i, 1620 &cleaned_cnt, ENETC_RXB_DMA_SIZE); 1621 if (!skb) 1622 break; 1623 1624 /* When set, the outer VLAN header is extracted and reported 1625 * in the receive buffer descriptor. So rx_byte_cnt should 1626 * add the length of the extracted VLAN header. 1627 */ 1628 if (bd_status & ENETC_RXBD_FLAG_VLAN) 1629 rx_byte_cnt += VLAN_HLEN; 1630 rx_byte_cnt += skb->len + ETH_HLEN; 1631 rx_frm_cnt++; 1632 1633 napi_gro_receive(napi, skb); 1634 } 1635 1636 rx_ring->next_to_clean = i; 1637 1638 rx_ring->stats.packets += rx_frm_cnt; 1639 rx_ring->stats.bytes += rx_byte_cnt; 1640 1641 return rx_frm_cnt; 1642 } 1643 1644 static void enetc_xdp_map_tx_buff(struct enetc_bdr *tx_ring, int i, 1645 struct enetc_tx_swbd *tx_swbd, 1646 int frm_len) 1647 { 1648 union enetc_tx_bd *txbd = ENETC_TXBD(*tx_ring, i); 1649 1650 prefetchw(txbd); 1651 1652 enetc_clear_tx_bd(txbd); 1653 txbd->addr = cpu_to_le64(tx_swbd->dma + tx_swbd->page_offset); 1654 txbd->buf_len = cpu_to_le16(tx_swbd->len); 1655 txbd->frm_len = cpu_to_le16(frm_len); 1656 1657 memcpy(&tx_ring->tx_swbd[i], tx_swbd, sizeof(*tx_swbd)); 1658 } 1659 1660 /* Puts in the TX ring one XDP frame, mapped as an array of TX software buffer 1661 * descriptors. 1662 */ 1663 static bool enetc_xdp_tx(struct enetc_bdr *tx_ring, 1664 struct enetc_tx_swbd *xdp_tx_arr, int num_tx_swbd) 1665 { 1666 struct enetc_tx_swbd *tmp_tx_swbd = xdp_tx_arr; 1667 int i, k, frm_len = tmp_tx_swbd->len; 1668 1669 if (unlikely(enetc_bd_unused(tx_ring) < ENETC_TXBDS_NEEDED(num_tx_swbd))) 1670 return false; 1671 1672 while (unlikely(!tmp_tx_swbd->is_eof)) { 1673 tmp_tx_swbd++; 1674 frm_len += tmp_tx_swbd->len; 1675 } 1676 1677 i = tx_ring->next_to_use; 1678 1679 for (k = 0; k < num_tx_swbd; k++) { 1680 struct enetc_tx_swbd *xdp_tx_swbd = &xdp_tx_arr[k]; 1681 1682 enetc_xdp_map_tx_buff(tx_ring, i, xdp_tx_swbd, frm_len); 1683 1684 /* last BD needs 'F' bit set */ 1685 if (xdp_tx_swbd->is_eof) { 1686 union enetc_tx_bd *txbd = ENETC_TXBD(*tx_ring, i); 1687 1688 txbd->flags = ENETC_TXBD_FLAGS_F; 1689 } 1690 1691 enetc_bdr_idx_inc(tx_ring, &i); 1692 } 1693 1694 tx_ring->next_to_use = i; 1695 1696 return true; 1697 } 1698 1699 static int enetc_xdp_frame_to_xdp_tx_swbd(struct enetc_bdr *tx_ring, 1700 struct enetc_tx_swbd *xdp_tx_arr, 1701 struct xdp_frame *xdp_frame) 1702 { 1703 struct enetc_tx_swbd *xdp_tx_swbd = &xdp_tx_arr[0]; 1704 struct skb_shared_info *shinfo; 1705 void *data = xdp_frame->data; 1706 int len = xdp_frame->len; 1707 skb_frag_t *frag; 1708 dma_addr_t dma; 1709 unsigned int f; 1710 int n = 0; 1711 1712 dma = dma_map_single(tx_ring->dev, data, len, DMA_TO_DEVICE); 1713 if (unlikely(dma_mapping_error(tx_ring->dev, dma))) { 1714 netdev_err(tx_ring->ndev, "DMA map error\n"); 1715 return -1; 1716 } 1717 1718 xdp_tx_swbd->dma = dma; 1719 xdp_tx_swbd->dir = DMA_TO_DEVICE; 1720 xdp_tx_swbd->len = len; 1721 xdp_tx_swbd->is_xdp_redirect = true; 1722 xdp_tx_swbd->is_eof = false; 1723 xdp_tx_swbd->xdp_frame = NULL; 1724 1725 n++; 1726 1727 if (!xdp_frame_has_frags(xdp_frame)) 1728 goto out; 1729 1730 xdp_tx_swbd = &xdp_tx_arr[n]; 1731 1732 shinfo = xdp_get_shared_info_from_frame(xdp_frame); 1733 1734 for (f = 0, frag = &shinfo->frags[0]; f < shinfo->nr_frags; 1735 f++, frag++) { 1736 data = skb_frag_address(frag); 1737 len = skb_frag_size(frag); 1738 1739 dma = dma_map_single(tx_ring->dev, data, len, DMA_TO_DEVICE); 1740 if (unlikely(dma_mapping_error(tx_ring->dev, dma))) { 1741 /* Undo the DMA mapping for all fragments */ 1742 while (--n >= 0) 1743 enetc_unmap_tx_buff(tx_ring, &xdp_tx_arr[n]); 1744 1745 netdev_err(tx_ring->ndev, "DMA map error\n"); 1746 return -1; 1747 } 1748 1749 xdp_tx_swbd->dma = dma; 1750 xdp_tx_swbd->dir = DMA_TO_DEVICE; 1751 xdp_tx_swbd->len = len; 1752 xdp_tx_swbd->is_xdp_redirect = true; 1753 xdp_tx_swbd->is_eof = false; 1754 xdp_tx_swbd->xdp_frame = NULL; 1755 1756 n++; 1757 xdp_tx_swbd = &xdp_tx_arr[n]; 1758 } 1759 out: 1760 xdp_tx_arr[n - 1].is_eof = true; 1761 xdp_tx_arr[n - 1].xdp_frame = xdp_frame; 1762 1763 return n; 1764 } 1765 1766 int enetc_xdp_xmit(struct net_device *ndev, int num_frames, 1767 struct xdp_frame **frames, u32 flags) 1768 { 1769 struct enetc_tx_swbd xdp_redirect_arr[ENETC_MAX_SKB_FRAGS] = {0}; 1770 struct enetc_ndev_priv *priv = netdev_priv(ndev); 1771 struct enetc_bdr *tx_ring; 1772 int xdp_tx_bd_cnt, i, k; 1773 int xdp_tx_frm_cnt = 0; 1774 1775 if (unlikely(test_bit(ENETC_TX_DOWN, &priv->flags))) 1776 return -ENETDOWN; 1777 1778 enetc_lock_mdio(); 1779 1780 tx_ring = priv->xdp_tx_ring[smp_processor_id()]; 1781 1782 prefetchw(ENETC_TXBD(*tx_ring, tx_ring->next_to_use)); 1783 1784 for (k = 0; k < num_frames; k++) { 1785 xdp_tx_bd_cnt = enetc_xdp_frame_to_xdp_tx_swbd(tx_ring, 1786 xdp_redirect_arr, 1787 frames[k]); 1788 if (unlikely(xdp_tx_bd_cnt < 0)) 1789 break; 1790 1791 if (unlikely(!enetc_xdp_tx(tx_ring, xdp_redirect_arr, 1792 xdp_tx_bd_cnt))) { 1793 for (i = 0; i < xdp_tx_bd_cnt; i++) 1794 enetc_unmap_tx_buff(tx_ring, 1795 &xdp_redirect_arr[i]); 1796 tx_ring->stats.xdp_tx_drops++; 1797 break; 1798 } 1799 1800 xdp_tx_frm_cnt++; 1801 } 1802 1803 if (unlikely((flags & XDP_XMIT_FLUSH) || k != xdp_tx_frm_cnt)) 1804 enetc_update_tx_ring_tail(tx_ring); 1805 1806 tx_ring->stats.xdp_tx += xdp_tx_frm_cnt; 1807 1808 enetc_unlock_mdio(); 1809 1810 return xdp_tx_frm_cnt; 1811 } 1812 EXPORT_SYMBOL_GPL(enetc_xdp_xmit); 1813 1814 static void enetc_map_rx_buff_to_xdp(struct enetc_bdr *rx_ring, int i, 1815 struct xdp_buff *xdp_buff, u16 size) 1816 { 1817 struct enetc_rx_swbd *rx_swbd = enetc_get_rx_buff(rx_ring, i, size); 1818 void *hard_start = page_address(rx_swbd->page) + rx_swbd->page_offset; 1819 1820 /* To be used for XDP_TX */ 1821 rx_swbd->len = size; 1822 1823 xdp_prepare_buff(xdp_buff, hard_start - rx_ring->buffer_offset, 1824 rx_ring->buffer_offset, size, false); 1825 } 1826 1827 static void enetc_add_rx_buff_to_xdp(struct enetc_bdr *rx_ring, int i, 1828 u16 size, struct xdp_buff *xdp_buff) 1829 { 1830 struct skb_shared_info *shinfo = xdp_get_shared_info_from_buff(xdp_buff); 1831 struct enetc_rx_swbd *rx_swbd = enetc_get_rx_buff(rx_ring, i, size); 1832 skb_frag_t *frag; 1833 1834 /* To be used for XDP_TX */ 1835 rx_swbd->len = size; 1836 1837 if (!xdp_buff_has_frags(xdp_buff)) { 1838 xdp_buff_set_frags_flag(xdp_buff); 1839 shinfo->xdp_frags_size = size; 1840 shinfo->nr_frags = 0; 1841 } else { 1842 shinfo->xdp_frags_size += size; 1843 } 1844 1845 if (page_is_pfmemalloc(rx_swbd->page)) 1846 xdp_buff_set_frag_pfmemalloc(xdp_buff); 1847 1848 frag = &shinfo->frags[shinfo->nr_frags]; 1849 skb_frag_fill_page_desc(frag, rx_swbd->page, rx_swbd->page_offset, 1850 size); 1851 1852 shinfo->nr_frags++; 1853 } 1854 1855 static void enetc_build_xdp_buff(struct enetc_bdr *rx_ring, u32 bd_status, 1856 union enetc_rx_bd **rxbd, int *i, 1857 int *cleaned_cnt, struct xdp_buff *xdp_buff) 1858 { 1859 u16 size = le16_to_cpu((*rxbd)->r.buf_len); 1860 1861 xdp_init_buff(xdp_buff, ENETC_RXB_TRUESIZE, &rx_ring->xdp.rxq); 1862 1863 enetc_map_rx_buff_to_xdp(rx_ring, *i, xdp_buff, size); 1864 (*cleaned_cnt)++; 1865 enetc_rxbd_next(rx_ring, rxbd, i); 1866 1867 /* not last BD in frame? */ 1868 while (!(bd_status & ENETC_RXBD_LSTATUS_F)) { 1869 bd_status = le32_to_cpu((*rxbd)->r.lstatus); 1870 size = ENETC_RXB_DMA_SIZE_XDP; 1871 1872 if (bd_status & ENETC_RXBD_LSTATUS_F) { 1873 dma_rmb(); 1874 size = le16_to_cpu((*rxbd)->r.buf_len); 1875 } 1876 1877 enetc_add_rx_buff_to_xdp(rx_ring, *i, size, xdp_buff); 1878 (*cleaned_cnt)++; 1879 enetc_rxbd_next(rx_ring, rxbd, i); 1880 } 1881 } 1882 1883 /* Convert RX buffer descriptors to TX buffer descriptors. These will be 1884 * recycled back into the RX ring in enetc_clean_tx_ring. 1885 */ 1886 static int enetc_rx_swbd_to_xdp_tx_swbd(struct enetc_tx_swbd *xdp_tx_arr, 1887 struct enetc_bdr *rx_ring, 1888 int rx_ring_first, int rx_ring_last) 1889 { 1890 int n = 0; 1891 1892 for (; rx_ring_first != rx_ring_last; 1893 n++, enetc_bdr_idx_inc(rx_ring, &rx_ring_first)) { 1894 struct enetc_rx_swbd *rx_swbd = &rx_ring->rx_swbd[rx_ring_first]; 1895 struct enetc_tx_swbd *tx_swbd = &xdp_tx_arr[n]; 1896 1897 /* No need to dma_map, we already have DMA_BIDIRECTIONAL */ 1898 tx_swbd->dma = rx_swbd->dma; 1899 tx_swbd->dir = rx_swbd->dir; 1900 tx_swbd->page = rx_swbd->page; 1901 tx_swbd->page_offset = rx_swbd->page_offset; 1902 tx_swbd->len = rx_swbd->len; 1903 tx_swbd->is_dma_page = true; 1904 tx_swbd->is_xdp_tx = true; 1905 tx_swbd->is_eof = false; 1906 } 1907 1908 /* We rely on caller providing an rx_ring_last > rx_ring_first */ 1909 xdp_tx_arr[n - 1].is_eof = true; 1910 1911 return n; 1912 } 1913 1914 static void enetc_xdp_drop(struct enetc_bdr *rx_ring, int rx_ring_first, 1915 int rx_ring_last) 1916 { 1917 while (rx_ring_first != rx_ring_last) { 1918 enetc_put_rx_buff(rx_ring, 1919 &rx_ring->rx_swbd[rx_ring_first]); 1920 enetc_bdr_idx_inc(rx_ring, &rx_ring_first); 1921 } 1922 } 1923 1924 static void enetc_bulk_flip_buff(struct enetc_bdr *rx_ring, int rx_ring_first, 1925 int rx_ring_last) 1926 { 1927 while (rx_ring_first != rx_ring_last) { 1928 enetc_flip_rx_buff(rx_ring, 1929 &rx_ring->rx_swbd[rx_ring_first]); 1930 enetc_bdr_idx_inc(rx_ring, &rx_ring_first); 1931 } 1932 } 1933 1934 static int enetc_clean_rx_ring_xdp(struct enetc_bdr *rx_ring, 1935 struct napi_struct *napi, int work_limit, 1936 struct bpf_prog *prog) 1937 { 1938 int xdp_tx_bd_cnt, xdp_tx_frm_cnt = 0, xdp_redirect_frm_cnt = 0; 1939 struct enetc_tx_swbd xdp_tx_arr[ENETC_MAX_SKB_FRAGS] = {0}; 1940 struct enetc_ndev_priv *priv = netdev_priv(rx_ring->ndev); 1941 int rx_frm_cnt = 0, rx_byte_cnt = 0; 1942 struct enetc_bdr *tx_ring; 1943 int cleaned_cnt, i; 1944 u32 xdp_act; 1945 1946 cleaned_cnt = enetc_bd_unused(rx_ring); 1947 /* next descriptor to process */ 1948 i = rx_ring->next_to_clean; 1949 1950 while (likely(rx_frm_cnt < work_limit)) { 1951 union enetc_rx_bd *rxbd, *orig_rxbd; 1952 struct xdp_buff xdp_buff; 1953 struct sk_buff *skb; 1954 int orig_i, err; 1955 u32 bd_status; 1956 1957 rxbd = enetc_rxbd(rx_ring, i); 1958 bd_status = le32_to_cpu(rxbd->r.lstatus); 1959 if (!bd_status) 1960 break; 1961 1962 enetc_wr_reg_hot(rx_ring->idr, BIT(rx_ring->index)); 1963 dma_rmb(); /* for reading other rxbd fields */ 1964 1965 if (enetc_check_bd_errors_and_consume(rx_ring, bd_status, 1966 &rxbd, &i)) 1967 break; 1968 1969 orig_rxbd = rxbd; 1970 orig_i = i; 1971 1972 enetc_build_xdp_buff(rx_ring, bd_status, &rxbd, &i, 1973 &cleaned_cnt, &xdp_buff); 1974 1975 /* When set, the outer VLAN header is extracted and reported 1976 * in the receive buffer descriptor. So rx_byte_cnt should 1977 * add the length of the extracted VLAN header. 1978 */ 1979 if (bd_status & ENETC_RXBD_FLAG_VLAN) 1980 rx_byte_cnt += VLAN_HLEN; 1981 rx_byte_cnt += xdp_get_buff_len(&xdp_buff); 1982 1983 xdp_act = bpf_prog_run_xdp(prog, &xdp_buff); 1984 1985 switch (xdp_act) { 1986 default: 1987 bpf_warn_invalid_xdp_action(rx_ring->ndev, prog, xdp_act); 1988 fallthrough; 1989 case XDP_ABORTED: 1990 trace_xdp_exception(rx_ring->ndev, prog, xdp_act); 1991 fallthrough; 1992 case XDP_DROP: 1993 enetc_xdp_drop(rx_ring, orig_i, i); 1994 rx_ring->stats.xdp_drops++; 1995 break; 1996 case XDP_PASS: 1997 skb = xdp_build_skb_from_buff(&xdp_buff); 1998 /* Probably under memory pressure, stop NAPI */ 1999 if (unlikely(!skb)) { 2000 enetc_xdp_drop(rx_ring, orig_i, i); 2001 rx_ring->stats.xdp_drops++; 2002 goto out; 2003 } 2004 2005 enetc_get_offloads(rx_ring, orig_rxbd, skb); 2006 2007 /* These buffers are about to be owned by the stack. 2008 * Update our buffer cache (the rx_swbd array elements) 2009 * with their other page halves. 2010 */ 2011 enetc_bulk_flip_buff(rx_ring, orig_i, i); 2012 2013 napi_gro_receive(napi, skb); 2014 break; 2015 case XDP_TX: 2016 tx_ring = priv->xdp_tx_ring[rx_ring->index]; 2017 if (unlikely(test_bit(ENETC_TX_DOWN, &priv->flags))) { 2018 enetc_xdp_drop(rx_ring, orig_i, i); 2019 tx_ring->stats.xdp_tx_drops++; 2020 break; 2021 } 2022 2023 xdp_tx_bd_cnt = enetc_rx_swbd_to_xdp_tx_swbd(xdp_tx_arr, 2024 rx_ring, 2025 orig_i, i); 2026 2027 if (!enetc_xdp_tx(tx_ring, xdp_tx_arr, xdp_tx_bd_cnt)) { 2028 enetc_xdp_drop(rx_ring, orig_i, i); 2029 tx_ring->stats.xdp_tx_drops++; 2030 } else { 2031 tx_ring->stats.xdp_tx++; 2032 rx_ring->xdp.xdp_tx_in_flight += xdp_tx_bd_cnt; 2033 xdp_tx_frm_cnt++; 2034 /* The XDP_TX enqueue was successful, so we 2035 * need to scrub the RX software BDs because 2036 * the ownership of the buffers no longer 2037 * belongs to the RX ring, and we must prevent 2038 * enetc_refill_rx_ring() from reusing 2039 * rx_swbd->page. 2040 */ 2041 while (orig_i != i) { 2042 rx_ring->rx_swbd[orig_i].page = NULL; 2043 enetc_bdr_idx_inc(rx_ring, &orig_i); 2044 } 2045 } 2046 break; 2047 case XDP_REDIRECT: 2048 err = xdp_do_redirect(rx_ring->ndev, &xdp_buff, prog); 2049 if (unlikely(err)) { 2050 enetc_xdp_drop(rx_ring, orig_i, i); 2051 rx_ring->stats.xdp_redirect_failures++; 2052 } else { 2053 enetc_bulk_flip_buff(rx_ring, orig_i, i); 2054 xdp_redirect_frm_cnt++; 2055 rx_ring->stats.xdp_redirect++; 2056 } 2057 } 2058 2059 rx_frm_cnt++; 2060 } 2061 2062 out: 2063 rx_ring->next_to_clean = i; 2064 2065 rx_ring->stats.packets += rx_frm_cnt; 2066 rx_ring->stats.bytes += rx_byte_cnt; 2067 2068 if (xdp_redirect_frm_cnt) 2069 xdp_do_flush(); 2070 2071 if (xdp_tx_frm_cnt) 2072 enetc_update_tx_ring_tail(tx_ring); 2073 2074 if (cleaned_cnt > rx_ring->xdp.xdp_tx_in_flight) 2075 enetc_refill_rx_ring(rx_ring, enetc_bd_unused(rx_ring) - 2076 rx_ring->xdp.xdp_tx_in_flight); 2077 2078 return rx_frm_cnt; 2079 } 2080 2081 static int enetc_poll(struct napi_struct *napi, int budget) 2082 { 2083 struct enetc_int_vector 2084 *v = container_of(napi, struct enetc_int_vector, napi); 2085 struct enetc_bdr *rx_ring = &v->rx_ring; 2086 struct bpf_prog *prog; 2087 bool complete = true; 2088 int work_done; 2089 int i; 2090 2091 enetc_lock_mdio(); 2092 2093 for (i = 0; i < v->count_tx_rings; i++) 2094 if (!enetc_clean_tx_ring(&v->tx_ring[i], budget)) 2095 complete = false; 2096 2097 prog = rx_ring->xdp.prog; 2098 if (prog) 2099 work_done = enetc_clean_rx_ring_xdp(rx_ring, napi, budget, prog); 2100 else 2101 work_done = enetc_clean_rx_ring(rx_ring, napi, budget); 2102 if (work_done == budget) 2103 complete = false; 2104 if (work_done) 2105 v->rx_napi_work = true; 2106 2107 if (!complete) { 2108 enetc_unlock_mdio(); 2109 return budget; 2110 } 2111 2112 napi_complete_done(napi, work_done); 2113 2114 if (likely(v->rx_dim_en)) 2115 enetc_rx_net_dim(v); 2116 2117 v->rx_napi_work = false; 2118 2119 /* enable interrupts */ 2120 enetc_wr_reg_hot(v->rbier, ENETC_RBIER_RXTIE); 2121 2122 for_each_set_bit(i, &v->tx_rings_map, ENETC_MAX_NUM_TXQS) 2123 enetc_wr_reg_hot(v->tbier_base + ENETC_BDR_OFF(i), 2124 ENETC_TBIER_TXTIE); 2125 2126 enetc_unlock_mdio(); 2127 2128 return work_done; 2129 } 2130 2131 /* Probing and Init */ 2132 #define ENETC_MAX_RFS_SIZE 64 2133 void enetc_get_si_caps(struct enetc_si *si) 2134 { 2135 struct enetc_hw *hw = &si->hw; 2136 u32 val; 2137 2138 /* find out how many of various resources we have to work with */ 2139 val = enetc_rd(hw, ENETC_SICAPR0); 2140 si->num_rx_rings = (val >> 16) & 0xff; 2141 si->num_tx_rings = val & 0xff; 2142 2143 val = enetc_rd(hw, ENETC_SIPCAPR0); 2144 if (val & ENETC_SIPCAPR0_RFS) { 2145 val = enetc_rd(hw, ENETC_SIRFSCAPR); 2146 si->num_fs_entries = ENETC_SIRFSCAPR_GET_NUM_RFS(val); 2147 si->num_fs_entries = min(si->num_fs_entries, ENETC_MAX_RFS_SIZE); 2148 } else { 2149 /* ENETC which not supports RFS */ 2150 si->num_fs_entries = 0; 2151 } 2152 2153 si->num_rss = 0; 2154 val = enetc_rd(hw, ENETC_SIPCAPR0); 2155 if (val & ENETC_SIPCAPR0_RSS) { 2156 u32 rss; 2157 2158 rss = enetc_rd(hw, ENETC_SIRSSCAPR); 2159 si->num_rss = ENETC_SIRSSCAPR_GET_NUM_RSS(rss); 2160 } 2161 2162 if (val & ENETC_SIPCAPR0_LSO) 2163 si->hw_features |= ENETC_SI_F_LSO; 2164 } 2165 EXPORT_SYMBOL_GPL(enetc_get_si_caps); 2166 2167 static int enetc_dma_alloc_bdr(struct enetc_bdr_resource *res) 2168 { 2169 size_t bd_base_size = res->bd_count * res->bd_size; 2170 2171 res->bd_base = dma_alloc_coherent(res->dev, bd_base_size, 2172 &res->bd_dma_base, GFP_KERNEL); 2173 if (!res->bd_base) 2174 return -ENOMEM; 2175 2176 /* h/w requires 128B alignment */ 2177 if (!IS_ALIGNED(res->bd_dma_base, 128)) { 2178 dma_free_coherent(res->dev, bd_base_size, res->bd_base, 2179 res->bd_dma_base); 2180 return -EINVAL; 2181 } 2182 2183 return 0; 2184 } 2185 2186 static void enetc_dma_free_bdr(const struct enetc_bdr_resource *res) 2187 { 2188 size_t bd_base_size = res->bd_count * res->bd_size; 2189 2190 dma_free_coherent(res->dev, bd_base_size, res->bd_base, 2191 res->bd_dma_base); 2192 } 2193 2194 static int enetc_alloc_tx_resource(struct enetc_bdr_resource *res, 2195 struct device *dev, size_t bd_count) 2196 { 2197 int err; 2198 2199 res->dev = dev; 2200 res->bd_count = bd_count; 2201 res->bd_size = sizeof(union enetc_tx_bd); 2202 2203 res->tx_swbd = vcalloc(bd_count, sizeof(*res->tx_swbd)); 2204 if (!res->tx_swbd) 2205 return -ENOMEM; 2206 2207 err = enetc_dma_alloc_bdr(res); 2208 if (err) 2209 goto err_alloc_bdr; 2210 2211 res->tso_headers = dma_alloc_coherent(dev, bd_count * TSO_HEADER_SIZE, 2212 &res->tso_headers_dma, 2213 GFP_KERNEL); 2214 if (!res->tso_headers) { 2215 err = -ENOMEM; 2216 goto err_alloc_tso; 2217 } 2218 2219 return 0; 2220 2221 err_alloc_tso: 2222 enetc_dma_free_bdr(res); 2223 err_alloc_bdr: 2224 vfree(res->tx_swbd); 2225 res->tx_swbd = NULL; 2226 2227 return err; 2228 } 2229 2230 static void enetc_free_tx_resource(const struct enetc_bdr_resource *res) 2231 { 2232 dma_free_coherent(res->dev, res->bd_count * TSO_HEADER_SIZE, 2233 res->tso_headers, res->tso_headers_dma); 2234 enetc_dma_free_bdr(res); 2235 vfree(res->tx_swbd); 2236 } 2237 2238 static struct enetc_bdr_resource * 2239 enetc_alloc_tx_resources(struct enetc_ndev_priv *priv) 2240 { 2241 struct enetc_bdr_resource *tx_res; 2242 int i, err; 2243 2244 tx_res = kcalloc(priv->num_tx_rings, sizeof(*tx_res), GFP_KERNEL); 2245 if (!tx_res) 2246 return ERR_PTR(-ENOMEM); 2247 2248 for (i = 0; i < priv->num_tx_rings; i++) { 2249 struct enetc_bdr *tx_ring = priv->tx_ring[i]; 2250 2251 err = enetc_alloc_tx_resource(&tx_res[i], tx_ring->dev, 2252 tx_ring->bd_count); 2253 if (err) 2254 goto fail; 2255 } 2256 2257 return tx_res; 2258 2259 fail: 2260 while (i-- > 0) 2261 enetc_free_tx_resource(&tx_res[i]); 2262 2263 kfree(tx_res); 2264 2265 return ERR_PTR(err); 2266 } 2267 2268 static void enetc_free_tx_resources(const struct enetc_bdr_resource *tx_res, 2269 size_t num_resources) 2270 { 2271 size_t i; 2272 2273 for (i = 0; i < num_resources; i++) 2274 enetc_free_tx_resource(&tx_res[i]); 2275 2276 kfree(tx_res); 2277 } 2278 2279 static int enetc_alloc_rx_resource(struct enetc_bdr_resource *res, 2280 struct device *dev, size_t bd_count, 2281 bool extended) 2282 { 2283 int err; 2284 2285 res->dev = dev; 2286 res->bd_count = bd_count; 2287 res->bd_size = sizeof(union enetc_rx_bd); 2288 if (extended) 2289 res->bd_size *= 2; 2290 2291 res->rx_swbd = vcalloc(bd_count, sizeof(struct enetc_rx_swbd)); 2292 if (!res->rx_swbd) 2293 return -ENOMEM; 2294 2295 err = enetc_dma_alloc_bdr(res); 2296 if (err) { 2297 vfree(res->rx_swbd); 2298 return err; 2299 } 2300 2301 return 0; 2302 } 2303 2304 static void enetc_free_rx_resource(const struct enetc_bdr_resource *res) 2305 { 2306 enetc_dma_free_bdr(res); 2307 vfree(res->rx_swbd); 2308 } 2309 2310 static struct enetc_bdr_resource * 2311 enetc_alloc_rx_resources(struct enetc_ndev_priv *priv, bool extended) 2312 { 2313 struct enetc_bdr_resource *rx_res; 2314 int i, err; 2315 2316 rx_res = kcalloc(priv->num_rx_rings, sizeof(*rx_res), GFP_KERNEL); 2317 if (!rx_res) 2318 return ERR_PTR(-ENOMEM); 2319 2320 for (i = 0; i < priv->num_rx_rings; i++) { 2321 struct enetc_bdr *rx_ring = priv->rx_ring[i]; 2322 2323 err = enetc_alloc_rx_resource(&rx_res[i], rx_ring->dev, 2324 rx_ring->bd_count, extended); 2325 if (err) 2326 goto fail; 2327 } 2328 2329 return rx_res; 2330 2331 fail: 2332 while (i-- > 0) 2333 enetc_free_rx_resource(&rx_res[i]); 2334 2335 kfree(rx_res); 2336 2337 return ERR_PTR(err); 2338 } 2339 2340 static void enetc_free_rx_resources(const struct enetc_bdr_resource *rx_res, 2341 size_t num_resources) 2342 { 2343 size_t i; 2344 2345 for (i = 0; i < num_resources; i++) 2346 enetc_free_rx_resource(&rx_res[i]); 2347 2348 kfree(rx_res); 2349 } 2350 2351 static void enetc_assign_tx_resource(struct enetc_bdr *tx_ring, 2352 const struct enetc_bdr_resource *res) 2353 { 2354 tx_ring->bd_base = res ? res->bd_base : NULL; 2355 tx_ring->bd_dma_base = res ? res->bd_dma_base : 0; 2356 tx_ring->tx_swbd = res ? res->tx_swbd : NULL; 2357 tx_ring->tso_headers = res ? res->tso_headers : NULL; 2358 tx_ring->tso_headers_dma = res ? res->tso_headers_dma : 0; 2359 } 2360 2361 static void enetc_assign_rx_resource(struct enetc_bdr *rx_ring, 2362 const struct enetc_bdr_resource *res) 2363 { 2364 rx_ring->bd_base = res ? res->bd_base : NULL; 2365 rx_ring->bd_dma_base = res ? res->bd_dma_base : 0; 2366 rx_ring->rx_swbd = res ? res->rx_swbd : NULL; 2367 } 2368 2369 static void enetc_assign_tx_resources(struct enetc_ndev_priv *priv, 2370 const struct enetc_bdr_resource *res) 2371 { 2372 int i; 2373 2374 if (priv->tx_res) 2375 enetc_free_tx_resources(priv->tx_res, priv->num_tx_rings); 2376 2377 for (i = 0; i < priv->num_tx_rings; i++) { 2378 enetc_assign_tx_resource(priv->tx_ring[i], 2379 res ? &res[i] : NULL); 2380 } 2381 2382 priv->tx_res = res; 2383 } 2384 2385 static void enetc_assign_rx_resources(struct enetc_ndev_priv *priv, 2386 const struct enetc_bdr_resource *res) 2387 { 2388 int i; 2389 2390 if (priv->rx_res) 2391 enetc_free_rx_resources(priv->rx_res, priv->num_rx_rings); 2392 2393 for (i = 0; i < priv->num_rx_rings; i++) { 2394 enetc_assign_rx_resource(priv->rx_ring[i], 2395 res ? &res[i] : NULL); 2396 } 2397 2398 priv->rx_res = res; 2399 } 2400 2401 static void enetc_free_tx_ring(struct enetc_bdr *tx_ring) 2402 { 2403 int i; 2404 2405 for (i = 0; i < tx_ring->bd_count; i++) { 2406 struct enetc_tx_swbd *tx_swbd = &tx_ring->tx_swbd[i]; 2407 2408 enetc_free_tx_frame(tx_ring, tx_swbd); 2409 } 2410 } 2411 2412 static void enetc_free_rx_ring(struct enetc_bdr *rx_ring) 2413 { 2414 int i; 2415 2416 for (i = 0; i < rx_ring->bd_count; i++) { 2417 struct enetc_rx_swbd *rx_swbd = &rx_ring->rx_swbd[i]; 2418 2419 if (!rx_swbd->page) 2420 continue; 2421 2422 dma_unmap_page(rx_ring->dev, rx_swbd->dma, PAGE_SIZE, 2423 rx_swbd->dir); 2424 __free_page(rx_swbd->page); 2425 rx_swbd->page = NULL; 2426 } 2427 } 2428 2429 static void enetc_free_rxtx_rings(struct enetc_ndev_priv *priv) 2430 { 2431 int i; 2432 2433 for (i = 0; i < priv->num_rx_rings; i++) 2434 enetc_free_rx_ring(priv->rx_ring[i]); 2435 2436 for (i = 0; i < priv->num_tx_rings; i++) 2437 enetc_free_tx_ring(priv->tx_ring[i]); 2438 } 2439 2440 static int enetc_setup_default_rss_table(struct enetc_si *si, int num_groups) 2441 { 2442 int *rss_table; 2443 int i; 2444 2445 rss_table = kmalloc_array(si->num_rss, sizeof(*rss_table), GFP_KERNEL); 2446 if (!rss_table) 2447 return -ENOMEM; 2448 2449 /* Set up RSS table defaults */ 2450 for (i = 0; i < si->num_rss; i++) 2451 rss_table[i] = i % num_groups; 2452 2453 si->ops->set_rss_table(si, rss_table, si->num_rss); 2454 2455 kfree(rss_table); 2456 2457 return 0; 2458 } 2459 2460 static void enetc_set_lso_flags_mask(struct enetc_hw *hw) 2461 { 2462 enetc_wr(hw, ENETC4_SILSOSFMR0, 2463 SILSOSFMR0_VAL_SET(ENETC4_TCP_NL_SEG_FLAGS_DMASK, 2464 ENETC4_TCP_NL_SEG_FLAGS_DMASK)); 2465 enetc_wr(hw, ENETC4_SILSOSFMR1, 0); 2466 } 2467 2468 static void enetc_set_rss(struct net_device *ndev, int en) 2469 { 2470 struct enetc_ndev_priv *priv = netdev_priv(ndev); 2471 struct enetc_hw *hw = &priv->si->hw; 2472 u32 reg; 2473 2474 enetc_wr(hw, ENETC_SIRBGCR, priv->num_rx_rings); 2475 2476 reg = enetc_rd(hw, ENETC_SIMR); 2477 reg &= ~ENETC_SIMR_RSSE; 2478 reg |= (en) ? ENETC_SIMR_RSSE : 0; 2479 enetc_wr(hw, ENETC_SIMR, reg); 2480 } 2481 2482 int enetc_configure_si(struct enetc_ndev_priv *priv) 2483 { 2484 struct enetc_si *si = priv->si; 2485 struct enetc_hw *hw = &si->hw; 2486 int err; 2487 2488 /* set SI cache attributes */ 2489 enetc_wr(hw, ENETC_SICAR0, 2490 ENETC_SICAR_RD_COHERENT | ENETC_SICAR_WR_COHERENT); 2491 enetc_wr(hw, ENETC_SICAR1, ENETC_SICAR_MSI); 2492 /* enable SI */ 2493 enetc_wr(hw, ENETC_SIMR, ENETC_SIMR_EN); 2494 2495 if (si->hw_features & ENETC_SI_F_LSO) 2496 enetc_set_lso_flags_mask(hw); 2497 2498 if (si->num_rss) { 2499 err = enetc_setup_default_rss_table(si, priv->num_rx_rings); 2500 if (err) 2501 return err; 2502 2503 if (priv->ndev->features & NETIF_F_RXHASH) 2504 enetc_set_rss(priv->ndev, true); 2505 } 2506 2507 return 0; 2508 } 2509 EXPORT_SYMBOL_GPL(enetc_configure_si); 2510 2511 void enetc_init_si_rings_params(struct enetc_ndev_priv *priv) 2512 { 2513 struct enetc_si *si = priv->si; 2514 int cpus = num_online_cpus(); 2515 2516 priv->tx_bd_count = ENETC_TX_RING_DEFAULT_SIZE; 2517 priv->rx_bd_count = ENETC_RX_RING_DEFAULT_SIZE; 2518 2519 /* Enable all available TX rings in order to configure as many 2520 * priorities as possible, when needed. 2521 * TODO: Make # of TX rings run-time configurable 2522 */ 2523 priv->num_rx_rings = min_t(int, cpus, si->num_rx_rings); 2524 priv->num_tx_rings = si->num_tx_rings; 2525 priv->bdr_int_num = priv->num_rx_rings; 2526 priv->ic_mode = ENETC_IC_RX_ADAPTIVE | ENETC_IC_TX_MANUAL; 2527 priv->tx_ictt = enetc_usecs_to_cycles(600, priv->sysclk_freq); 2528 } 2529 EXPORT_SYMBOL_GPL(enetc_init_si_rings_params); 2530 2531 int enetc_alloc_si_resources(struct enetc_ndev_priv *priv) 2532 { 2533 struct enetc_si *si = priv->si; 2534 2535 priv->cls_rules = kcalloc(si->num_fs_entries, sizeof(*priv->cls_rules), 2536 GFP_KERNEL); 2537 if (!priv->cls_rules) 2538 return -ENOMEM; 2539 2540 return 0; 2541 } 2542 EXPORT_SYMBOL_GPL(enetc_alloc_si_resources); 2543 2544 void enetc_free_si_resources(struct enetc_ndev_priv *priv) 2545 { 2546 kfree(priv->cls_rules); 2547 } 2548 EXPORT_SYMBOL_GPL(enetc_free_si_resources); 2549 2550 static void enetc_setup_txbdr(struct enetc_hw *hw, struct enetc_bdr *tx_ring) 2551 { 2552 int idx = tx_ring->index; 2553 u32 tbmr; 2554 2555 enetc_txbdr_wr(hw, idx, ENETC_TBBAR0, 2556 lower_32_bits(tx_ring->bd_dma_base)); 2557 2558 enetc_txbdr_wr(hw, idx, ENETC_TBBAR1, 2559 upper_32_bits(tx_ring->bd_dma_base)); 2560 2561 WARN_ON(!IS_ALIGNED(tx_ring->bd_count, 64)); /* multiple of 64 */ 2562 enetc_txbdr_wr(hw, idx, ENETC_TBLENR, 2563 ENETC_RTBLENR_LEN(tx_ring->bd_count)); 2564 2565 /* clearing PI/CI registers for Tx not supported, adjust sw indexes */ 2566 tx_ring->next_to_use = enetc_txbdr_rd(hw, idx, ENETC_TBPIR); 2567 tx_ring->next_to_clean = enetc_txbdr_rd(hw, idx, ENETC_TBCIR); 2568 2569 /* enable Tx ints by setting pkt thr to 1 */ 2570 enetc_txbdr_wr(hw, idx, ENETC_TBICR0, ENETC_TBICR0_ICEN | 0x1); 2571 2572 tbmr = ENETC_TBMR_SET_PRIO(tx_ring->prio); 2573 if (tx_ring->ndev->features & NETIF_F_HW_VLAN_CTAG_TX) 2574 tbmr |= ENETC_TBMR_VIH; 2575 2576 /* enable ring */ 2577 enetc_txbdr_wr(hw, idx, ENETC_TBMR, tbmr); 2578 2579 tx_ring->tpir = hw->reg + ENETC_BDR(TX, idx, ENETC_TBPIR); 2580 tx_ring->tcir = hw->reg + ENETC_BDR(TX, idx, ENETC_TBCIR); 2581 tx_ring->idr = hw->reg + ENETC_SITXIDR; 2582 } 2583 2584 static void enetc_setup_rxbdr(struct enetc_hw *hw, struct enetc_bdr *rx_ring, 2585 bool extended) 2586 { 2587 int idx = rx_ring->index; 2588 u32 rbmr = 0; 2589 2590 enetc_rxbdr_wr(hw, idx, ENETC_RBBAR0, 2591 lower_32_bits(rx_ring->bd_dma_base)); 2592 2593 enetc_rxbdr_wr(hw, idx, ENETC_RBBAR1, 2594 upper_32_bits(rx_ring->bd_dma_base)); 2595 2596 WARN_ON(!IS_ALIGNED(rx_ring->bd_count, 64)); /* multiple of 64 */ 2597 enetc_rxbdr_wr(hw, idx, ENETC_RBLENR, 2598 ENETC_RTBLENR_LEN(rx_ring->bd_count)); 2599 2600 if (rx_ring->xdp.prog) 2601 enetc_rxbdr_wr(hw, idx, ENETC_RBBSR, ENETC_RXB_DMA_SIZE_XDP); 2602 else 2603 enetc_rxbdr_wr(hw, idx, ENETC_RBBSR, ENETC_RXB_DMA_SIZE); 2604 2605 /* Also prepare the consumer index in case page allocation never 2606 * succeeds. In that case, hardware will never advance producer index 2607 * to match consumer index, and will drop all frames. 2608 */ 2609 enetc_rxbdr_wr(hw, idx, ENETC_RBPIR, 0); 2610 enetc_rxbdr_wr(hw, idx, ENETC_RBCIR, 1); 2611 2612 /* enable Rx ints by setting pkt thr to 1 */ 2613 enetc_rxbdr_wr(hw, idx, ENETC_RBICR0, ENETC_RBICR0_ICEN | 0x1); 2614 2615 rx_ring->ext_en = extended; 2616 if (rx_ring->ext_en) 2617 rbmr |= ENETC_RBMR_BDS; 2618 2619 if (rx_ring->ndev->features & NETIF_F_HW_VLAN_CTAG_RX) 2620 rbmr |= ENETC_RBMR_VTE; 2621 2622 rx_ring->rcir = hw->reg + ENETC_BDR(RX, idx, ENETC_RBCIR); 2623 rx_ring->idr = hw->reg + ENETC_SIRXIDR; 2624 2625 rx_ring->next_to_clean = 0; 2626 rx_ring->next_to_use = 0; 2627 rx_ring->next_to_alloc = 0; 2628 2629 enetc_lock_mdio(); 2630 enetc_refill_rx_ring(rx_ring, enetc_bd_unused(rx_ring)); 2631 enetc_unlock_mdio(); 2632 2633 enetc_rxbdr_wr(hw, idx, ENETC_RBMR, rbmr); 2634 } 2635 2636 static void enetc_setup_bdrs(struct enetc_ndev_priv *priv, bool extended) 2637 { 2638 struct enetc_hw *hw = &priv->si->hw; 2639 int i; 2640 2641 for (i = 0; i < priv->num_tx_rings; i++) 2642 enetc_setup_txbdr(hw, priv->tx_ring[i]); 2643 2644 for (i = 0; i < priv->num_rx_rings; i++) 2645 enetc_setup_rxbdr(hw, priv->rx_ring[i], extended); 2646 } 2647 2648 static void enetc_enable_txbdr(struct enetc_hw *hw, struct enetc_bdr *tx_ring) 2649 { 2650 int idx = tx_ring->index; 2651 u32 tbmr; 2652 2653 tbmr = enetc_txbdr_rd(hw, idx, ENETC_TBMR); 2654 tbmr |= ENETC_TBMR_EN; 2655 enetc_txbdr_wr(hw, idx, ENETC_TBMR, tbmr); 2656 } 2657 2658 static void enetc_enable_rxbdr(struct enetc_hw *hw, struct enetc_bdr *rx_ring) 2659 { 2660 int idx = rx_ring->index; 2661 u32 rbmr; 2662 2663 rbmr = enetc_rxbdr_rd(hw, idx, ENETC_RBMR); 2664 rbmr |= ENETC_RBMR_EN; 2665 enetc_rxbdr_wr(hw, idx, ENETC_RBMR, rbmr); 2666 } 2667 2668 static void enetc_enable_rx_bdrs(struct enetc_ndev_priv *priv) 2669 { 2670 struct enetc_hw *hw = &priv->si->hw; 2671 int i; 2672 2673 for (i = 0; i < priv->num_rx_rings; i++) 2674 enetc_enable_rxbdr(hw, priv->rx_ring[i]); 2675 } 2676 2677 static void enetc_enable_tx_bdrs(struct enetc_ndev_priv *priv) 2678 { 2679 struct enetc_hw *hw = &priv->si->hw; 2680 int i; 2681 2682 for (i = 0; i < priv->num_tx_rings; i++) 2683 enetc_enable_txbdr(hw, priv->tx_ring[i]); 2684 } 2685 2686 static void enetc_disable_rxbdr(struct enetc_hw *hw, struct enetc_bdr *rx_ring) 2687 { 2688 int idx = rx_ring->index; 2689 2690 /* disable EN bit on ring */ 2691 enetc_rxbdr_wr(hw, idx, ENETC_RBMR, 0); 2692 } 2693 2694 static void enetc_disable_txbdr(struct enetc_hw *hw, struct enetc_bdr *rx_ring) 2695 { 2696 int idx = rx_ring->index; 2697 2698 /* disable EN bit on ring */ 2699 enetc_txbdr_wr(hw, idx, ENETC_TBMR, 0); 2700 } 2701 2702 static void enetc_disable_rx_bdrs(struct enetc_ndev_priv *priv) 2703 { 2704 struct enetc_hw *hw = &priv->si->hw; 2705 int i; 2706 2707 for (i = 0; i < priv->num_rx_rings; i++) 2708 enetc_disable_rxbdr(hw, priv->rx_ring[i]); 2709 } 2710 2711 static void enetc_disable_tx_bdrs(struct enetc_ndev_priv *priv) 2712 { 2713 struct enetc_hw *hw = &priv->si->hw; 2714 int i; 2715 2716 for (i = 0; i < priv->num_tx_rings; i++) 2717 enetc_disable_txbdr(hw, priv->tx_ring[i]); 2718 } 2719 2720 static void enetc_wait_txbdr(struct enetc_hw *hw, struct enetc_bdr *tx_ring) 2721 { 2722 int delay = 8, timeout = 100; 2723 int idx = tx_ring->index; 2724 2725 /* wait for busy to clear */ 2726 while (delay < timeout && 2727 enetc_txbdr_rd(hw, idx, ENETC_TBSR) & ENETC_TBSR_BUSY) { 2728 msleep(delay); 2729 delay *= 2; 2730 } 2731 2732 if (delay >= timeout) 2733 netdev_warn(tx_ring->ndev, "timeout for tx ring #%d clear\n", 2734 idx); 2735 } 2736 2737 static void enetc_wait_bdrs(struct enetc_ndev_priv *priv) 2738 { 2739 struct enetc_hw *hw = &priv->si->hw; 2740 int i; 2741 2742 for (i = 0; i < priv->num_tx_rings; i++) 2743 enetc_wait_txbdr(hw, priv->tx_ring[i]); 2744 } 2745 2746 static int enetc_setup_irqs(struct enetc_ndev_priv *priv) 2747 { 2748 struct pci_dev *pdev = priv->si->pdev; 2749 struct enetc_hw *hw = &priv->si->hw; 2750 int i, j, err; 2751 2752 for (i = 0; i < priv->bdr_int_num; i++) { 2753 int irq = pci_irq_vector(pdev, ENETC_BDR_INT_BASE_IDX + i); 2754 struct enetc_int_vector *v = priv->int_vector[i]; 2755 int entry = ENETC_BDR_INT_BASE_IDX + i; 2756 2757 snprintf(v->name, sizeof(v->name), "%s-rxtx%d", 2758 priv->ndev->name, i); 2759 err = request_irq(irq, enetc_msix, IRQF_NO_AUTOEN, v->name, v); 2760 if (err) { 2761 dev_err(priv->dev, "request_irq() failed!\n"); 2762 goto irq_err; 2763 } 2764 2765 v->tbier_base = hw->reg + ENETC_BDR(TX, 0, ENETC_TBIER); 2766 v->rbier = hw->reg + ENETC_BDR(RX, i, ENETC_RBIER); 2767 v->ricr1 = hw->reg + ENETC_BDR(RX, i, ENETC_RBICR1); 2768 2769 enetc_wr(hw, ENETC_SIMSIRRV(i), entry); 2770 2771 for (j = 0; j < v->count_tx_rings; j++) { 2772 int idx = v->tx_ring[j].index; 2773 2774 enetc_wr(hw, ENETC_SIMSITRV(idx), entry); 2775 } 2776 irq_set_affinity_hint(irq, get_cpu_mask(i % num_online_cpus())); 2777 } 2778 2779 return 0; 2780 2781 irq_err: 2782 while (i--) { 2783 int irq = pci_irq_vector(pdev, ENETC_BDR_INT_BASE_IDX + i); 2784 2785 irq_set_affinity_hint(irq, NULL); 2786 free_irq(irq, priv->int_vector[i]); 2787 } 2788 2789 return err; 2790 } 2791 2792 static void enetc_free_irqs(struct enetc_ndev_priv *priv) 2793 { 2794 struct pci_dev *pdev = priv->si->pdev; 2795 int i; 2796 2797 for (i = 0; i < priv->bdr_int_num; i++) { 2798 int irq = pci_irq_vector(pdev, ENETC_BDR_INT_BASE_IDX + i); 2799 2800 irq_set_affinity_hint(irq, NULL); 2801 free_irq(irq, priv->int_vector[i]); 2802 } 2803 } 2804 2805 static void enetc_setup_interrupts(struct enetc_ndev_priv *priv) 2806 { 2807 struct enetc_hw *hw = &priv->si->hw; 2808 u32 icpt, ictt; 2809 int i; 2810 2811 /* enable Tx & Rx event indication */ 2812 if (priv->ic_mode & 2813 (ENETC_IC_RX_MANUAL | ENETC_IC_RX_ADAPTIVE)) { 2814 icpt = ENETC_RBICR0_SET_ICPT(ENETC_RXIC_PKTTHR); 2815 /* init to non-0 minimum, will be adjusted later */ 2816 ictt = 0x1; 2817 } else { 2818 icpt = 0x1; /* enable Rx ints by setting pkt thr to 1 */ 2819 ictt = 0; 2820 } 2821 2822 for (i = 0; i < priv->num_rx_rings; i++) { 2823 enetc_rxbdr_wr(hw, i, ENETC_RBICR1, ictt); 2824 enetc_rxbdr_wr(hw, i, ENETC_RBICR0, ENETC_RBICR0_ICEN | icpt); 2825 enetc_rxbdr_wr(hw, i, ENETC_RBIER, ENETC_RBIER_RXTIE); 2826 } 2827 2828 if (priv->ic_mode & ENETC_IC_TX_MANUAL) 2829 icpt = ENETC_TBICR0_SET_ICPT(ENETC_TXIC_PKTTHR); 2830 else 2831 icpt = 0x1; /* enable Tx ints by setting pkt thr to 1 */ 2832 2833 for (i = 0; i < priv->num_tx_rings; i++) { 2834 enetc_txbdr_wr(hw, i, ENETC_TBICR1, priv->tx_ictt); 2835 enetc_txbdr_wr(hw, i, ENETC_TBICR0, ENETC_TBICR0_ICEN | icpt); 2836 enetc_txbdr_wr(hw, i, ENETC_TBIER, ENETC_TBIER_TXTIE); 2837 } 2838 } 2839 2840 static void enetc_clear_interrupts(struct enetc_ndev_priv *priv) 2841 { 2842 struct enetc_hw *hw = &priv->si->hw; 2843 int i; 2844 2845 for (i = 0; i < priv->num_tx_rings; i++) 2846 enetc_txbdr_wr(hw, i, ENETC_TBIER, 0); 2847 2848 for (i = 0; i < priv->num_rx_rings; i++) 2849 enetc_rxbdr_wr(hw, i, ENETC_RBIER, 0); 2850 } 2851 2852 static int enetc_phylink_connect(struct net_device *ndev) 2853 { 2854 struct enetc_ndev_priv *priv = netdev_priv(ndev); 2855 struct ethtool_keee edata; 2856 int err; 2857 2858 if (!priv->phylink) { 2859 /* phy-less mode */ 2860 netif_carrier_on(ndev); 2861 return 0; 2862 } 2863 2864 err = phylink_of_phy_connect(priv->phylink, priv->dev->of_node, 0); 2865 if (err) { 2866 dev_err(&ndev->dev, "could not attach to PHY\n"); 2867 return err; 2868 } 2869 2870 /* disable EEE autoneg, until ENETC driver supports it */ 2871 memset(&edata, 0, sizeof(struct ethtool_keee)); 2872 phylink_ethtool_set_eee(priv->phylink, &edata); 2873 2874 phylink_start(priv->phylink); 2875 2876 return 0; 2877 } 2878 2879 static void enetc_tx_onestep_tstamp(struct work_struct *work) 2880 { 2881 struct enetc_ndev_priv *priv; 2882 struct sk_buff *skb; 2883 2884 priv = container_of(work, struct enetc_ndev_priv, tx_onestep_tstamp); 2885 2886 netif_tx_lock_bh(priv->ndev); 2887 2888 clear_bit_unlock(ENETC_TX_ONESTEP_TSTAMP_IN_PROGRESS, &priv->flags); 2889 skb = skb_dequeue(&priv->tx_skbs); 2890 if (skb) 2891 enetc_start_xmit(skb, priv->ndev); 2892 2893 netif_tx_unlock_bh(priv->ndev); 2894 } 2895 2896 static void enetc_tx_onestep_tstamp_init(struct enetc_ndev_priv *priv) 2897 { 2898 INIT_WORK(&priv->tx_onestep_tstamp, enetc_tx_onestep_tstamp); 2899 skb_queue_head_init(&priv->tx_skbs); 2900 } 2901 2902 void enetc_start(struct net_device *ndev) 2903 { 2904 struct enetc_ndev_priv *priv = netdev_priv(ndev); 2905 int i; 2906 2907 enetc_setup_interrupts(priv); 2908 2909 for (i = 0; i < priv->bdr_int_num; i++) { 2910 int irq = pci_irq_vector(priv->si->pdev, 2911 ENETC_BDR_INT_BASE_IDX + i); 2912 2913 napi_enable(&priv->int_vector[i]->napi); 2914 enable_irq(irq); 2915 } 2916 2917 enetc_enable_tx_bdrs(priv); 2918 2919 enetc_enable_rx_bdrs(priv); 2920 2921 netif_tx_start_all_queues(ndev); 2922 2923 clear_bit(ENETC_TX_DOWN, &priv->flags); 2924 } 2925 EXPORT_SYMBOL_GPL(enetc_start); 2926 2927 int enetc_open(struct net_device *ndev) 2928 { 2929 struct enetc_ndev_priv *priv = netdev_priv(ndev); 2930 struct enetc_bdr_resource *tx_res, *rx_res; 2931 bool extended; 2932 int err; 2933 2934 extended = !!(priv->active_offloads & ENETC_F_RX_TSTAMP); 2935 2936 err = clk_prepare_enable(priv->ref_clk); 2937 if (err) 2938 return err; 2939 2940 err = enetc_setup_irqs(priv); 2941 if (err) 2942 goto err_setup_irqs; 2943 2944 err = enetc_phylink_connect(ndev); 2945 if (err) 2946 goto err_phy_connect; 2947 2948 tx_res = enetc_alloc_tx_resources(priv); 2949 if (IS_ERR(tx_res)) { 2950 err = PTR_ERR(tx_res); 2951 goto err_alloc_tx; 2952 } 2953 2954 rx_res = enetc_alloc_rx_resources(priv, extended); 2955 if (IS_ERR(rx_res)) { 2956 err = PTR_ERR(rx_res); 2957 goto err_alloc_rx; 2958 } 2959 2960 enetc_tx_onestep_tstamp_init(priv); 2961 enetc_assign_tx_resources(priv, tx_res); 2962 enetc_assign_rx_resources(priv, rx_res); 2963 enetc_setup_bdrs(priv, extended); 2964 enetc_start(ndev); 2965 2966 return 0; 2967 2968 err_alloc_rx: 2969 enetc_free_tx_resources(tx_res, priv->num_tx_rings); 2970 err_alloc_tx: 2971 if (priv->phylink) 2972 phylink_disconnect_phy(priv->phylink); 2973 err_phy_connect: 2974 enetc_free_irqs(priv); 2975 err_setup_irqs: 2976 clk_disable_unprepare(priv->ref_clk); 2977 2978 return err; 2979 } 2980 EXPORT_SYMBOL_GPL(enetc_open); 2981 2982 void enetc_stop(struct net_device *ndev) 2983 { 2984 struct enetc_ndev_priv *priv = netdev_priv(ndev); 2985 int i; 2986 2987 set_bit(ENETC_TX_DOWN, &priv->flags); 2988 2989 netif_tx_stop_all_queues(ndev); 2990 2991 enetc_disable_rx_bdrs(priv); 2992 2993 enetc_wait_bdrs(priv); 2994 2995 enetc_disable_tx_bdrs(priv); 2996 2997 for (i = 0; i < priv->bdr_int_num; i++) { 2998 int irq = pci_irq_vector(priv->si->pdev, 2999 ENETC_BDR_INT_BASE_IDX + i); 3000 3001 disable_irq(irq); 3002 napi_synchronize(&priv->int_vector[i]->napi); 3003 napi_disable(&priv->int_vector[i]->napi); 3004 } 3005 3006 enetc_clear_interrupts(priv); 3007 } 3008 EXPORT_SYMBOL_GPL(enetc_stop); 3009 3010 int enetc_close(struct net_device *ndev) 3011 { 3012 struct enetc_ndev_priv *priv = netdev_priv(ndev); 3013 3014 enetc_stop(ndev); 3015 3016 if (priv->phylink) { 3017 phylink_stop(priv->phylink); 3018 phylink_disconnect_phy(priv->phylink); 3019 } else { 3020 netif_carrier_off(ndev); 3021 } 3022 3023 enetc_free_rxtx_rings(priv); 3024 3025 /* Avoids dangling pointers and also frees old resources */ 3026 enetc_assign_rx_resources(priv, NULL); 3027 enetc_assign_tx_resources(priv, NULL); 3028 3029 enetc_free_irqs(priv); 3030 clk_disable_unprepare(priv->ref_clk); 3031 3032 return 0; 3033 } 3034 EXPORT_SYMBOL_GPL(enetc_close); 3035 3036 static int enetc_reconfigure(struct enetc_ndev_priv *priv, bool extended, 3037 int (*cb)(struct enetc_ndev_priv *priv, void *ctx), 3038 void *ctx) 3039 { 3040 struct enetc_bdr_resource *tx_res, *rx_res; 3041 int err; 3042 3043 ASSERT_RTNL(); 3044 3045 /* If the interface is down, run the callback right away, 3046 * without reconfiguration. 3047 */ 3048 if (!netif_running(priv->ndev)) { 3049 if (cb) { 3050 err = cb(priv, ctx); 3051 if (err) 3052 return err; 3053 } 3054 3055 return 0; 3056 } 3057 3058 tx_res = enetc_alloc_tx_resources(priv); 3059 if (IS_ERR(tx_res)) { 3060 err = PTR_ERR(tx_res); 3061 goto out; 3062 } 3063 3064 rx_res = enetc_alloc_rx_resources(priv, extended); 3065 if (IS_ERR(rx_res)) { 3066 err = PTR_ERR(rx_res); 3067 goto out_free_tx_res; 3068 } 3069 3070 enetc_stop(priv->ndev); 3071 enetc_free_rxtx_rings(priv); 3072 3073 /* Interface is down, run optional callback now */ 3074 if (cb) { 3075 err = cb(priv, ctx); 3076 if (err) 3077 goto out_restart; 3078 } 3079 3080 enetc_assign_tx_resources(priv, tx_res); 3081 enetc_assign_rx_resources(priv, rx_res); 3082 enetc_setup_bdrs(priv, extended); 3083 enetc_start(priv->ndev); 3084 3085 return 0; 3086 3087 out_restart: 3088 enetc_setup_bdrs(priv, extended); 3089 enetc_start(priv->ndev); 3090 enetc_free_rx_resources(rx_res, priv->num_rx_rings); 3091 out_free_tx_res: 3092 enetc_free_tx_resources(tx_res, priv->num_tx_rings); 3093 out: 3094 return err; 3095 } 3096 3097 static void enetc_debug_tx_ring_prios(struct enetc_ndev_priv *priv) 3098 { 3099 int i; 3100 3101 for (i = 0; i < priv->num_tx_rings; i++) 3102 netdev_dbg(priv->ndev, "TX ring %d prio %d\n", i, 3103 priv->tx_ring[i]->prio); 3104 } 3105 3106 void enetc_reset_tc_mqprio(struct net_device *ndev) 3107 { 3108 struct enetc_ndev_priv *priv = netdev_priv(ndev); 3109 struct enetc_hw *hw = &priv->si->hw; 3110 struct enetc_bdr *tx_ring; 3111 int num_stack_tx_queues; 3112 int i; 3113 3114 num_stack_tx_queues = enetc_num_stack_tx_queues(priv); 3115 3116 netdev_reset_tc(ndev); 3117 netif_set_real_num_tx_queues(ndev, num_stack_tx_queues); 3118 priv->min_num_stack_tx_queues = num_possible_cpus(); 3119 3120 /* Reset all ring priorities to 0 */ 3121 for (i = 0; i < priv->num_tx_rings; i++) { 3122 tx_ring = priv->tx_ring[i]; 3123 tx_ring->prio = 0; 3124 enetc_set_bdr_prio(hw, tx_ring->index, tx_ring->prio); 3125 } 3126 3127 enetc_debug_tx_ring_prios(priv); 3128 3129 enetc_change_preemptible_tcs(priv, 0); 3130 } 3131 EXPORT_SYMBOL_GPL(enetc_reset_tc_mqprio); 3132 3133 int enetc_setup_tc_mqprio(struct net_device *ndev, void *type_data) 3134 { 3135 struct tc_mqprio_qopt_offload *mqprio = type_data; 3136 struct enetc_ndev_priv *priv = netdev_priv(ndev); 3137 struct tc_mqprio_qopt *qopt = &mqprio->qopt; 3138 struct enetc_hw *hw = &priv->si->hw; 3139 int num_stack_tx_queues = 0; 3140 struct enetc_bdr *tx_ring; 3141 u8 num_tc = qopt->num_tc; 3142 int offset, count; 3143 int err, tc, q; 3144 3145 if (!num_tc) { 3146 enetc_reset_tc_mqprio(ndev); 3147 return 0; 3148 } 3149 3150 err = netdev_set_num_tc(ndev, num_tc); 3151 if (err) 3152 return err; 3153 3154 for (tc = 0; tc < num_tc; tc++) { 3155 offset = qopt->offset[tc]; 3156 count = qopt->count[tc]; 3157 num_stack_tx_queues += count; 3158 3159 err = netdev_set_tc_queue(ndev, tc, count, offset); 3160 if (err) 3161 goto err_reset_tc; 3162 3163 for (q = offset; q < offset + count; q++) { 3164 tx_ring = priv->tx_ring[q]; 3165 /* The prio_tc_map is skb_tx_hash()'s way of selecting 3166 * between TX queues based on skb->priority. As such, 3167 * there's nothing to offload based on it. 3168 * Make the mqprio "traffic class" be the priority of 3169 * this ring group, and leave the Tx IPV to traffic 3170 * class mapping as its default mapping value of 1:1. 3171 */ 3172 tx_ring->prio = tc; 3173 enetc_set_bdr_prio(hw, tx_ring->index, tx_ring->prio); 3174 } 3175 } 3176 3177 err = netif_set_real_num_tx_queues(ndev, num_stack_tx_queues); 3178 if (err) 3179 goto err_reset_tc; 3180 3181 priv->min_num_stack_tx_queues = num_stack_tx_queues; 3182 3183 enetc_debug_tx_ring_prios(priv); 3184 3185 enetc_change_preemptible_tcs(priv, mqprio->preemptible_tcs); 3186 3187 return 0; 3188 3189 err_reset_tc: 3190 enetc_reset_tc_mqprio(ndev); 3191 return err; 3192 } 3193 EXPORT_SYMBOL_GPL(enetc_setup_tc_mqprio); 3194 3195 static int enetc_reconfigure_xdp_cb(struct enetc_ndev_priv *priv, void *ctx) 3196 { 3197 struct bpf_prog *old_prog, *prog = ctx; 3198 int num_stack_tx_queues; 3199 int err, i; 3200 3201 old_prog = xchg(&priv->xdp_prog, prog); 3202 3203 num_stack_tx_queues = enetc_num_stack_tx_queues(priv); 3204 err = netif_set_real_num_tx_queues(priv->ndev, num_stack_tx_queues); 3205 if (err) { 3206 xchg(&priv->xdp_prog, old_prog); 3207 return err; 3208 } 3209 3210 if (old_prog) 3211 bpf_prog_put(old_prog); 3212 3213 for (i = 0; i < priv->num_rx_rings; i++) { 3214 struct enetc_bdr *rx_ring = priv->rx_ring[i]; 3215 3216 rx_ring->xdp.prog = prog; 3217 3218 if (prog) 3219 rx_ring->buffer_offset = XDP_PACKET_HEADROOM; 3220 else 3221 rx_ring->buffer_offset = ENETC_RXB_PAD; 3222 } 3223 3224 return 0; 3225 } 3226 3227 static int enetc_setup_xdp_prog(struct net_device *ndev, struct bpf_prog *prog, 3228 struct netlink_ext_ack *extack) 3229 { 3230 int num_xdp_tx_queues = prog ? num_possible_cpus() : 0; 3231 struct enetc_ndev_priv *priv = netdev_priv(ndev); 3232 bool extended; 3233 3234 if (priv->min_num_stack_tx_queues + num_xdp_tx_queues > 3235 priv->num_tx_rings) { 3236 NL_SET_ERR_MSG_FMT_MOD(extack, 3237 "Reserving %d XDP TXQs leaves under %d for stack (total %d)", 3238 num_xdp_tx_queues, 3239 priv->min_num_stack_tx_queues, 3240 priv->num_tx_rings); 3241 return -EBUSY; 3242 } 3243 3244 extended = !!(priv->active_offloads & ENETC_F_RX_TSTAMP); 3245 3246 /* The buffer layout is changing, so we need to drain the old 3247 * RX buffers and seed new ones. 3248 */ 3249 return enetc_reconfigure(priv, extended, enetc_reconfigure_xdp_cb, prog); 3250 } 3251 3252 int enetc_setup_bpf(struct net_device *ndev, struct netdev_bpf *bpf) 3253 { 3254 switch (bpf->command) { 3255 case XDP_SETUP_PROG: 3256 return enetc_setup_xdp_prog(ndev, bpf->prog, bpf->extack); 3257 default: 3258 return -EINVAL; 3259 } 3260 3261 return 0; 3262 } 3263 EXPORT_SYMBOL_GPL(enetc_setup_bpf); 3264 3265 struct net_device_stats *enetc_get_stats(struct net_device *ndev) 3266 { 3267 struct enetc_ndev_priv *priv = netdev_priv(ndev); 3268 struct net_device_stats *stats = &ndev->stats; 3269 unsigned long packets = 0, bytes = 0; 3270 unsigned long tx_dropped = 0; 3271 int i; 3272 3273 for (i = 0; i < priv->num_rx_rings; i++) { 3274 packets += priv->rx_ring[i]->stats.packets; 3275 bytes += priv->rx_ring[i]->stats.bytes; 3276 } 3277 3278 stats->rx_packets = packets; 3279 stats->rx_bytes = bytes; 3280 bytes = 0; 3281 packets = 0; 3282 3283 for (i = 0; i < priv->num_tx_rings; i++) { 3284 packets += priv->tx_ring[i]->stats.packets; 3285 bytes += priv->tx_ring[i]->stats.bytes; 3286 tx_dropped += priv->tx_ring[i]->stats.win_drop; 3287 } 3288 3289 stats->tx_packets = packets; 3290 stats->tx_bytes = bytes; 3291 stats->tx_dropped = tx_dropped; 3292 3293 return stats; 3294 } 3295 EXPORT_SYMBOL_GPL(enetc_get_stats); 3296 3297 static void enetc_enable_rxvlan(struct net_device *ndev, bool en) 3298 { 3299 struct enetc_ndev_priv *priv = netdev_priv(ndev); 3300 struct enetc_hw *hw = &priv->si->hw; 3301 int i; 3302 3303 for (i = 0; i < priv->num_rx_rings; i++) 3304 enetc_bdr_enable_rxvlan(hw, i, en); 3305 } 3306 3307 static void enetc_enable_txvlan(struct net_device *ndev, bool en) 3308 { 3309 struct enetc_ndev_priv *priv = netdev_priv(ndev); 3310 struct enetc_hw *hw = &priv->si->hw; 3311 int i; 3312 3313 for (i = 0; i < priv->num_tx_rings; i++) 3314 enetc_bdr_enable_txvlan(hw, i, en); 3315 } 3316 3317 void enetc_set_features(struct net_device *ndev, netdev_features_t features) 3318 { 3319 netdev_features_t changed = ndev->features ^ features; 3320 3321 if (changed & NETIF_F_RXHASH) 3322 enetc_set_rss(ndev, !!(features & NETIF_F_RXHASH)); 3323 3324 if (changed & NETIF_F_HW_VLAN_CTAG_RX) 3325 enetc_enable_rxvlan(ndev, 3326 !!(features & NETIF_F_HW_VLAN_CTAG_RX)); 3327 3328 if (changed & NETIF_F_HW_VLAN_CTAG_TX) 3329 enetc_enable_txvlan(ndev, 3330 !!(features & NETIF_F_HW_VLAN_CTAG_TX)); 3331 } 3332 EXPORT_SYMBOL_GPL(enetc_set_features); 3333 3334 int enetc_hwtstamp_set(struct net_device *ndev, 3335 struct kernel_hwtstamp_config *config, 3336 struct netlink_ext_ack *extack) 3337 { 3338 struct enetc_ndev_priv *priv = netdev_priv(ndev); 3339 int err, new_offloads = priv->active_offloads; 3340 3341 if (!enetc_ptp_clock_is_enabled(priv->si)) 3342 return -EOPNOTSUPP; 3343 3344 switch (config->tx_type) { 3345 case HWTSTAMP_TX_OFF: 3346 new_offloads &= ~ENETC_F_TX_TSTAMP_MASK; 3347 break; 3348 case HWTSTAMP_TX_ON: 3349 new_offloads &= ~ENETC_F_TX_TSTAMP_MASK; 3350 new_offloads |= ENETC_F_TX_TSTAMP; 3351 break; 3352 case HWTSTAMP_TX_ONESTEP_SYNC: 3353 if (!enetc_si_is_pf(priv->si)) 3354 return -EOPNOTSUPP; 3355 3356 new_offloads &= ~ENETC_F_TX_TSTAMP_MASK; 3357 new_offloads |= ENETC_F_TX_ONESTEP_SYNC_TSTAMP; 3358 break; 3359 default: 3360 return -ERANGE; 3361 } 3362 3363 switch (config->rx_filter) { 3364 case HWTSTAMP_FILTER_NONE: 3365 new_offloads &= ~ENETC_F_RX_TSTAMP; 3366 break; 3367 default: 3368 new_offloads |= ENETC_F_RX_TSTAMP; 3369 config->rx_filter = HWTSTAMP_FILTER_ALL; 3370 } 3371 3372 if ((new_offloads ^ priv->active_offloads) & ENETC_F_RX_TSTAMP) { 3373 bool extended = !!(new_offloads & ENETC_F_RX_TSTAMP); 3374 3375 err = enetc_reconfigure(priv, extended, NULL, NULL); 3376 if (err) 3377 return err; 3378 } 3379 3380 priv->active_offloads = new_offloads; 3381 3382 return 0; 3383 } 3384 EXPORT_SYMBOL_GPL(enetc_hwtstamp_set); 3385 3386 int enetc_hwtstamp_get(struct net_device *ndev, 3387 struct kernel_hwtstamp_config *config) 3388 { 3389 struct enetc_ndev_priv *priv = netdev_priv(ndev); 3390 3391 if (!enetc_ptp_clock_is_enabled(priv->si)) 3392 return -EOPNOTSUPP; 3393 3394 if (priv->active_offloads & ENETC_F_TX_ONESTEP_SYNC_TSTAMP) 3395 config->tx_type = HWTSTAMP_TX_ONESTEP_SYNC; 3396 else if (priv->active_offloads & ENETC_F_TX_TSTAMP) 3397 config->tx_type = HWTSTAMP_TX_ON; 3398 else 3399 config->tx_type = HWTSTAMP_TX_OFF; 3400 3401 config->rx_filter = (priv->active_offloads & ENETC_F_RX_TSTAMP) ? 3402 HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE; 3403 3404 return 0; 3405 } 3406 EXPORT_SYMBOL_GPL(enetc_hwtstamp_get); 3407 3408 int enetc_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) 3409 { 3410 struct enetc_ndev_priv *priv = netdev_priv(ndev); 3411 3412 if (!priv->phylink) 3413 return -EOPNOTSUPP; 3414 3415 return phylink_mii_ioctl(priv->phylink, rq, cmd); 3416 } 3417 EXPORT_SYMBOL_GPL(enetc_ioctl); 3418 3419 static int enetc_int_vector_init(struct enetc_ndev_priv *priv, int i, 3420 int v_tx_rings) 3421 { 3422 struct enetc_int_vector *v; 3423 struct enetc_bdr *bdr; 3424 int j, err; 3425 3426 v = kzalloc(struct_size(v, tx_ring, v_tx_rings), GFP_KERNEL); 3427 if (!v) 3428 return -ENOMEM; 3429 3430 priv->int_vector[i] = v; 3431 bdr = &v->rx_ring; 3432 bdr->index = i; 3433 bdr->ndev = priv->ndev; 3434 bdr->dev = priv->dev; 3435 bdr->bd_count = priv->rx_bd_count; 3436 bdr->buffer_offset = ENETC_RXB_PAD; 3437 priv->rx_ring[i] = bdr; 3438 3439 err = __xdp_rxq_info_reg(&bdr->xdp.rxq, priv->ndev, i, 0, 3440 ENETC_RXB_DMA_SIZE_XDP); 3441 if (err) 3442 goto free_vector; 3443 3444 err = xdp_rxq_info_reg_mem_model(&bdr->xdp.rxq, MEM_TYPE_PAGE_SHARED, 3445 NULL); 3446 if (err) { 3447 xdp_rxq_info_unreg(&bdr->xdp.rxq); 3448 goto free_vector; 3449 } 3450 3451 /* init defaults for adaptive IC */ 3452 if (priv->ic_mode & ENETC_IC_RX_ADAPTIVE) { 3453 v->rx_ictt = 0x1; 3454 v->rx_dim_en = true; 3455 } 3456 3457 INIT_WORK(&v->rx_dim.work, enetc_rx_dim_work); 3458 netif_napi_add(priv->ndev, &v->napi, enetc_poll); 3459 v->count_tx_rings = v_tx_rings; 3460 3461 for (j = 0; j < v_tx_rings; j++) { 3462 int idx; 3463 3464 /* default tx ring mapping policy */ 3465 idx = priv->bdr_int_num * j + i; 3466 __set_bit(idx, &v->tx_rings_map); 3467 bdr = &v->tx_ring[j]; 3468 bdr->index = idx; 3469 bdr->ndev = priv->ndev; 3470 bdr->dev = priv->dev; 3471 bdr->bd_count = priv->tx_bd_count; 3472 priv->tx_ring[idx] = bdr; 3473 } 3474 3475 return 0; 3476 3477 free_vector: 3478 priv->rx_ring[i] = NULL; 3479 priv->int_vector[i] = NULL; 3480 kfree(v); 3481 3482 return err; 3483 } 3484 3485 static void enetc_int_vector_destroy(struct enetc_ndev_priv *priv, int i) 3486 { 3487 struct enetc_int_vector *v = priv->int_vector[i]; 3488 struct enetc_bdr *rx_ring = &v->rx_ring; 3489 int j, tx_ring_index; 3490 3491 xdp_rxq_info_unreg_mem_model(&rx_ring->xdp.rxq); 3492 xdp_rxq_info_unreg(&rx_ring->xdp.rxq); 3493 netif_napi_del(&v->napi); 3494 cancel_work_sync(&v->rx_dim.work); 3495 3496 for (j = 0; j < v->count_tx_rings; j++) { 3497 tx_ring_index = priv->bdr_int_num * j + i; 3498 priv->tx_ring[tx_ring_index] = NULL; 3499 } 3500 3501 priv->rx_ring[i] = NULL; 3502 priv->int_vector[i] = NULL; 3503 kfree(v); 3504 } 3505 3506 int enetc_alloc_msix(struct enetc_ndev_priv *priv) 3507 { 3508 struct pci_dev *pdev = priv->si->pdev; 3509 int v_tx_rings, v_remainder; 3510 int num_stack_tx_queues; 3511 int first_xdp_tx_ring; 3512 int i, n, err, nvec; 3513 3514 nvec = ENETC_BDR_INT_BASE_IDX + priv->bdr_int_num; 3515 /* allocate MSIX for both messaging and Rx/Tx interrupts */ 3516 n = pci_alloc_irq_vectors(pdev, nvec, nvec, PCI_IRQ_MSIX); 3517 3518 if (n < 0) 3519 return n; 3520 3521 if (n != nvec) 3522 return -EPERM; 3523 3524 /* # of tx rings per int vector */ 3525 v_tx_rings = priv->num_tx_rings / priv->bdr_int_num; 3526 v_remainder = priv->num_tx_rings % priv->bdr_int_num; 3527 3528 for (i = 0; i < priv->bdr_int_num; i++) { 3529 /* Distribute the remaining TX rings to the first v_remainder 3530 * interrupt vectors 3531 */ 3532 int num_tx_rings = i < v_remainder ? v_tx_rings + 1 : v_tx_rings; 3533 3534 err = enetc_int_vector_init(priv, i, num_tx_rings); 3535 if (err) 3536 goto fail; 3537 } 3538 3539 num_stack_tx_queues = enetc_num_stack_tx_queues(priv); 3540 3541 err = netif_set_real_num_tx_queues(priv->ndev, num_stack_tx_queues); 3542 if (err) 3543 goto fail; 3544 3545 err = netif_set_real_num_rx_queues(priv->ndev, priv->num_rx_rings); 3546 if (err) 3547 goto fail; 3548 3549 priv->min_num_stack_tx_queues = num_possible_cpus(); 3550 first_xdp_tx_ring = priv->num_tx_rings - num_possible_cpus(); 3551 priv->xdp_tx_ring = &priv->tx_ring[first_xdp_tx_ring]; 3552 3553 return 0; 3554 3555 fail: 3556 while (i--) 3557 enetc_int_vector_destroy(priv, i); 3558 3559 pci_free_irq_vectors(pdev); 3560 3561 return err; 3562 } 3563 EXPORT_SYMBOL_GPL(enetc_alloc_msix); 3564 3565 void enetc_free_msix(struct enetc_ndev_priv *priv) 3566 { 3567 int i; 3568 3569 for (i = 0; i < priv->bdr_int_num; i++) 3570 enetc_int_vector_destroy(priv, i); 3571 3572 /* disable all MSIX for this device */ 3573 pci_free_irq_vectors(priv->si->pdev); 3574 } 3575 EXPORT_SYMBOL_GPL(enetc_free_msix); 3576 3577 static void enetc_kfree_si(struct enetc_si *si) 3578 { 3579 char *p = (char *)si - si->pad; 3580 3581 kfree(p); 3582 } 3583 3584 static void enetc_detect_errata(struct enetc_si *si) 3585 { 3586 if (si->pdev->revision == ENETC_REV1) 3587 si->errata = ENETC_ERR_VLAN_ISOL | ENETC_ERR_UCMCSWP; 3588 } 3589 3590 int enetc_pci_probe(struct pci_dev *pdev, const char *name, int sizeof_priv) 3591 { 3592 struct enetc_si *si, *p; 3593 struct enetc_hw *hw; 3594 size_t alloc_size; 3595 int err, len; 3596 3597 pcie_flr(pdev); 3598 err = pci_enable_device_mem(pdev); 3599 if (err) 3600 return dev_err_probe(&pdev->dev, err, "device enable failed\n"); 3601 3602 /* set up for high or low dma */ 3603 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 3604 if (err) { 3605 dev_err(&pdev->dev, "DMA configuration failed: 0x%x\n", err); 3606 goto err_dma; 3607 } 3608 3609 err = pci_request_mem_regions(pdev, name); 3610 if (err) { 3611 dev_err(&pdev->dev, "pci_request_regions failed err=%d\n", err); 3612 goto err_pci_mem_reg; 3613 } 3614 3615 pci_set_master(pdev); 3616 3617 alloc_size = sizeof(struct enetc_si); 3618 if (sizeof_priv) { 3619 /* align priv to 32B */ 3620 alloc_size = ALIGN(alloc_size, ENETC_SI_ALIGN); 3621 alloc_size += sizeof_priv; 3622 } 3623 /* force 32B alignment for enetc_si */ 3624 alloc_size += ENETC_SI_ALIGN - 1; 3625 3626 p = kzalloc(alloc_size, GFP_KERNEL); 3627 if (!p) { 3628 err = -ENOMEM; 3629 goto err_alloc_si; 3630 } 3631 3632 si = PTR_ALIGN(p, ENETC_SI_ALIGN); 3633 si->pad = (char *)si - (char *)p; 3634 3635 pci_set_drvdata(pdev, si); 3636 si->pdev = pdev; 3637 hw = &si->hw; 3638 3639 len = pci_resource_len(pdev, ENETC_BAR_REGS); 3640 hw->reg = ioremap(pci_resource_start(pdev, ENETC_BAR_REGS), len); 3641 if (!hw->reg) { 3642 err = -ENXIO; 3643 dev_err(&pdev->dev, "ioremap() failed\n"); 3644 goto err_ioremap; 3645 } 3646 if (len > ENETC_PORT_BASE) 3647 hw->port = hw->reg + ENETC_PORT_BASE; 3648 if (len > ENETC_GLOBAL_BASE) 3649 hw->global = hw->reg + ENETC_GLOBAL_BASE; 3650 3651 enetc_detect_errata(si); 3652 3653 return 0; 3654 3655 err_ioremap: 3656 enetc_kfree_si(si); 3657 err_alloc_si: 3658 pci_release_mem_regions(pdev); 3659 err_pci_mem_reg: 3660 err_dma: 3661 pci_disable_device(pdev); 3662 3663 return err; 3664 } 3665 EXPORT_SYMBOL_GPL(enetc_pci_probe); 3666 3667 void enetc_pci_remove(struct pci_dev *pdev) 3668 { 3669 struct enetc_si *si = pci_get_drvdata(pdev); 3670 struct enetc_hw *hw = &si->hw; 3671 3672 iounmap(hw->reg); 3673 enetc_kfree_si(si); 3674 pci_release_mem_regions(pdev); 3675 pci_disable_device(pdev); 3676 } 3677 EXPORT_SYMBOL_GPL(enetc_pci_remove); 3678 3679 static const struct enetc_drvdata enetc_pf_data = { 3680 .sysclk_freq = ENETC_CLK_400M, 3681 .pmac_offset = ENETC_PMAC_OFFSET, 3682 .max_frags = ENETC_MAX_SKB_FRAGS, 3683 .eth_ops = &enetc_pf_ethtool_ops, 3684 }; 3685 3686 static const struct enetc_drvdata enetc4_pf_data = { 3687 .sysclk_freq = ENETC_CLK_333M, 3688 .tx_csum = true, 3689 .max_frags = ENETC4_MAX_SKB_FRAGS, 3690 .pmac_offset = ENETC4_PMAC_OFFSET, 3691 .eth_ops = &enetc4_pf_ethtool_ops, 3692 }; 3693 3694 static const struct enetc_drvdata enetc_vf_data = { 3695 .sysclk_freq = ENETC_CLK_400M, 3696 .max_frags = ENETC_MAX_SKB_FRAGS, 3697 .eth_ops = &enetc_vf_ethtool_ops, 3698 }; 3699 3700 static const struct enetc_platform_info enetc_info[] = { 3701 { .revision = ENETC_REV_1_0, 3702 .dev_id = ENETC_DEV_ID_PF, 3703 .data = &enetc_pf_data, 3704 }, 3705 { .revision = ENETC_REV_4_1, 3706 .dev_id = NXP_ENETC_PF_DEV_ID, 3707 .data = &enetc4_pf_data, 3708 }, 3709 { .revision = ENETC_REV_1_0, 3710 .dev_id = ENETC_DEV_ID_VF, 3711 .data = &enetc_vf_data, 3712 }, 3713 }; 3714 3715 int enetc_get_driver_data(struct enetc_si *si) 3716 { 3717 u16 dev_id = si->pdev->device; 3718 int i; 3719 3720 for (i = 0; i < ARRAY_SIZE(enetc_info); i++) { 3721 if (si->revision == enetc_info[i].revision && 3722 dev_id == enetc_info[i].dev_id) { 3723 si->drvdata = enetc_info[i].data; 3724 3725 return 0; 3726 } 3727 } 3728 3729 return -ERANGE; 3730 } 3731 EXPORT_SYMBOL_GPL(enetc_get_driver_data); 3732 3733 MODULE_DESCRIPTION("NXP ENETC Ethernet driver"); 3734 MODULE_LICENSE("Dual BSD/GPL"); 3735