xref: /linux/drivers/net/ethernet/freescale/dpaa2/dpsw-cmd.h (revision 65d2dbb300197839eafc4171cfeb57a14c452724)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright 2014-2016 Freescale Semiconductor Inc.
4  * Copyright 2017-2021 NXP
5  *
6  */
7 
8 #ifndef __FSL_DPSW_CMD_H
9 #define __FSL_DPSW_CMD_H
10 
11 #include "dpsw.h"
12 
13 /* DPSW Version */
14 #define DPSW_VER_MAJOR		8
15 #define DPSW_VER_MINOR		9
16 
17 #define DPSW_CMD_BASE_VERSION	1
18 #define DPSW_CMD_VERSION_2	2
19 #define DPSW_CMD_ID_OFFSET	4
20 
21 #define DPSW_CMD_ID(id)	(((id) << DPSW_CMD_ID_OFFSET) | DPSW_CMD_BASE_VERSION)
22 #define DPSW_CMD_V2(id) (((id) << DPSW_CMD_ID_OFFSET) | DPSW_CMD_VERSION_2)
23 
24 /* Command IDs */
25 #define DPSW_CMDID_CLOSE                    DPSW_CMD_ID(0x800)
26 #define DPSW_CMDID_OPEN                     DPSW_CMD_ID(0x802)
27 
28 #define DPSW_CMDID_GET_API_VERSION          DPSW_CMD_ID(0xa02)
29 
30 #define DPSW_CMDID_ENABLE                   DPSW_CMD_ID(0x002)
31 #define DPSW_CMDID_DISABLE                  DPSW_CMD_ID(0x003)
32 #define DPSW_CMDID_GET_ATTR                 DPSW_CMD_V2(0x004)
33 #define DPSW_CMDID_RESET                    DPSW_CMD_ID(0x005)
34 
35 #define DPSW_CMDID_SET_IRQ_ENABLE           DPSW_CMD_ID(0x012)
36 
37 #define DPSW_CMDID_SET_IRQ_MASK             DPSW_CMD_ID(0x014)
38 
39 #define DPSW_CMDID_GET_IRQ_STATUS           DPSW_CMD_ID(0x016)
40 #define DPSW_CMDID_CLEAR_IRQ_STATUS         DPSW_CMD_ID(0x017)
41 
42 #define DPSW_CMDID_IF_SET_TCI               DPSW_CMD_ID(0x030)
43 #define DPSW_CMDID_IF_SET_STP               DPSW_CMD_ID(0x031)
44 
45 #define DPSW_CMDID_IF_GET_COUNTER           DPSW_CMD_V2(0x034)
46 
47 #define DPSW_CMDID_IF_ENABLE                DPSW_CMD_ID(0x03D)
48 #define DPSW_CMDID_IF_DISABLE               DPSW_CMD_ID(0x03E)
49 
50 #define DPSW_CMDID_IF_GET_ATTR              DPSW_CMD_ID(0x042)
51 
52 #define DPSW_CMDID_IF_SET_MAX_FRAME_LENGTH  DPSW_CMD_ID(0x044)
53 
54 #define DPSW_CMDID_IF_GET_LINK_STATE        DPSW_CMD_ID(0x046)
55 
56 #define DPSW_CMDID_IF_GET_TCI               DPSW_CMD_ID(0x04A)
57 
58 #define DPSW_CMDID_IF_SET_LINK_CFG          DPSW_CMD_ID(0x04C)
59 
60 #define DPSW_CMDID_VLAN_ADD                 DPSW_CMD_ID(0x060)
61 #define DPSW_CMDID_VLAN_ADD_IF              DPSW_CMD_V2(0x061)
62 #define DPSW_CMDID_VLAN_ADD_IF_UNTAGGED     DPSW_CMD_ID(0x062)
63 
64 #define DPSW_CMDID_VLAN_REMOVE_IF           DPSW_CMD_ID(0x064)
65 #define DPSW_CMDID_VLAN_REMOVE_IF_UNTAGGED  DPSW_CMD_ID(0x065)
66 #define DPSW_CMDID_VLAN_REMOVE_IF_FLOODING  DPSW_CMD_ID(0x066)
67 #define DPSW_CMDID_VLAN_REMOVE              DPSW_CMD_ID(0x067)
68 
69 #define DPSW_CMDID_FDB_ADD                  DPSW_CMD_ID(0x082)
70 #define DPSW_CMDID_FDB_REMOVE               DPSW_CMD_ID(0x083)
71 #define DPSW_CMDID_FDB_ADD_UNICAST          DPSW_CMD_ID(0x084)
72 #define DPSW_CMDID_FDB_REMOVE_UNICAST       DPSW_CMD_ID(0x085)
73 #define DPSW_CMDID_FDB_ADD_MULTICAST        DPSW_CMD_ID(0x086)
74 #define DPSW_CMDID_FDB_REMOVE_MULTICAST     DPSW_CMD_ID(0x087)
75 #define DPSW_CMDID_FDB_DUMP                 DPSW_CMD_ID(0x08A)
76 
77 #define DPSW_CMDID_IF_GET_PORT_MAC_ADDR     DPSW_CMD_ID(0x0A7)
78 
79 #define DPSW_CMDID_CTRL_IF_GET_ATTR         DPSW_CMD_ID(0x0A0)
80 #define DPSW_CMDID_CTRL_IF_SET_POOLS        DPSW_CMD_ID(0x0A1)
81 #define DPSW_CMDID_CTRL_IF_ENABLE           DPSW_CMD_ID(0x0A2)
82 #define DPSW_CMDID_CTRL_IF_DISABLE          DPSW_CMD_ID(0x0A3)
83 #define DPSW_CMDID_CTRL_IF_SET_QUEUE        DPSW_CMD_ID(0x0A6)
84 
85 #define DPSW_CMDID_SET_EGRESS_FLOOD         DPSW_CMD_ID(0x0AC)
86 #define DPSW_CMDID_IF_SET_LEARNING_MODE     DPSW_CMD_ID(0x0AD)
87 
88 /* Macros for accessing command fields smaller than 1byte */
89 #define DPSW_MASK(field)        \
90 	GENMASK(DPSW_##field##_SHIFT + DPSW_##field##_SIZE - 1, \
91 		DPSW_##field##_SHIFT)
92 #define dpsw_set_field(var, field, val) \
93 	((var) |= (((val) << DPSW_##field##_SHIFT) & DPSW_MASK(field)))
94 #define dpsw_get_field(var, field)      \
95 	(((var) & DPSW_MASK(field)) >> DPSW_##field##_SHIFT)
96 #define dpsw_get_bit(var, bit) \
97 	(((var)  >> (bit)) & GENMASK(0, 0))
98 
99 #pragma pack(push, 1)
100 struct dpsw_cmd_open {
101 	__le32 dpsw_id;
102 };
103 
104 #define DPSW_COMPONENT_TYPE_SHIFT	0
105 #define DPSW_COMPONENT_TYPE_SIZE	4
106 
107 struct dpsw_cmd_create {
108 	/* cmd word 0 */
109 	__le16 num_ifs;
110 	u8 max_fdbs;
111 	u8 max_meters_per_if;
112 	/* from LSB: only the first 4 bits */
113 	u8 component_type;
114 	u8 pad[3];
115 	/* cmd word 1 */
116 	__le16 max_vlans;
117 	__le16 max_fdb_entries;
118 	__le16 fdb_aging_time;
119 	__le16 max_fdb_mc_groups;
120 	/* cmd word 2 */
121 	__le64 options;
122 };
123 
124 struct dpsw_cmd_destroy {
125 	__le32 dpsw_id;
126 };
127 
128 #define DPSW_ENABLE_SHIFT 0
129 #define DPSW_ENABLE_SIZE  1
130 
131 struct dpsw_rsp_is_enabled {
132 	/* from LSB: enable:1 */
133 	u8 enabled;
134 };
135 
136 struct dpsw_cmd_set_irq_enable {
137 	u8 enable_state;
138 	u8 pad[3];
139 	u8 irq_index;
140 };
141 
142 struct dpsw_cmd_get_irq_enable {
143 	__le32 pad;
144 	u8 irq_index;
145 };
146 
147 struct dpsw_rsp_get_irq_enable {
148 	u8 enable_state;
149 };
150 
151 struct dpsw_cmd_set_irq_mask {
152 	__le32 mask;
153 	u8 irq_index;
154 };
155 
156 struct dpsw_cmd_get_irq_mask {
157 	__le32 pad;
158 	u8 irq_index;
159 };
160 
161 struct dpsw_rsp_get_irq_mask {
162 	__le32 mask;
163 };
164 
165 struct dpsw_cmd_get_irq_status {
166 	__le32 status;
167 	u8 irq_index;
168 };
169 
170 struct dpsw_rsp_get_irq_status {
171 	__le32 status;
172 };
173 
174 struct dpsw_cmd_clear_irq_status {
175 	__le32 status;
176 	u8 irq_index;
177 };
178 
179 #define DPSW_COMPONENT_TYPE_SHIFT	0
180 #define DPSW_COMPONENT_TYPE_SIZE	4
181 
182 #define DPSW_FLOODING_CFG_SHIFT		0
183 #define DPSW_FLOODING_CFG_SIZE		4
184 
185 #define DPSW_BROADCAST_CFG_SHIFT	4
186 #define DPSW_BROADCAST_CFG_SIZE		4
187 
188 struct dpsw_rsp_get_attr {
189 	/* cmd word 0 */
190 	__le16 num_ifs;
191 	u8 max_fdbs;
192 	u8 num_fdbs;
193 	__le16 max_vlans;
194 	__le16 num_vlans;
195 	/* cmd word 1 */
196 	__le16 max_fdb_entries;
197 	__le16 fdb_aging_time;
198 	__le32 dpsw_id;
199 	/* cmd word 2 */
200 	__le16 mem_size;
201 	__le16 max_fdb_mc_groups;
202 	u8 max_meters_per_if;
203 	/* from LSB only the first 4 bits */
204 	u8 component_type;
205 	/* [0:3] - flooding configuration
206 	 * [4:7] - broadcast configuration
207 	 */
208 	u8 repl_cfg;
209 	u8 pad;
210 	/* cmd word 3 */
211 	__le64 options;
212 };
213 
214 #define DPSW_VLAN_ID_SHIFT	0
215 #define DPSW_VLAN_ID_SIZE	12
216 #define DPSW_DEI_SHIFT		12
217 #define DPSW_DEI_SIZE		1
218 #define DPSW_PCP_SHIFT		13
219 #define DPSW_PCP_SIZE		3
220 
221 struct dpsw_cmd_if_set_tci {
222 	__le16 if_id;
223 	/* from LSB: VLAN_ID:12 DEI:1 PCP:3 */
224 	__le16 conf;
225 };
226 
227 struct dpsw_cmd_if_get_tci {
228 	__le16 if_id;
229 };
230 
231 struct dpsw_rsp_if_get_tci {
232 	__le16 pad;
233 	__le16 vlan_id;
234 	u8 dei;
235 	u8 pcp;
236 };
237 
238 #define DPSW_STATE_SHIFT	0
239 #define DPSW_STATE_SIZE		4
240 
241 struct dpsw_cmd_if_set_stp {
242 	__le16 if_id;
243 	__le16 vlan_id;
244 	/* only the first LSB 4 bits */
245 	u8 state;
246 };
247 
248 #define DPSW_COUNTER_TYPE_SHIFT		0
249 #define DPSW_COUNTER_TYPE_SIZE		5
250 
251 struct dpsw_cmd_if_get_counter {
252 	__le16 if_id;
253 	/* from LSB: type:5 */
254 	u8 type;
255 };
256 
257 struct dpsw_rsp_if_get_counter {
258 	__le64 pad;
259 	__le64 counter;
260 };
261 
262 struct dpsw_cmd_if {
263 	__le16 if_id;
264 };
265 
266 #define DPSW_ADMIT_UNTAGGED_SHIFT	0
267 #define DPSW_ADMIT_UNTAGGED_SIZE	4
268 #define DPSW_ENABLED_SHIFT		5
269 #define DPSW_ENABLED_SIZE		1
270 #define DPSW_ACCEPT_ALL_VLAN_SHIFT	6
271 #define DPSW_ACCEPT_ALL_VLAN_SIZE	1
272 
273 struct dpsw_rsp_if_get_attr {
274 	/* cmd word 0 */
275 	/* from LSB: admit_untagged:4 enabled:1 accept_all_vlan:1 */
276 	u8 conf;
277 	u8 pad1;
278 	u8 num_tcs;
279 	u8 pad2;
280 	__le16 qdid;
281 	/* cmd word 1 */
282 	__le32 options;
283 	__le32 pad3;
284 	/* cmd word 2 */
285 	__le32 rate;
286 };
287 
288 struct dpsw_cmd_if_set_max_frame_length {
289 	__le16 if_id;
290 	__le16 frame_length;
291 };
292 
293 struct dpsw_cmd_if_set_link_cfg {
294 	/* cmd word 0 */
295 	__le16 if_id;
296 	u8 pad[6];
297 	/* cmd word 1 */
298 	__le32 rate;
299 	__le32 pad1;
300 	/* cmd word 2 */
301 	__le64 options;
302 };
303 
304 struct dpsw_cmd_if_get_link_state {
305 	__le16 if_id;
306 };
307 
308 #define DPSW_UP_SHIFT	0
309 #define DPSW_UP_SIZE	1
310 
311 struct dpsw_rsp_if_get_link_state {
312 	/* cmd word 0 */
313 	__le32 pad0;
314 	u8 up;
315 	u8 pad1[3];
316 	/* cmd word 1 */
317 	__le32 rate;
318 	__le32 pad2;
319 	/* cmd word 2 */
320 	__le64 options;
321 };
322 
323 struct dpsw_vlan_add {
324 	__le16 fdb_id;
325 	__le16 vlan_id;
326 };
327 
328 struct dpsw_cmd_vlan_add_if {
329 	/* cmd word 0 */
330 	__le16 options;
331 	__le16 vlan_id;
332 	__le16 fdb_id;
333 	__le16 pad0;
334 	/* cmd word 1-4 */
335 	__le64 if_id;
336 };
337 
338 struct dpsw_cmd_vlan_manage_if {
339 	/* cmd word 0 */
340 	__le16 pad0;
341 	__le16 vlan_id;
342 	__le32 pad1;
343 	/* cmd word 1-4 */
344 	__le64 if_id;
345 };
346 
347 struct dpsw_cmd_vlan_remove {
348 	__le16 pad;
349 	__le16 vlan_id;
350 };
351 
352 struct dpsw_cmd_fdb_add {
353 	__le32 pad;
354 	__le16 fdb_ageing_time;
355 	__le16 num_fdb_entries;
356 };
357 
358 struct dpsw_rsp_fdb_add {
359 	__le16 fdb_id;
360 };
361 
362 struct dpsw_cmd_fdb_remove {
363 	__le16 fdb_id;
364 };
365 
366 #define DPSW_ENTRY_TYPE_SHIFT	0
367 #define DPSW_ENTRY_TYPE_SIZE	4
368 
369 struct dpsw_cmd_fdb_unicast_op {
370 	/* cmd word 0 */
371 	__le16 fdb_id;
372 	u8 mac_addr[6];
373 	/* cmd word 1 */
374 	__le16 if_egress;
375 	/* only the first 4 bits from LSB */
376 	u8 type;
377 };
378 
379 struct dpsw_cmd_fdb_multicast_op {
380 	/* cmd word 0 */
381 	__le16 fdb_id;
382 	__le16 num_ifs;
383 	/* only the first 4 bits from LSB */
384 	u8 type;
385 	u8 pad[3];
386 	/* cmd word 1 */
387 	u8 mac_addr[6];
388 	__le16 pad2;
389 	/* cmd word 2-5 */
390 	__le64 if_id;
391 };
392 
393 struct dpsw_cmd_fdb_dump {
394 	__le16 fdb_id;
395 	__le16 pad0;
396 	__le32 pad1;
397 	__le64 iova_addr;
398 	__le32 iova_size;
399 };
400 
401 struct dpsw_rsp_fdb_dump {
402 	__le16 num_entries;
403 };
404 
405 struct dpsw_rsp_ctrl_if_get_attr {
406 	__le64 pad;
407 	__le32 rx_fqid;
408 	__le32 rx_err_fqid;
409 	__le32 tx_err_conf_fqid;
410 };
411 
412 #define DPSW_BACKUP_POOL(val, order)	(((val) & 0x1) << (order))
413 struct dpsw_cmd_ctrl_if_set_pools {
414 	u8 num_dpbp;
415 	u8 backup_pool_mask;
416 	__le16 pad;
417 	__le32 dpbp_id[DPSW_MAX_DPBP];
418 	__le16 buffer_size[DPSW_MAX_DPBP];
419 };
420 
421 #define DPSW_DEST_TYPE_SHIFT	0
422 #define DPSW_DEST_TYPE_SIZE	4
423 
424 struct dpsw_cmd_ctrl_if_set_queue {
425 	__le32 dest_id;
426 	u8 dest_priority;
427 	u8 pad;
428 	/* from LSB: dest_type:4 */
429 	u8 dest_type;
430 	u8 qtype;
431 	__le64 user_ctx;
432 	__le32 options;
433 };
434 
435 struct dpsw_rsp_get_api_version {
436 	__le16 version_major;
437 	__le16 version_minor;
438 };
439 
440 struct dpsw_rsp_if_get_mac_addr {
441 	__le16 pad;
442 	u8 mac_addr[6];
443 };
444 
445 struct dpsw_cmd_set_egress_flood {
446 	__le16 fdb_id;
447 	u8 flood_type;
448 	u8 pad[5];
449 	__le64 if_id;
450 };
451 
452 #define DPSW_LEARNING_MODE_SHIFT	0
453 #define DPSW_LEARNING_MODE_SIZE		4
454 
455 struct dpsw_cmd_if_set_learning_mode {
456 	__le16 if_id;
457 	/* only the first 4 bits from LSB */
458 	u8 mode;
459 };
460 #pragma pack(pop)
461 #endif /* __FSL_DPSW_CMD_H */
462