1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright 2013-2016 Freescale Semiconductor Inc. 4 * Copyright 2016-2018 NXP 5 */ 6 7 #ifndef __FSL_DPRTC_H 8 #define __FSL_DPRTC_H 9 10 /* Data Path Real Time Counter API 11 * Contains initialization APIs and runtime control APIs for RTC 12 */ 13 14 struct fsl_mc_io; 15 16 #define DPRTC_MAX_IRQ_NUM 1 17 #define DPRTC_IRQ_INDEX 0 18 19 #define DPRTC_EVENT_PPS 0x08000000 20 #define DPRTC_EVENT_ETS1 0x00800000 21 #define DPRTC_EVENT_ETS2 0x00400000 22 23 int dprtc_open(struct fsl_mc_io *mc_io, 24 u32 cmd_flags, 25 int dprtc_id, 26 u16 *token); 27 28 int dprtc_close(struct fsl_mc_io *mc_io, 29 u32 cmd_flags, 30 u16 token); 31 32 int dprtc_set_irq_enable(struct fsl_mc_io *mc_io, 33 u32 cmd_flags, 34 u16 token, 35 u8 irq_index, 36 u8 en); 37 38 int dprtc_get_irq_enable(struct fsl_mc_io *mc_io, 39 u32 cmd_flags, 40 u16 token, 41 u8 irq_index, 42 u8 *en); 43 44 int dprtc_set_irq_mask(struct fsl_mc_io *mc_io, 45 u32 cmd_flags, 46 u16 token, 47 u8 irq_index, 48 u32 mask); 49 50 int dprtc_get_irq_mask(struct fsl_mc_io *mc_io, 51 u32 cmd_flags, 52 u16 token, 53 u8 irq_index, 54 u32 *mask); 55 56 int dprtc_get_irq_status(struct fsl_mc_io *mc_io, 57 u32 cmd_flags, 58 u16 token, 59 u8 irq_index, 60 u32 *status); 61 62 int dprtc_clear_irq_status(struct fsl_mc_io *mc_io, 63 u32 cmd_flags, 64 u16 token, 65 u8 irq_index, 66 u32 status); 67 68 #endif /* __FSL_DPRTC_H */ 69