1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ 2 /* Copyright 2014-2016 Freescale Semiconductor Inc. 3 * Copyright 2016 NXP 4 */ 5 6 #ifndef __DPAA2_ETH_H 7 #define __DPAA2_ETH_H 8 9 #include <linux/netdevice.h> 10 #include <linux/if_vlan.h> 11 #include <linux/fsl/mc.h> 12 13 #include <soc/fsl/dpaa2-io.h> 14 #include <soc/fsl/dpaa2-fd.h> 15 #include "dpni.h" 16 #include "dpni-cmd.h" 17 18 #include "dpaa2-eth-trace.h" 19 20 #define DPAA2_WRIOP_VERSION(x, y, z) ((x) << 10 | (y) << 5 | (z) << 0) 21 22 #define DPAA2_ETH_STORE_SIZE 16 23 24 /* Maximum number of scatter-gather entries in an ingress frame, 25 * considering the maximum receive frame size is 64K 26 */ 27 #define DPAA2_ETH_MAX_SG_ENTRIES ((64 * 1024) / DPAA2_ETH_RX_BUF_SIZE) 28 29 /* Maximum acceptable MTU value. It is in direct relation with the hardware 30 * enforced Max Frame Length (currently 10k). 31 */ 32 #define DPAA2_ETH_MFL (10 * 1024) 33 #define DPAA2_ETH_MAX_MTU (DPAA2_ETH_MFL - VLAN_ETH_HLEN) 34 /* Convert L3 MTU to L2 MFL */ 35 #define DPAA2_ETH_L2_MAX_FRM(mtu) ((mtu) + VLAN_ETH_HLEN) 36 37 /* Set the taildrop threshold (in bytes) to allow the enqueue of several jumbo 38 * frames in the Rx queues (length of the current frame is not 39 * taken into account when making the taildrop decision) 40 */ 41 #define DPAA2_ETH_TAILDROP_THRESH (64 * 1024) 42 43 /* Maximum number of Tx confirmation frames to be processed 44 * in a single NAPI call 45 */ 46 #define DPAA2_ETH_TXCONF_PER_NAPI 256 47 48 /* Buffer quota per queue. Must be large enough such that for minimum sized 49 * frames taildrop kicks in before the bpool gets depleted, so we compute 50 * how many 64B frames fit inside the taildrop threshold and add a margin 51 * to accommodate the buffer refill delay. 52 */ 53 #define DPAA2_ETH_MAX_FRAMES_PER_QUEUE (DPAA2_ETH_TAILDROP_THRESH / 64) 54 #define DPAA2_ETH_NUM_BUFS (DPAA2_ETH_MAX_FRAMES_PER_QUEUE + 256) 55 #define DPAA2_ETH_REFILL_THRESH DPAA2_ETH_MAX_FRAMES_PER_QUEUE 56 57 /* Maximum number of buffers that can be acquired/released through a single 58 * QBMan command 59 */ 60 #define DPAA2_ETH_BUFS_PER_CMD 7 61 62 /* Hardware requires alignment for ingress/egress buffer addresses */ 63 #define DPAA2_ETH_TX_BUF_ALIGN 64 64 65 #define DPAA2_ETH_RX_BUF_SIZE 2048 66 #define DPAA2_ETH_SKB_SIZE \ 67 (DPAA2_ETH_RX_BUF_SIZE + SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 68 69 /* Hardware annotation area in RX/TX buffers */ 70 #define DPAA2_ETH_RX_HWA_SIZE 64 71 #define DPAA2_ETH_TX_HWA_SIZE 128 72 73 /* PTP nominal frequency 1GHz */ 74 #define DPAA2_PTP_CLK_PERIOD_NS 1 75 76 /* Due to a limitation in WRIOP 1.0.0, the RX buffer data must be aligned 77 * to 256B. For newer revisions, the requirement is only for 64B alignment 78 */ 79 #define DPAA2_ETH_RX_BUF_ALIGN_REV1 256 80 #define DPAA2_ETH_RX_BUF_ALIGN 64 81 82 /* We are accommodating a skb backpointer and some S/G info 83 * in the frame's software annotation. The hardware 84 * options are either 0 or 64, so we choose the latter. 85 */ 86 #define DPAA2_ETH_SWA_SIZE 64 87 88 /* Must keep this struct smaller than DPAA2_ETH_SWA_SIZE */ 89 struct dpaa2_eth_swa { 90 struct sk_buff *skb; 91 struct scatterlist *scl; 92 int num_sg; 93 int sgt_size; 94 }; 95 96 /* Annotation valid bits in FD FRC */ 97 #define DPAA2_FD_FRC_FASV 0x8000 98 #define DPAA2_FD_FRC_FAEADV 0x4000 99 #define DPAA2_FD_FRC_FAPRV 0x2000 100 #define DPAA2_FD_FRC_FAIADV 0x1000 101 #define DPAA2_FD_FRC_FASWOV 0x0800 102 #define DPAA2_FD_FRC_FAICFDV 0x0400 103 104 /* Error bits in FD CTRL */ 105 #define DPAA2_FD_RX_ERR_MASK (FD_CTRL_SBE | FD_CTRL_FAERR) 106 #define DPAA2_FD_TX_ERR_MASK (FD_CTRL_UFD | \ 107 FD_CTRL_SBE | \ 108 FD_CTRL_FSE | \ 109 FD_CTRL_FAERR) 110 111 /* Annotation bits in FD CTRL */ 112 #define DPAA2_FD_CTRL_ASAL 0x00020000 /* ASAL = 128B */ 113 114 /* Frame annotation status */ 115 struct dpaa2_fas { 116 u8 reserved; 117 u8 ppid; 118 __le16 ifpid; 119 __le32 status; 120 }; 121 122 /* Frame annotation status word is located in the first 8 bytes 123 * of the buffer's hardware annoatation area 124 */ 125 #define DPAA2_FAS_OFFSET 0 126 #define DPAA2_FAS_SIZE (sizeof(struct dpaa2_fas)) 127 128 /* Timestamp is located in the next 8 bytes of the buffer's 129 * hardware annotation area 130 */ 131 #define DPAA2_TS_OFFSET 0x8 132 133 /* Frame annotation egress action descriptor */ 134 #define DPAA2_FAEAD_OFFSET 0x58 135 136 struct dpaa2_faead { 137 __le32 conf_fqid; 138 __le32 ctrl; 139 }; 140 141 #define DPAA2_FAEAD_A2V 0x20000000 142 #define DPAA2_FAEAD_A4V 0x08000000 143 #define DPAA2_FAEAD_UPDV 0x00001000 144 #define DPAA2_FAEAD_EBDDV 0x00002000 145 #define DPAA2_FAEAD_UPD 0x00000010 146 147 /* Accessors for the hardware annotation fields that we use */ 148 static inline void *dpaa2_get_hwa(void *buf_addr, bool swa) 149 { 150 return buf_addr + (swa ? DPAA2_ETH_SWA_SIZE : 0); 151 } 152 153 static inline struct dpaa2_fas *dpaa2_get_fas(void *buf_addr, bool swa) 154 { 155 return dpaa2_get_hwa(buf_addr, swa) + DPAA2_FAS_OFFSET; 156 } 157 158 static inline __le64 *dpaa2_get_ts(void *buf_addr, bool swa) 159 { 160 return dpaa2_get_hwa(buf_addr, swa) + DPAA2_TS_OFFSET; 161 } 162 163 static inline struct dpaa2_faead *dpaa2_get_faead(void *buf_addr, bool swa) 164 { 165 return dpaa2_get_hwa(buf_addr, swa) + DPAA2_FAEAD_OFFSET; 166 } 167 168 /* Error and status bits in the frame annotation status word */ 169 /* Debug frame, otherwise supposed to be discarded */ 170 #define DPAA2_FAS_DISC 0x80000000 171 /* MACSEC frame */ 172 #define DPAA2_FAS_MS 0x40000000 173 #define DPAA2_FAS_PTP 0x08000000 174 /* Ethernet multicast frame */ 175 #define DPAA2_FAS_MC 0x04000000 176 /* Ethernet broadcast frame */ 177 #define DPAA2_FAS_BC 0x02000000 178 #define DPAA2_FAS_KSE 0x00040000 179 #define DPAA2_FAS_EOFHE 0x00020000 180 #define DPAA2_FAS_MNLE 0x00010000 181 #define DPAA2_FAS_TIDE 0x00008000 182 #define DPAA2_FAS_PIEE 0x00004000 183 /* Frame length error */ 184 #define DPAA2_FAS_FLE 0x00002000 185 /* Frame physical error */ 186 #define DPAA2_FAS_FPE 0x00001000 187 #define DPAA2_FAS_PTE 0x00000080 188 #define DPAA2_FAS_ISP 0x00000040 189 #define DPAA2_FAS_PHE 0x00000020 190 #define DPAA2_FAS_BLE 0x00000010 191 /* L3 csum validation performed */ 192 #define DPAA2_FAS_L3CV 0x00000008 193 /* L3 csum error */ 194 #define DPAA2_FAS_L3CE 0x00000004 195 /* L4 csum validation performed */ 196 #define DPAA2_FAS_L4CV 0x00000002 197 /* L4 csum error */ 198 #define DPAA2_FAS_L4CE 0x00000001 199 /* Possible errors on the ingress path */ 200 #define DPAA2_FAS_RX_ERR_MASK (DPAA2_FAS_KSE | \ 201 DPAA2_FAS_EOFHE | \ 202 DPAA2_FAS_MNLE | \ 203 DPAA2_FAS_TIDE | \ 204 DPAA2_FAS_PIEE | \ 205 DPAA2_FAS_FLE | \ 206 DPAA2_FAS_FPE | \ 207 DPAA2_FAS_PTE | \ 208 DPAA2_FAS_ISP | \ 209 DPAA2_FAS_PHE | \ 210 DPAA2_FAS_BLE | \ 211 DPAA2_FAS_L3CE | \ 212 DPAA2_FAS_L4CE) 213 214 /* Time in milliseconds between link state updates */ 215 #define DPAA2_ETH_LINK_STATE_REFRESH 1000 216 217 /* Number of times to retry a frame enqueue before giving up. 218 * Value determined empirically, in order to minimize the number 219 * of frames dropped on Tx 220 */ 221 #define DPAA2_ETH_ENQUEUE_RETRIES 10 222 223 /* Driver statistics, other than those in struct rtnl_link_stats64. 224 * These are usually collected per-CPU and aggregated by ethtool. 225 */ 226 struct dpaa2_eth_drv_stats { 227 __u64 tx_conf_frames; 228 __u64 tx_conf_bytes; 229 __u64 tx_sg_frames; 230 __u64 tx_sg_bytes; 231 __u64 tx_reallocs; 232 __u64 rx_sg_frames; 233 __u64 rx_sg_bytes; 234 /* Enqueues retried due to portal busy */ 235 __u64 tx_portal_busy; 236 }; 237 238 /* Per-FQ statistics */ 239 struct dpaa2_eth_fq_stats { 240 /* Number of frames received on this queue */ 241 __u64 frames; 242 }; 243 244 /* Per-channel statistics */ 245 struct dpaa2_eth_ch_stats { 246 /* Volatile dequeues retried due to portal busy */ 247 __u64 dequeue_portal_busy; 248 /* Pull errors */ 249 __u64 pull_err; 250 /* Number of CDANs; useful to estimate avg NAPI len */ 251 __u64 cdan; 252 /* XDP counters */ 253 __u64 xdp_drop; 254 __u64 xdp_tx; 255 __u64 xdp_tx_err; 256 }; 257 258 /* Maximum number of queues associated with a DPNI */ 259 #define DPAA2_ETH_MAX_RX_QUEUES 16 260 #define DPAA2_ETH_MAX_TX_QUEUES 16 261 #define DPAA2_ETH_MAX_QUEUES (DPAA2_ETH_MAX_RX_QUEUES + \ 262 DPAA2_ETH_MAX_TX_QUEUES) 263 264 #define DPAA2_ETH_MAX_DPCONS 16 265 266 enum dpaa2_eth_fq_type { 267 DPAA2_RX_FQ = 0, 268 DPAA2_TX_CONF_FQ, 269 }; 270 271 struct dpaa2_eth_priv; 272 273 struct dpaa2_eth_fq { 274 u32 fqid; 275 u32 tx_qdbin; 276 u16 flowid; 277 int target_cpu; 278 u32 dq_frames; 279 u32 dq_bytes; 280 struct dpaa2_eth_channel *channel; 281 enum dpaa2_eth_fq_type type; 282 283 void (*consume)(struct dpaa2_eth_priv *priv, 284 struct dpaa2_eth_channel *ch, 285 const struct dpaa2_fd *fd, 286 struct dpaa2_eth_fq *fq); 287 struct dpaa2_eth_fq_stats stats; 288 }; 289 290 struct dpaa2_eth_ch_xdp { 291 struct bpf_prog *prog; 292 u64 drop_bufs[DPAA2_ETH_BUFS_PER_CMD]; 293 int drop_cnt; 294 }; 295 296 struct dpaa2_eth_channel { 297 struct dpaa2_io_notification_ctx nctx; 298 struct fsl_mc_device *dpcon; 299 int dpcon_id; 300 int ch_id; 301 struct napi_struct napi; 302 struct dpaa2_io *dpio; 303 struct dpaa2_io_store *store; 304 struct dpaa2_eth_priv *priv; 305 int buf_count; 306 struct dpaa2_eth_ch_stats stats; 307 struct dpaa2_eth_ch_xdp xdp; 308 }; 309 310 struct dpaa2_eth_dist_fields { 311 u64 rxnfc_field; 312 enum net_prot cls_prot; 313 int cls_field; 314 int size; 315 }; 316 317 struct dpaa2_eth_cls_rule { 318 struct ethtool_rx_flow_spec fs; 319 u8 in_use; 320 }; 321 322 /* Driver private data */ 323 struct dpaa2_eth_priv { 324 struct net_device *net_dev; 325 326 u8 num_fqs; 327 struct dpaa2_eth_fq fq[DPAA2_ETH_MAX_QUEUES]; 328 329 u8 num_channels; 330 struct dpaa2_eth_channel *channel[DPAA2_ETH_MAX_DPCONS]; 331 332 struct dpni_attr dpni_attrs; 333 u16 dpni_ver_major; 334 u16 dpni_ver_minor; 335 u16 tx_data_offset; 336 337 struct fsl_mc_device *dpbp_dev; 338 u16 bpid; 339 struct iommu_domain *iommu_domain; 340 341 bool tx_tstamp; /* Tx timestamping enabled */ 342 bool rx_tstamp; /* Rx timestamping enabled */ 343 344 u16 tx_qdid; 345 u16 rx_buf_align; 346 struct fsl_mc_io *mc_io; 347 /* Cores which have an affine DPIO/DPCON. 348 * This is the cpu set on which Rx and Tx conf frames are processed 349 */ 350 struct cpumask dpio_cpumask; 351 352 /* Standard statistics */ 353 struct rtnl_link_stats64 __percpu *percpu_stats; 354 /* Extra stats, in addition to the ones known by the kernel */ 355 struct dpaa2_eth_drv_stats __percpu *percpu_extras; 356 357 u16 mc_token; 358 359 struct dpni_link_state link_state; 360 bool do_link_poll; 361 struct task_struct *poll_thread; 362 363 /* enabled ethtool hashing bits */ 364 u64 rx_hash_fields; 365 struct dpaa2_eth_cls_rule *cls_rules; 366 u8 rx_cls_enabled; 367 struct bpf_prog *xdp_prog; 368 }; 369 370 #define DPAA2_RXH_SUPPORTED (RXH_L2DA | RXH_VLAN | RXH_L3_PROTO \ 371 | RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 \ 372 | RXH_L4_B_2_3) 373 374 /* default Rx hash options, set during probing */ 375 #define DPAA2_RXH_DEFAULT (RXH_L3_PROTO | RXH_IP_SRC | RXH_IP_DST | \ 376 RXH_L4_B_0_1 | RXH_L4_B_2_3) 377 378 #define dpaa2_eth_hash_enabled(priv) \ 379 ((priv)->dpni_attrs.num_queues > 1) 380 381 /* Required by struct dpni_rx_tc_dist_cfg::key_cfg_iova */ 382 #define DPAA2_CLASSIFIER_DMA_SIZE 256 383 384 extern const struct ethtool_ops dpaa2_ethtool_ops; 385 extern int dpaa2_phc_index; 386 387 static inline int dpaa2_eth_cmp_dpni_ver(struct dpaa2_eth_priv *priv, 388 u16 ver_major, u16 ver_minor) 389 { 390 if (priv->dpni_ver_major == ver_major) 391 return priv->dpni_ver_minor - ver_minor; 392 return priv->dpni_ver_major - ver_major; 393 } 394 395 /* Minimum firmware version that supports a more flexible API 396 * for configuring the Rx flow hash key 397 */ 398 #define DPNI_RX_DIST_KEY_VER_MAJOR 7 399 #define DPNI_RX_DIST_KEY_VER_MINOR 5 400 401 #define dpaa2_eth_has_legacy_dist(priv) \ 402 (dpaa2_eth_cmp_dpni_ver((priv), DPNI_RX_DIST_KEY_VER_MAJOR, \ 403 DPNI_RX_DIST_KEY_VER_MINOR) < 0) 404 405 #define dpaa2_eth_fs_count(priv) \ 406 ((priv)->dpni_attrs.fs_entries) 407 408 enum dpaa2_eth_rx_dist { 409 DPAA2_ETH_RX_DIST_HASH, 410 DPAA2_ETH_RX_DIST_CLS 411 }; 412 413 /* Hardware only sees DPAA2_ETH_RX_BUF_SIZE, but the skb built around 414 * the buffer also needs space for its shared info struct, and we need 415 * to allocate enough to accommodate hardware alignment restrictions 416 */ 417 static inline unsigned int dpaa2_eth_buf_raw_size(struct dpaa2_eth_priv *priv) 418 { 419 return DPAA2_ETH_SKB_SIZE + priv->rx_buf_align; 420 } 421 422 static inline 423 unsigned int dpaa2_eth_needed_headroom(struct dpaa2_eth_priv *priv, 424 struct sk_buff *skb) 425 { 426 unsigned int headroom = DPAA2_ETH_SWA_SIZE; 427 428 /* For non-linear skbs we have no headroom requirement, as we build a 429 * SG frame with a newly allocated SGT buffer 430 */ 431 if (skb_is_nonlinear(skb)) 432 return 0; 433 434 /* If we have Tx timestamping, need 128B hardware annotation */ 435 if (priv->tx_tstamp && skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) 436 headroom += DPAA2_ETH_TX_HWA_SIZE; 437 438 return headroom; 439 } 440 441 /* Extra headroom space requested to hardware, in order to make sure there's 442 * no realloc'ing in forwarding scenarios 443 */ 444 static inline unsigned int dpaa2_eth_rx_head_room(struct dpaa2_eth_priv *priv) 445 { 446 return priv->tx_data_offset + DPAA2_ETH_TX_BUF_ALIGN - 447 DPAA2_ETH_RX_HWA_SIZE; 448 } 449 450 /* We have exactly one {Rx, Tx conf} queue per channel */ 451 static int dpaa2_eth_queue_count(struct dpaa2_eth_priv *priv) 452 { 453 return priv->num_channels; 454 } 455 456 int dpaa2_eth_set_hash(struct net_device *net_dev, u64 flags); 457 int dpaa2_eth_cls_key_size(void); 458 int dpaa2_eth_cls_fld_off(int prot, int field); 459 460 #endif /* __DPAA2_H */ 461