1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ 2 /* Copyright 2014-2016 Freescale Semiconductor Inc. 3 * Copyright 2016 NXP 4 */ 5 6 #ifndef __DPAA2_ETH_H 7 #define __DPAA2_ETH_H 8 9 #include <linux/netdevice.h> 10 #include <linux/if_vlan.h> 11 #include <linux/fsl/mc.h> 12 13 #include <soc/fsl/dpaa2-io.h> 14 #include <soc/fsl/dpaa2-fd.h> 15 #include "dpni.h" 16 #include "dpni-cmd.h" 17 18 #include "dpaa2-eth-trace.h" 19 #include "dpaa2-eth-debugfs.h" 20 21 #define DPAA2_WRIOP_VERSION(x, y, z) ((x) << 10 | (y) << 5 | (z) << 0) 22 23 #define DPAA2_ETH_STORE_SIZE 16 24 25 /* Maximum number of scatter-gather entries in an ingress frame, 26 * considering the maximum receive frame size is 64K 27 */ 28 #define DPAA2_ETH_MAX_SG_ENTRIES ((64 * 1024) / DPAA2_ETH_RX_BUF_SIZE) 29 30 /* Maximum acceptable MTU value. It is in direct relation with the hardware 31 * enforced Max Frame Length (currently 10k). 32 */ 33 #define DPAA2_ETH_MFL (10 * 1024) 34 #define DPAA2_ETH_MAX_MTU (DPAA2_ETH_MFL - VLAN_ETH_HLEN) 35 /* Convert L3 MTU to L2 MFL */ 36 #define DPAA2_ETH_L2_MAX_FRM(mtu) ((mtu) + VLAN_ETH_HLEN) 37 38 /* Set the taildrop threshold (in bytes) to allow the enqueue of several jumbo 39 * frames in the Rx queues (length of the current frame is not 40 * taken into account when making the taildrop decision) 41 */ 42 #define DPAA2_ETH_TAILDROP_THRESH (64 * 1024) 43 44 /* Maximum number of Tx confirmation frames to be processed 45 * in a single NAPI call 46 */ 47 #define DPAA2_ETH_TXCONF_PER_NAPI 256 48 49 /* Buffer quota per queue. Must be large enough such that for minimum sized 50 * frames taildrop kicks in before the bpool gets depleted, so we compute 51 * how many 64B frames fit inside the taildrop threshold and add a margin 52 * to accommodate the buffer refill delay. 53 */ 54 #define DPAA2_ETH_MAX_FRAMES_PER_QUEUE (DPAA2_ETH_TAILDROP_THRESH / 64) 55 #define DPAA2_ETH_NUM_BUFS (DPAA2_ETH_MAX_FRAMES_PER_QUEUE + 256) 56 #define DPAA2_ETH_REFILL_THRESH \ 57 (DPAA2_ETH_NUM_BUFS - DPAA2_ETH_BUFS_PER_CMD) 58 59 /* Maximum number of buffers that can be acquired/released through a single 60 * QBMan command 61 */ 62 #define DPAA2_ETH_BUFS_PER_CMD 7 63 64 /* Hardware requires alignment for ingress/egress buffer addresses */ 65 #define DPAA2_ETH_TX_BUF_ALIGN 64 66 67 #define DPAA2_ETH_RX_BUF_RAW_SIZE PAGE_SIZE 68 #define DPAA2_ETH_RX_BUF_TAILROOM \ 69 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) 70 #define DPAA2_ETH_RX_BUF_SIZE \ 71 (DPAA2_ETH_RX_BUF_RAW_SIZE - DPAA2_ETH_RX_BUF_TAILROOM) 72 73 /* Hardware annotation area in RX/TX buffers */ 74 #define DPAA2_ETH_RX_HWA_SIZE 64 75 #define DPAA2_ETH_TX_HWA_SIZE 128 76 77 /* PTP nominal frequency 1GHz */ 78 #define DPAA2_PTP_CLK_PERIOD_NS 1 79 80 /* Due to a limitation in WRIOP 1.0.0, the RX buffer data must be aligned 81 * to 256B. For newer revisions, the requirement is only for 64B alignment 82 */ 83 #define DPAA2_ETH_RX_BUF_ALIGN_REV1 256 84 #define DPAA2_ETH_RX_BUF_ALIGN 64 85 86 /* We are accommodating a skb backpointer and some S/G info 87 * in the frame's software annotation. The hardware 88 * options are either 0 or 64, so we choose the latter. 89 */ 90 #define DPAA2_ETH_SWA_SIZE 64 91 92 /* Must keep this struct smaller than DPAA2_ETH_SWA_SIZE */ 93 struct dpaa2_eth_swa { 94 struct sk_buff *skb; 95 struct scatterlist *scl; 96 int num_sg; 97 int sgt_size; 98 }; 99 100 /* Annotation valid bits in FD FRC */ 101 #define DPAA2_FD_FRC_FASV 0x8000 102 #define DPAA2_FD_FRC_FAEADV 0x4000 103 #define DPAA2_FD_FRC_FAPRV 0x2000 104 #define DPAA2_FD_FRC_FAIADV 0x1000 105 #define DPAA2_FD_FRC_FASWOV 0x0800 106 #define DPAA2_FD_FRC_FAICFDV 0x0400 107 108 /* Error bits in FD CTRL */ 109 #define DPAA2_FD_RX_ERR_MASK (FD_CTRL_SBE | FD_CTRL_FAERR) 110 #define DPAA2_FD_TX_ERR_MASK (FD_CTRL_UFD | \ 111 FD_CTRL_SBE | \ 112 FD_CTRL_FSE | \ 113 FD_CTRL_FAERR) 114 115 /* Annotation bits in FD CTRL */ 116 #define DPAA2_FD_CTRL_ASAL 0x00020000 /* ASAL = 128B */ 117 118 /* Frame annotation status */ 119 struct dpaa2_fas { 120 u8 reserved; 121 u8 ppid; 122 __le16 ifpid; 123 __le32 status; 124 }; 125 126 /* Frame annotation status word is located in the first 8 bytes 127 * of the buffer's hardware annoatation area 128 */ 129 #define DPAA2_FAS_OFFSET 0 130 #define DPAA2_FAS_SIZE (sizeof(struct dpaa2_fas)) 131 132 /* Timestamp is located in the next 8 bytes of the buffer's 133 * hardware annotation area 134 */ 135 #define DPAA2_TS_OFFSET 0x8 136 137 /* Frame annotation egress action descriptor */ 138 #define DPAA2_FAEAD_OFFSET 0x58 139 140 struct dpaa2_faead { 141 __le32 conf_fqid; 142 __le32 ctrl; 143 }; 144 145 #define DPAA2_FAEAD_A2V 0x20000000 146 #define DPAA2_FAEAD_A4V 0x08000000 147 #define DPAA2_FAEAD_UPDV 0x00001000 148 #define DPAA2_FAEAD_EBDDV 0x00002000 149 #define DPAA2_FAEAD_UPD 0x00000010 150 151 /* Accessors for the hardware annotation fields that we use */ 152 static inline void *dpaa2_get_hwa(void *buf_addr, bool swa) 153 { 154 return buf_addr + (swa ? DPAA2_ETH_SWA_SIZE : 0); 155 } 156 157 static inline struct dpaa2_fas *dpaa2_get_fas(void *buf_addr, bool swa) 158 { 159 return dpaa2_get_hwa(buf_addr, swa) + DPAA2_FAS_OFFSET; 160 } 161 162 static inline __le64 *dpaa2_get_ts(void *buf_addr, bool swa) 163 { 164 return dpaa2_get_hwa(buf_addr, swa) + DPAA2_TS_OFFSET; 165 } 166 167 static inline struct dpaa2_faead *dpaa2_get_faead(void *buf_addr, bool swa) 168 { 169 return dpaa2_get_hwa(buf_addr, swa) + DPAA2_FAEAD_OFFSET; 170 } 171 172 /* Error and status bits in the frame annotation status word */ 173 /* Debug frame, otherwise supposed to be discarded */ 174 #define DPAA2_FAS_DISC 0x80000000 175 /* MACSEC frame */ 176 #define DPAA2_FAS_MS 0x40000000 177 #define DPAA2_FAS_PTP 0x08000000 178 /* Ethernet multicast frame */ 179 #define DPAA2_FAS_MC 0x04000000 180 /* Ethernet broadcast frame */ 181 #define DPAA2_FAS_BC 0x02000000 182 #define DPAA2_FAS_KSE 0x00040000 183 #define DPAA2_FAS_EOFHE 0x00020000 184 #define DPAA2_FAS_MNLE 0x00010000 185 #define DPAA2_FAS_TIDE 0x00008000 186 #define DPAA2_FAS_PIEE 0x00004000 187 /* Frame length error */ 188 #define DPAA2_FAS_FLE 0x00002000 189 /* Frame physical error */ 190 #define DPAA2_FAS_FPE 0x00001000 191 #define DPAA2_FAS_PTE 0x00000080 192 #define DPAA2_FAS_ISP 0x00000040 193 #define DPAA2_FAS_PHE 0x00000020 194 #define DPAA2_FAS_BLE 0x00000010 195 /* L3 csum validation performed */ 196 #define DPAA2_FAS_L3CV 0x00000008 197 /* L3 csum error */ 198 #define DPAA2_FAS_L3CE 0x00000004 199 /* L4 csum validation performed */ 200 #define DPAA2_FAS_L4CV 0x00000002 201 /* L4 csum error */ 202 #define DPAA2_FAS_L4CE 0x00000001 203 /* Possible errors on the ingress path */ 204 #define DPAA2_FAS_RX_ERR_MASK (DPAA2_FAS_KSE | \ 205 DPAA2_FAS_EOFHE | \ 206 DPAA2_FAS_MNLE | \ 207 DPAA2_FAS_TIDE | \ 208 DPAA2_FAS_PIEE | \ 209 DPAA2_FAS_FLE | \ 210 DPAA2_FAS_FPE | \ 211 DPAA2_FAS_PTE | \ 212 DPAA2_FAS_ISP | \ 213 DPAA2_FAS_PHE | \ 214 DPAA2_FAS_BLE | \ 215 DPAA2_FAS_L3CE | \ 216 DPAA2_FAS_L4CE) 217 218 /* Time in milliseconds between link state updates */ 219 #define DPAA2_ETH_LINK_STATE_REFRESH 1000 220 221 /* Number of times to retry a frame enqueue before giving up. 222 * Value determined empirically, in order to minimize the number 223 * of frames dropped on Tx 224 */ 225 #define DPAA2_ETH_ENQUEUE_RETRIES 10 226 227 /* Driver statistics, other than those in struct rtnl_link_stats64. 228 * These are usually collected per-CPU and aggregated by ethtool. 229 */ 230 struct dpaa2_eth_drv_stats { 231 __u64 tx_conf_frames; 232 __u64 tx_conf_bytes; 233 __u64 tx_sg_frames; 234 __u64 tx_sg_bytes; 235 __u64 tx_reallocs; 236 __u64 rx_sg_frames; 237 __u64 rx_sg_bytes; 238 /* Enqueues retried due to portal busy */ 239 __u64 tx_portal_busy; 240 }; 241 242 /* Per-FQ statistics */ 243 struct dpaa2_eth_fq_stats { 244 /* Number of frames received on this queue */ 245 __u64 frames; 246 }; 247 248 /* Per-channel statistics */ 249 struct dpaa2_eth_ch_stats { 250 /* Volatile dequeues retried due to portal busy */ 251 __u64 dequeue_portal_busy; 252 /* Pull errors */ 253 __u64 pull_err; 254 /* Number of CDANs; useful to estimate avg NAPI len */ 255 __u64 cdan; 256 /* XDP counters */ 257 __u64 xdp_drop; 258 __u64 xdp_tx; 259 __u64 xdp_tx_err; 260 }; 261 262 /* Maximum number of queues associated with a DPNI */ 263 #define DPAA2_ETH_MAX_RX_QUEUES 16 264 #define DPAA2_ETH_MAX_TX_QUEUES 16 265 #define DPAA2_ETH_MAX_QUEUES (DPAA2_ETH_MAX_RX_QUEUES + \ 266 DPAA2_ETH_MAX_TX_QUEUES) 267 268 #define DPAA2_ETH_MAX_DPCONS 16 269 270 enum dpaa2_eth_fq_type { 271 DPAA2_RX_FQ = 0, 272 DPAA2_TX_CONF_FQ, 273 }; 274 275 struct dpaa2_eth_priv; 276 277 struct dpaa2_eth_fq { 278 u32 fqid; 279 u32 tx_qdbin; 280 u32 tx_fqid; 281 u16 flowid; 282 int target_cpu; 283 u32 dq_frames; 284 u32 dq_bytes; 285 struct dpaa2_eth_channel *channel; 286 enum dpaa2_eth_fq_type type; 287 288 void (*consume)(struct dpaa2_eth_priv *priv, 289 struct dpaa2_eth_channel *ch, 290 const struct dpaa2_fd *fd, 291 struct dpaa2_eth_fq *fq); 292 struct dpaa2_eth_fq_stats stats; 293 }; 294 295 struct dpaa2_eth_ch_xdp { 296 struct bpf_prog *prog; 297 u64 drop_bufs[DPAA2_ETH_BUFS_PER_CMD]; 298 int drop_cnt; 299 }; 300 301 struct dpaa2_eth_channel { 302 struct dpaa2_io_notification_ctx nctx; 303 struct fsl_mc_device *dpcon; 304 int dpcon_id; 305 int ch_id; 306 struct napi_struct napi; 307 struct dpaa2_io *dpio; 308 struct dpaa2_io_store *store; 309 struct dpaa2_eth_priv *priv; 310 int buf_count; 311 struct dpaa2_eth_ch_stats stats; 312 struct dpaa2_eth_ch_xdp xdp; 313 }; 314 315 struct dpaa2_eth_dist_fields { 316 u64 rxnfc_field; 317 enum net_prot cls_prot; 318 int cls_field; 319 int size; 320 }; 321 322 struct dpaa2_eth_cls_rule { 323 struct ethtool_rx_flow_spec fs; 324 u8 in_use; 325 }; 326 327 /* Driver private data */ 328 struct dpaa2_eth_priv { 329 struct net_device *net_dev; 330 331 u8 num_fqs; 332 struct dpaa2_eth_fq fq[DPAA2_ETH_MAX_QUEUES]; 333 int (*enqueue)(struct dpaa2_eth_priv *priv, 334 struct dpaa2_eth_fq *fq, 335 struct dpaa2_fd *fd, u8 prio); 336 337 u8 num_channels; 338 struct dpaa2_eth_channel *channel[DPAA2_ETH_MAX_DPCONS]; 339 340 struct dpni_attr dpni_attrs; 341 u16 dpni_ver_major; 342 u16 dpni_ver_minor; 343 u16 tx_data_offset; 344 345 struct fsl_mc_device *dpbp_dev; 346 u16 bpid; 347 struct iommu_domain *iommu_domain; 348 349 bool tx_tstamp; /* Tx timestamping enabled */ 350 bool rx_tstamp; /* Rx timestamping enabled */ 351 352 u16 tx_qdid; 353 struct fsl_mc_io *mc_io; 354 /* Cores which have an affine DPIO/DPCON. 355 * This is the cpu set on which Rx and Tx conf frames are processed 356 */ 357 struct cpumask dpio_cpumask; 358 359 /* Standard statistics */ 360 struct rtnl_link_stats64 __percpu *percpu_stats; 361 /* Extra stats, in addition to the ones known by the kernel */ 362 struct dpaa2_eth_drv_stats __percpu *percpu_extras; 363 364 u16 mc_token; 365 366 struct dpni_link_state link_state; 367 bool do_link_poll; 368 struct task_struct *poll_thread; 369 370 /* enabled ethtool hashing bits */ 371 u64 rx_hash_fields; 372 struct dpaa2_eth_cls_rule *cls_rules; 373 u8 rx_cls_enabled; 374 struct bpf_prog *xdp_prog; 375 #ifdef CONFIG_DEBUG_FS 376 struct dpaa2_debugfs dbg; 377 #endif 378 }; 379 380 #define DPAA2_RXH_SUPPORTED (RXH_L2DA | RXH_VLAN | RXH_L3_PROTO \ 381 | RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 \ 382 | RXH_L4_B_2_3) 383 384 /* default Rx hash options, set during probing */ 385 #define DPAA2_RXH_DEFAULT (RXH_L3_PROTO | RXH_IP_SRC | RXH_IP_DST | \ 386 RXH_L4_B_0_1 | RXH_L4_B_2_3) 387 388 #define dpaa2_eth_hash_enabled(priv) \ 389 ((priv)->dpni_attrs.num_queues > 1) 390 391 /* Required by struct dpni_rx_tc_dist_cfg::key_cfg_iova */ 392 #define DPAA2_CLASSIFIER_DMA_SIZE 256 393 394 extern const struct ethtool_ops dpaa2_ethtool_ops; 395 extern int dpaa2_phc_index; 396 397 static inline int dpaa2_eth_cmp_dpni_ver(struct dpaa2_eth_priv *priv, 398 u16 ver_major, u16 ver_minor) 399 { 400 if (priv->dpni_ver_major == ver_major) 401 return priv->dpni_ver_minor - ver_minor; 402 return priv->dpni_ver_major - ver_major; 403 } 404 405 /* Minimum firmware version that supports a more flexible API 406 * for configuring the Rx flow hash key 407 */ 408 #define DPNI_RX_DIST_KEY_VER_MAJOR 7 409 #define DPNI_RX_DIST_KEY_VER_MINOR 5 410 411 #define dpaa2_eth_has_legacy_dist(priv) \ 412 (dpaa2_eth_cmp_dpni_ver((priv), DPNI_RX_DIST_KEY_VER_MAJOR, \ 413 DPNI_RX_DIST_KEY_VER_MINOR) < 0) 414 415 #define dpaa2_eth_fs_count(priv) \ 416 ((priv)->dpni_attrs.fs_entries) 417 418 /* We have exactly one {Rx, Tx conf} queue per channel */ 419 #define dpaa2_eth_queue_count(priv) \ 420 ((priv)->num_channels) 421 422 enum dpaa2_eth_rx_dist { 423 DPAA2_ETH_RX_DIST_HASH, 424 DPAA2_ETH_RX_DIST_CLS 425 }; 426 427 static inline 428 unsigned int dpaa2_eth_needed_headroom(struct dpaa2_eth_priv *priv, 429 struct sk_buff *skb) 430 { 431 unsigned int headroom = DPAA2_ETH_SWA_SIZE; 432 433 /* For non-linear skbs we have no headroom requirement, as we build a 434 * SG frame with a newly allocated SGT buffer 435 */ 436 if (skb_is_nonlinear(skb)) 437 return 0; 438 439 /* If we have Tx timestamping, need 128B hardware annotation */ 440 if (priv->tx_tstamp && skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) 441 headroom += DPAA2_ETH_TX_HWA_SIZE; 442 443 return headroom; 444 } 445 446 /* Extra headroom space requested to hardware, in order to make sure there's 447 * no realloc'ing in forwarding scenarios 448 */ 449 static inline unsigned int dpaa2_eth_rx_head_room(struct dpaa2_eth_priv *priv) 450 { 451 return priv->tx_data_offset - DPAA2_ETH_RX_HWA_SIZE; 452 } 453 454 int dpaa2_eth_set_hash(struct net_device *net_dev, u64 flags); 455 int dpaa2_eth_cls_key_size(void); 456 int dpaa2_eth_cls_fld_off(int prot, int field); 457 458 #endif /* __DPAA2_H */ 459