1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ 2 /* Copyright 2014-2016 Freescale Semiconductor Inc. 3 * Copyright 2016-2020 NXP 4 */ 5 6 #ifndef __DPAA2_ETH_H 7 #define __DPAA2_ETH_H 8 9 #include <linux/dcbnl.h> 10 #include <linux/netdevice.h> 11 #include <linux/if_vlan.h> 12 #include <linux/fsl/mc.h> 13 14 #include <soc/fsl/dpaa2-io.h> 15 #include <soc/fsl/dpaa2-fd.h> 16 #include "dpni.h" 17 #include "dpni-cmd.h" 18 19 #include "dpaa2-eth-trace.h" 20 #include "dpaa2-eth-debugfs.h" 21 #include "dpaa2-mac.h" 22 23 #define DPAA2_WRIOP_VERSION(x, y, z) ((x) << 10 | (y) << 5 | (z) << 0) 24 25 #define DPAA2_ETH_STORE_SIZE 16 26 27 /* Maximum number of scatter-gather entries in an ingress frame, 28 * considering the maximum receive frame size is 64K 29 */ 30 #define DPAA2_ETH_MAX_SG_ENTRIES ((64 * 1024) / DPAA2_ETH_RX_BUF_SIZE) 31 32 /* Maximum acceptable MTU value. It is in direct relation with the hardware 33 * enforced Max Frame Length (currently 10k). 34 */ 35 #define DPAA2_ETH_MFL (10 * 1024) 36 #define DPAA2_ETH_MAX_MTU (DPAA2_ETH_MFL - VLAN_ETH_HLEN) 37 /* Convert L3 MTU to L2 MFL */ 38 #define DPAA2_ETH_L2_MAX_FRM(mtu) ((mtu) + VLAN_ETH_HLEN) 39 40 /* Set the taildrop threshold (in bytes) to allow the enqueue of a large 41 * enough number of jumbo frames in the Rx queues (length of the current 42 * frame is not taken into account when making the taildrop decision) 43 */ 44 #define DPAA2_ETH_FQ_TAILDROP_THRESH (1024 * 1024) 45 46 /* Maximum number of Tx confirmation frames to be processed 47 * in a single NAPI call 48 */ 49 #define DPAA2_ETH_TXCONF_PER_NAPI 256 50 51 /* Buffer qouta per channel. We want to keep in check number of ingress frames 52 * in flight: for small sized frames, congestion group taildrop may kick in 53 * first; for large sizes, Rx FQ taildrop threshold will ensure only a 54 * reasonable number of frames will be pending at any given time. 55 * Ingress frame drop due to buffer pool depletion should be a corner case only 56 */ 57 #define DPAA2_ETH_NUM_BUFS 1280 58 #define DPAA2_ETH_REFILL_THRESH \ 59 (DPAA2_ETH_NUM_BUFS - DPAA2_ETH_BUFS_PER_CMD) 60 61 /* Congestion group taildrop threshold: number of frames allowed to accumulate 62 * at any moment in a group of Rx queues belonging to the same traffic class. 63 * Choose value such that we don't risk depleting the buffer pool before the 64 * taildrop kicks in 65 */ 66 #define DPAA2_ETH_CG_TAILDROP_THRESH(priv) \ 67 (1024 * dpaa2_eth_queue_count(priv) / dpaa2_eth_tc_count(priv)) 68 69 /* Congestion group notification threshold: when this many frames accumulate 70 * on the Rx queues belonging to the same TC, the MAC is instructed to send 71 * PFC frames for that TC. 72 * When number of pending frames drops below exit threshold transmission of 73 * PFC frames is stopped. 74 */ 75 #define DPAA2_ETH_CN_THRESH_ENTRY(priv) \ 76 (DPAA2_ETH_CG_TAILDROP_THRESH(priv) / 2) 77 #define DPAA2_ETH_CN_THRESH_EXIT(priv) \ 78 (DPAA2_ETH_CN_THRESH_ENTRY(priv) * 3 / 4) 79 80 /* Maximum number of buffers that can be acquired/released through a single 81 * QBMan command 82 */ 83 #define DPAA2_ETH_BUFS_PER_CMD 7 84 85 /* Hardware requires alignment for ingress/egress buffer addresses */ 86 #define DPAA2_ETH_TX_BUF_ALIGN 64 87 88 #define DPAA2_ETH_RX_BUF_RAW_SIZE PAGE_SIZE 89 #define DPAA2_ETH_RX_BUF_TAILROOM \ 90 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) 91 #define DPAA2_ETH_RX_BUF_SIZE \ 92 (DPAA2_ETH_RX_BUF_RAW_SIZE - DPAA2_ETH_RX_BUF_TAILROOM) 93 94 /* Hardware annotation area in RX/TX buffers */ 95 #define DPAA2_ETH_RX_HWA_SIZE 64 96 #define DPAA2_ETH_TX_HWA_SIZE 128 97 98 /* PTP nominal frequency 1GHz */ 99 #define DPAA2_PTP_CLK_PERIOD_NS 1 100 101 /* Due to a limitation in WRIOP 1.0.0, the RX buffer data must be aligned 102 * to 256B. For newer revisions, the requirement is only for 64B alignment 103 */ 104 #define DPAA2_ETH_RX_BUF_ALIGN_REV1 256 105 #define DPAA2_ETH_RX_BUF_ALIGN 64 106 107 /* We are accommodating a skb backpointer and some S/G info 108 * in the frame's software annotation. The hardware 109 * options are either 0 or 64, so we choose the latter. 110 */ 111 #define DPAA2_ETH_SWA_SIZE 64 112 113 /* We store different information in the software annotation area of a Tx frame 114 * based on what type of frame it is 115 */ 116 enum dpaa2_eth_swa_type { 117 DPAA2_ETH_SWA_SINGLE, 118 DPAA2_ETH_SWA_SG, 119 DPAA2_ETH_SWA_XDP, 120 }; 121 122 /* Must keep this struct smaller than DPAA2_ETH_SWA_SIZE */ 123 struct dpaa2_eth_swa { 124 enum dpaa2_eth_swa_type type; 125 union { 126 struct { 127 struct sk_buff *skb; 128 int sgt_size; 129 } single; 130 struct { 131 struct sk_buff *skb; 132 struct scatterlist *scl; 133 int num_sg; 134 int sgt_size; 135 } sg; 136 struct { 137 int dma_size; 138 struct xdp_frame *xdpf; 139 } xdp; 140 }; 141 }; 142 143 /* Annotation valid bits in FD FRC */ 144 #define DPAA2_FD_FRC_FASV 0x8000 145 #define DPAA2_FD_FRC_FAEADV 0x4000 146 #define DPAA2_FD_FRC_FAPRV 0x2000 147 #define DPAA2_FD_FRC_FAIADV 0x1000 148 #define DPAA2_FD_FRC_FASWOV 0x0800 149 #define DPAA2_FD_FRC_FAICFDV 0x0400 150 151 /* Error bits in FD CTRL */ 152 #define DPAA2_FD_RX_ERR_MASK (FD_CTRL_SBE | FD_CTRL_FAERR) 153 #define DPAA2_FD_TX_ERR_MASK (FD_CTRL_UFD | \ 154 FD_CTRL_SBE | \ 155 FD_CTRL_FSE | \ 156 FD_CTRL_FAERR) 157 158 /* Annotation bits in FD CTRL */ 159 #define DPAA2_FD_CTRL_ASAL 0x00020000 /* ASAL = 128B */ 160 161 /* Frame annotation status */ 162 struct dpaa2_fas { 163 u8 reserved; 164 u8 ppid; 165 __le16 ifpid; 166 __le32 status; 167 }; 168 169 /* Frame annotation status word is located in the first 8 bytes 170 * of the buffer's hardware annoatation area 171 */ 172 #define DPAA2_FAS_OFFSET 0 173 #define DPAA2_FAS_SIZE (sizeof(struct dpaa2_fas)) 174 175 /* Timestamp is located in the next 8 bytes of the buffer's 176 * hardware annotation area 177 */ 178 #define DPAA2_TS_OFFSET 0x8 179 180 /* Frame annotation egress action descriptor */ 181 #define DPAA2_FAEAD_OFFSET 0x58 182 183 struct dpaa2_faead { 184 __le32 conf_fqid; 185 __le32 ctrl; 186 }; 187 188 #define DPAA2_FAEAD_A2V 0x20000000 189 #define DPAA2_FAEAD_A4V 0x08000000 190 #define DPAA2_FAEAD_UPDV 0x00001000 191 #define DPAA2_FAEAD_EBDDV 0x00002000 192 #define DPAA2_FAEAD_UPD 0x00000010 193 194 /* Accessors for the hardware annotation fields that we use */ 195 static inline void *dpaa2_get_hwa(void *buf_addr, bool swa) 196 { 197 return buf_addr + (swa ? DPAA2_ETH_SWA_SIZE : 0); 198 } 199 200 static inline struct dpaa2_fas *dpaa2_get_fas(void *buf_addr, bool swa) 201 { 202 return dpaa2_get_hwa(buf_addr, swa) + DPAA2_FAS_OFFSET; 203 } 204 205 static inline __le64 *dpaa2_get_ts(void *buf_addr, bool swa) 206 { 207 return dpaa2_get_hwa(buf_addr, swa) + DPAA2_TS_OFFSET; 208 } 209 210 static inline struct dpaa2_faead *dpaa2_get_faead(void *buf_addr, bool swa) 211 { 212 return dpaa2_get_hwa(buf_addr, swa) + DPAA2_FAEAD_OFFSET; 213 } 214 215 /* Error and status bits in the frame annotation status word */ 216 /* Debug frame, otherwise supposed to be discarded */ 217 #define DPAA2_FAS_DISC 0x80000000 218 /* MACSEC frame */ 219 #define DPAA2_FAS_MS 0x40000000 220 #define DPAA2_FAS_PTP 0x08000000 221 /* Ethernet multicast frame */ 222 #define DPAA2_FAS_MC 0x04000000 223 /* Ethernet broadcast frame */ 224 #define DPAA2_FAS_BC 0x02000000 225 #define DPAA2_FAS_KSE 0x00040000 226 #define DPAA2_FAS_EOFHE 0x00020000 227 #define DPAA2_FAS_MNLE 0x00010000 228 #define DPAA2_FAS_TIDE 0x00008000 229 #define DPAA2_FAS_PIEE 0x00004000 230 /* Frame length error */ 231 #define DPAA2_FAS_FLE 0x00002000 232 /* Frame physical error */ 233 #define DPAA2_FAS_FPE 0x00001000 234 #define DPAA2_FAS_PTE 0x00000080 235 #define DPAA2_FAS_ISP 0x00000040 236 #define DPAA2_FAS_PHE 0x00000020 237 #define DPAA2_FAS_BLE 0x00000010 238 /* L3 csum validation performed */ 239 #define DPAA2_FAS_L3CV 0x00000008 240 /* L3 csum error */ 241 #define DPAA2_FAS_L3CE 0x00000004 242 /* L4 csum validation performed */ 243 #define DPAA2_FAS_L4CV 0x00000002 244 /* L4 csum error */ 245 #define DPAA2_FAS_L4CE 0x00000001 246 /* Possible errors on the ingress path */ 247 #define DPAA2_FAS_RX_ERR_MASK (DPAA2_FAS_KSE | \ 248 DPAA2_FAS_EOFHE | \ 249 DPAA2_FAS_MNLE | \ 250 DPAA2_FAS_TIDE | \ 251 DPAA2_FAS_PIEE | \ 252 DPAA2_FAS_FLE | \ 253 DPAA2_FAS_FPE | \ 254 DPAA2_FAS_PTE | \ 255 DPAA2_FAS_ISP | \ 256 DPAA2_FAS_PHE | \ 257 DPAA2_FAS_BLE | \ 258 DPAA2_FAS_L3CE | \ 259 DPAA2_FAS_L4CE) 260 261 /* Time in milliseconds between link state updates */ 262 #define DPAA2_ETH_LINK_STATE_REFRESH 1000 263 264 /* Number of times to retry a frame enqueue before giving up. 265 * Value determined empirically, in order to minimize the number 266 * of frames dropped on Tx 267 */ 268 #define DPAA2_ETH_ENQUEUE_RETRIES 10 269 270 /* Number of times to retry DPIO portal operations while waiting 271 * for portal to finish executing current command and become 272 * available. We want to avoid being stuck in a while loop in case 273 * hardware becomes unresponsive, but not give up too easily if 274 * the portal really is busy for valid reasons 275 */ 276 #define DPAA2_ETH_SWP_BUSY_RETRIES 1000 277 278 /* Driver statistics, other than those in struct rtnl_link_stats64. 279 * These are usually collected per-CPU and aggregated by ethtool. 280 */ 281 struct dpaa2_eth_drv_stats { 282 __u64 tx_conf_frames; 283 __u64 tx_conf_bytes; 284 __u64 tx_sg_frames; 285 __u64 tx_sg_bytes; 286 __u64 rx_sg_frames; 287 __u64 rx_sg_bytes; 288 /* Linear skbs sent as a S/G FD due to insufficient headroom */ 289 __u64 tx_converted_sg_frames; 290 __u64 tx_converted_sg_bytes; 291 /* Enqueues retried due to portal busy */ 292 __u64 tx_portal_busy; 293 }; 294 295 /* Per-FQ statistics */ 296 struct dpaa2_eth_fq_stats { 297 /* Number of frames received on this queue */ 298 __u64 frames; 299 }; 300 301 /* Per-channel statistics */ 302 struct dpaa2_eth_ch_stats { 303 /* Volatile dequeues retried due to portal busy */ 304 __u64 dequeue_portal_busy; 305 /* Pull errors */ 306 __u64 pull_err; 307 /* Number of CDANs; useful to estimate avg NAPI len */ 308 __u64 cdan; 309 /* XDP counters */ 310 __u64 xdp_drop; 311 __u64 xdp_tx; 312 __u64 xdp_tx_err; 313 __u64 xdp_redirect; 314 /* Must be last, does not show up in ethtool stats */ 315 __u64 frames; 316 }; 317 318 /* Maximum number of queues associated with a DPNI */ 319 #define DPAA2_ETH_MAX_TCS 8 320 #define DPAA2_ETH_MAX_RX_QUEUES_PER_TC 16 321 #define DPAA2_ETH_MAX_RX_QUEUES \ 322 (DPAA2_ETH_MAX_RX_QUEUES_PER_TC * DPAA2_ETH_MAX_TCS) 323 #define DPAA2_ETH_MAX_TX_QUEUES 16 324 #define DPAA2_ETH_MAX_QUEUES (DPAA2_ETH_MAX_RX_QUEUES + \ 325 DPAA2_ETH_MAX_TX_QUEUES) 326 #define DPAA2_ETH_MAX_NETDEV_QUEUES \ 327 (DPAA2_ETH_MAX_TX_QUEUES * DPAA2_ETH_MAX_TCS) 328 329 #define DPAA2_ETH_MAX_DPCONS 16 330 331 enum dpaa2_eth_fq_type { 332 DPAA2_RX_FQ = 0, 333 DPAA2_TX_CONF_FQ, 334 }; 335 336 struct dpaa2_eth_priv; 337 338 struct dpaa2_eth_xdp_fds { 339 struct dpaa2_fd fds[DEV_MAP_BULK_SIZE]; 340 ssize_t num; 341 }; 342 343 struct dpaa2_eth_fq { 344 u32 fqid; 345 u32 tx_qdbin; 346 u32 tx_fqid[DPAA2_ETH_MAX_TCS]; 347 u16 flowid; 348 u8 tc; 349 int target_cpu; 350 u32 dq_frames; 351 u32 dq_bytes; 352 struct dpaa2_eth_channel *channel; 353 enum dpaa2_eth_fq_type type; 354 355 void (*consume)(struct dpaa2_eth_priv *priv, 356 struct dpaa2_eth_channel *ch, 357 const struct dpaa2_fd *fd, 358 struct dpaa2_eth_fq *fq); 359 struct dpaa2_eth_fq_stats stats; 360 361 struct dpaa2_eth_xdp_fds xdp_redirect_fds; 362 struct dpaa2_eth_xdp_fds xdp_tx_fds; 363 }; 364 365 struct dpaa2_eth_ch_xdp { 366 struct bpf_prog *prog; 367 u64 drop_bufs[DPAA2_ETH_BUFS_PER_CMD]; 368 int drop_cnt; 369 unsigned int res; 370 }; 371 372 struct dpaa2_eth_channel { 373 struct dpaa2_io_notification_ctx nctx; 374 struct fsl_mc_device *dpcon; 375 int dpcon_id; 376 int ch_id; 377 struct napi_struct napi; 378 struct dpaa2_io *dpio; 379 struct dpaa2_io_store *store; 380 struct dpaa2_eth_priv *priv; 381 int buf_count; 382 struct dpaa2_eth_ch_stats stats; 383 struct dpaa2_eth_ch_xdp xdp; 384 struct xdp_rxq_info xdp_rxq; 385 struct list_head *rx_list; 386 }; 387 388 struct dpaa2_eth_dist_fields { 389 u64 rxnfc_field; 390 enum net_prot cls_prot; 391 int cls_field; 392 int size; 393 u64 id; 394 }; 395 396 struct dpaa2_eth_cls_rule { 397 struct ethtool_rx_flow_spec fs; 398 u8 in_use; 399 }; 400 401 #define DPAA2_ETH_SGT_CACHE_SIZE 256 402 struct dpaa2_eth_sgt_cache { 403 void *buf[DPAA2_ETH_SGT_CACHE_SIZE]; 404 u16 count; 405 }; 406 407 /* Driver private data */ 408 struct dpaa2_eth_priv { 409 struct net_device *net_dev; 410 411 u8 num_fqs; 412 struct dpaa2_eth_fq fq[DPAA2_ETH_MAX_QUEUES]; 413 int (*enqueue)(struct dpaa2_eth_priv *priv, 414 struct dpaa2_eth_fq *fq, 415 struct dpaa2_fd *fd, u8 prio, 416 u32 num_frames, 417 int *frames_enqueued); 418 419 u8 num_channels; 420 struct dpaa2_eth_channel *channel[DPAA2_ETH_MAX_DPCONS]; 421 struct dpaa2_eth_sgt_cache __percpu *sgt_cache; 422 423 struct dpni_attr dpni_attrs; 424 u16 dpni_ver_major; 425 u16 dpni_ver_minor; 426 u16 tx_data_offset; 427 428 struct fsl_mc_device *dpbp_dev; 429 u16 rx_buf_size; 430 u16 bpid; 431 struct iommu_domain *iommu_domain; 432 433 bool tx_tstamp; /* Tx timestamping enabled */ 434 bool rx_tstamp; /* Rx timestamping enabled */ 435 436 u16 tx_qdid; 437 struct fsl_mc_io *mc_io; 438 /* Cores which have an affine DPIO/DPCON. 439 * This is the cpu set on which Rx and Tx conf frames are processed 440 */ 441 struct cpumask dpio_cpumask; 442 443 /* Standard statistics */ 444 struct rtnl_link_stats64 __percpu *percpu_stats; 445 /* Extra stats, in addition to the ones known by the kernel */ 446 struct dpaa2_eth_drv_stats __percpu *percpu_extras; 447 448 u16 mc_token; 449 u8 rx_fqtd_enabled; 450 u8 rx_cgtd_enabled; 451 452 struct dpni_link_state link_state; 453 bool do_link_poll; 454 struct task_struct *poll_thread; 455 456 /* enabled ethtool hashing bits */ 457 u64 rx_hash_fields; 458 u64 rx_cls_fields; 459 struct dpaa2_eth_cls_rule *cls_rules; 460 u8 rx_cls_enabled; 461 u8 vlan_cls_enabled; 462 u8 pfc_enabled; 463 #ifdef CONFIG_FSL_DPAA2_ETH_DCB 464 u8 dcbx_mode; 465 struct ieee_pfc pfc; 466 #endif 467 struct bpf_prog *xdp_prog; 468 #ifdef CONFIG_DEBUG_FS 469 struct dpaa2_debugfs dbg; 470 #endif 471 472 struct dpaa2_mac *mac; 473 }; 474 475 #define DPAA2_RXH_SUPPORTED (RXH_L2DA | RXH_VLAN | RXH_L3_PROTO \ 476 | RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 \ 477 | RXH_L4_B_2_3) 478 479 /* default Rx hash options, set during probing */ 480 #define DPAA2_RXH_DEFAULT (RXH_L3_PROTO | RXH_IP_SRC | RXH_IP_DST | \ 481 RXH_L4_B_0_1 | RXH_L4_B_2_3) 482 483 #define dpaa2_eth_hash_enabled(priv) \ 484 ((priv)->dpni_attrs.num_queues > 1) 485 486 /* Required by struct dpni_rx_tc_dist_cfg::key_cfg_iova */ 487 #define DPAA2_CLASSIFIER_DMA_SIZE 256 488 489 extern const struct ethtool_ops dpaa2_ethtool_ops; 490 extern int dpaa2_phc_index; 491 492 static inline int dpaa2_eth_cmp_dpni_ver(struct dpaa2_eth_priv *priv, 493 u16 ver_major, u16 ver_minor) 494 { 495 if (priv->dpni_ver_major == ver_major) 496 return priv->dpni_ver_minor - ver_minor; 497 return priv->dpni_ver_major - ver_major; 498 } 499 500 /* Minimum firmware version that supports a more flexible API 501 * for configuring the Rx flow hash key 502 */ 503 #define DPNI_RX_DIST_KEY_VER_MAJOR 7 504 #define DPNI_RX_DIST_KEY_VER_MINOR 5 505 506 #define dpaa2_eth_has_legacy_dist(priv) \ 507 (dpaa2_eth_cmp_dpni_ver((priv), DPNI_RX_DIST_KEY_VER_MAJOR, \ 508 DPNI_RX_DIST_KEY_VER_MINOR) < 0) 509 510 #define dpaa2_eth_fs_enabled(priv) \ 511 (!((priv)->dpni_attrs.options & DPNI_OPT_NO_FS)) 512 513 #define dpaa2_eth_fs_mask_enabled(priv) \ 514 ((priv)->dpni_attrs.options & DPNI_OPT_HAS_KEY_MASKING) 515 516 #define dpaa2_eth_fs_count(priv) \ 517 ((priv)->dpni_attrs.fs_entries) 518 519 #define dpaa2_eth_tc_count(priv) \ 520 ((priv)->dpni_attrs.num_tcs) 521 522 /* We have exactly one {Rx, Tx conf} queue per channel */ 523 #define dpaa2_eth_queue_count(priv) \ 524 ((priv)->num_channels) 525 526 enum dpaa2_eth_rx_dist { 527 DPAA2_ETH_RX_DIST_HASH, 528 DPAA2_ETH_RX_DIST_CLS 529 }; 530 531 /* Unique IDs for the supported Rx classification header fields */ 532 #define DPAA2_ETH_DIST_ETHDST BIT(0) 533 #define DPAA2_ETH_DIST_ETHSRC BIT(1) 534 #define DPAA2_ETH_DIST_ETHTYPE BIT(2) 535 #define DPAA2_ETH_DIST_VLAN BIT(3) 536 #define DPAA2_ETH_DIST_IPSRC BIT(4) 537 #define DPAA2_ETH_DIST_IPDST BIT(5) 538 #define DPAA2_ETH_DIST_IPPROTO BIT(6) 539 #define DPAA2_ETH_DIST_L4SRC BIT(7) 540 #define DPAA2_ETH_DIST_L4DST BIT(8) 541 #define DPAA2_ETH_DIST_ALL (~0ULL) 542 543 #define DPNI_PAUSE_VER_MAJOR 7 544 #define DPNI_PAUSE_VER_MINOR 13 545 #define dpaa2_eth_has_pause_support(priv) \ 546 (dpaa2_eth_cmp_dpni_ver((priv), DPNI_PAUSE_VER_MAJOR, \ 547 DPNI_PAUSE_VER_MINOR) >= 0) 548 549 static inline bool dpaa2_eth_tx_pause_enabled(u64 link_options) 550 { 551 return !!(link_options & DPNI_LINK_OPT_PAUSE) ^ 552 !!(link_options & DPNI_LINK_OPT_ASYM_PAUSE); 553 } 554 555 static inline bool dpaa2_eth_rx_pause_enabled(u64 link_options) 556 { 557 return !!(link_options & DPNI_LINK_OPT_PAUSE); 558 } 559 560 static inline 561 unsigned int dpaa2_eth_needed_headroom(struct dpaa2_eth_priv *priv, 562 struct sk_buff *skb) 563 { 564 unsigned int headroom = DPAA2_ETH_SWA_SIZE; 565 566 /* If we don't have an skb (e.g. XDP buffer), we only need space for 567 * the software annotation area 568 */ 569 if (!skb) 570 return headroom; 571 572 /* For non-linear skbs we have no headroom requirement, as we build a 573 * SG frame with a newly allocated SGT buffer 574 */ 575 if (skb_is_nonlinear(skb)) 576 return 0; 577 578 /* If we have Tx timestamping, need 128B hardware annotation */ 579 if (priv->tx_tstamp && skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) 580 headroom += DPAA2_ETH_TX_HWA_SIZE; 581 582 return headroom; 583 } 584 585 /* Extra headroom space requested to hardware, in order to make sure there's 586 * no realloc'ing in forwarding scenarios 587 */ 588 static inline unsigned int dpaa2_eth_rx_head_room(struct dpaa2_eth_priv *priv) 589 { 590 return priv->tx_data_offset - DPAA2_ETH_RX_HWA_SIZE; 591 } 592 593 int dpaa2_eth_set_hash(struct net_device *net_dev, u64 flags); 594 int dpaa2_eth_set_cls(struct net_device *net_dev, u64 key); 595 int dpaa2_eth_cls_key_size(u64 key); 596 int dpaa2_eth_cls_fld_off(int prot, int field); 597 void dpaa2_eth_cls_trim_rule(void *key_mem, u64 fields); 598 599 void dpaa2_eth_set_rx_taildrop(struct dpaa2_eth_priv *priv, 600 bool tx_pause, bool pfc); 601 602 extern const struct dcbnl_rtnl_ops dpaa2_eth_dcbnl_ops; 603 604 #endif /* __DPAA2_H */ 605