1 /* 2 * Faraday FTGMAC100 Gigabit Ethernet 3 * 4 * (C) Copyright 2009-2011 Faraday Technology 5 * Po-Yu Chuang <ratbert@faraday-tech.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 20 */ 21 22 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 23 24 #include <linux/dma-mapping.h> 25 #include <linux/etherdevice.h> 26 #include <linux/ethtool.h> 27 #include <linux/init.h> 28 #include <linux/io.h> 29 #include <linux/module.h> 30 #include <linux/netdevice.h> 31 #include <linux/phy.h> 32 #include <linux/platform_device.h> 33 #include <net/ip.h> 34 35 #include "ftgmac100.h" 36 37 #define DRV_NAME "ftgmac100" 38 #define DRV_VERSION "0.7" 39 40 #define RX_QUEUE_ENTRIES 256 /* must be power of 2 */ 41 #define TX_QUEUE_ENTRIES 512 /* must be power of 2 */ 42 43 #define MAX_PKT_SIZE 1518 44 #define RX_BUF_SIZE PAGE_SIZE /* must be smaller than 0x3fff */ 45 46 /****************************************************************************** 47 * private data 48 *****************************************************************************/ 49 struct ftgmac100_descs { 50 struct ftgmac100_rxdes rxdes[RX_QUEUE_ENTRIES]; 51 struct ftgmac100_txdes txdes[TX_QUEUE_ENTRIES]; 52 }; 53 54 struct ftgmac100 { 55 struct resource *res; 56 void __iomem *base; 57 int irq; 58 59 struct ftgmac100_descs *descs; 60 dma_addr_t descs_dma_addr; 61 62 unsigned int rx_pointer; 63 unsigned int tx_clean_pointer; 64 unsigned int tx_pointer; 65 unsigned int tx_pending; 66 67 spinlock_t tx_lock; 68 69 struct net_device *netdev; 70 struct device *dev; 71 struct napi_struct napi; 72 73 struct mii_bus *mii_bus; 74 int phy_irq[PHY_MAX_ADDR]; 75 struct phy_device *phydev; 76 int old_speed; 77 }; 78 79 static int ftgmac100_alloc_rx_page(struct ftgmac100 *priv, 80 struct ftgmac100_rxdes *rxdes, gfp_t gfp); 81 82 /****************************************************************************** 83 * internal functions (hardware register access) 84 *****************************************************************************/ 85 #define INT_MASK_ALL_ENABLED (FTGMAC100_INT_RPKT_LOST | \ 86 FTGMAC100_INT_XPKT_ETH | \ 87 FTGMAC100_INT_XPKT_LOST | \ 88 FTGMAC100_INT_AHB_ERR | \ 89 FTGMAC100_INT_PHYSTS_CHG | \ 90 FTGMAC100_INT_RPKT_BUF | \ 91 FTGMAC100_INT_NO_RXBUF) 92 93 static void ftgmac100_set_rx_ring_base(struct ftgmac100 *priv, dma_addr_t addr) 94 { 95 iowrite32(addr, priv->base + FTGMAC100_OFFSET_RXR_BADR); 96 } 97 98 static void ftgmac100_set_rx_buffer_size(struct ftgmac100 *priv, 99 unsigned int size) 100 { 101 size = FTGMAC100_RBSR_SIZE(size); 102 iowrite32(size, priv->base + FTGMAC100_OFFSET_RBSR); 103 } 104 105 static void ftgmac100_set_normal_prio_tx_ring_base(struct ftgmac100 *priv, 106 dma_addr_t addr) 107 { 108 iowrite32(addr, priv->base + FTGMAC100_OFFSET_NPTXR_BADR); 109 } 110 111 static void ftgmac100_txdma_normal_prio_start_polling(struct ftgmac100 *priv) 112 { 113 iowrite32(1, priv->base + FTGMAC100_OFFSET_NPTXPD); 114 } 115 116 static int ftgmac100_reset_hw(struct ftgmac100 *priv) 117 { 118 struct net_device *netdev = priv->netdev; 119 int i; 120 121 /* NOTE: reset clears all registers */ 122 iowrite32(FTGMAC100_MACCR_SW_RST, priv->base + FTGMAC100_OFFSET_MACCR); 123 for (i = 0; i < 5; i++) { 124 unsigned int maccr; 125 126 maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR); 127 if (!(maccr & FTGMAC100_MACCR_SW_RST)) 128 return 0; 129 130 udelay(1000); 131 } 132 133 netdev_err(netdev, "software reset failed\n"); 134 return -EIO; 135 } 136 137 static void ftgmac100_set_mac(struct ftgmac100 *priv, const unsigned char *mac) 138 { 139 unsigned int maddr = mac[0] << 8 | mac[1]; 140 unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5]; 141 142 iowrite32(maddr, priv->base + FTGMAC100_OFFSET_MAC_MADR); 143 iowrite32(laddr, priv->base + FTGMAC100_OFFSET_MAC_LADR); 144 } 145 146 static void ftgmac100_init_hw(struct ftgmac100 *priv) 147 { 148 /* setup ring buffer base registers */ 149 ftgmac100_set_rx_ring_base(priv, 150 priv->descs_dma_addr + 151 offsetof(struct ftgmac100_descs, rxdes)); 152 ftgmac100_set_normal_prio_tx_ring_base(priv, 153 priv->descs_dma_addr + 154 offsetof(struct ftgmac100_descs, txdes)); 155 156 ftgmac100_set_rx_buffer_size(priv, RX_BUF_SIZE); 157 158 iowrite32(FTGMAC100_APTC_RXPOLL_CNT(1), priv->base + FTGMAC100_OFFSET_APTC); 159 160 ftgmac100_set_mac(priv, priv->netdev->dev_addr); 161 } 162 163 #define MACCR_ENABLE_ALL (FTGMAC100_MACCR_TXDMA_EN | \ 164 FTGMAC100_MACCR_RXDMA_EN | \ 165 FTGMAC100_MACCR_TXMAC_EN | \ 166 FTGMAC100_MACCR_RXMAC_EN | \ 167 FTGMAC100_MACCR_FULLDUP | \ 168 FTGMAC100_MACCR_CRC_APD | \ 169 FTGMAC100_MACCR_RX_RUNT | \ 170 FTGMAC100_MACCR_RX_BROADPKT) 171 172 static void ftgmac100_start_hw(struct ftgmac100 *priv, int speed) 173 { 174 int maccr = MACCR_ENABLE_ALL; 175 176 switch (speed) { 177 default: 178 case 10: 179 break; 180 181 case 100: 182 maccr |= FTGMAC100_MACCR_FAST_MODE; 183 break; 184 185 case 1000: 186 maccr |= FTGMAC100_MACCR_GIGA_MODE; 187 break; 188 } 189 190 iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR); 191 } 192 193 static void ftgmac100_stop_hw(struct ftgmac100 *priv) 194 { 195 iowrite32(0, priv->base + FTGMAC100_OFFSET_MACCR); 196 } 197 198 /****************************************************************************** 199 * internal functions (receive descriptor) 200 *****************************************************************************/ 201 static bool ftgmac100_rxdes_first_segment(struct ftgmac100_rxdes *rxdes) 202 { 203 return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_FRS); 204 } 205 206 static bool ftgmac100_rxdes_last_segment(struct ftgmac100_rxdes *rxdes) 207 { 208 return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_LRS); 209 } 210 211 static bool ftgmac100_rxdes_packet_ready(struct ftgmac100_rxdes *rxdes) 212 { 213 return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RXPKT_RDY); 214 } 215 216 static void ftgmac100_rxdes_set_dma_own(struct ftgmac100_rxdes *rxdes) 217 { 218 /* clear status bits */ 219 rxdes->rxdes0 &= cpu_to_le32(FTGMAC100_RXDES0_EDORR); 220 } 221 222 static bool ftgmac100_rxdes_rx_error(struct ftgmac100_rxdes *rxdes) 223 { 224 return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RX_ERR); 225 } 226 227 static bool ftgmac100_rxdes_crc_error(struct ftgmac100_rxdes *rxdes) 228 { 229 return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_CRC_ERR); 230 } 231 232 static bool ftgmac100_rxdes_frame_too_long(struct ftgmac100_rxdes *rxdes) 233 { 234 return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_FTL); 235 } 236 237 static bool ftgmac100_rxdes_runt(struct ftgmac100_rxdes *rxdes) 238 { 239 return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RUNT); 240 } 241 242 static bool ftgmac100_rxdes_odd_nibble(struct ftgmac100_rxdes *rxdes) 243 { 244 return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RX_ODD_NB); 245 } 246 247 static unsigned int ftgmac100_rxdes_data_length(struct ftgmac100_rxdes *rxdes) 248 { 249 return le32_to_cpu(rxdes->rxdes0) & FTGMAC100_RXDES0_VDBC; 250 } 251 252 static bool ftgmac100_rxdes_multicast(struct ftgmac100_rxdes *rxdes) 253 { 254 return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_MULTICAST); 255 } 256 257 static void ftgmac100_rxdes_set_end_of_ring(struct ftgmac100_rxdes *rxdes) 258 { 259 rxdes->rxdes0 |= cpu_to_le32(FTGMAC100_RXDES0_EDORR); 260 } 261 262 static void ftgmac100_rxdes_set_dma_addr(struct ftgmac100_rxdes *rxdes, 263 dma_addr_t addr) 264 { 265 rxdes->rxdes3 = cpu_to_le32(addr); 266 } 267 268 static dma_addr_t ftgmac100_rxdes_get_dma_addr(struct ftgmac100_rxdes *rxdes) 269 { 270 return le32_to_cpu(rxdes->rxdes3); 271 } 272 273 static bool ftgmac100_rxdes_is_tcp(struct ftgmac100_rxdes *rxdes) 274 { 275 return (rxdes->rxdes1 & cpu_to_le32(FTGMAC100_RXDES1_PROT_MASK)) == 276 cpu_to_le32(FTGMAC100_RXDES1_PROT_TCPIP); 277 } 278 279 static bool ftgmac100_rxdes_is_udp(struct ftgmac100_rxdes *rxdes) 280 { 281 return (rxdes->rxdes1 & cpu_to_le32(FTGMAC100_RXDES1_PROT_MASK)) == 282 cpu_to_le32(FTGMAC100_RXDES1_PROT_UDPIP); 283 } 284 285 static bool ftgmac100_rxdes_tcpcs_err(struct ftgmac100_rxdes *rxdes) 286 { 287 return rxdes->rxdes1 & cpu_to_le32(FTGMAC100_RXDES1_TCP_CHKSUM_ERR); 288 } 289 290 static bool ftgmac100_rxdes_udpcs_err(struct ftgmac100_rxdes *rxdes) 291 { 292 return rxdes->rxdes1 & cpu_to_le32(FTGMAC100_RXDES1_UDP_CHKSUM_ERR); 293 } 294 295 static bool ftgmac100_rxdes_ipcs_err(struct ftgmac100_rxdes *rxdes) 296 { 297 return rxdes->rxdes1 & cpu_to_le32(FTGMAC100_RXDES1_IP_CHKSUM_ERR); 298 } 299 300 /* 301 * rxdes2 is not used by hardware. We use it to keep track of page. 302 * Since hardware does not touch it, we can skip cpu_to_le32()/le32_to_cpu(). 303 */ 304 static void ftgmac100_rxdes_set_page(struct ftgmac100_rxdes *rxdes, struct page *page) 305 { 306 rxdes->rxdes2 = (unsigned int)page; 307 } 308 309 static struct page *ftgmac100_rxdes_get_page(struct ftgmac100_rxdes *rxdes) 310 { 311 return (struct page *)rxdes->rxdes2; 312 } 313 314 /****************************************************************************** 315 * internal functions (receive) 316 *****************************************************************************/ 317 static int ftgmac100_next_rx_pointer(int pointer) 318 { 319 return (pointer + 1) & (RX_QUEUE_ENTRIES - 1); 320 } 321 322 static void ftgmac100_rx_pointer_advance(struct ftgmac100 *priv) 323 { 324 priv->rx_pointer = ftgmac100_next_rx_pointer(priv->rx_pointer); 325 } 326 327 static struct ftgmac100_rxdes *ftgmac100_current_rxdes(struct ftgmac100 *priv) 328 { 329 return &priv->descs->rxdes[priv->rx_pointer]; 330 } 331 332 static struct ftgmac100_rxdes * 333 ftgmac100_rx_locate_first_segment(struct ftgmac100 *priv) 334 { 335 struct ftgmac100_rxdes *rxdes = ftgmac100_current_rxdes(priv); 336 337 while (ftgmac100_rxdes_packet_ready(rxdes)) { 338 if (ftgmac100_rxdes_first_segment(rxdes)) 339 return rxdes; 340 341 ftgmac100_rxdes_set_dma_own(rxdes); 342 ftgmac100_rx_pointer_advance(priv); 343 rxdes = ftgmac100_current_rxdes(priv); 344 } 345 346 return NULL; 347 } 348 349 static bool ftgmac100_rx_packet_error(struct ftgmac100 *priv, 350 struct ftgmac100_rxdes *rxdes) 351 { 352 struct net_device *netdev = priv->netdev; 353 bool error = false; 354 355 if (unlikely(ftgmac100_rxdes_rx_error(rxdes))) { 356 if (net_ratelimit()) 357 netdev_info(netdev, "rx err\n"); 358 359 netdev->stats.rx_errors++; 360 error = true; 361 } 362 363 if (unlikely(ftgmac100_rxdes_crc_error(rxdes))) { 364 if (net_ratelimit()) 365 netdev_info(netdev, "rx crc err\n"); 366 367 netdev->stats.rx_crc_errors++; 368 error = true; 369 } else if (unlikely(ftgmac100_rxdes_ipcs_err(rxdes))) { 370 if (net_ratelimit()) 371 netdev_info(netdev, "rx IP checksum err\n"); 372 373 error = true; 374 } 375 376 if (unlikely(ftgmac100_rxdes_frame_too_long(rxdes))) { 377 if (net_ratelimit()) 378 netdev_info(netdev, "rx frame too long\n"); 379 380 netdev->stats.rx_length_errors++; 381 error = true; 382 } else if (unlikely(ftgmac100_rxdes_runt(rxdes))) { 383 if (net_ratelimit()) 384 netdev_info(netdev, "rx runt\n"); 385 386 netdev->stats.rx_length_errors++; 387 error = true; 388 } else if (unlikely(ftgmac100_rxdes_odd_nibble(rxdes))) { 389 if (net_ratelimit()) 390 netdev_info(netdev, "rx odd nibble\n"); 391 392 netdev->stats.rx_length_errors++; 393 error = true; 394 } 395 396 return error; 397 } 398 399 static void ftgmac100_rx_drop_packet(struct ftgmac100 *priv) 400 { 401 struct net_device *netdev = priv->netdev; 402 struct ftgmac100_rxdes *rxdes = ftgmac100_current_rxdes(priv); 403 bool done = false; 404 405 if (net_ratelimit()) 406 netdev_dbg(netdev, "drop packet %p\n", rxdes); 407 408 do { 409 if (ftgmac100_rxdes_last_segment(rxdes)) 410 done = true; 411 412 ftgmac100_rxdes_set_dma_own(rxdes); 413 ftgmac100_rx_pointer_advance(priv); 414 rxdes = ftgmac100_current_rxdes(priv); 415 } while (!done && ftgmac100_rxdes_packet_ready(rxdes)); 416 417 netdev->stats.rx_dropped++; 418 } 419 420 static bool ftgmac100_rx_packet(struct ftgmac100 *priv, int *processed) 421 { 422 struct net_device *netdev = priv->netdev; 423 struct ftgmac100_rxdes *rxdes; 424 struct sk_buff *skb; 425 bool done = false; 426 427 rxdes = ftgmac100_rx_locate_first_segment(priv); 428 if (!rxdes) 429 return false; 430 431 if (unlikely(ftgmac100_rx_packet_error(priv, rxdes))) { 432 ftgmac100_rx_drop_packet(priv); 433 return true; 434 } 435 436 /* start processing */ 437 skb = netdev_alloc_skb_ip_align(netdev, 128); 438 if (unlikely(!skb)) { 439 if (net_ratelimit()) 440 netdev_err(netdev, "rx skb alloc failed\n"); 441 442 ftgmac100_rx_drop_packet(priv); 443 return true; 444 } 445 446 if (unlikely(ftgmac100_rxdes_multicast(rxdes))) 447 netdev->stats.multicast++; 448 449 /* 450 * It seems that HW does checksum incorrectly with fragmented packets, 451 * so we are conservative here - if HW checksum error, let software do 452 * the checksum again. 453 */ 454 if ((ftgmac100_rxdes_is_tcp(rxdes) && !ftgmac100_rxdes_tcpcs_err(rxdes)) || 455 (ftgmac100_rxdes_is_udp(rxdes) && !ftgmac100_rxdes_udpcs_err(rxdes))) 456 skb->ip_summed = CHECKSUM_UNNECESSARY; 457 458 do { 459 dma_addr_t map = ftgmac100_rxdes_get_dma_addr(rxdes); 460 struct page *page = ftgmac100_rxdes_get_page(rxdes); 461 unsigned int size; 462 463 dma_unmap_page(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE); 464 465 size = ftgmac100_rxdes_data_length(rxdes); 466 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags, page, 0, size); 467 468 skb->len += size; 469 skb->data_len += size; 470 skb->truesize += PAGE_SIZE; 471 472 if (ftgmac100_rxdes_last_segment(rxdes)) 473 done = true; 474 475 ftgmac100_alloc_rx_page(priv, rxdes, GFP_ATOMIC); 476 477 ftgmac100_rx_pointer_advance(priv); 478 rxdes = ftgmac100_current_rxdes(priv); 479 } while (!done); 480 481 if (skb->len <= 64) 482 skb->truesize -= PAGE_SIZE; 483 __pskb_pull_tail(skb, min(skb->len, 64U)); 484 skb->protocol = eth_type_trans(skb, netdev); 485 486 netdev->stats.rx_packets++; 487 netdev->stats.rx_bytes += skb->len; 488 489 /* push packet to protocol stack */ 490 napi_gro_receive(&priv->napi, skb); 491 492 (*processed)++; 493 return true; 494 } 495 496 /****************************************************************************** 497 * internal functions (transmit descriptor) 498 *****************************************************************************/ 499 static void ftgmac100_txdes_reset(struct ftgmac100_txdes *txdes) 500 { 501 /* clear all except end of ring bit */ 502 txdes->txdes0 &= cpu_to_le32(FTGMAC100_TXDES0_EDOTR); 503 txdes->txdes1 = 0; 504 txdes->txdes2 = 0; 505 txdes->txdes3 = 0; 506 } 507 508 static bool ftgmac100_txdes_owned_by_dma(struct ftgmac100_txdes *txdes) 509 { 510 return txdes->txdes0 & cpu_to_le32(FTGMAC100_TXDES0_TXDMA_OWN); 511 } 512 513 static void ftgmac100_txdes_set_dma_own(struct ftgmac100_txdes *txdes) 514 { 515 /* 516 * Make sure dma own bit will not be set before any other 517 * descriptor fields. 518 */ 519 wmb(); 520 txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_TXDMA_OWN); 521 } 522 523 static void ftgmac100_txdes_set_end_of_ring(struct ftgmac100_txdes *txdes) 524 { 525 txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_EDOTR); 526 } 527 528 static void ftgmac100_txdes_set_first_segment(struct ftgmac100_txdes *txdes) 529 { 530 txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_FTS); 531 } 532 533 static void ftgmac100_txdes_set_last_segment(struct ftgmac100_txdes *txdes) 534 { 535 txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_LTS); 536 } 537 538 static void ftgmac100_txdes_set_buffer_size(struct ftgmac100_txdes *txdes, 539 unsigned int len) 540 { 541 txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_TXBUF_SIZE(len)); 542 } 543 544 static void ftgmac100_txdes_set_txint(struct ftgmac100_txdes *txdes) 545 { 546 txdes->txdes1 |= cpu_to_le32(FTGMAC100_TXDES1_TXIC); 547 } 548 549 static void ftgmac100_txdes_set_tcpcs(struct ftgmac100_txdes *txdes) 550 { 551 txdes->txdes1 |= cpu_to_le32(FTGMAC100_TXDES1_TCP_CHKSUM); 552 } 553 554 static void ftgmac100_txdes_set_udpcs(struct ftgmac100_txdes *txdes) 555 { 556 txdes->txdes1 |= cpu_to_le32(FTGMAC100_TXDES1_UDP_CHKSUM); 557 } 558 559 static void ftgmac100_txdes_set_ipcs(struct ftgmac100_txdes *txdes) 560 { 561 txdes->txdes1 |= cpu_to_le32(FTGMAC100_TXDES1_IP_CHKSUM); 562 } 563 564 static void ftgmac100_txdes_set_dma_addr(struct ftgmac100_txdes *txdes, 565 dma_addr_t addr) 566 { 567 txdes->txdes3 = cpu_to_le32(addr); 568 } 569 570 static dma_addr_t ftgmac100_txdes_get_dma_addr(struct ftgmac100_txdes *txdes) 571 { 572 return le32_to_cpu(txdes->txdes3); 573 } 574 575 /* 576 * txdes2 is not used by hardware. We use it to keep track of socket buffer. 577 * Since hardware does not touch it, we can skip cpu_to_le32()/le32_to_cpu(). 578 */ 579 static void ftgmac100_txdes_set_skb(struct ftgmac100_txdes *txdes, 580 struct sk_buff *skb) 581 { 582 txdes->txdes2 = (unsigned int)skb; 583 } 584 585 static struct sk_buff *ftgmac100_txdes_get_skb(struct ftgmac100_txdes *txdes) 586 { 587 return (struct sk_buff *)txdes->txdes2; 588 } 589 590 /****************************************************************************** 591 * internal functions (transmit) 592 *****************************************************************************/ 593 static int ftgmac100_next_tx_pointer(int pointer) 594 { 595 return (pointer + 1) & (TX_QUEUE_ENTRIES - 1); 596 } 597 598 static void ftgmac100_tx_pointer_advance(struct ftgmac100 *priv) 599 { 600 priv->tx_pointer = ftgmac100_next_tx_pointer(priv->tx_pointer); 601 } 602 603 static void ftgmac100_tx_clean_pointer_advance(struct ftgmac100 *priv) 604 { 605 priv->tx_clean_pointer = ftgmac100_next_tx_pointer(priv->tx_clean_pointer); 606 } 607 608 static struct ftgmac100_txdes *ftgmac100_current_txdes(struct ftgmac100 *priv) 609 { 610 return &priv->descs->txdes[priv->tx_pointer]; 611 } 612 613 static struct ftgmac100_txdes * 614 ftgmac100_current_clean_txdes(struct ftgmac100 *priv) 615 { 616 return &priv->descs->txdes[priv->tx_clean_pointer]; 617 } 618 619 static bool ftgmac100_tx_complete_packet(struct ftgmac100 *priv) 620 { 621 struct net_device *netdev = priv->netdev; 622 struct ftgmac100_txdes *txdes; 623 struct sk_buff *skb; 624 dma_addr_t map; 625 626 if (priv->tx_pending == 0) 627 return false; 628 629 txdes = ftgmac100_current_clean_txdes(priv); 630 631 if (ftgmac100_txdes_owned_by_dma(txdes)) 632 return false; 633 634 skb = ftgmac100_txdes_get_skb(txdes); 635 map = ftgmac100_txdes_get_dma_addr(txdes); 636 637 netdev->stats.tx_packets++; 638 netdev->stats.tx_bytes += skb->len; 639 640 dma_unmap_single(priv->dev, map, skb_headlen(skb), DMA_TO_DEVICE); 641 642 dev_kfree_skb(skb); 643 644 ftgmac100_txdes_reset(txdes); 645 646 ftgmac100_tx_clean_pointer_advance(priv); 647 648 spin_lock(&priv->tx_lock); 649 priv->tx_pending--; 650 spin_unlock(&priv->tx_lock); 651 netif_wake_queue(netdev); 652 653 return true; 654 } 655 656 static void ftgmac100_tx_complete(struct ftgmac100 *priv) 657 { 658 while (ftgmac100_tx_complete_packet(priv)) 659 ; 660 } 661 662 static int ftgmac100_xmit(struct ftgmac100 *priv, struct sk_buff *skb, 663 dma_addr_t map) 664 { 665 struct net_device *netdev = priv->netdev; 666 struct ftgmac100_txdes *txdes; 667 unsigned int len = (skb->len < ETH_ZLEN) ? ETH_ZLEN : skb->len; 668 669 txdes = ftgmac100_current_txdes(priv); 670 ftgmac100_tx_pointer_advance(priv); 671 672 /* setup TX descriptor */ 673 ftgmac100_txdes_set_skb(txdes, skb); 674 ftgmac100_txdes_set_dma_addr(txdes, map); 675 ftgmac100_txdes_set_buffer_size(txdes, len); 676 677 ftgmac100_txdes_set_first_segment(txdes); 678 ftgmac100_txdes_set_last_segment(txdes); 679 ftgmac100_txdes_set_txint(txdes); 680 if (skb->ip_summed == CHECKSUM_PARTIAL) { 681 __be16 protocol = skb->protocol; 682 683 if (protocol == cpu_to_be16(ETH_P_IP)) { 684 u8 ip_proto = ip_hdr(skb)->protocol; 685 686 ftgmac100_txdes_set_ipcs(txdes); 687 if (ip_proto == IPPROTO_TCP) 688 ftgmac100_txdes_set_tcpcs(txdes); 689 else if (ip_proto == IPPROTO_UDP) 690 ftgmac100_txdes_set_udpcs(txdes); 691 } 692 } 693 694 spin_lock(&priv->tx_lock); 695 priv->tx_pending++; 696 if (priv->tx_pending == TX_QUEUE_ENTRIES) 697 netif_stop_queue(netdev); 698 699 /* start transmit */ 700 ftgmac100_txdes_set_dma_own(txdes); 701 spin_unlock(&priv->tx_lock); 702 703 ftgmac100_txdma_normal_prio_start_polling(priv); 704 705 return NETDEV_TX_OK; 706 } 707 708 /****************************************************************************** 709 * internal functions (buffer) 710 *****************************************************************************/ 711 static int ftgmac100_alloc_rx_page(struct ftgmac100 *priv, 712 struct ftgmac100_rxdes *rxdes, gfp_t gfp) 713 { 714 struct net_device *netdev = priv->netdev; 715 struct page *page; 716 dma_addr_t map; 717 718 page = alloc_page(gfp); 719 if (!page) { 720 if (net_ratelimit()) 721 netdev_err(netdev, "failed to allocate rx page\n"); 722 return -ENOMEM; 723 } 724 725 map = dma_map_page(priv->dev, page, 0, RX_BUF_SIZE, DMA_FROM_DEVICE); 726 if (unlikely(dma_mapping_error(priv->dev, map))) { 727 if (net_ratelimit()) 728 netdev_err(netdev, "failed to map rx page\n"); 729 __free_page(page); 730 return -ENOMEM; 731 } 732 733 ftgmac100_rxdes_set_page(rxdes, page); 734 ftgmac100_rxdes_set_dma_addr(rxdes, map); 735 ftgmac100_rxdes_set_dma_own(rxdes); 736 return 0; 737 } 738 739 static void ftgmac100_free_buffers(struct ftgmac100 *priv) 740 { 741 int i; 742 743 for (i = 0; i < RX_QUEUE_ENTRIES; i++) { 744 struct ftgmac100_rxdes *rxdes = &priv->descs->rxdes[i]; 745 struct page *page = ftgmac100_rxdes_get_page(rxdes); 746 dma_addr_t map = ftgmac100_rxdes_get_dma_addr(rxdes); 747 748 if (!page) 749 continue; 750 751 dma_unmap_page(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE); 752 __free_page(page); 753 } 754 755 for (i = 0; i < TX_QUEUE_ENTRIES; i++) { 756 struct ftgmac100_txdes *txdes = &priv->descs->txdes[i]; 757 struct sk_buff *skb = ftgmac100_txdes_get_skb(txdes); 758 dma_addr_t map = ftgmac100_txdes_get_dma_addr(txdes); 759 760 if (!skb) 761 continue; 762 763 dma_unmap_single(priv->dev, map, skb_headlen(skb), DMA_TO_DEVICE); 764 dev_kfree_skb(skb); 765 } 766 767 dma_free_coherent(priv->dev, sizeof(struct ftgmac100_descs), 768 priv->descs, priv->descs_dma_addr); 769 } 770 771 static int ftgmac100_alloc_buffers(struct ftgmac100 *priv) 772 { 773 int i; 774 775 priv->descs = dma_alloc_coherent(priv->dev, 776 sizeof(struct ftgmac100_descs), 777 &priv->descs_dma_addr, GFP_KERNEL); 778 if (!priv->descs) 779 return -ENOMEM; 780 781 memset(priv->descs, 0, sizeof(struct ftgmac100_descs)); 782 783 /* initialize RX ring */ 784 ftgmac100_rxdes_set_end_of_ring(&priv->descs->rxdes[RX_QUEUE_ENTRIES - 1]); 785 786 for (i = 0; i < RX_QUEUE_ENTRIES; i++) { 787 struct ftgmac100_rxdes *rxdes = &priv->descs->rxdes[i]; 788 789 if (ftgmac100_alloc_rx_page(priv, rxdes, GFP_KERNEL)) 790 goto err; 791 } 792 793 /* initialize TX ring */ 794 ftgmac100_txdes_set_end_of_ring(&priv->descs->txdes[TX_QUEUE_ENTRIES - 1]); 795 return 0; 796 797 err: 798 ftgmac100_free_buffers(priv); 799 return -ENOMEM; 800 } 801 802 /****************************************************************************** 803 * internal functions (mdio) 804 *****************************************************************************/ 805 static void ftgmac100_adjust_link(struct net_device *netdev) 806 { 807 struct ftgmac100 *priv = netdev_priv(netdev); 808 struct phy_device *phydev = priv->phydev; 809 int ier; 810 811 if (phydev->speed == priv->old_speed) 812 return; 813 814 priv->old_speed = phydev->speed; 815 816 ier = ioread32(priv->base + FTGMAC100_OFFSET_IER); 817 818 /* disable all interrupts */ 819 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER); 820 821 netif_stop_queue(netdev); 822 ftgmac100_stop_hw(priv); 823 824 netif_start_queue(netdev); 825 ftgmac100_init_hw(priv); 826 ftgmac100_start_hw(priv, phydev->speed); 827 828 /* re-enable interrupts */ 829 iowrite32(ier, priv->base + FTGMAC100_OFFSET_IER); 830 } 831 832 static int ftgmac100_mii_probe(struct ftgmac100 *priv) 833 { 834 struct net_device *netdev = priv->netdev; 835 struct phy_device *phydev = NULL; 836 int i; 837 838 /* search for connect PHY device */ 839 for (i = 0; i < PHY_MAX_ADDR; i++) { 840 struct phy_device *tmp = priv->mii_bus->phy_map[i]; 841 842 if (tmp) { 843 phydev = tmp; 844 break; 845 } 846 } 847 848 /* now we are supposed to have a proper phydev, to attach to... */ 849 if (!phydev) { 850 netdev_info(netdev, "%s: no PHY found\n", netdev->name); 851 return -ENODEV; 852 } 853 854 phydev = phy_connect(netdev, dev_name(&phydev->dev), 855 &ftgmac100_adjust_link, 0, 856 PHY_INTERFACE_MODE_GMII); 857 858 if (IS_ERR(phydev)) { 859 netdev_err(netdev, "%s: Could not attach to PHY\n", netdev->name); 860 return PTR_ERR(phydev); 861 } 862 863 priv->phydev = phydev; 864 return 0; 865 } 866 867 /****************************************************************************** 868 * struct mii_bus functions 869 *****************************************************************************/ 870 static int ftgmac100_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum) 871 { 872 struct net_device *netdev = bus->priv; 873 struct ftgmac100 *priv = netdev_priv(netdev); 874 unsigned int phycr; 875 int i; 876 877 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR); 878 879 /* preserve MDC cycle threshold */ 880 phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK; 881 882 phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) | 883 FTGMAC100_PHYCR_REGAD(regnum) | 884 FTGMAC100_PHYCR_MIIRD; 885 886 iowrite32(phycr, priv->base + FTGMAC100_OFFSET_PHYCR); 887 888 for (i = 0; i < 10; i++) { 889 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR); 890 891 if ((phycr & FTGMAC100_PHYCR_MIIRD) == 0) { 892 int data; 893 894 data = ioread32(priv->base + FTGMAC100_OFFSET_PHYDATA); 895 return FTGMAC100_PHYDATA_MIIRDATA(data); 896 } 897 898 udelay(100); 899 } 900 901 netdev_err(netdev, "mdio read timed out\n"); 902 return -EIO; 903 } 904 905 static int ftgmac100_mdiobus_write(struct mii_bus *bus, int phy_addr, 906 int regnum, u16 value) 907 { 908 struct net_device *netdev = bus->priv; 909 struct ftgmac100 *priv = netdev_priv(netdev); 910 unsigned int phycr; 911 int data; 912 int i; 913 914 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR); 915 916 /* preserve MDC cycle threshold */ 917 phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK; 918 919 phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) | 920 FTGMAC100_PHYCR_REGAD(regnum) | 921 FTGMAC100_PHYCR_MIIWR; 922 923 data = FTGMAC100_PHYDATA_MIIWDATA(value); 924 925 iowrite32(data, priv->base + FTGMAC100_OFFSET_PHYDATA); 926 iowrite32(phycr, priv->base + FTGMAC100_OFFSET_PHYCR); 927 928 for (i = 0; i < 10; i++) { 929 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR); 930 931 if ((phycr & FTGMAC100_PHYCR_MIIWR) == 0) 932 return 0; 933 934 udelay(100); 935 } 936 937 netdev_err(netdev, "mdio write timed out\n"); 938 return -EIO; 939 } 940 941 static int ftgmac100_mdiobus_reset(struct mii_bus *bus) 942 { 943 return 0; 944 } 945 946 /****************************************************************************** 947 * struct ethtool_ops functions 948 *****************************************************************************/ 949 static void ftgmac100_get_drvinfo(struct net_device *netdev, 950 struct ethtool_drvinfo *info) 951 { 952 strcpy(info->driver, DRV_NAME); 953 strcpy(info->version, DRV_VERSION); 954 strcpy(info->bus_info, dev_name(&netdev->dev)); 955 } 956 957 static int ftgmac100_get_settings(struct net_device *netdev, 958 struct ethtool_cmd *cmd) 959 { 960 struct ftgmac100 *priv = netdev_priv(netdev); 961 962 return phy_ethtool_gset(priv->phydev, cmd); 963 } 964 965 static int ftgmac100_set_settings(struct net_device *netdev, 966 struct ethtool_cmd *cmd) 967 { 968 struct ftgmac100 *priv = netdev_priv(netdev); 969 970 return phy_ethtool_sset(priv->phydev, cmd); 971 } 972 973 static const struct ethtool_ops ftgmac100_ethtool_ops = { 974 .set_settings = ftgmac100_set_settings, 975 .get_settings = ftgmac100_get_settings, 976 .get_drvinfo = ftgmac100_get_drvinfo, 977 .get_link = ethtool_op_get_link, 978 }; 979 980 /****************************************************************************** 981 * interrupt handler 982 *****************************************************************************/ 983 static irqreturn_t ftgmac100_interrupt(int irq, void *dev_id) 984 { 985 struct net_device *netdev = dev_id; 986 struct ftgmac100 *priv = netdev_priv(netdev); 987 988 if (likely(netif_running(netdev))) { 989 /* Disable interrupts for polling */ 990 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER); 991 napi_schedule(&priv->napi); 992 } 993 994 return IRQ_HANDLED; 995 } 996 997 /****************************************************************************** 998 * struct napi_struct functions 999 *****************************************************************************/ 1000 static int ftgmac100_poll(struct napi_struct *napi, int budget) 1001 { 1002 struct ftgmac100 *priv = container_of(napi, struct ftgmac100, napi); 1003 struct net_device *netdev = priv->netdev; 1004 unsigned int status; 1005 bool completed = true; 1006 int rx = 0; 1007 1008 status = ioread32(priv->base + FTGMAC100_OFFSET_ISR); 1009 iowrite32(status, priv->base + FTGMAC100_OFFSET_ISR); 1010 1011 if (status & (FTGMAC100_INT_RPKT_BUF | FTGMAC100_INT_NO_RXBUF)) { 1012 /* 1013 * FTGMAC100_INT_RPKT_BUF: 1014 * RX DMA has received packets into RX buffer successfully 1015 * 1016 * FTGMAC100_INT_NO_RXBUF: 1017 * RX buffer unavailable 1018 */ 1019 bool retry; 1020 1021 do { 1022 retry = ftgmac100_rx_packet(priv, &rx); 1023 } while (retry && rx < budget); 1024 1025 if (retry && rx == budget) 1026 completed = false; 1027 } 1028 1029 if (status & (FTGMAC100_INT_XPKT_ETH | FTGMAC100_INT_XPKT_LOST)) { 1030 /* 1031 * FTGMAC100_INT_XPKT_ETH: 1032 * packet transmitted to ethernet successfully 1033 * 1034 * FTGMAC100_INT_XPKT_LOST: 1035 * packet transmitted to ethernet lost due to late 1036 * collision or excessive collision 1037 */ 1038 ftgmac100_tx_complete(priv); 1039 } 1040 1041 if (status & (FTGMAC100_INT_NO_RXBUF | FTGMAC100_INT_RPKT_LOST | 1042 FTGMAC100_INT_AHB_ERR | FTGMAC100_INT_PHYSTS_CHG)) { 1043 if (net_ratelimit()) 1044 netdev_info(netdev, "[ISR] = 0x%x: %s%s%s%s\n", status, 1045 status & FTGMAC100_INT_NO_RXBUF ? "NO_RXBUF " : "", 1046 status & FTGMAC100_INT_RPKT_LOST ? "RPKT_LOST " : "", 1047 status & FTGMAC100_INT_AHB_ERR ? "AHB_ERR " : "", 1048 status & FTGMAC100_INT_PHYSTS_CHG ? "PHYSTS_CHG" : ""); 1049 1050 if (status & FTGMAC100_INT_NO_RXBUF) { 1051 /* RX buffer unavailable */ 1052 netdev->stats.rx_over_errors++; 1053 } 1054 1055 if (status & FTGMAC100_INT_RPKT_LOST) { 1056 /* received packet lost due to RX FIFO full */ 1057 netdev->stats.rx_fifo_errors++; 1058 } 1059 } 1060 1061 if (completed) { 1062 napi_complete(napi); 1063 1064 /* enable all interrupts */ 1065 iowrite32(INT_MASK_ALL_ENABLED, priv->base + FTGMAC100_OFFSET_IER); 1066 } 1067 1068 return rx; 1069 } 1070 1071 /****************************************************************************** 1072 * struct net_device_ops functions 1073 *****************************************************************************/ 1074 static int ftgmac100_open(struct net_device *netdev) 1075 { 1076 struct ftgmac100 *priv = netdev_priv(netdev); 1077 int err; 1078 1079 err = ftgmac100_alloc_buffers(priv); 1080 if (err) { 1081 netdev_err(netdev, "failed to allocate buffers\n"); 1082 goto err_alloc; 1083 } 1084 1085 err = request_irq(priv->irq, ftgmac100_interrupt, 0, netdev->name, netdev); 1086 if (err) { 1087 netdev_err(netdev, "failed to request irq %d\n", priv->irq); 1088 goto err_irq; 1089 } 1090 1091 priv->rx_pointer = 0; 1092 priv->tx_clean_pointer = 0; 1093 priv->tx_pointer = 0; 1094 priv->tx_pending = 0; 1095 1096 err = ftgmac100_reset_hw(priv); 1097 if (err) 1098 goto err_hw; 1099 1100 ftgmac100_init_hw(priv); 1101 ftgmac100_start_hw(priv, 10); 1102 1103 phy_start(priv->phydev); 1104 1105 napi_enable(&priv->napi); 1106 netif_start_queue(netdev); 1107 1108 /* enable all interrupts */ 1109 iowrite32(INT_MASK_ALL_ENABLED, priv->base + FTGMAC100_OFFSET_IER); 1110 return 0; 1111 1112 err_hw: 1113 free_irq(priv->irq, netdev); 1114 err_irq: 1115 ftgmac100_free_buffers(priv); 1116 err_alloc: 1117 return err; 1118 } 1119 1120 static int ftgmac100_stop(struct net_device *netdev) 1121 { 1122 struct ftgmac100 *priv = netdev_priv(netdev); 1123 1124 /* disable all interrupts */ 1125 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER); 1126 1127 netif_stop_queue(netdev); 1128 napi_disable(&priv->napi); 1129 phy_stop(priv->phydev); 1130 1131 ftgmac100_stop_hw(priv); 1132 free_irq(priv->irq, netdev); 1133 ftgmac100_free_buffers(priv); 1134 1135 return 0; 1136 } 1137 1138 static int ftgmac100_hard_start_xmit(struct sk_buff *skb, 1139 struct net_device *netdev) 1140 { 1141 struct ftgmac100 *priv = netdev_priv(netdev); 1142 dma_addr_t map; 1143 1144 if (unlikely(skb->len > MAX_PKT_SIZE)) { 1145 if (net_ratelimit()) 1146 netdev_dbg(netdev, "tx packet too big\n"); 1147 1148 netdev->stats.tx_dropped++; 1149 dev_kfree_skb(skb); 1150 return NETDEV_TX_OK; 1151 } 1152 1153 map = dma_map_single(priv->dev, skb->data, skb_headlen(skb), DMA_TO_DEVICE); 1154 if (unlikely(dma_mapping_error(priv->dev, map))) { 1155 /* drop packet */ 1156 if (net_ratelimit()) 1157 netdev_err(netdev, "map socket buffer failed\n"); 1158 1159 netdev->stats.tx_dropped++; 1160 dev_kfree_skb(skb); 1161 return NETDEV_TX_OK; 1162 } 1163 1164 return ftgmac100_xmit(priv, skb, map); 1165 } 1166 1167 /* optional */ 1168 static int ftgmac100_do_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 1169 { 1170 struct ftgmac100 *priv = netdev_priv(netdev); 1171 1172 return phy_mii_ioctl(priv->phydev, ifr, cmd); 1173 } 1174 1175 static const struct net_device_ops ftgmac100_netdev_ops = { 1176 .ndo_open = ftgmac100_open, 1177 .ndo_stop = ftgmac100_stop, 1178 .ndo_start_xmit = ftgmac100_hard_start_xmit, 1179 .ndo_set_mac_address = eth_mac_addr, 1180 .ndo_validate_addr = eth_validate_addr, 1181 .ndo_do_ioctl = ftgmac100_do_ioctl, 1182 }; 1183 1184 /****************************************************************************** 1185 * struct platform_driver functions 1186 *****************************************************************************/ 1187 static int ftgmac100_probe(struct platform_device *pdev) 1188 { 1189 struct resource *res; 1190 int irq; 1191 struct net_device *netdev; 1192 struct ftgmac100 *priv; 1193 int err; 1194 int i; 1195 1196 if (!pdev) 1197 return -ENODEV; 1198 1199 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1200 if (!res) 1201 return -ENXIO; 1202 1203 irq = platform_get_irq(pdev, 0); 1204 if (irq < 0) 1205 return irq; 1206 1207 /* setup net_device */ 1208 netdev = alloc_etherdev(sizeof(*priv)); 1209 if (!netdev) { 1210 err = -ENOMEM; 1211 goto err_alloc_etherdev; 1212 } 1213 1214 SET_NETDEV_DEV(netdev, &pdev->dev); 1215 1216 SET_ETHTOOL_OPS(netdev, &ftgmac100_ethtool_ops); 1217 netdev->netdev_ops = &ftgmac100_netdev_ops; 1218 netdev->features = NETIF_F_IP_CSUM | NETIF_F_GRO; 1219 1220 platform_set_drvdata(pdev, netdev); 1221 1222 /* setup private data */ 1223 priv = netdev_priv(netdev); 1224 priv->netdev = netdev; 1225 priv->dev = &pdev->dev; 1226 1227 spin_lock_init(&priv->tx_lock); 1228 1229 /* initialize NAPI */ 1230 netif_napi_add(netdev, &priv->napi, ftgmac100_poll, 64); 1231 1232 /* map io memory */ 1233 priv->res = request_mem_region(res->start, resource_size(res), 1234 dev_name(&pdev->dev)); 1235 if (!priv->res) { 1236 dev_err(&pdev->dev, "Could not reserve memory region\n"); 1237 err = -ENOMEM; 1238 goto err_req_mem; 1239 } 1240 1241 priv->base = ioremap(res->start, resource_size(res)); 1242 if (!priv->base) { 1243 dev_err(&pdev->dev, "Failed to ioremap ethernet registers\n"); 1244 err = -EIO; 1245 goto err_ioremap; 1246 } 1247 1248 priv->irq = irq; 1249 1250 /* initialize mdio bus */ 1251 priv->mii_bus = mdiobus_alloc(); 1252 if (!priv->mii_bus) { 1253 err = -EIO; 1254 goto err_alloc_mdiobus; 1255 } 1256 1257 priv->mii_bus->name = "ftgmac100_mdio"; 1258 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "ftgmac100_mii"); 1259 1260 priv->mii_bus->priv = netdev; 1261 priv->mii_bus->read = ftgmac100_mdiobus_read; 1262 priv->mii_bus->write = ftgmac100_mdiobus_write; 1263 priv->mii_bus->reset = ftgmac100_mdiobus_reset; 1264 priv->mii_bus->irq = priv->phy_irq; 1265 1266 for (i = 0; i < PHY_MAX_ADDR; i++) 1267 priv->mii_bus->irq[i] = PHY_POLL; 1268 1269 err = mdiobus_register(priv->mii_bus); 1270 if (err) { 1271 dev_err(&pdev->dev, "Cannot register MDIO bus!\n"); 1272 goto err_register_mdiobus; 1273 } 1274 1275 err = ftgmac100_mii_probe(priv); 1276 if (err) { 1277 dev_err(&pdev->dev, "MII Probe failed!\n"); 1278 goto err_mii_probe; 1279 } 1280 1281 /* register network device */ 1282 err = register_netdev(netdev); 1283 if (err) { 1284 dev_err(&pdev->dev, "Failed to register netdev\n"); 1285 goto err_register_netdev; 1286 } 1287 1288 netdev_info(netdev, "irq %d, mapped at %p\n", priv->irq, priv->base); 1289 1290 if (!is_valid_ether_addr(netdev->dev_addr)) { 1291 random_ether_addr(netdev->dev_addr); 1292 netdev_info(netdev, "generated random MAC address %pM\n", 1293 netdev->dev_addr); 1294 } 1295 1296 return 0; 1297 1298 err_register_netdev: 1299 phy_disconnect(priv->phydev); 1300 err_mii_probe: 1301 mdiobus_unregister(priv->mii_bus); 1302 err_register_mdiobus: 1303 mdiobus_free(priv->mii_bus); 1304 err_alloc_mdiobus: 1305 iounmap(priv->base); 1306 err_ioremap: 1307 release_resource(priv->res); 1308 err_req_mem: 1309 netif_napi_del(&priv->napi); 1310 platform_set_drvdata(pdev, NULL); 1311 free_netdev(netdev); 1312 err_alloc_etherdev: 1313 return err; 1314 } 1315 1316 static int __exit ftgmac100_remove(struct platform_device *pdev) 1317 { 1318 struct net_device *netdev; 1319 struct ftgmac100 *priv; 1320 1321 netdev = platform_get_drvdata(pdev); 1322 priv = netdev_priv(netdev); 1323 1324 unregister_netdev(netdev); 1325 1326 phy_disconnect(priv->phydev); 1327 mdiobus_unregister(priv->mii_bus); 1328 mdiobus_free(priv->mii_bus); 1329 1330 iounmap(priv->base); 1331 release_resource(priv->res); 1332 1333 netif_napi_del(&priv->napi); 1334 platform_set_drvdata(pdev, NULL); 1335 free_netdev(netdev); 1336 return 0; 1337 } 1338 1339 static struct platform_driver ftgmac100_driver = { 1340 .probe = ftgmac100_probe, 1341 .remove = __exit_p(ftgmac100_remove), 1342 .driver = { 1343 .name = DRV_NAME, 1344 .owner = THIS_MODULE, 1345 }, 1346 }; 1347 1348 /****************************************************************************** 1349 * initialization / finalization 1350 *****************************************************************************/ 1351 static int __init ftgmac100_init(void) 1352 { 1353 pr_info("Loading version " DRV_VERSION " ...\n"); 1354 return platform_driver_register(&ftgmac100_driver); 1355 } 1356 1357 static void __exit ftgmac100_exit(void) 1358 { 1359 platform_driver_unregister(&ftgmac100_driver); 1360 } 1361 1362 module_init(ftgmac100_init); 1363 module_exit(ftgmac100_exit); 1364 1365 MODULE_AUTHOR("Po-Yu Chuang <ratbert@faraday-tech.com>"); 1366 MODULE_DESCRIPTION("FTGMAC100 driver"); 1367 MODULE_LICENSE("GPL"); 1368