1 /* 2 * Faraday FTGMAC100 Gigabit Ethernet 3 * 4 * (C) Copyright 2009-2011 Faraday Technology 5 * Po-Yu Chuang <ratbert@faraday-tech.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 20 */ 21 22 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 23 24 #include <linux/dma-mapping.h> 25 #include <linux/etherdevice.h> 26 #include <linux/ethtool.h> 27 #include <linux/init.h> 28 #include <linux/interrupt.h> 29 #include <linux/io.h> 30 #include <linux/module.h> 31 #include <linux/netdevice.h> 32 #include <linux/phy.h> 33 #include <linux/platform_device.h> 34 #include <net/ip.h> 35 36 #include "ftgmac100.h" 37 38 #define DRV_NAME "ftgmac100" 39 #define DRV_VERSION "0.7" 40 41 #define RX_QUEUE_ENTRIES 256 /* must be power of 2 */ 42 #define TX_QUEUE_ENTRIES 512 /* must be power of 2 */ 43 44 #define MAX_PKT_SIZE 1518 45 #define RX_BUF_SIZE PAGE_SIZE /* must be smaller than 0x3fff */ 46 47 /****************************************************************************** 48 * private data 49 *****************************************************************************/ 50 struct ftgmac100_descs { 51 struct ftgmac100_rxdes rxdes[RX_QUEUE_ENTRIES]; 52 struct ftgmac100_txdes txdes[TX_QUEUE_ENTRIES]; 53 }; 54 55 struct ftgmac100 { 56 struct resource *res; 57 void __iomem *base; 58 int irq; 59 60 struct ftgmac100_descs *descs; 61 dma_addr_t descs_dma_addr; 62 63 unsigned int rx_pointer; 64 unsigned int tx_clean_pointer; 65 unsigned int tx_pointer; 66 unsigned int tx_pending; 67 68 spinlock_t tx_lock; 69 70 struct net_device *netdev; 71 struct device *dev; 72 struct napi_struct napi; 73 74 struct mii_bus *mii_bus; 75 int phy_irq[PHY_MAX_ADDR]; 76 struct phy_device *phydev; 77 int old_speed; 78 }; 79 80 static int ftgmac100_alloc_rx_page(struct ftgmac100 *priv, 81 struct ftgmac100_rxdes *rxdes, gfp_t gfp); 82 83 /****************************************************************************** 84 * internal functions (hardware register access) 85 *****************************************************************************/ 86 #define INT_MASK_ALL_ENABLED (FTGMAC100_INT_RPKT_LOST | \ 87 FTGMAC100_INT_XPKT_ETH | \ 88 FTGMAC100_INT_XPKT_LOST | \ 89 FTGMAC100_INT_AHB_ERR | \ 90 FTGMAC100_INT_PHYSTS_CHG | \ 91 FTGMAC100_INT_RPKT_BUF | \ 92 FTGMAC100_INT_NO_RXBUF) 93 94 static void ftgmac100_set_rx_ring_base(struct ftgmac100 *priv, dma_addr_t addr) 95 { 96 iowrite32(addr, priv->base + FTGMAC100_OFFSET_RXR_BADR); 97 } 98 99 static void ftgmac100_set_rx_buffer_size(struct ftgmac100 *priv, 100 unsigned int size) 101 { 102 size = FTGMAC100_RBSR_SIZE(size); 103 iowrite32(size, priv->base + FTGMAC100_OFFSET_RBSR); 104 } 105 106 static void ftgmac100_set_normal_prio_tx_ring_base(struct ftgmac100 *priv, 107 dma_addr_t addr) 108 { 109 iowrite32(addr, priv->base + FTGMAC100_OFFSET_NPTXR_BADR); 110 } 111 112 static void ftgmac100_txdma_normal_prio_start_polling(struct ftgmac100 *priv) 113 { 114 iowrite32(1, priv->base + FTGMAC100_OFFSET_NPTXPD); 115 } 116 117 static int ftgmac100_reset_hw(struct ftgmac100 *priv) 118 { 119 struct net_device *netdev = priv->netdev; 120 int i; 121 122 /* NOTE: reset clears all registers */ 123 iowrite32(FTGMAC100_MACCR_SW_RST, priv->base + FTGMAC100_OFFSET_MACCR); 124 for (i = 0; i < 5; i++) { 125 unsigned int maccr; 126 127 maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR); 128 if (!(maccr & FTGMAC100_MACCR_SW_RST)) 129 return 0; 130 131 udelay(1000); 132 } 133 134 netdev_err(netdev, "software reset failed\n"); 135 return -EIO; 136 } 137 138 static void ftgmac100_set_mac(struct ftgmac100 *priv, const unsigned char *mac) 139 { 140 unsigned int maddr = mac[0] << 8 | mac[1]; 141 unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5]; 142 143 iowrite32(maddr, priv->base + FTGMAC100_OFFSET_MAC_MADR); 144 iowrite32(laddr, priv->base + FTGMAC100_OFFSET_MAC_LADR); 145 } 146 147 static void ftgmac100_init_hw(struct ftgmac100 *priv) 148 { 149 /* setup ring buffer base registers */ 150 ftgmac100_set_rx_ring_base(priv, 151 priv->descs_dma_addr + 152 offsetof(struct ftgmac100_descs, rxdes)); 153 ftgmac100_set_normal_prio_tx_ring_base(priv, 154 priv->descs_dma_addr + 155 offsetof(struct ftgmac100_descs, txdes)); 156 157 ftgmac100_set_rx_buffer_size(priv, RX_BUF_SIZE); 158 159 iowrite32(FTGMAC100_APTC_RXPOLL_CNT(1), priv->base + FTGMAC100_OFFSET_APTC); 160 161 ftgmac100_set_mac(priv, priv->netdev->dev_addr); 162 } 163 164 #define MACCR_ENABLE_ALL (FTGMAC100_MACCR_TXDMA_EN | \ 165 FTGMAC100_MACCR_RXDMA_EN | \ 166 FTGMAC100_MACCR_TXMAC_EN | \ 167 FTGMAC100_MACCR_RXMAC_EN | \ 168 FTGMAC100_MACCR_FULLDUP | \ 169 FTGMAC100_MACCR_CRC_APD | \ 170 FTGMAC100_MACCR_RX_RUNT | \ 171 FTGMAC100_MACCR_RX_BROADPKT) 172 173 static void ftgmac100_start_hw(struct ftgmac100 *priv, int speed) 174 { 175 int maccr = MACCR_ENABLE_ALL; 176 177 switch (speed) { 178 default: 179 case 10: 180 break; 181 182 case 100: 183 maccr |= FTGMAC100_MACCR_FAST_MODE; 184 break; 185 186 case 1000: 187 maccr |= FTGMAC100_MACCR_GIGA_MODE; 188 break; 189 } 190 191 iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR); 192 } 193 194 static void ftgmac100_stop_hw(struct ftgmac100 *priv) 195 { 196 iowrite32(0, priv->base + FTGMAC100_OFFSET_MACCR); 197 } 198 199 /****************************************************************************** 200 * internal functions (receive descriptor) 201 *****************************************************************************/ 202 static bool ftgmac100_rxdes_first_segment(struct ftgmac100_rxdes *rxdes) 203 { 204 return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_FRS); 205 } 206 207 static bool ftgmac100_rxdes_last_segment(struct ftgmac100_rxdes *rxdes) 208 { 209 return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_LRS); 210 } 211 212 static bool ftgmac100_rxdes_packet_ready(struct ftgmac100_rxdes *rxdes) 213 { 214 return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RXPKT_RDY); 215 } 216 217 static void ftgmac100_rxdes_set_dma_own(struct ftgmac100_rxdes *rxdes) 218 { 219 /* clear status bits */ 220 rxdes->rxdes0 &= cpu_to_le32(FTGMAC100_RXDES0_EDORR); 221 } 222 223 static bool ftgmac100_rxdes_rx_error(struct ftgmac100_rxdes *rxdes) 224 { 225 return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RX_ERR); 226 } 227 228 static bool ftgmac100_rxdes_crc_error(struct ftgmac100_rxdes *rxdes) 229 { 230 return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_CRC_ERR); 231 } 232 233 static bool ftgmac100_rxdes_frame_too_long(struct ftgmac100_rxdes *rxdes) 234 { 235 return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_FTL); 236 } 237 238 static bool ftgmac100_rxdes_runt(struct ftgmac100_rxdes *rxdes) 239 { 240 return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RUNT); 241 } 242 243 static bool ftgmac100_rxdes_odd_nibble(struct ftgmac100_rxdes *rxdes) 244 { 245 return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RX_ODD_NB); 246 } 247 248 static unsigned int ftgmac100_rxdes_data_length(struct ftgmac100_rxdes *rxdes) 249 { 250 return le32_to_cpu(rxdes->rxdes0) & FTGMAC100_RXDES0_VDBC; 251 } 252 253 static bool ftgmac100_rxdes_multicast(struct ftgmac100_rxdes *rxdes) 254 { 255 return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_MULTICAST); 256 } 257 258 static void ftgmac100_rxdes_set_end_of_ring(struct ftgmac100_rxdes *rxdes) 259 { 260 rxdes->rxdes0 |= cpu_to_le32(FTGMAC100_RXDES0_EDORR); 261 } 262 263 static void ftgmac100_rxdes_set_dma_addr(struct ftgmac100_rxdes *rxdes, 264 dma_addr_t addr) 265 { 266 rxdes->rxdes3 = cpu_to_le32(addr); 267 } 268 269 static dma_addr_t ftgmac100_rxdes_get_dma_addr(struct ftgmac100_rxdes *rxdes) 270 { 271 return le32_to_cpu(rxdes->rxdes3); 272 } 273 274 static bool ftgmac100_rxdes_is_tcp(struct ftgmac100_rxdes *rxdes) 275 { 276 return (rxdes->rxdes1 & cpu_to_le32(FTGMAC100_RXDES1_PROT_MASK)) == 277 cpu_to_le32(FTGMAC100_RXDES1_PROT_TCPIP); 278 } 279 280 static bool ftgmac100_rxdes_is_udp(struct ftgmac100_rxdes *rxdes) 281 { 282 return (rxdes->rxdes1 & cpu_to_le32(FTGMAC100_RXDES1_PROT_MASK)) == 283 cpu_to_le32(FTGMAC100_RXDES1_PROT_UDPIP); 284 } 285 286 static bool ftgmac100_rxdes_tcpcs_err(struct ftgmac100_rxdes *rxdes) 287 { 288 return rxdes->rxdes1 & cpu_to_le32(FTGMAC100_RXDES1_TCP_CHKSUM_ERR); 289 } 290 291 static bool ftgmac100_rxdes_udpcs_err(struct ftgmac100_rxdes *rxdes) 292 { 293 return rxdes->rxdes1 & cpu_to_le32(FTGMAC100_RXDES1_UDP_CHKSUM_ERR); 294 } 295 296 static bool ftgmac100_rxdes_ipcs_err(struct ftgmac100_rxdes *rxdes) 297 { 298 return rxdes->rxdes1 & cpu_to_le32(FTGMAC100_RXDES1_IP_CHKSUM_ERR); 299 } 300 301 /* 302 * rxdes2 is not used by hardware. We use it to keep track of page. 303 * Since hardware does not touch it, we can skip cpu_to_le32()/le32_to_cpu(). 304 */ 305 static void ftgmac100_rxdes_set_page(struct ftgmac100_rxdes *rxdes, struct page *page) 306 { 307 rxdes->rxdes2 = (unsigned int)page; 308 } 309 310 static struct page *ftgmac100_rxdes_get_page(struct ftgmac100_rxdes *rxdes) 311 { 312 return (struct page *)rxdes->rxdes2; 313 } 314 315 /****************************************************************************** 316 * internal functions (receive) 317 *****************************************************************************/ 318 static int ftgmac100_next_rx_pointer(int pointer) 319 { 320 return (pointer + 1) & (RX_QUEUE_ENTRIES - 1); 321 } 322 323 static void ftgmac100_rx_pointer_advance(struct ftgmac100 *priv) 324 { 325 priv->rx_pointer = ftgmac100_next_rx_pointer(priv->rx_pointer); 326 } 327 328 static struct ftgmac100_rxdes *ftgmac100_current_rxdes(struct ftgmac100 *priv) 329 { 330 return &priv->descs->rxdes[priv->rx_pointer]; 331 } 332 333 static struct ftgmac100_rxdes * 334 ftgmac100_rx_locate_first_segment(struct ftgmac100 *priv) 335 { 336 struct ftgmac100_rxdes *rxdes = ftgmac100_current_rxdes(priv); 337 338 while (ftgmac100_rxdes_packet_ready(rxdes)) { 339 if (ftgmac100_rxdes_first_segment(rxdes)) 340 return rxdes; 341 342 ftgmac100_rxdes_set_dma_own(rxdes); 343 ftgmac100_rx_pointer_advance(priv); 344 rxdes = ftgmac100_current_rxdes(priv); 345 } 346 347 return NULL; 348 } 349 350 static bool ftgmac100_rx_packet_error(struct ftgmac100 *priv, 351 struct ftgmac100_rxdes *rxdes) 352 { 353 struct net_device *netdev = priv->netdev; 354 bool error = false; 355 356 if (unlikely(ftgmac100_rxdes_rx_error(rxdes))) { 357 if (net_ratelimit()) 358 netdev_info(netdev, "rx err\n"); 359 360 netdev->stats.rx_errors++; 361 error = true; 362 } 363 364 if (unlikely(ftgmac100_rxdes_crc_error(rxdes))) { 365 if (net_ratelimit()) 366 netdev_info(netdev, "rx crc err\n"); 367 368 netdev->stats.rx_crc_errors++; 369 error = true; 370 } else if (unlikely(ftgmac100_rxdes_ipcs_err(rxdes))) { 371 if (net_ratelimit()) 372 netdev_info(netdev, "rx IP checksum err\n"); 373 374 error = true; 375 } 376 377 if (unlikely(ftgmac100_rxdes_frame_too_long(rxdes))) { 378 if (net_ratelimit()) 379 netdev_info(netdev, "rx frame too long\n"); 380 381 netdev->stats.rx_length_errors++; 382 error = true; 383 } else if (unlikely(ftgmac100_rxdes_runt(rxdes))) { 384 if (net_ratelimit()) 385 netdev_info(netdev, "rx runt\n"); 386 387 netdev->stats.rx_length_errors++; 388 error = true; 389 } else if (unlikely(ftgmac100_rxdes_odd_nibble(rxdes))) { 390 if (net_ratelimit()) 391 netdev_info(netdev, "rx odd nibble\n"); 392 393 netdev->stats.rx_length_errors++; 394 error = true; 395 } 396 397 return error; 398 } 399 400 static void ftgmac100_rx_drop_packet(struct ftgmac100 *priv) 401 { 402 struct net_device *netdev = priv->netdev; 403 struct ftgmac100_rxdes *rxdes = ftgmac100_current_rxdes(priv); 404 bool done = false; 405 406 if (net_ratelimit()) 407 netdev_dbg(netdev, "drop packet %p\n", rxdes); 408 409 do { 410 if (ftgmac100_rxdes_last_segment(rxdes)) 411 done = true; 412 413 ftgmac100_rxdes_set_dma_own(rxdes); 414 ftgmac100_rx_pointer_advance(priv); 415 rxdes = ftgmac100_current_rxdes(priv); 416 } while (!done && ftgmac100_rxdes_packet_ready(rxdes)); 417 418 netdev->stats.rx_dropped++; 419 } 420 421 static bool ftgmac100_rx_packet(struct ftgmac100 *priv, int *processed) 422 { 423 struct net_device *netdev = priv->netdev; 424 struct ftgmac100_rxdes *rxdes; 425 struct sk_buff *skb; 426 bool done = false; 427 428 rxdes = ftgmac100_rx_locate_first_segment(priv); 429 if (!rxdes) 430 return false; 431 432 if (unlikely(ftgmac100_rx_packet_error(priv, rxdes))) { 433 ftgmac100_rx_drop_packet(priv); 434 return true; 435 } 436 437 /* start processing */ 438 skb = netdev_alloc_skb_ip_align(netdev, 128); 439 if (unlikely(!skb)) { 440 if (net_ratelimit()) 441 netdev_err(netdev, "rx skb alloc failed\n"); 442 443 ftgmac100_rx_drop_packet(priv); 444 return true; 445 } 446 447 if (unlikely(ftgmac100_rxdes_multicast(rxdes))) 448 netdev->stats.multicast++; 449 450 /* 451 * It seems that HW does checksum incorrectly with fragmented packets, 452 * so we are conservative here - if HW checksum error, let software do 453 * the checksum again. 454 */ 455 if ((ftgmac100_rxdes_is_tcp(rxdes) && !ftgmac100_rxdes_tcpcs_err(rxdes)) || 456 (ftgmac100_rxdes_is_udp(rxdes) && !ftgmac100_rxdes_udpcs_err(rxdes))) 457 skb->ip_summed = CHECKSUM_UNNECESSARY; 458 459 do { 460 dma_addr_t map = ftgmac100_rxdes_get_dma_addr(rxdes); 461 struct page *page = ftgmac100_rxdes_get_page(rxdes); 462 unsigned int size; 463 464 dma_unmap_page(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE); 465 466 size = ftgmac100_rxdes_data_length(rxdes); 467 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags, page, 0, size); 468 469 skb->len += size; 470 skb->data_len += size; 471 skb->truesize += PAGE_SIZE; 472 473 if (ftgmac100_rxdes_last_segment(rxdes)) 474 done = true; 475 476 ftgmac100_alloc_rx_page(priv, rxdes, GFP_ATOMIC); 477 478 ftgmac100_rx_pointer_advance(priv); 479 rxdes = ftgmac100_current_rxdes(priv); 480 } while (!done); 481 482 /* Small frames are copied into linear part of skb to free one page */ 483 if (skb->len <= 128) { 484 skb->truesize -= PAGE_SIZE; 485 __pskb_pull_tail(skb, skb->len); 486 } else { 487 /* We pull the minimum amount into linear part */ 488 __pskb_pull_tail(skb, ETH_HLEN); 489 } 490 skb->protocol = eth_type_trans(skb, netdev); 491 492 netdev->stats.rx_packets++; 493 netdev->stats.rx_bytes += skb->len; 494 495 /* push packet to protocol stack */ 496 napi_gro_receive(&priv->napi, skb); 497 498 (*processed)++; 499 return true; 500 } 501 502 /****************************************************************************** 503 * internal functions (transmit descriptor) 504 *****************************************************************************/ 505 static void ftgmac100_txdes_reset(struct ftgmac100_txdes *txdes) 506 { 507 /* clear all except end of ring bit */ 508 txdes->txdes0 &= cpu_to_le32(FTGMAC100_TXDES0_EDOTR); 509 txdes->txdes1 = 0; 510 txdes->txdes2 = 0; 511 txdes->txdes3 = 0; 512 } 513 514 static bool ftgmac100_txdes_owned_by_dma(struct ftgmac100_txdes *txdes) 515 { 516 return txdes->txdes0 & cpu_to_le32(FTGMAC100_TXDES0_TXDMA_OWN); 517 } 518 519 static void ftgmac100_txdes_set_dma_own(struct ftgmac100_txdes *txdes) 520 { 521 /* 522 * Make sure dma own bit will not be set before any other 523 * descriptor fields. 524 */ 525 wmb(); 526 txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_TXDMA_OWN); 527 } 528 529 static void ftgmac100_txdes_set_end_of_ring(struct ftgmac100_txdes *txdes) 530 { 531 txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_EDOTR); 532 } 533 534 static void ftgmac100_txdes_set_first_segment(struct ftgmac100_txdes *txdes) 535 { 536 txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_FTS); 537 } 538 539 static void ftgmac100_txdes_set_last_segment(struct ftgmac100_txdes *txdes) 540 { 541 txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_LTS); 542 } 543 544 static void ftgmac100_txdes_set_buffer_size(struct ftgmac100_txdes *txdes, 545 unsigned int len) 546 { 547 txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_TXBUF_SIZE(len)); 548 } 549 550 static void ftgmac100_txdes_set_txint(struct ftgmac100_txdes *txdes) 551 { 552 txdes->txdes1 |= cpu_to_le32(FTGMAC100_TXDES1_TXIC); 553 } 554 555 static void ftgmac100_txdes_set_tcpcs(struct ftgmac100_txdes *txdes) 556 { 557 txdes->txdes1 |= cpu_to_le32(FTGMAC100_TXDES1_TCP_CHKSUM); 558 } 559 560 static void ftgmac100_txdes_set_udpcs(struct ftgmac100_txdes *txdes) 561 { 562 txdes->txdes1 |= cpu_to_le32(FTGMAC100_TXDES1_UDP_CHKSUM); 563 } 564 565 static void ftgmac100_txdes_set_ipcs(struct ftgmac100_txdes *txdes) 566 { 567 txdes->txdes1 |= cpu_to_le32(FTGMAC100_TXDES1_IP_CHKSUM); 568 } 569 570 static void ftgmac100_txdes_set_dma_addr(struct ftgmac100_txdes *txdes, 571 dma_addr_t addr) 572 { 573 txdes->txdes3 = cpu_to_le32(addr); 574 } 575 576 static dma_addr_t ftgmac100_txdes_get_dma_addr(struct ftgmac100_txdes *txdes) 577 { 578 return le32_to_cpu(txdes->txdes3); 579 } 580 581 /* 582 * txdes2 is not used by hardware. We use it to keep track of socket buffer. 583 * Since hardware does not touch it, we can skip cpu_to_le32()/le32_to_cpu(). 584 */ 585 static void ftgmac100_txdes_set_skb(struct ftgmac100_txdes *txdes, 586 struct sk_buff *skb) 587 { 588 txdes->txdes2 = (unsigned int)skb; 589 } 590 591 static struct sk_buff *ftgmac100_txdes_get_skb(struct ftgmac100_txdes *txdes) 592 { 593 return (struct sk_buff *)txdes->txdes2; 594 } 595 596 /****************************************************************************** 597 * internal functions (transmit) 598 *****************************************************************************/ 599 static int ftgmac100_next_tx_pointer(int pointer) 600 { 601 return (pointer + 1) & (TX_QUEUE_ENTRIES - 1); 602 } 603 604 static void ftgmac100_tx_pointer_advance(struct ftgmac100 *priv) 605 { 606 priv->tx_pointer = ftgmac100_next_tx_pointer(priv->tx_pointer); 607 } 608 609 static void ftgmac100_tx_clean_pointer_advance(struct ftgmac100 *priv) 610 { 611 priv->tx_clean_pointer = ftgmac100_next_tx_pointer(priv->tx_clean_pointer); 612 } 613 614 static struct ftgmac100_txdes *ftgmac100_current_txdes(struct ftgmac100 *priv) 615 { 616 return &priv->descs->txdes[priv->tx_pointer]; 617 } 618 619 static struct ftgmac100_txdes * 620 ftgmac100_current_clean_txdes(struct ftgmac100 *priv) 621 { 622 return &priv->descs->txdes[priv->tx_clean_pointer]; 623 } 624 625 static bool ftgmac100_tx_complete_packet(struct ftgmac100 *priv) 626 { 627 struct net_device *netdev = priv->netdev; 628 struct ftgmac100_txdes *txdes; 629 struct sk_buff *skb; 630 dma_addr_t map; 631 632 if (priv->tx_pending == 0) 633 return false; 634 635 txdes = ftgmac100_current_clean_txdes(priv); 636 637 if (ftgmac100_txdes_owned_by_dma(txdes)) 638 return false; 639 640 skb = ftgmac100_txdes_get_skb(txdes); 641 map = ftgmac100_txdes_get_dma_addr(txdes); 642 643 netdev->stats.tx_packets++; 644 netdev->stats.tx_bytes += skb->len; 645 646 dma_unmap_single(priv->dev, map, skb_headlen(skb), DMA_TO_DEVICE); 647 648 dev_kfree_skb(skb); 649 650 ftgmac100_txdes_reset(txdes); 651 652 ftgmac100_tx_clean_pointer_advance(priv); 653 654 spin_lock(&priv->tx_lock); 655 priv->tx_pending--; 656 spin_unlock(&priv->tx_lock); 657 netif_wake_queue(netdev); 658 659 return true; 660 } 661 662 static void ftgmac100_tx_complete(struct ftgmac100 *priv) 663 { 664 while (ftgmac100_tx_complete_packet(priv)) 665 ; 666 } 667 668 static int ftgmac100_xmit(struct ftgmac100 *priv, struct sk_buff *skb, 669 dma_addr_t map) 670 { 671 struct net_device *netdev = priv->netdev; 672 struct ftgmac100_txdes *txdes; 673 unsigned int len = (skb->len < ETH_ZLEN) ? ETH_ZLEN : skb->len; 674 675 txdes = ftgmac100_current_txdes(priv); 676 ftgmac100_tx_pointer_advance(priv); 677 678 /* setup TX descriptor */ 679 ftgmac100_txdes_set_skb(txdes, skb); 680 ftgmac100_txdes_set_dma_addr(txdes, map); 681 ftgmac100_txdes_set_buffer_size(txdes, len); 682 683 ftgmac100_txdes_set_first_segment(txdes); 684 ftgmac100_txdes_set_last_segment(txdes); 685 ftgmac100_txdes_set_txint(txdes); 686 if (skb->ip_summed == CHECKSUM_PARTIAL) { 687 __be16 protocol = skb->protocol; 688 689 if (protocol == cpu_to_be16(ETH_P_IP)) { 690 u8 ip_proto = ip_hdr(skb)->protocol; 691 692 ftgmac100_txdes_set_ipcs(txdes); 693 if (ip_proto == IPPROTO_TCP) 694 ftgmac100_txdes_set_tcpcs(txdes); 695 else if (ip_proto == IPPROTO_UDP) 696 ftgmac100_txdes_set_udpcs(txdes); 697 } 698 } 699 700 spin_lock(&priv->tx_lock); 701 priv->tx_pending++; 702 if (priv->tx_pending == TX_QUEUE_ENTRIES) 703 netif_stop_queue(netdev); 704 705 /* start transmit */ 706 ftgmac100_txdes_set_dma_own(txdes); 707 spin_unlock(&priv->tx_lock); 708 709 ftgmac100_txdma_normal_prio_start_polling(priv); 710 711 return NETDEV_TX_OK; 712 } 713 714 /****************************************************************************** 715 * internal functions (buffer) 716 *****************************************************************************/ 717 static int ftgmac100_alloc_rx_page(struct ftgmac100 *priv, 718 struct ftgmac100_rxdes *rxdes, gfp_t gfp) 719 { 720 struct net_device *netdev = priv->netdev; 721 struct page *page; 722 dma_addr_t map; 723 724 page = alloc_page(gfp); 725 if (!page) { 726 if (net_ratelimit()) 727 netdev_err(netdev, "failed to allocate rx page\n"); 728 return -ENOMEM; 729 } 730 731 map = dma_map_page(priv->dev, page, 0, RX_BUF_SIZE, DMA_FROM_DEVICE); 732 if (unlikely(dma_mapping_error(priv->dev, map))) { 733 if (net_ratelimit()) 734 netdev_err(netdev, "failed to map rx page\n"); 735 __free_page(page); 736 return -ENOMEM; 737 } 738 739 ftgmac100_rxdes_set_page(rxdes, page); 740 ftgmac100_rxdes_set_dma_addr(rxdes, map); 741 ftgmac100_rxdes_set_dma_own(rxdes); 742 return 0; 743 } 744 745 static void ftgmac100_free_buffers(struct ftgmac100 *priv) 746 { 747 int i; 748 749 for (i = 0; i < RX_QUEUE_ENTRIES; i++) { 750 struct ftgmac100_rxdes *rxdes = &priv->descs->rxdes[i]; 751 struct page *page = ftgmac100_rxdes_get_page(rxdes); 752 dma_addr_t map = ftgmac100_rxdes_get_dma_addr(rxdes); 753 754 if (!page) 755 continue; 756 757 dma_unmap_page(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE); 758 __free_page(page); 759 } 760 761 for (i = 0; i < TX_QUEUE_ENTRIES; i++) { 762 struct ftgmac100_txdes *txdes = &priv->descs->txdes[i]; 763 struct sk_buff *skb = ftgmac100_txdes_get_skb(txdes); 764 dma_addr_t map = ftgmac100_txdes_get_dma_addr(txdes); 765 766 if (!skb) 767 continue; 768 769 dma_unmap_single(priv->dev, map, skb_headlen(skb), DMA_TO_DEVICE); 770 dev_kfree_skb(skb); 771 } 772 773 dma_free_coherent(priv->dev, sizeof(struct ftgmac100_descs), 774 priv->descs, priv->descs_dma_addr); 775 } 776 777 static int ftgmac100_alloc_buffers(struct ftgmac100 *priv) 778 { 779 int i; 780 781 priv->descs = dma_alloc_coherent(priv->dev, 782 sizeof(struct ftgmac100_descs), 783 &priv->descs_dma_addr, 784 GFP_KERNEL | __GFP_ZERO); 785 if (!priv->descs) 786 return -ENOMEM; 787 788 /* initialize RX ring */ 789 ftgmac100_rxdes_set_end_of_ring(&priv->descs->rxdes[RX_QUEUE_ENTRIES - 1]); 790 791 for (i = 0; i < RX_QUEUE_ENTRIES; i++) { 792 struct ftgmac100_rxdes *rxdes = &priv->descs->rxdes[i]; 793 794 if (ftgmac100_alloc_rx_page(priv, rxdes, GFP_KERNEL)) 795 goto err; 796 } 797 798 /* initialize TX ring */ 799 ftgmac100_txdes_set_end_of_ring(&priv->descs->txdes[TX_QUEUE_ENTRIES - 1]); 800 return 0; 801 802 err: 803 ftgmac100_free_buffers(priv); 804 return -ENOMEM; 805 } 806 807 /****************************************************************************** 808 * internal functions (mdio) 809 *****************************************************************************/ 810 static void ftgmac100_adjust_link(struct net_device *netdev) 811 { 812 struct ftgmac100 *priv = netdev_priv(netdev); 813 struct phy_device *phydev = priv->phydev; 814 int ier; 815 816 if (phydev->speed == priv->old_speed) 817 return; 818 819 priv->old_speed = phydev->speed; 820 821 ier = ioread32(priv->base + FTGMAC100_OFFSET_IER); 822 823 /* disable all interrupts */ 824 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER); 825 826 netif_stop_queue(netdev); 827 ftgmac100_stop_hw(priv); 828 829 netif_start_queue(netdev); 830 ftgmac100_init_hw(priv); 831 ftgmac100_start_hw(priv, phydev->speed); 832 833 /* re-enable interrupts */ 834 iowrite32(ier, priv->base + FTGMAC100_OFFSET_IER); 835 } 836 837 static int ftgmac100_mii_probe(struct ftgmac100 *priv) 838 { 839 struct net_device *netdev = priv->netdev; 840 struct phy_device *phydev = NULL; 841 int i; 842 843 /* search for connect PHY device */ 844 for (i = 0; i < PHY_MAX_ADDR; i++) { 845 struct phy_device *tmp = priv->mii_bus->phy_map[i]; 846 847 if (tmp) { 848 phydev = tmp; 849 break; 850 } 851 } 852 853 /* now we are supposed to have a proper phydev, to attach to... */ 854 if (!phydev) { 855 netdev_info(netdev, "%s: no PHY found\n", netdev->name); 856 return -ENODEV; 857 } 858 859 phydev = phy_connect(netdev, dev_name(&phydev->dev), 860 &ftgmac100_adjust_link, PHY_INTERFACE_MODE_GMII); 861 862 if (IS_ERR(phydev)) { 863 netdev_err(netdev, "%s: Could not attach to PHY\n", netdev->name); 864 return PTR_ERR(phydev); 865 } 866 867 priv->phydev = phydev; 868 return 0; 869 } 870 871 /****************************************************************************** 872 * struct mii_bus functions 873 *****************************************************************************/ 874 static int ftgmac100_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum) 875 { 876 struct net_device *netdev = bus->priv; 877 struct ftgmac100 *priv = netdev_priv(netdev); 878 unsigned int phycr; 879 int i; 880 881 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR); 882 883 /* preserve MDC cycle threshold */ 884 phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK; 885 886 phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) | 887 FTGMAC100_PHYCR_REGAD(regnum) | 888 FTGMAC100_PHYCR_MIIRD; 889 890 iowrite32(phycr, priv->base + FTGMAC100_OFFSET_PHYCR); 891 892 for (i = 0; i < 10; i++) { 893 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR); 894 895 if ((phycr & FTGMAC100_PHYCR_MIIRD) == 0) { 896 int data; 897 898 data = ioread32(priv->base + FTGMAC100_OFFSET_PHYDATA); 899 return FTGMAC100_PHYDATA_MIIRDATA(data); 900 } 901 902 udelay(100); 903 } 904 905 netdev_err(netdev, "mdio read timed out\n"); 906 return -EIO; 907 } 908 909 static int ftgmac100_mdiobus_write(struct mii_bus *bus, int phy_addr, 910 int regnum, u16 value) 911 { 912 struct net_device *netdev = bus->priv; 913 struct ftgmac100 *priv = netdev_priv(netdev); 914 unsigned int phycr; 915 int data; 916 int i; 917 918 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR); 919 920 /* preserve MDC cycle threshold */ 921 phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK; 922 923 phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) | 924 FTGMAC100_PHYCR_REGAD(regnum) | 925 FTGMAC100_PHYCR_MIIWR; 926 927 data = FTGMAC100_PHYDATA_MIIWDATA(value); 928 929 iowrite32(data, priv->base + FTGMAC100_OFFSET_PHYDATA); 930 iowrite32(phycr, priv->base + FTGMAC100_OFFSET_PHYCR); 931 932 for (i = 0; i < 10; i++) { 933 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR); 934 935 if ((phycr & FTGMAC100_PHYCR_MIIWR) == 0) 936 return 0; 937 938 udelay(100); 939 } 940 941 netdev_err(netdev, "mdio write timed out\n"); 942 return -EIO; 943 } 944 945 static int ftgmac100_mdiobus_reset(struct mii_bus *bus) 946 { 947 return 0; 948 } 949 950 /****************************************************************************** 951 * struct ethtool_ops functions 952 *****************************************************************************/ 953 static void ftgmac100_get_drvinfo(struct net_device *netdev, 954 struct ethtool_drvinfo *info) 955 { 956 strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); 957 strlcpy(info->version, DRV_VERSION, sizeof(info->version)); 958 strlcpy(info->bus_info, dev_name(&netdev->dev), sizeof(info->bus_info)); 959 } 960 961 static int ftgmac100_get_settings(struct net_device *netdev, 962 struct ethtool_cmd *cmd) 963 { 964 struct ftgmac100 *priv = netdev_priv(netdev); 965 966 return phy_ethtool_gset(priv->phydev, cmd); 967 } 968 969 static int ftgmac100_set_settings(struct net_device *netdev, 970 struct ethtool_cmd *cmd) 971 { 972 struct ftgmac100 *priv = netdev_priv(netdev); 973 974 return phy_ethtool_sset(priv->phydev, cmd); 975 } 976 977 static const struct ethtool_ops ftgmac100_ethtool_ops = { 978 .set_settings = ftgmac100_set_settings, 979 .get_settings = ftgmac100_get_settings, 980 .get_drvinfo = ftgmac100_get_drvinfo, 981 .get_link = ethtool_op_get_link, 982 }; 983 984 /****************************************************************************** 985 * interrupt handler 986 *****************************************************************************/ 987 static irqreturn_t ftgmac100_interrupt(int irq, void *dev_id) 988 { 989 struct net_device *netdev = dev_id; 990 struct ftgmac100 *priv = netdev_priv(netdev); 991 992 if (likely(netif_running(netdev))) { 993 /* Disable interrupts for polling */ 994 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER); 995 napi_schedule(&priv->napi); 996 } 997 998 return IRQ_HANDLED; 999 } 1000 1001 /****************************************************************************** 1002 * struct napi_struct functions 1003 *****************************************************************************/ 1004 static int ftgmac100_poll(struct napi_struct *napi, int budget) 1005 { 1006 struct ftgmac100 *priv = container_of(napi, struct ftgmac100, napi); 1007 struct net_device *netdev = priv->netdev; 1008 unsigned int status; 1009 bool completed = true; 1010 int rx = 0; 1011 1012 status = ioread32(priv->base + FTGMAC100_OFFSET_ISR); 1013 iowrite32(status, priv->base + FTGMAC100_OFFSET_ISR); 1014 1015 if (status & (FTGMAC100_INT_RPKT_BUF | FTGMAC100_INT_NO_RXBUF)) { 1016 /* 1017 * FTGMAC100_INT_RPKT_BUF: 1018 * RX DMA has received packets into RX buffer successfully 1019 * 1020 * FTGMAC100_INT_NO_RXBUF: 1021 * RX buffer unavailable 1022 */ 1023 bool retry; 1024 1025 do { 1026 retry = ftgmac100_rx_packet(priv, &rx); 1027 } while (retry && rx < budget); 1028 1029 if (retry && rx == budget) 1030 completed = false; 1031 } 1032 1033 if (status & (FTGMAC100_INT_XPKT_ETH | FTGMAC100_INT_XPKT_LOST)) { 1034 /* 1035 * FTGMAC100_INT_XPKT_ETH: 1036 * packet transmitted to ethernet successfully 1037 * 1038 * FTGMAC100_INT_XPKT_LOST: 1039 * packet transmitted to ethernet lost due to late 1040 * collision or excessive collision 1041 */ 1042 ftgmac100_tx_complete(priv); 1043 } 1044 1045 if (status & (FTGMAC100_INT_NO_RXBUF | FTGMAC100_INT_RPKT_LOST | 1046 FTGMAC100_INT_AHB_ERR | FTGMAC100_INT_PHYSTS_CHG)) { 1047 if (net_ratelimit()) 1048 netdev_info(netdev, "[ISR] = 0x%x: %s%s%s%s\n", status, 1049 status & FTGMAC100_INT_NO_RXBUF ? "NO_RXBUF " : "", 1050 status & FTGMAC100_INT_RPKT_LOST ? "RPKT_LOST " : "", 1051 status & FTGMAC100_INT_AHB_ERR ? "AHB_ERR " : "", 1052 status & FTGMAC100_INT_PHYSTS_CHG ? "PHYSTS_CHG" : ""); 1053 1054 if (status & FTGMAC100_INT_NO_RXBUF) { 1055 /* RX buffer unavailable */ 1056 netdev->stats.rx_over_errors++; 1057 } 1058 1059 if (status & FTGMAC100_INT_RPKT_LOST) { 1060 /* received packet lost due to RX FIFO full */ 1061 netdev->stats.rx_fifo_errors++; 1062 } 1063 } 1064 1065 if (completed) { 1066 napi_complete(napi); 1067 1068 /* enable all interrupts */ 1069 iowrite32(INT_MASK_ALL_ENABLED, priv->base + FTGMAC100_OFFSET_IER); 1070 } 1071 1072 return rx; 1073 } 1074 1075 /****************************************************************************** 1076 * struct net_device_ops functions 1077 *****************************************************************************/ 1078 static int ftgmac100_open(struct net_device *netdev) 1079 { 1080 struct ftgmac100 *priv = netdev_priv(netdev); 1081 int err; 1082 1083 err = ftgmac100_alloc_buffers(priv); 1084 if (err) { 1085 netdev_err(netdev, "failed to allocate buffers\n"); 1086 goto err_alloc; 1087 } 1088 1089 err = request_irq(priv->irq, ftgmac100_interrupt, 0, netdev->name, netdev); 1090 if (err) { 1091 netdev_err(netdev, "failed to request irq %d\n", priv->irq); 1092 goto err_irq; 1093 } 1094 1095 priv->rx_pointer = 0; 1096 priv->tx_clean_pointer = 0; 1097 priv->tx_pointer = 0; 1098 priv->tx_pending = 0; 1099 1100 err = ftgmac100_reset_hw(priv); 1101 if (err) 1102 goto err_hw; 1103 1104 ftgmac100_init_hw(priv); 1105 ftgmac100_start_hw(priv, 10); 1106 1107 phy_start(priv->phydev); 1108 1109 napi_enable(&priv->napi); 1110 netif_start_queue(netdev); 1111 1112 /* enable all interrupts */ 1113 iowrite32(INT_MASK_ALL_ENABLED, priv->base + FTGMAC100_OFFSET_IER); 1114 return 0; 1115 1116 err_hw: 1117 free_irq(priv->irq, netdev); 1118 err_irq: 1119 ftgmac100_free_buffers(priv); 1120 err_alloc: 1121 return err; 1122 } 1123 1124 static int ftgmac100_stop(struct net_device *netdev) 1125 { 1126 struct ftgmac100 *priv = netdev_priv(netdev); 1127 1128 /* disable all interrupts */ 1129 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER); 1130 1131 netif_stop_queue(netdev); 1132 napi_disable(&priv->napi); 1133 phy_stop(priv->phydev); 1134 1135 ftgmac100_stop_hw(priv); 1136 free_irq(priv->irq, netdev); 1137 ftgmac100_free_buffers(priv); 1138 1139 return 0; 1140 } 1141 1142 static int ftgmac100_hard_start_xmit(struct sk_buff *skb, 1143 struct net_device *netdev) 1144 { 1145 struct ftgmac100 *priv = netdev_priv(netdev); 1146 dma_addr_t map; 1147 1148 if (unlikely(skb->len > MAX_PKT_SIZE)) { 1149 if (net_ratelimit()) 1150 netdev_dbg(netdev, "tx packet too big\n"); 1151 1152 netdev->stats.tx_dropped++; 1153 dev_kfree_skb(skb); 1154 return NETDEV_TX_OK; 1155 } 1156 1157 map = dma_map_single(priv->dev, skb->data, skb_headlen(skb), DMA_TO_DEVICE); 1158 if (unlikely(dma_mapping_error(priv->dev, map))) { 1159 /* drop packet */ 1160 if (net_ratelimit()) 1161 netdev_err(netdev, "map socket buffer failed\n"); 1162 1163 netdev->stats.tx_dropped++; 1164 dev_kfree_skb(skb); 1165 return NETDEV_TX_OK; 1166 } 1167 1168 return ftgmac100_xmit(priv, skb, map); 1169 } 1170 1171 /* optional */ 1172 static int ftgmac100_do_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 1173 { 1174 struct ftgmac100 *priv = netdev_priv(netdev); 1175 1176 return phy_mii_ioctl(priv->phydev, ifr, cmd); 1177 } 1178 1179 static const struct net_device_ops ftgmac100_netdev_ops = { 1180 .ndo_open = ftgmac100_open, 1181 .ndo_stop = ftgmac100_stop, 1182 .ndo_start_xmit = ftgmac100_hard_start_xmit, 1183 .ndo_set_mac_address = eth_mac_addr, 1184 .ndo_validate_addr = eth_validate_addr, 1185 .ndo_do_ioctl = ftgmac100_do_ioctl, 1186 }; 1187 1188 /****************************************************************************** 1189 * struct platform_driver functions 1190 *****************************************************************************/ 1191 static int ftgmac100_probe(struct platform_device *pdev) 1192 { 1193 struct resource *res; 1194 int irq; 1195 struct net_device *netdev; 1196 struct ftgmac100 *priv; 1197 int err; 1198 int i; 1199 1200 if (!pdev) 1201 return -ENODEV; 1202 1203 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1204 if (!res) 1205 return -ENXIO; 1206 1207 irq = platform_get_irq(pdev, 0); 1208 if (irq < 0) 1209 return irq; 1210 1211 /* setup net_device */ 1212 netdev = alloc_etherdev(sizeof(*priv)); 1213 if (!netdev) { 1214 err = -ENOMEM; 1215 goto err_alloc_etherdev; 1216 } 1217 1218 SET_NETDEV_DEV(netdev, &pdev->dev); 1219 1220 SET_ETHTOOL_OPS(netdev, &ftgmac100_ethtool_ops); 1221 netdev->netdev_ops = &ftgmac100_netdev_ops; 1222 netdev->features = NETIF_F_IP_CSUM | NETIF_F_GRO; 1223 1224 platform_set_drvdata(pdev, netdev); 1225 1226 /* setup private data */ 1227 priv = netdev_priv(netdev); 1228 priv->netdev = netdev; 1229 priv->dev = &pdev->dev; 1230 1231 spin_lock_init(&priv->tx_lock); 1232 1233 /* initialize NAPI */ 1234 netif_napi_add(netdev, &priv->napi, ftgmac100_poll, 64); 1235 1236 /* map io memory */ 1237 priv->res = request_mem_region(res->start, resource_size(res), 1238 dev_name(&pdev->dev)); 1239 if (!priv->res) { 1240 dev_err(&pdev->dev, "Could not reserve memory region\n"); 1241 err = -ENOMEM; 1242 goto err_req_mem; 1243 } 1244 1245 priv->base = ioremap(res->start, resource_size(res)); 1246 if (!priv->base) { 1247 dev_err(&pdev->dev, "Failed to ioremap ethernet registers\n"); 1248 err = -EIO; 1249 goto err_ioremap; 1250 } 1251 1252 priv->irq = irq; 1253 1254 /* initialize mdio bus */ 1255 priv->mii_bus = mdiobus_alloc(); 1256 if (!priv->mii_bus) { 1257 err = -EIO; 1258 goto err_alloc_mdiobus; 1259 } 1260 1261 priv->mii_bus->name = "ftgmac100_mdio"; 1262 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "ftgmac100_mii"); 1263 1264 priv->mii_bus->priv = netdev; 1265 priv->mii_bus->read = ftgmac100_mdiobus_read; 1266 priv->mii_bus->write = ftgmac100_mdiobus_write; 1267 priv->mii_bus->reset = ftgmac100_mdiobus_reset; 1268 priv->mii_bus->irq = priv->phy_irq; 1269 1270 for (i = 0; i < PHY_MAX_ADDR; i++) 1271 priv->mii_bus->irq[i] = PHY_POLL; 1272 1273 err = mdiobus_register(priv->mii_bus); 1274 if (err) { 1275 dev_err(&pdev->dev, "Cannot register MDIO bus!\n"); 1276 goto err_register_mdiobus; 1277 } 1278 1279 err = ftgmac100_mii_probe(priv); 1280 if (err) { 1281 dev_err(&pdev->dev, "MII Probe failed!\n"); 1282 goto err_mii_probe; 1283 } 1284 1285 /* register network device */ 1286 err = register_netdev(netdev); 1287 if (err) { 1288 dev_err(&pdev->dev, "Failed to register netdev\n"); 1289 goto err_register_netdev; 1290 } 1291 1292 netdev_info(netdev, "irq %d, mapped at %p\n", priv->irq, priv->base); 1293 1294 if (!is_valid_ether_addr(netdev->dev_addr)) { 1295 eth_hw_addr_random(netdev); 1296 netdev_info(netdev, "generated random MAC address %pM\n", 1297 netdev->dev_addr); 1298 } 1299 1300 return 0; 1301 1302 err_register_netdev: 1303 phy_disconnect(priv->phydev); 1304 err_mii_probe: 1305 mdiobus_unregister(priv->mii_bus); 1306 err_register_mdiobus: 1307 mdiobus_free(priv->mii_bus); 1308 err_alloc_mdiobus: 1309 iounmap(priv->base); 1310 err_ioremap: 1311 release_resource(priv->res); 1312 err_req_mem: 1313 netif_napi_del(&priv->napi); 1314 free_netdev(netdev); 1315 err_alloc_etherdev: 1316 return err; 1317 } 1318 1319 static int __exit ftgmac100_remove(struct platform_device *pdev) 1320 { 1321 struct net_device *netdev; 1322 struct ftgmac100 *priv; 1323 1324 netdev = platform_get_drvdata(pdev); 1325 priv = netdev_priv(netdev); 1326 1327 unregister_netdev(netdev); 1328 1329 phy_disconnect(priv->phydev); 1330 mdiobus_unregister(priv->mii_bus); 1331 mdiobus_free(priv->mii_bus); 1332 1333 iounmap(priv->base); 1334 release_resource(priv->res); 1335 1336 netif_napi_del(&priv->napi); 1337 free_netdev(netdev); 1338 return 0; 1339 } 1340 1341 static struct platform_driver ftgmac100_driver = { 1342 .probe = ftgmac100_probe, 1343 .remove = __exit_p(ftgmac100_remove), 1344 .driver = { 1345 .name = DRV_NAME, 1346 .owner = THIS_MODULE, 1347 }, 1348 }; 1349 1350 module_platform_driver(ftgmac100_driver); 1351 1352 MODULE_AUTHOR("Po-Yu Chuang <ratbert@faraday-tech.com>"); 1353 MODULE_DESCRIPTION("FTGMAC100 driver"); 1354 MODULE_LICENSE("GPL"); 1355