1 /* 2 * Copyright(c) 2015 EZchip Technologies. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * The full GNU General Public License is included in this distribution in 14 * the file called "COPYING". 15 */ 16 17 #include <linux/module.h> 18 #include <linux/etherdevice.h> 19 #include <linux/of_address.h> 20 #include <linux/of_irq.h> 21 #include <linux/of_net.h> 22 #include <linux/of_platform.h> 23 #include "nps_enet.h" 24 25 #define DRV_NAME "nps_mgt_enet" 26 27 static void nps_enet_clean_rx_fifo(struct net_device *ndev, u32 frame_len) 28 { 29 struct nps_enet_priv *priv = netdev_priv(ndev); 30 u32 i, len = DIV_ROUND_UP(frame_len, sizeof(u32)); 31 32 /* Empty Rx FIFO buffer by reading all words */ 33 for (i = 0; i < len; i++) 34 nps_enet_reg_get(priv, NPS_ENET_REG_RX_BUF); 35 } 36 37 static void nps_enet_read_rx_fifo(struct net_device *ndev, 38 unsigned char *dst, u32 length) 39 { 40 struct nps_enet_priv *priv = netdev_priv(ndev); 41 s32 i, last = length & (sizeof(u32) - 1); 42 u32 *reg = (u32 *)dst, len = length / sizeof(u32); 43 bool dst_is_aligned = IS_ALIGNED((unsigned long)dst, sizeof(u32)); 44 45 /* In case dst is not aligned we need an intermediate buffer */ 46 if (dst_is_aligned) 47 for (i = 0; i < len; i++, reg++) 48 *reg = nps_enet_reg_get(priv, NPS_ENET_REG_RX_BUF); 49 else { /* !dst_is_aligned */ 50 for (i = 0; i < len; i++, reg++) { 51 u32 buf = 52 nps_enet_reg_get(priv, NPS_ENET_REG_RX_BUF); 53 54 /* to accommodate word-unaligned address of "reg" 55 * we have to do memcpy_toio() instead of simple "=". 56 */ 57 memcpy_toio((void __iomem *)reg, &buf, sizeof(buf)); 58 } 59 } 60 61 /* copy last bytes (if any) */ 62 if (last) { 63 u32 buf = nps_enet_reg_get(priv, NPS_ENET_REG_RX_BUF); 64 65 memcpy_toio((void __iomem *)reg, &buf, last); 66 } 67 } 68 69 static u32 nps_enet_rx_handler(struct net_device *ndev) 70 { 71 u32 frame_len, err = 0; 72 u32 work_done = 0; 73 struct nps_enet_priv *priv = netdev_priv(ndev); 74 struct sk_buff *skb; 75 struct nps_enet_rx_ctl rx_ctrl; 76 77 rx_ctrl.value = nps_enet_reg_get(priv, NPS_ENET_REG_RX_CTL); 78 frame_len = rx_ctrl.nr; 79 80 /* Check if we got RX */ 81 if (!rx_ctrl.cr) 82 return work_done; 83 84 /* If we got here there is a work for us */ 85 work_done++; 86 87 /* Check Rx error */ 88 if (rx_ctrl.er) { 89 ndev->stats.rx_errors++; 90 err = 1; 91 } 92 93 /* Check Rx CRC error */ 94 if (rx_ctrl.crc) { 95 ndev->stats.rx_crc_errors++; 96 ndev->stats.rx_dropped++; 97 err = 1; 98 } 99 100 /* Check Frame length Min 64b */ 101 if (unlikely(frame_len < ETH_ZLEN)) { 102 ndev->stats.rx_length_errors++; 103 ndev->stats.rx_dropped++; 104 err = 1; 105 } 106 107 if (err) 108 goto rx_irq_clean; 109 110 /* Skb allocation */ 111 skb = netdev_alloc_skb_ip_align(ndev, frame_len); 112 if (unlikely(!skb)) { 113 ndev->stats.rx_errors++; 114 ndev->stats.rx_dropped++; 115 goto rx_irq_clean; 116 } 117 118 /* Copy frame from Rx fifo into the skb */ 119 nps_enet_read_rx_fifo(ndev, skb->data, frame_len); 120 121 skb_put(skb, frame_len); 122 skb->protocol = eth_type_trans(skb, ndev); 123 skb->ip_summed = CHECKSUM_UNNECESSARY; 124 125 ndev->stats.rx_packets++; 126 ndev->stats.rx_bytes += frame_len; 127 netif_receive_skb(skb); 128 129 goto rx_irq_frame_done; 130 131 rx_irq_clean: 132 /* Clean Rx fifo */ 133 nps_enet_clean_rx_fifo(ndev, frame_len); 134 135 rx_irq_frame_done: 136 /* Ack Rx ctrl register */ 137 nps_enet_reg_set(priv, NPS_ENET_REG_RX_CTL, 0); 138 139 return work_done; 140 } 141 142 static void nps_enet_tx_handler(struct net_device *ndev) 143 { 144 struct nps_enet_priv *priv = netdev_priv(ndev); 145 struct nps_enet_tx_ctl tx_ctrl; 146 147 tx_ctrl.value = nps_enet_reg_get(priv, NPS_ENET_REG_TX_CTL); 148 149 /* Check if we got TX */ 150 if (!priv->tx_packet_sent || tx_ctrl.ct) 151 return; 152 153 /* Ack Tx ctrl register */ 154 nps_enet_reg_set(priv, NPS_ENET_REG_TX_CTL, 0); 155 156 /* Check Tx transmit error */ 157 if (unlikely(tx_ctrl.et)) { 158 ndev->stats.tx_errors++; 159 } else { 160 ndev->stats.tx_packets++; 161 ndev->stats.tx_bytes += tx_ctrl.nt; 162 } 163 164 dev_kfree_skb(priv->tx_skb); 165 priv->tx_packet_sent = false; 166 167 if (netif_queue_stopped(ndev)) 168 netif_wake_queue(ndev); 169 } 170 171 /** 172 * nps_enet_poll - NAPI poll handler. 173 * @napi: Pointer to napi_struct structure. 174 * @budget: How many frames to process on one call. 175 * 176 * returns: Number of processed frames 177 */ 178 static int nps_enet_poll(struct napi_struct *napi, int budget) 179 { 180 struct net_device *ndev = napi->dev; 181 struct nps_enet_priv *priv = netdev_priv(ndev); 182 u32 work_done; 183 184 nps_enet_tx_handler(ndev); 185 work_done = nps_enet_rx_handler(ndev); 186 if (work_done < budget) { 187 struct nps_enet_buf_int_enable buf_int_enable; 188 189 napi_complete(napi); 190 buf_int_enable.rx_rdy = NPS_ENET_ENABLE; 191 buf_int_enable.tx_done = NPS_ENET_ENABLE; 192 nps_enet_reg_set(priv, NPS_ENET_REG_BUF_INT_ENABLE, 193 buf_int_enable.value); 194 } 195 196 return work_done; 197 } 198 199 /** 200 * nps_enet_irq_handler - Global interrupt handler for ENET. 201 * @irq: irq number. 202 * @dev_instance: device instance. 203 * 204 * returns: IRQ_HANDLED for all cases. 205 * 206 * EZchip ENET has 2 interrupt causes, and depending on bits raised in 207 * CTRL registers we may tell what is a reason for interrupt to fire up. 208 * We got one for RX and the other for TX (completion). 209 */ 210 static irqreturn_t nps_enet_irq_handler(s32 irq, void *dev_instance) 211 { 212 struct net_device *ndev = dev_instance; 213 struct nps_enet_priv *priv = netdev_priv(ndev); 214 struct nps_enet_rx_ctl rx_ctrl; 215 struct nps_enet_tx_ctl tx_ctrl; 216 217 rx_ctrl.value = nps_enet_reg_get(priv, NPS_ENET_REG_RX_CTL); 218 tx_ctrl.value = nps_enet_reg_get(priv, NPS_ENET_REG_TX_CTL); 219 220 if ((!tx_ctrl.ct && priv->tx_packet_sent) || rx_ctrl.cr) 221 if (likely(napi_schedule_prep(&priv->napi))) { 222 nps_enet_reg_set(priv, NPS_ENET_REG_BUF_INT_ENABLE, 0); 223 __napi_schedule(&priv->napi); 224 } 225 226 return IRQ_HANDLED; 227 } 228 229 static void nps_enet_set_hw_mac_address(struct net_device *ndev) 230 { 231 struct nps_enet_priv *priv = netdev_priv(ndev); 232 struct nps_enet_ge_mac_cfg_1 ge_mac_cfg_1; 233 struct nps_enet_ge_mac_cfg_2 *ge_mac_cfg_2 = &priv->ge_mac_cfg_2; 234 235 /* set MAC address in HW */ 236 ge_mac_cfg_1.octet_0 = ndev->dev_addr[0]; 237 ge_mac_cfg_1.octet_1 = ndev->dev_addr[1]; 238 ge_mac_cfg_1.octet_2 = ndev->dev_addr[2]; 239 ge_mac_cfg_1.octet_3 = ndev->dev_addr[3]; 240 ge_mac_cfg_2->octet_4 = ndev->dev_addr[4]; 241 ge_mac_cfg_2->octet_5 = ndev->dev_addr[5]; 242 243 nps_enet_reg_set(priv, NPS_ENET_REG_GE_MAC_CFG_1, 244 ge_mac_cfg_1.value); 245 246 nps_enet_reg_set(priv, NPS_ENET_REG_GE_MAC_CFG_2, 247 ge_mac_cfg_2->value); 248 } 249 250 /** 251 * nps_enet_hw_reset - Reset the network device. 252 * @ndev: Pointer to the network device. 253 * 254 * This function reset the PCS and TX fifo. 255 * The programming model is to set the relevant reset bits 256 * wait for some time for this to propagate and then unset 257 * the reset bits. This way we ensure that reset procedure 258 * is done successfully by device. 259 */ 260 static void nps_enet_hw_reset(struct net_device *ndev) 261 { 262 struct nps_enet_priv *priv = netdev_priv(ndev); 263 struct nps_enet_ge_rst ge_rst; 264 struct nps_enet_phase_fifo_ctl phase_fifo_ctl; 265 266 ge_rst.value = 0; 267 phase_fifo_ctl.value = 0; 268 /* Pcs reset sequence*/ 269 ge_rst.gmac_0 = NPS_ENET_ENABLE; 270 nps_enet_reg_set(priv, NPS_ENET_REG_GE_RST, ge_rst.value); 271 usleep_range(10, 20); 272 ge_rst.value = 0; 273 nps_enet_reg_set(priv, NPS_ENET_REG_GE_RST, ge_rst.value); 274 275 /* Tx fifo reset sequence */ 276 phase_fifo_ctl.rst = NPS_ENET_ENABLE; 277 phase_fifo_ctl.init = NPS_ENET_ENABLE; 278 nps_enet_reg_set(priv, NPS_ENET_REG_PHASE_FIFO_CTL, 279 phase_fifo_ctl.value); 280 usleep_range(10, 20); 281 phase_fifo_ctl.value = 0; 282 nps_enet_reg_set(priv, NPS_ENET_REG_PHASE_FIFO_CTL, 283 phase_fifo_ctl.value); 284 } 285 286 static void nps_enet_hw_enable_control(struct net_device *ndev) 287 { 288 struct nps_enet_priv *priv = netdev_priv(ndev); 289 struct nps_enet_ge_mac_cfg_0 ge_mac_cfg_0; 290 struct nps_enet_buf_int_enable buf_int_enable; 291 struct nps_enet_ge_mac_cfg_2 *ge_mac_cfg_2 = &priv->ge_mac_cfg_2; 292 struct nps_enet_ge_mac_cfg_3 *ge_mac_cfg_3 = &priv->ge_mac_cfg_3; 293 s32 max_frame_length; 294 295 ge_mac_cfg_0.value = 0; 296 buf_int_enable.value = 0; 297 /* Enable Rx and Tx statistics */ 298 ge_mac_cfg_2->stat_en = NPS_ENET_GE_MAC_CFG_2_STAT_EN; 299 300 /* Discard packets with different MAC address */ 301 ge_mac_cfg_2->disc_da = NPS_ENET_ENABLE; 302 303 /* Discard multicast packets */ 304 ge_mac_cfg_2->disc_mc = NPS_ENET_ENABLE; 305 306 nps_enet_reg_set(priv, NPS_ENET_REG_GE_MAC_CFG_2, 307 ge_mac_cfg_2->value); 308 309 /* Discard Packets bigger than max frame length */ 310 max_frame_length = ETH_HLEN + ndev->mtu + ETH_FCS_LEN; 311 if (max_frame_length <= NPS_ENET_MAX_FRAME_LENGTH) 312 ge_mac_cfg_3->max_len = max_frame_length; 313 314 /* Enable interrupts */ 315 buf_int_enable.rx_rdy = NPS_ENET_ENABLE; 316 buf_int_enable.tx_done = NPS_ENET_ENABLE; 317 nps_enet_reg_set(priv, NPS_ENET_REG_BUF_INT_ENABLE, 318 buf_int_enable.value); 319 320 /* Write device MAC address to HW */ 321 nps_enet_set_hw_mac_address(ndev); 322 323 /* Rx and Tx HW features */ 324 ge_mac_cfg_0.tx_pad_en = NPS_ENET_ENABLE; 325 ge_mac_cfg_0.tx_crc_en = NPS_ENET_ENABLE; 326 ge_mac_cfg_0.rx_crc_strip = NPS_ENET_ENABLE; 327 328 /* IFG configuration */ 329 ge_mac_cfg_0.rx_ifg = NPS_ENET_GE_MAC_CFG_0_RX_IFG; 330 ge_mac_cfg_0.tx_ifg = NPS_ENET_GE_MAC_CFG_0_TX_IFG; 331 332 /* preamble configuration */ 333 ge_mac_cfg_0.rx_pr_check_en = NPS_ENET_ENABLE; 334 ge_mac_cfg_0.tx_pr_len = NPS_ENET_GE_MAC_CFG_0_TX_PR_LEN; 335 336 /* enable flow control frames */ 337 ge_mac_cfg_0.tx_fc_en = NPS_ENET_ENABLE; 338 ge_mac_cfg_0.rx_fc_en = NPS_ENET_ENABLE; 339 ge_mac_cfg_0.tx_fc_retr = NPS_ENET_GE_MAC_CFG_0_TX_FC_RETR; 340 ge_mac_cfg_3->cf_drop = NPS_ENET_ENABLE; 341 342 /* Enable Rx and Tx */ 343 ge_mac_cfg_0.rx_en = NPS_ENET_ENABLE; 344 ge_mac_cfg_0.tx_en = NPS_ENET_ENABLE; 345 346 nps_enet_reg_set(priv, NPS_ENET_REG_GE_MAC_CFG_3, 347 ge_mac_cfg_3->value); 348 nps_enet_reg_set(priv, NPS_ENET_REG_GE_MAC_CFG_0, 349 ge_mac_cfg_0.value); 350 } 351 352 static void nps_enet_hw_disable_control(struct net_device *ndev) 353 { 354 struct nps_enet_priv *priv = netdev_priv(ndev); 355 356 /* Disable interrupts */ 357 nps_enet_reg_set(priv, NPS_ENET_REG_BUF_INT_ENABLE, 0); 358 359 /* Disable Rx and Tx */ 360 nps_enet_reg_set(priv, NPS_ENET_REG_GE_MAC_CFG_0, 0); 361 } 362 363 static void nps_enet_send_frame(struct net_device *ndev, 364 struct sk_buff *skb) 365 { 366 struct nps_enet_priv *priv = netdev_priv(ndev); 367 struct nps_enet_tx_ctl tx_ctrl; 368 short length = skb->len; 369 u32 i, len = DIV_ROUND_UP(length, sizeof(u32)); 370 u32 *src = (u32 *)virt_to_phys(skb->data); 371 bool src_is_aligned = IS_ALIGNED((unsigned long)src, sizeof(u32)); 372 373 tx_ctrl.value = 0; 374 /* In case src is not aligned we need an intermediate buffer */ 375 if (src_is_aligned) 376 for (i = 0; i < len; i++, src++) 377 nps_enet_reg_set(priv, NPS_ENET_REG_TX_BUF, *src); 378 else { /* !src_is_aligned */ 379 for (i = 0; i < len; i++, src++) { 380 u32 buf; 381 382 /* to accommodate word-unaligned address of "src" 383 * we have to do memcpy_fromio() instead of simple "=" 384 */ 385 memcpy_fromio(&buf, (void __iomem *)src, sizeof(buf)); 386 nps_enet_reg_set(priv, NPS_ENET_REG_TX_BUF, buf); 387 } 388 } 389 /* Write the length of the Frame */ 390 tx_ctrl.nt = length; 391 392 /* Indicate SW is done */ 393 priv->tx_packet_sent = true; 394 tx_ctrl.ct = NPS_ENET_ENABLE; 395 396 /* Send Frame */ 397 nps_enet_reg_set(priv, NPS_ENET_REG_TX_CTL, tx_ctrl.value); 398 } 399 400 /** 401 * nps_enet_set_mac_address - Set the MAC address for this device. 402 * @ndev: Pointer to net_device structure. 403 * @p: 6 byte Address to be written as MAC address. 404 * 405 * This function copies the HW address from the sockaddr structure to the 406 * net_device structure and updates the address in HW. 407 * 408 * returns: -EBUSY if the net device is busy or 0 if the address is set 409 * successfully. 410 */ 411 static s32 nps_enet_set_mac_address(struct net_device *ndev, void *p) 412 { 413 struct sockaddr *addr = p; 414 s32 res; 415 416 if (netif_running(ndev)) 417 return -EBUSY; 418 419 res = eth_mac_addr(ndev, p); 420 if (!res) { 421 ether_addr_copy(ndev->dev_addr, addr->sa_data); 422 nps_enet_set_hw_mac_address(ndev); 423 } 424 425 return res; 426 } 427 428 /** 429 * nps_enet_set_rx_mode - Change the receive filtering mode. 430 * @ndev: Pointer to the network device. 431 * 432 * This function enables/disables promiscuous mode 433 */ 434 static void nps_enet_set_rx_mode(struct net_device *ndev) 435 { 436 struct nps_enet_priv *priv = netdev_priv(ndev); 437 struct nps_enet_ge_mac_cfg_2 ge_mac_cfg_2; 438 439 ge_mac_cfg_2.value = priv->ge_mac_cfg_2.value; 440 441 if (ndev->flags & IFF_PROMISC) { 442 ge_mac_cfg_2.disc_da = NPS_ENET_DISABLE; 443 ge_mac_cfg_2.disc_mc = NPS_ENET_DISABLE; 444 } else { 445 ge_mac_cfg_2.disc_da = NPS_ENET_ENABLE; 446 ge_mac_cfg_2.disc_mc = NPS_ENET_ENABLE; 447 } 448 449 nps_enet_reg_set(priv, NPS_ENET_REG_GE_MAC_CFG_2, ge_mac_cfg_2.value); 450 } 451 452 /** 453 * nps_enet_open - Open the network device. 454 * @ndev: Pointer to the network device. 455 * 456 * returns: 0, on success or non-zero error value on failure. 457 * 458 * This function sets the MAC address, requests and enables an IRQ 459 * for the ENET device and starts the Tx queue. 460 */ 461 static s32 nps_enet_open(struct net_device *ndev) 462 { 463 struct nps_enet_priv *priv = netdev_priv(ndev); 464 s32 err; 465 466 /* Reset private variables */ 467 priv->tx_packet_sent = false; 468 priv->ge_mac_cfg_2.value = 0; 469 priv->ge_mac_cfg_3.value = 0; 470 471 /* ge_mac_cfg_3 default values */ 472 priv->ge_mac_cfg_3.rx_ifg_th = NPS_ENET_GE_MAC_CFG_3_RX_IFG_TH; 473 priv->ge_mac_cfg_3.max_len = NPS_ENET_GE_MAC_CFG_3_MAX_LEN; 474 475 /* Disable HW device */ 476 nps_enet_hw_disable_control(ndev); 477 478 /* irq Rx allocation */ 479 err = request_irq(priv->irq, nps_enet_irq_handler, 480 0, "enet-rx-tx", ndev); 481 if (err) 482 return err; 483 484 napi_enable(&priv->napi); 485 486 /* Enable HW device */ 487 nps_enet_hw_reset(ndev); 488 nps_enet_hw_enable_control(ndev); 489 490 netif_start_queue(ndev); 491 492 return 0; 493 } 494 495 /** 496 * nps_enet_stop - Close the network device. 497 * @ndev: Pointer to the network device. 498 * 499 * This function stops the Tx queue, disables interrupts for the ENET device. 500 */ 501 static s32 nps_enet_stop(struct net_device *ndev) 502 { 503 struct nps_enet_priv *priv = netdev_priv(ndev); 504 505 napi_disable(&priv->napi); 506 netif_stop_queue(ndev); 507 nps_enet_hw_disable_control(ndev); 508 free_irq(priv->irq, ndev); 509 510 return 0; 511 } 512 513 /** 514 * nps_enet_start_xmit - Starts the data transmission. 515 * @skb: sk_buff pointer that contains data to be Transmitted. 516 * @ndev: Pointer to net_device structure. 517 * 518 * returns: NETDEV_TX_OK, on success 519 * NETDEV_TX_BUSY, if any of the descriptors are not free. 520 * 521 * This function is invoked from upper layers to initiate transmission. 522 */ 523 static netdev_tx_t nps_enet_start_xmit(struct sk_buff *skb, 524 struct net_device *ndev) 525 { 526 struct nps_enet_priv *priv = netdev_priv(ndev); 527 528 /* This driver handles one frame at a time */ 529 netif_stop_queue(ndev); 530 531 priv->tx_skb = skb; 532 533 nps_enet_send_frame(ndev, skb); 534 535 return NETDEV_TX_OK; 536 } 537 538 #ifdef CONFIG_NET_POLL_CONTROLLER 539 static void nps_enet_poll_controller(struct net_device *ndev) 540 { 541 disable_irq(ndev->irq); 542 nps_enet_irq_handler(ndev->irq, ndev); 543 enable_irq(ndev->irq); 544 } 545 #endif 546 547 static const struct net_device_ops nps_netdev_ops = { 548 .ndo_open = nps_enet_open, 549 .ndo_stop = nps_enet_stop, 550 .ndo_start_xmit = nps_enet_start_xmit, 551 .ndo_set_mac_address = nps_enet_set_mac_address, 552 .ndo_set_rx_mode = nps_enet_set_rx_mode, 553 #ifdef CONFIG_NET_POLL_CONTROLLER 554 .ndo_poll_controller = nps_enet_poll_controller, 555 #endif 556 }; 557 558 static s32 nps_enet_probe(struct platform_device *pdev) 559 { 560 struct device *dev = &pdev->dev; 561 struct net_device *ndev; 562 struct nps_enet_priv *priv; 563 s32 err = 0; 564 const char *mac_addr; 565 struct resource *res_regs; 566 567 if (!dev->of_node) 568 return -ENODEV; 569 570 ndev = alloc_etherdev(sizeof(struct nps_enet_priv)); 571 if (!ndev) 572 return -ENOMEM; 573 574 platform_set_drvdata(pdev, ndev); 575 SET_NETDEV_DEV(ndev, dev); 576 priv = netdev_priv(ndev); 577 578 /* The EZ NET specific entries in the device structure. */ 579 ndev->netdev_ops = &nps_netdev_ops; 580 ndev->watchdog_timeo = (400 * HZ / 1000); 581 /* FIXME :: no multicast support yet */ 582 ndev->flags &= ~IFF_MULTICAST; 583 584 res_regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 585 priv->regs_base = devm_ioremap_resource(dev, res_regs); 586 if (IS_ERR(priv->regs_base)) { 587 err = PTR_ERR(priv->regs_base); 588 goto out_netdev; 589 } 590 dev_dbg(dev, "Registers base address is 0x%p\n", priv->regs_base); 591 592 /* set kernel MAC address to dev */ 593 mac_addr = of_get_mac_address(dev->of_node); 594 if (mac_addr) 595 ether_addr_copy(ndev->dev_addr, mac_addr); 596 else 597 eth_hw_addr_random(ndev); 598 599 /* Get IRQ number */ 600 priv->irq = platform_get_irq(pdev, 0); 601 if (!priv->irq) { 602 dev_err(dev, "failed to retrieve <irq Rx-Tx> value from device tree\n"); 603 err = -ENODEV; 604 goto out_netdev; 605 } 606 607 netif_napi_add(ndev, &priv->napi, nps_enet_poll, 608 NPS_ENET_NAPI_POLL_WEIGHT); 609 610 /* Register the driver. Should be the last thing in probe */ 611 err = register_netdev(ndev); 612 if (err) { 613 dev_err(dev, "Failed to register ndev for %s, err = 0x%08x\n", 614 ndev->name, (s32)err); 615 goto out_netif_api; 616 } 617 618 dev_info(dev, "(rx/tx=%d)\n", priv->irq); 619 return 0; 620 621 out_netif_api: 622 netif_napi_del(&priv->napi); 623 out_netdev: 624 if (err) 625 free_netdev(ndev); 626 627 return err; 628 } 629 630 static s32 nps_enet_remove(struct platform_device *pdev) 631 { 632 struct net_device *ndev = platform_get_drvdata(pdev); 633 struct nps_enet_priv *priv = netdev_priv(ndev); 634 635 unregister_netdev(ndev); 636 free_netdev(ndev); 637 netif_napi_del(&priv->napi); 638 639 return 0; 640 } 641 642 static const struct of_device_id nps_enet_dt_ids[] = { 643 { .compatible = "ezchip,nps-mgt-enet" }, 644 { /* Sentinel */ } 645 }; 646 647 static struct platform_driver nps_enet_driver = { 648 .probe = nps_enet_probe, 649 .remove = nps_enet_remove, 650 .driver = { 651 .name = DRV_NAME, 652 .of_match_table = nps_enet_dt_ids, 653 }, 654 }; 655 656 module_platform_driver(nps_enet_driver); 657 658 MODULE_AUTHOR("EZchip Semiconductor"); 659 MODULE_LICENSE("GPL v2"); 660