1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright(c) 2015 EZchip Technologies. 4 */ 5 6 #include <linux/module.h> 7 #include <linux/etherdevice.h> 8 #include <linux/interrupt.h> 9 #include <linux/of_address.h> 10 #include <linux/of_irq.h> 11 #include <linux/of_net.h> 12 #include <linux/of_platform.h> 13 #include "nps_enet.h" 14 15 #define DRV_NAME "nps_mgt_enet" 16 17 static inline bool nps_enet_is_tx_pending(struct nps_enet_priv *priv) 18 { 19 u32 tx_ctrl_value = nps_enet_reg_get(priv, NPS_ENET_REG_TX_CTL); 20 u32 tx_ctrl_ct = (tx_ctrl_value & TX_CTL_CT_MASK) >> TX_CTL_CT_SHIFT; 21 22 return (!tx_ctrl_ct && priv->tx_skb); 23 } 24 25 static void nps_enet_clean_rx_fifo(struct net_device *ndev, u32 frame_len) 26 { 27 struct nps_enet_priv *priv = netdev_priv(ndev); 28 u32 i, len = DIV_ROUND_UP(frame_len, sizeof(u32)); 29 30 /* Empty Rx FIFO buffer by reading all words */ 31 for (i = 0; i < len; i++) 32 nps_enet_reg_get(priv, NPS_ENET_REG_RX_BUF); 33 } 34 35 static void nps_enet_read_rx_fifo(struct net_device *ndev, 36 unsigned char *dst, u32 length) 37 { 38 struct nps_enet_priv *priv = netdev_priv(ndev); 39 s32 i, last = length & (sizeof(u32) - 1); 40 u32 *reg = (u32 *)dst, len = length / sizeof(u32); 41 bool dst_is_aligned = IS_ALIGNED((unsigned long)dst, sizeof(u32)); 42 43 /* In case dst is not aligned we need an intermediate buffer */ 44 if (dst_is_aligned) { 45 ioread32_rep(priv->regs_base + NPS_ENET_REG_RX_BUF, reg, len); 46 reg += len; 47 } else { /* !dst_is_aligned */ 48 for (i = 0; i < len; i++, reg++) { 49 u32 buf = nps_enet_reg_get(priv, NPS_ENET_REG_RX_BUF); 50 51 put_unaligned_be32(buf, reg); 52 } 53 } 54 /* copy last bytes (if any) */ 55 if (last) { 56 u32 buf; 57 58 ioread32_rep(priv->regs_base + NPS_ENET_REG_RX_BUF, &buf, 1); 59 memcpy((u8 *)reg, &buf, last); 60 } 61 } 62 63 static u32 nps_enet_rx_handler(struct net_device *ndev) 64 { 65 u32 frame_len, err = 0; 66 u32 work_done = 0; 67 struct nps_enet_priv *priv = netdev_priv(ndev); 68 struct sk_buff *skb; 69 u32 rx_ctrl_value = nps_enet_reg_get(priv, NPS_ENET_REG_RX_CTL); 70 u32 rx_ctrl_cr = (rx_ctrl_value & RX_CTL_CR_MASK) >> RX_CTL_CR_SHIFT; 71 u32 rx_ctrl_er = (rx_ctrl_value & RX_CTL_ER_MASK) >> RX_CTL_ER_SHIFT; 72 u32 rx_ctrl_crc = (rx_ctrl_value & RX_CTL_CRC_MASK) >> RX_CTL_CRC_SHIFT; 73 74 frame_len = (rx_ctrl_value & RX_CTL_NR_MASK) >> RX_CTL_NR_SHIFT; 75 76 /* Check if we got RX */ 77 if (!rx_ctrl_cr) 78 return work_done; 79 80 /* If we got here there is a work for us */ 81 work_done++; 82 83 /* Check Rx error */ 84 if (rx_ctrl_er) { 85 ndev->stats.rx_errors++; 86 err = 1; 87 } 88 89 /* Check Rx CRC error */ 90 if (rx_ctrl_crc) { 91 ndev->stats.rx_crc_errors++; 92 ndev->stats.rx_dropped++; 93 err = 1; 94 } 95 96 /* Check Frame length Min 64b */ 97 if (unlikely(frame_len < ETH_ZLEN)) { 98 ndev->stats.rx_length_errors++; 99 ndev->stats.rx_dropped++; 100 err = 1; 101 } 102 103 if (err) 104 goto rx_irq_clean; 105 106 /* Skb allocation */ 107 skb = netdev_alloc_skb_ip_align(ndev, frame_len); 108 if (unlikely(!skb)) { 109 ndev->stats.rx_errors++; 110 ndev->stats.rx_dropped++; 111 goto rx_irq_clean; 112 } 113 114 /* Copy frame from Rx fifo into the skb */ 115 nps_enet_read_rx_fifo(ndev, skb->data, frame_len); 116 117 skb_put(skb, frame_len); 118 skb->protocol = eth_type_trans(skb, ndev); 119 skb->ip_summed = CHECKSUM_UNNECESSARY; 120 121 ndev->stats.rx_packets++; 122 ndev->stats.rx_bytes += frame_len; 123 netif_receive_skb(skb); 124 125 goto rx_irq_frame_done; 126 127 rx_irq_clean: 128 /* Clean Rx fifo */ 129 nps_enet_clean_rx_fifo(ndev, frame_len); 130 131 rx_irq_frame_done: 132 /* Ack Rx ctrl register */ 133 nps_enet_reg_set(priv, NPS_ENET_REG_RX_CTL, 0); 134 135 return work_done; 136 } 137 138 static void nps_enet_tx_handler(struct net_device *ndev) 139 { 140 struct nps_enet_priv *priv = netdev_priv(ndev); 141 u32 tx_ctrl_value = nps_enet_reg_get(priv, NPS_ENET_REG_TX_CTL); 142 u32 tx_ctrl_et = (tx_ctrl_value & TX_CTL_ET_MASK) >> TX_CTL_ET_SHIFT; 143 u32 tx_ctrl_nt = (tx_ctrl_value & TX_CTL_NT_MASK) >> TX_CTL_NT_SHIFT; 144 145 /* Check if we got TX */ 146 if (!nps_enet_is_tx_pending(priv)) 147 return; 148 149 /* Ack Tx ctrl register */ 150 nps_enet_reg_set(priv, NPS_ENET_REG_TX_CTL, 0); 151 152 /* Check Tx transmit error */ 153 if (unlikely(tx_ctrl_et)) { 154 ndev->stats.tx_errors++; 155 } else { 156 ndev->stats.tx_packets++; 157 ndev->stats.tx_bytes += tx_ctrl_nt; 158 } 159 160 dev_kfree_skb(priv->tx_skb); 161 priv->tx_skb = NULL; 162 163 if (netif_queue_stopped(ndev)) 164 netif_wake_queue(ndev); 165 } 166 167 /** 168 * nps_enet_poll - NAPI poll handler. 169 * @napi: Pointer to napi_struct structure. 170 * @budget: How many frames to process on one call. 171 * 172 * returns: Number of processed frames 173 */ 174 static int nps_enet_poll(struct napi_struct *napi, int budget) 175 { 176 struct net_device *ndev = napi->dev; 177 struct nps_enet_priv *priv = netdev_priv(ndev); 178 u32 work_done; 179 180 nps_enet_tx_handler(ndev); 181 work_done = nps_enet_rx_handler(ndev); 182 if ((work_done < budget) && napi_complete_done(napi, work_done)) { 183 u32 buf_int_enable_value = 0; 184 185 /* set tx_done and rx_rdy bits */ 186 buf_int_enable_value |= NPS_ENET_ENABLE << RX_RDY_SHIFT; 187 buf_int_enable_value |= NPS_ENET_ENABLE << TX_DONE_SHIFT; 188 189 nps_enet_reg_set(priv, NPS_ENET_REG_BUF_INT_ENABLE, 190 buf_int_enable_value); 191 192 /* in case we will get a tx interrupt while interrupts 193 * are masked, we will lose it since the tx is edge interrupt. 194 * specifically, while executing the code section above, 195 * between nps_enet_tx_handler and the interrupts enable, all 196 * tx requests will be stuck until we will get an rx interrupt. 197 * the two code lines below will solve this situation by 198 * re-adding ourselves to the poll list. 199 */ 200 if (nps_enet_is_tx_pending(priv)) { 201 nps_enet_reg_set(priv, NPS_ENET_REG_BUF_INT_ENABLE, 0); 202 napi_reschedule(napi); 203 } 204 } 205 206 return work_done; 207 } 208 209 /** 210 * nps_enet_irq_handler - Global interrupt handler for ENET. 211 * @irq: irq number. 212 * @dev_instance: device instance. 213 * 214 * returns: IRQ_HANDLED for all cases. 215 * 216 * EZchip ENET has 2 interrupt causes, and depending on bits raised in 217 * CTRL registers we may tell what is a reason for interrupt to fire up. 218 * We got one for RX and the other for TX (completion). 219 */ 220 static irqreturn_t nps_enet_irq_handler(s32 irq, void *dev_instance) 221 { 222 struct net_device *ndev = dev_instance; 223 struct nps_enet_priv *priv = netdev_priv(ndev); 224 u32 rx_ctrl_value = nps_enet_reg_get(priv, NPS_ENET_REG_RX_CTL); 225 u32 rx_ctrl_cr = (rx_ctrl_value & RX_CTL_CR_MASK) >> RX_CTL_CR_SHIFT; 226 227 if (nps_enet_is_tx_pending(priv) || rx_ctrl_cr) 228 if (likely(napi_schedule_prep(&priv->napi))) { 229 nps_enet_reg_set(priv, NPS_ENET_REG_BUF_INT_ENABLE, 0); 230 __napi_schedule(&priv->napi); 231 } 232 233 return IRQ_HANDLED; 234 } 235 236 static void nps_enet_set_hw_mac_address(struct net_device *ndev) 237 { 238 struct nps_enet_priv *priv = netdev_priv(ndev); 239 u32 ge_mac_cfg_1_value = 0; 240 u32 *ge_mac_cfg_2_value = &priv->ge_mac_cfg_2_value; 241 242 /* set MAC address in HW */ 243 ge_mac_cfg_1_value |= ndev->dev_addr[0] << CFG_1_OCTET_0_SHIFT; 244 ge_mac_cfg_1_value |= ndev->dev_addr[1] << CFG_1_OCTET_1_SHIFT; 245 ge_mac_cfg_1_value |= ndev->dev_addr[2] << CFG_1_OCTET_2_SHIFT; 246 ge_mac_cfg_1_value |= ndev->dev_addr[3] << CFG_1_OCTET_3_SHIFT; 247 *ge_mac_cfg_2_value = (*ge_mac_cfg_2_value & ~CFG_2_OCTET_4_MASK) 248 | ndev->dev_addr[4] << CFG_2_OCTET_4_SHIFT; 249 *ge_mac_cfg_2_value = (*ge_mac_cfg_2_value & ~CFG_2_OCTET_5_MASK) 250 | ndev->dev_addr[5] << CFG_2_OCTET_5_SHIFT; 251 252 nps_enet_reg_set(priv, NPS_ENET_REG_GE_MAC_CFG_1, 253 ge_mac_cfg_1_value); 254 255 nps_enet_reg_set(priv, NPS_ENET_REG_GE_MAC_CFG_2, 256 *ge_mac_cfg_2_value); 257 } 258 259 /** 260 * nps_enet_hw_reset - Reset the network device. 261 * @ndev: Pointer to the network device. 262 * 263 * This function reset the PCS and TX fifo. 264 * The programming model is to set the relevant reset bits 265 * wait for some time for this to propagate and then unset 266 * the reset bits. This way we ensure that reset procedure 267 * is done successfully by device. 268 */ 269 static void nps_enet_hw_reset(struct net_device *ndev) 270 { 271 struct nps_enet_priv *priv = netdev_priv(ndev); 272 u32 ge_rst_value = 0, phase_fifo_ctl_value = 0; 273 274 /* Pcs reset sequence*/ 275 ge_rst_value |= NPS_ENET_ENABLE << RST_GMAC_0_SHIFT; 276 nps_enet_reg_set(priv, NPS_ENET_REG_GE_RST, ge_rst_value); 277 usleep_range(10, 20); 278 ge_rst_value = 0; 279 nps_enet_reg_set(priv, NPS_ENET_REG_GE_RST, ge_rst_value); 280 281 /* Tx fifo reset sequence */ 282 phase_fifo_ctl_value |= NPS_ENET_ENABLE << PHASE_FIFO_CTL_RST_SHIFT; 283 phase_fifo_ctl_value |= NPS_ENET_ENABLE << PHASE_FIFO_CTL_INIT_SHIFT; 284 nps_enet_reg_set(priv, NPS_ENET_REG_PHASE_FIFO_CTL, 285 phase_fifo_ctl_value); 286 usleep_range(10, 20); 287 phase_fifo_ctl_value = 0; 288 nps_enet_reg_set(priv, NPS_ENET_REG_PHASE_FIFO_CTL, 289 phase_fifo_ctl_value); 290 } 291 292 static void nps_enet_hw_enable_control(struct net_device *ndev) 293 { 294 struct nps_enet_priv *priv = netdev_priv(ndev); 295 u32 ge_mac_cfg_0_value = 0, buf_int_enable_value = 0; 296 u32 *ge_mac_cfg_2_value = &priv->ge_mac_cfg_2_value; 297 u32 *ge_mac_cfg_3_value = &priv->ge_mac_cfg_3_value; 298 s32 max_frame_length; 299 300 /* Enable Rx and Tx statistics */ 301 *ge_mac_cfg_2_value = (*ge_mac_cfg_2_value & ~CFG_2_STAT_EN_MASK) 302 | NPS_ENET_GE_MAC_CFG_2_STAT_EN << CFG_2_STAT_EN_SHIFT; 303 304 /* Discard packets with different MAC address */ 305 *ge_mac_cfg_2_value = (*ge_mac_cfg_2_value & ~CFG_2_DISK_DA_MASK) 306 | NPS_ENET_ENABLE << CFG_2_DISK_DA_SHIFT; 307 308 /* Discard multicast packets */ 309 *ge_mac_cfg_2_value = (*ge_mac_cfg_2_value & ~CFG_2_DISK_MC_MASK) 310 | NPS_ENET_ENABLE << CFG_2_DISK_MC_SHIFT; 311 312 nps_enet_reg_set(priv, NPS_ENET_REG_GE_MAC_CFG_2, 313 *ge_mac_cfg_2_value); 314 315 /* Discard Packets bigger than max frame length */ 316 max_frame_length = ETH_HLEN + ndev->mtu + ETH_FCS_LEN; 317 if (max_frame_length <= NPS_ENET_MAX_FRAME_LENGTH) { 318 *ge_mac_cfg_3_value = 319 (*ge_mac_cfg_3_value & ~CFG_3_MAX_LEN_MASK) 320 | max_frame_length << CFG_3_MAX_LEN_SHIFT; 321 } 322 323 /* Enable interrupts */ 324 buf_int_enable_value |= NPS_ENET_ENABLE << RX_RDY_SHIFT; 325 buf_int_enable_value |= NPS_ENET_ENABLE << TX_DONE_SHIFT; 326 nps_enet_reg_set(priv, NPS_ENET_REG_BUF_INT_ENABLE, 327 buf_int_enable_value); 328 329 /* Write device MAC address to HW */ 330 nps_enet_set_hw_mac_address(ndev); 331 332 /* Rx and Tx HW features */ 333 ge_mac_cfg_0_value |= NPS_ENET_ENABLE << CFG_0_TX_PAD_EN_SHIFT; 334 ge_mac_cfg_0_value |= NPS_ENET_ENABLE << CFG_0_TX_CRC_EN_SHIFT; 335 ge_mac_cfg_0_value |= NPS_ENET_ENABLE << CFG_0_RX_CRC_STRIP_SHIFT; 336 337 /* IFG configuration */ 338 ge_mac_cfg_0_value |= 339 NPS_ENET_GE_MAC_CFG_0_RX_IFG << CFG_0_RX_IFG_SHIFT; 340 ge_mac_cfg_0_value |= 341 NPS_ENET_GE_MAC_CFG_0_TX_IFG << CFG_0_TX_IFG_SHIFT; 342 343 /* preamble configuration */ 344 ge_mac_cfg_0_value |= NPS_ENET_ENABLE << CFG_0_RX_PR_CHECK_EN_SHIFT; 345 ge_mac_cfg_0_value |= 346 NPS_ENET_GE_MAC_CFG_0_TX_PR_LEN << CFG_0_TX_PR_LEN_SHIFT; 347 348 /* enable flow control frames */ 349 ge_mac_cfg_0_value |= NPS_ENET_ENABLE << CFG_0_TX_FC_EN_SHIFT; 350 ge_mac_cfg_0_value |= NPS_ENET_ENABLE << CFG_0_RX_FC_EN_SHIFT; 351 ge_mac_cfg_0_value |= 352 NPS_ENET_GE_MAC_CFG_0_TX_FC_RETR << CFG_0_TX_FC_RETR_SHIFT; 353 *ge_mac_cfg_3_value = (*ge_mac_cfg_3_value & ~CFG_3_CF_DROP_MASK) 354 | NPS_ENET_ENABLE << CFG_3_CF_DROP_SHIFT; 355 356 /* Enable Rx and Tx */ 357 ge_mac_cfg_0_value |= NPS_ENET_ENABLE << CFG_0_RX_EN_SHIFT; 358 ge_mac_cfg_0_value |= NPS_ENET_ENABLE << CFG_0_TX_EN_SHIFT; 359 360 nps_enet_reg_set(priv, NPS_ENET_REG_GE_MAC_CFG_3, 361 *ge_mac_cfg_3_value); 362 nps_enet_reg_set(priv, NPS_ENET_REG_GE_MAC_CFG_0, 363 ge_mac_cfg_0_value); 364 } 365 366 static void nps_enet_hw_disable_control(struct net_device *ndev) 367 { 368 struct nps_enet_priv *priv = netdev_priv(ndev); 369 370 /* Disable interrupts */ 371 nps_enet_reg_set(priv, NPS_ENET_REG_BUF_INT_ENABLE, 0); 372 373 /* Disable Rx and Tx */ 374 nps_enet_reg_set(priv, NPS_ENET_REG_GE_MAC_CFG_0, 0); 375 } 376 377 static void nps_enet_send_frame(struct net_device *ndev, 378 struct sk_buff *skb) 379 { 380 struct nps_enet_priv *priv = netdev_priv(ndev); 381 u32 tx_ctrl_value = 0; 382 short length = skb->len; 383 u32 i, len = DIV_ROUND_UP(length, sizeof(u32)); 384 u32 *src = (void *)skb->data; 385 bool src_is_aligned = IS_ALIGNED((unsigned long)src, sizeof(u32)); 386 387 /* In case src is not aligned we need an intermediate buffer */ 388 if (src_is_aligned) 389 iowrite32_rep(priv->regs_base + NPS_ENET_REG_TX_BUF, src, len); 390 else /* !src_is_aligned */ 391 for (i = 0; i < len; i++, src++) 392 nps_enet_reg_set(priv, NPS_ENET_REG_TX_BUF, 393 get_unaligned_be32(src)); 394 395 /* Write the length of the Frame */ 396 tx_ctrl_value |= length << TX_CTL_NT_SHIFT; 397 398 tx_ctrl_value |= NPS_ENET_ENABLE << TX_CTL_CT_SHIFT; 399 /* Send Frame */ 400 nps_enet_reg_set(priv, NPS_ENET_REG_TX_CTL, tx_ctrl_value); 401 } 402 403 /** 404 * nps_enet_set_mac_address - Set the MAC address for this device. 405 * @ndev: Pointer to net_device structure. 406 * @p: 6 byte Address to be written as MAC address. 407 * 408 * This function copies the HW address from the sockaddr structure to the 409 * net_device structure and updates the address in HW. 410 * 411 * returns: -EBUSY if the net device is busy or 0 if the address is set 412 * successfully. 413 */ 414 static s32 nps_enet_set_mac_address(struct net_device *ndev, void *p) 415 { 416 struct sockaddr *addr = p; 417 s32 res; 418 419 if (netif_running(ndev)) 420 return -EBUSY; 421 422 res = eth_mac_addr(ndev, p); 423 if (!res) { 424 eth_hw_addr_set(ndev, addr->sa_data); 425 nps_enet_set_hw_mac_address(ndev); 426 } 427 428 return res; 429 } 430 431 /** 432 * nps_enet_set_rx_mode - Change the receive filtering mode. 433 * @ndev: Pointer to the network device. 434 * 435 * This function enables/disables promiscuous mode 436 */ 437 static void nps_enet_set_rx_mode(struct net_device *ndev) 438 { 439 struct nps_enet_priv *priv = netdev_priv(ndev); 440 u32 ge_mac_cfg_2_value = priv->ge_mac_cfg_2_value; 441 442 if (ndev->flags & IFF_PROMISC) { 443 ge_mac_cfg_2_value = (ge_mac_cfg_2_value & ~CFG_2_DISK_DA_MASK) 444 | NPS_ENET_DISABLE << CFG_2_DISK_DA_SHIFT; 445 ge_mac_cfg_2_value = (ge_mac_cfg_2_value & ~CFG_2_DISK_MC_MASK) 446 | NPS_ENET_DISABLE << CFG_2_DISK_MC_SHIFT; 447 448 } else { 449 ge_mac_cfg_2_value = (ge_mac_cfg_2_value & ~CFG_2_DISK_DA_MASK) 450 | NPS_ENET_ENABLE << CFG_2_DISK_DA_SHIFT; 451 ge_mac_cfg_2_value = (ge_mac_cfg_2_value & ~CFG_2_DISK_MC_MASK) 452 | NPS_ENET_ENABLE << CFG_2_DISK_MC_SHIFT; 453 } 454 455 nps_enet_reg_set(priv, NPS_ENET_REG_GE_MAC_CFG_2, ge_mac_cfg_2_value); 456 } 457 458 /** 459 * nps_enet_open - Open the network device. 460 * @ndev: Pointer to the network device. 461 * 462 * returns: 0, on success or non-zero error value on failure. 463 * 464 * This function sets the MAC address, requests and enables an IRQ 465 * for the ENET device and starts the Tx queue. 466 */ 467 static s32 nps_enet_open(struct net_device *ndev) 468 { 469 struct nps_enet_priv *priv = netdev_priv(ndev); 470 s32 err; 471 472 /* Reset private variables */ 473 priv->tx_skb = NULL; 474 priv->ge_mac_cfg_2_value = 0; 475 priv->ge_mac_cfg_3_value = 0; 476 477 /* ge_mac_cfg_3 default values */ 478 priv->ge_mac_cfg_3_value |= 479 NPS_ENET_GE_MAC_CFG_3_RX_IFG_TH << CFG_3_RX_IFG_TH_SHIFT; 480 481 priv->ge_mac_cfg_3_value |= 482 NPS_ENET_GE_MAC_CFG_3_MAX_LEN << CFG_3_MAX_LEN_SHIFT; 483 484 /* Disable HW device */ 485 nps_enet_hw_disable_control(ndev); 486 487 /* irq Rx allocation */ 488 err = request_irq(priv->irq, nps_enet_irq_handler, 489 0, "enet-rx-tx", ndev); 490 if (err) 491 return err; 492 493 napi_enable(&priv->napi); 494 495 /* Enable HW device */ 496 nps_enet_hw_reset(ndev); 497 nps_enet_hw_enable_control(ndev); 498 499 netif_start_queue(ndev); 500 501 return 0; 502 } 503 504 /** 505 * nps_enet_stop - Close the network device. 506 * @ndev: Pointer to the network device. 507 * 508 * This function stops the Tx queue, disables interrupts for the ENET device. 509 */ 510 static s32 nps_enet_stop(struct net_device *ndev) 511 { 512 struct nps_enet_priv *priv = netdev_priv(ndev); 513 514 napi_disable(&priv->napi); 515 netif_stop_queue(ndev); 516 nps_enet_hw_disable_control(ndev); 517 free_irq(priv->irq, ndev); 518 519 return 0; 520 } 521 522 /** 523 * nps_enet_start_xmit - Starts the data transmission. 524 * @skb: sk_buff pointer that contains data to be Transmitted. 525 * @ndev: Pointer to net_device structure. 526 * 527 * returns: NETDEV_TX_OK, on success 528 * NETDEV_TX_BUSY, if any of the descriptors are not free. 529 * 530 * This function is invoked from upper layers to initiate transmission. 531 */ 532 static netdev_tx_t nps_enet_start_xmit(struct sk_buff *skb, 533 struct net_device *ndev) 534 { 535 struct nps_enet_priv *priv = netdev_priv(ndev); 536 537 /* This driver handles one frame at a time */ 538 netif_stop_queue(ndev); 539 540 priv->tx_skb = skb; 541 542 /* make sure tx_skb is actually written to the memory 543 * before the HW is informed and the IRQ is fired. 544 */ 545 wmb(); 546 547 nps_enet_send_frame(ndev, skb); 548 549 return NETDEV_TX_OK; 550 } 551 552 #ifdef CONFIG_NET_POLL_CONTROLLER 553 static void nps_enet_poll_controller(struct net_device *ndev) 554 { 555 disable_irq(ndev->irq); 556 nps_enet_irq_handler(ndev->irq, ndev); 557 enable_irq(ndev->irq); 558 } 559 #endif 560 561 static const struct net_device_ops nps_netdev_ops = { 562 .ndo_open = nps_enet_open, 563 .ndo_stop = nps_enet_stop, 564 .ndo_start_xmit = nps_enet_start_xmit, 565 .ndo_set_mac_address = nps_enet_set_mac_address, 566 .ndo_set_rx_mode = nps_enet_set_rx_mode, 567 #ifdef CONFIG_NET_POLL_CONTROLLER 568 .ndo_poll_controller = nps_enet_poll_controller, 569 #endif 570 }; 571 572 static s32 nps_enet_probe(struct platform_device *pdev) 573 { 574 struct device *dev = &pdev->dev; 575 struct net_device *ndev; 576 struct nps_enet_priv *priv; 577 s32 err = 0; 578 579 if (!dev->of_node) 580 return -ENODEV; 581 582 ndev = alloc_etherdev(sizeof(struct nps_enet_priv)); 583 if (!ndev) 584 return -ENOMEM; 585 586 platform_set_drvdata(pdev, ndev); 587 SET_NETDEV_DEV(ndev, dev); 588 priv = netdev_priv(ndev); 589 590 /* The EZ NET specific entries in the device structure. */ 591 ndev->netdev_ops = &nps_netdev_ops; 592 ndev->watchdog_timeo = (400 * HZ / 1000); 593 /* FIXME :: no multicast support yet */ 594 ndev->flags &= ~IFF_MULTICAST; 595 596 priv->regs_base = devm_platform_ioremap_resource(pdev, 0); 597 if (IS_ERR(priv->regs_base)) { 598 err = PTR_ERR(priv->regs_base); 599 goto out_netdev; 600 } 601 dev_dbg(dev, "Registers base address is 0x%p\n", priv->regs_base); 602 603 /* set kernel MAC address to dev */ 604 err = of_get_ethdev_address(dev->of_node, ndev); 605 if (err) 606 eth_hw_addr_random(ndev); 607 608 /* Get IRQ number */ 609 priv->irq = platform_get_irq(pdev, 0); 610 if (priv->irq < 0) { 611 err = -ENODEV; 612 goto out_netdev; 613 } 614 615 netif_napi_add_weight(ndev, &priv->napi, nps_enet_poll, 616 NPS_ENET_NAPI_POLL_WEIGHT); 617 618 /* Register the driver. Should be the last thing in probe */ 619 err = register_netdev(ndev); 620 if (err) { 621 dev_err(dev, "Failed to register ndev for %s, err = 0x%08x\n", 622 ndev->name, (s32)err); 623 goto out_netif_api; 624 } 625 626 dev_info(dev, "(rx/tx=%d)\n", priv->irq); 627 return 0; 628 629 out_netif_api: 630 netif_napi_del(&priv->napi); 631 out_netdev: 632 free_netdev(ndev); 633 634 return err; 635 } 636 637 static s32 nps_enet_remove(struct platform_device *pdev) 638 { 639 struct net_device *ndev = platform_get_drvdata(pdev); 640 struct nps_enet_priv *priv = netdev_priv(ndev); 641 642 unregister_netdev(ndev); 643 netif_napi_del(&priv->napi); 644 free_netdev(ndev); 645 646 return 0; 647 } 648 649 static const struct of_device_id nps_enet_dt_ids[] = { 650 { .compatible = "ezchip,nps-mgt-enet" }, 651 { /* Sentinel */ } 652 }; 653 MODULE_DEVICE_TABLE(of, nps_enet_dt_ids); 654 655 static struct platform_driver nps_enet_driver = { 656 .probe = nps_enet_probe, 657 .remove = nps_enet_remove, 658 .driver = { 659 .name = DRV_NAME, 660 .of_match_table = nps_enet_dt_ids, 661 }, 662 }; 663 664 module_platform_driver(nps_enet_driver); 665 666 MODULE_AUTHOR("EZchip Semiconductor"); 667 MODULE_LICENSE("GPL v2"); 668