1 /* 2 * Copyright(c) 2015 EZchip Technologies. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * The full GNU General Public License is included in this distribution in 14 * the file called "COPYING". 15 */ 16 17 #include <linux/module.h> 18 #include <linux/etherdevice.h> 19 #include <linux/of_address.h> 20 #include <linux/of_irq.h> 21 #include <linux/of_net.h> 22 #include <linux/of_platform.h> 23 #include "nps_enet.h" 24 25 #define DRV_NAME "nps_mgt_enet" 26 27 static void nps_enet_clean_rx_fifo(struct net_device *ndev, u32 frame_len) 28 { 29 struct nps_enet_priv *priv = netdev_priv(ndev); 30 u32 i, len = DIV_ROUND_UP(frame_len, sizeof(u32)); 31 32 /* Empty Rx FIFO buffer by reading all words */ 33 for (i = 0; i < len; i++) 34 nps_enet_reg_get(priv, NPS_ENET_REG_RX_BUF); 35 } 36 37 static void nps_enet_read_rx_fifo(struct net_device *ndev, 38 unsigned char *dst, u32 length) 39 { 40 struct nps_enet_priv *priv = netdev_priv(ndev); 41 s32 i, last = length & (sizeof(u32) - 1); 42 u32 *reg = (u32 *)dst, len = length / sizeof(u32); 43 bool dst_is_aligned = IS_ALIGNED((unsigned long)dst, sizeof(u32)); 44 45 /* In case dst is not aligned we need an intermediate buffer */ 46 if (dst_is_aligned) { 47 ioread32_rep(priv->regs_base + NPS_ENET_REG_RX_BUF, reg, len); 48 reg += len; 49 } 50 else { /* !dst_is_aligned */ 51 for (i = 0; i < len; i++, reg++) { 52 u32 buf = nps_enet_reg_get(priv, NPS_ENET_REG_RX_BUF); 53 put_unaligned_be32(buf, reg); 54 } 55 } 56 /* copy last bytes (if any) */ 57 if (last) { 58 u32 buf; 59 ioread32_rep(priv->regs_base + NPS_ENET_REG_RX_BUF, &buf, 1); 60 memcpy((u8 *)reg, &buf, last); 61 } 62 } 63 64 static u32 nps_enet_rx_handler(struct net_device *ndev) 65 { 66 u32 frame_len, err = 0; 67 u32 work_done = 0; 68 struct nps_enet_priv *priv = netdev_priv(ndev); 69 struct sk_buff *skb; 70 u32 rx_ctrl_value = nps_enet_reg_get(priv, NPS_ENET_REG_RX_CTL); 71 u32 rx_ctrl_cr = (rx_ctrl_value & RX_CTL_CR_MASK) >> RX_CTL_CR_SHIFT; 72 u32 rx_ctrl_er = (rx_ctrl_value & RX_CTL_ER_MASK) >> RX_CTL_ER_SHIFT; 73 u32 rx_ctrl_crc = (rx_ctrl_value & RX_CTL_CRC_MASK) >> RX_CTL_CRC_SHIFT; 74 75 frame_len = (rx_ctrl_value & RX_CTL_NR_MASK) >> RX_CTL_NR_SHIFT; 76 77 /* Check if we got RX */ 78 if (!rx_ctrl_cr) 79 return work_done; 80 81 /* If we got here there is a work for us */ 82 work_done++; 83 84 /* Check Rx error */ 85 if (rx_ctrl_er) { 86 ndev->stats.rx_errors++; 87 err = 1; 88 } 89 90 /* Check Rx CRC error */ 91 if (rx_ctrl_crc) { 92 ndev->stats.rx_crc_errors++; 93 ndev->stats.rx_dropped++; 94 err = 1; 95 } 96 97 /* Check Frame length Min 64b */ 98 if (unlikely(frame_len < ETH_ZLEN)) { 99 ndev->stats.rx_length_errors++; 100 ndev->stats.rx_dropped++; 101 err = 1; 102 } 103 104 if (err) 105 goto rx_irq_clean; 106 107 /* Skb allocation */ 108 skb = netdev_alloc_skb_ip_align(ndev, frame_len); 109 if (unlikely(!skb)) { 110 ndev->stats.rx_errors++; 111 ndev->stats.rx_dropped++; 112 goto rx_irq_clean; 113 } 114 115 /* Copy frame from Rx fifo into the skb */ 116 nps_enet_read_rx_fifo(ndev, skb->data, frame_len); 117 118 skb_put(skb, frame_len); 119 skb->protocol = eth_type_trans(skb, ndev); 120 skb->ip_summed = CHECKSUM_UNNECESSARY; 121 122 ndev->stats.rx_packets++; 123 ndev->stats.rx_bytes += frame_len; 124 netif_receive_skb(skb); 125 126 goto rx_irq_frame_done; 127 128 rx_irq_clean: 129 /* Clean Rx fifo */ 130 nps_enet_clean_rx_fifo(ndev, frame_len); 131 132 rx_irq_frame_done: 133 /* Ack Rx ctrl register */ 134 nps_enet_reg_set(priv, NPS_ENET_REG_RX_CTL, 0); 135 136 return work_done; 137 } 138 139 static void nps_enet_tx_handler(struct net_device *ndev) 140 { 141 struct nps_enet_priv *priv = netdev_priv(ndev); 142 u32 tx_ctrl_value = nps_enet_reg_get(priv, NPS_ENET_REG_TX_CTL); 143 u32 tx_ctrl_ct = (tx_ctrl_value & TX_CTL_CT_MASK) >> TX_CTL_CT_SHIFT; 144 u32 tx_ctrl_et = (tx_ctrl_value & TX_CTL_ET_MASK) >> TX_CTL_ET_SHIFT; 145 u32 tx_ctrl_nt = (tx_ctrl_value & TX_CTL_NT_MASK) >> TX_CTL_NT_SHIFT; 146 147 /* Check if we got TX */ 148 if (!priv->tx_skb || tx_ctrl_ct) 149 return; 150 151 /* Ack Tx ctrl register */ 152 nps_enet_reg_set(priv, NPS_ENET_REG_TX_CTL, 0); 153 154 /* Check Tx transmit error */ 155 if (unlikely(tx_ctrl_et)) { 156 ndev->stats.tx_errors++; 157 } else { 158 ndev->stats.tx_packets++; 159 ndev->stats.tx_bytes += tx_ctrl_nt; 160 } 161 162 dev_kfree_skb(priv->tx_skb); 163 priv->tx_skb = NULL; 164 165 if (netif_queue_stopped(ndev)) 166 netif_wake_queue(ndev); 167 } 168 169 /** 170 * nps_enet_poll - NAPI poll handler. 171 * @napi: Pointer to napi_struct structure. 172 * @budget: How many frames to process on one call. 173 * 174 * returns: Number of processed frames 175 */ 176 static int nps_enet_poll(struct napi_struct *napi, int budget) 177 { 178 struct net_device *ndev = napi->dev; 179 struct nps_enet_priv *priv = netdev_priv(ndev); 180 u32 work_done; 181 182 nps_enet_tx_handler(ndev); 183 work_done = nps_enet_rx_handler(ndev); 184 if (work_done < budget) { 185 u32 buf_int_enable_value = 0; 186 u32 tx_ctrl_value = nps_enet_reg_get(priv, NPS_ENET_REG_TX_CTL); 187 u32 tx_ctrl_ct = 188 (tx_ctrl_value & TX_CTL_CT_MASK) >> TX_CTL_CT_SHIFT; 189 190 napi_complete(napi); 191 192 /* set tx_done and rx_rdy bits */ 193 buf_int_enable_value |= NPS_ENET_ENABLE << RX_RDY_SHIFT; 194 buf_int_enable_value |= NPS_ENET_ENABLE << TX_DONE_SHIFT; 195 196 nps_enet_reg_set(priv, NPS_ENET_REG_BUF_INT_ENABLE, 197 buf_int_enable_value); 198 199 /* in case we will get a tx interrupt while interrupts 200 * are masked, we will lose it since the tx is edge interrupt. 201 * specifically, while executing the code section above, 202 * between nps_enet_tx_handler and the interrupts enable, all 203 * tx requests will be stuck until we will get an rx interrupt. 204 * the two code lines below will solve this situation by 205 * re-adding ourselves to the poll list. 206 */ 207 208 if (priv->tx_skb && !tx_ctrl_ct) { 209 nps_enet_reg_set(priv, NPS_ENET_REG_BUF_INT_ENABLE, 0); 210 napi_reschedule(napi); 211 } 212 } 213 214 return work_done; 215 } 216 217 /** 218 * nps_enet_irq_handler - Global interrupt handler for ENET. 219 * @irq: irq number. 220 * @dev_instance: device instance. 221 * 222 * returns: IRQ_HANDLED for all cases. 223 * 224 * EZchip ENET has 2 interrupt causes, and depending on bits raised in 225 * CTRL registers we may tell what is a reason for interrupt to fire up. 226 * We got one for RX and the other for TX (completion). 227 */ 228 static irqreturn_t nps_enet_irq_handler(s32 irq, void *dev_instance) 229 { 230 struct net_device *ndev = dev_instance; 231 struct nps_enet_priv *priv = netdev_priv(ndev); 232 u32 rx_ctrl_value = nps_enet_reg_get(priv, NPS_ENET_REG_RX_CTL); 233 u32 tx_ctrl_value = nps_enet_reg_get(priv, NPS_ENET_REG_TX_CTL); 234 u32 tx_ctrl_ct = (tx_ctrl_value & TX_CTL_CT_MASK) >> TX_CTL_CT_SHIFT; 235 u32 rx_ctrl_cr = (rx_ctrl_value & RX_CTL_CR_MASK) >> RX_CTL_CR_SHIFT; 236 237 if ((!tx_ctrl_ct && priv->tx_skb) || rx_ctrl_cr) 238 if (likely(napi_schedule_prep(&priv->napi))) { 239 nps_enet_reg_set(priv, NPS_ENET_REG_BUF_INT_ENABLE, 0); 240 __napi_schedule(&priv->napi); 241 } 242 243 return IRQ_HANDLED; 244 } 245 246 static void nps_enet_set_hw_mac_address(struct net_device *ndev) 247 { 248 struct nps_enet_priv *priv = netdev_priv(ndev); 249 u32 ge_mac_cfg_1_value = 0; 250 u32 *ge_mac_cfg_2_value = &priv->ge_mac_cfg_2_value; 251 252 /* set MAC address in HW */ 253 ge_mac_cfg_1_value |= ndev->dev_addr[0] << CFG_1_OCTET_0_SHIFT; 254 ge_mac_cfg_1_value |= ndev->dev_addr[1] << CFG_1_OCTET_1_SHIFT; 255 ge_mac_cfg_1_value |= ndev->dev_addr[2] << CFG_1_OCTET_2_SHIFT; 256 ge_mac_cfg_1_value |= ndev->dev_addr[3] << CFG_1_OCTET_3_SHIFT; 257 *ge_mac_cfg_2_value = (*ge_mac_cfg_2_value & ~CFG_2_OCTET_4_MASK) 258 | ndev->dev_addr[4] << CFG_2_OCTET_4_SHIFT; 259 *ge_mac_cfg_2_value = (*ge_mac_cfg_2_value & ~CFG_2_OCTET_5_MASK) 260 | ndev->dev_addr[5] << CFG_2_OCTET_5_SHIFT; 261 262 nps_enet_reg_set(priv, NPS_ENET_REG_GE_MAC_CFG_1, 263 ge_mac_cfg_1_value); 264 265 nps_enet_reg_set(priv, NPS_ENET_REG_GE_MAC_CFG_2, 266 *ge_mac_cfg_2_value); 267 } 268 269 /** 270 * nps_enet_hw_reset - Reset the network device. 271 * @ndev: Pointer to the network device. 272 * 273 * This function reset the PCS and TX fifo. 274 * The programming model is to set the relevant reset bits 275 * wait for some time for this to propagate and then unset 276 * the reset bits. This way we ensure that reset procedure 277 * is done successfully by device. 278 */ 279 static void nps_enet_hw_reset(struct net_device *ndev) 280 { 281 struct nps_enet_priv *priv = netdev_priv(ndev); 282 u32 ge_rst_value = 0, phase_fifo_ctl_value = 0; 283 284 /* Pcs reset sequence*/ 285 ge_rst_value |= NPS_ENET_ENABLE << RST_GMAC_0_SHIFT; 286 nps_enet_reg_set(priv, NPS_ENET_REG_GE_RST, ge_rst_value); 287 usleep_range(10, 20); 288 nps_enet_reg_set(priv, NPS_ENET_REG_GE_RST, ge_rst_value); 289 290 /* Tx fifo reset sequence */ 291 phase_fifo_ctl_value |= NPS_ENET_ENABLE << PHASE_FIFO_CTL_RST_SHIFT; 292 phase_fifo_ctl_value |= NPS_ENET_ENABLE << PHASE_FIFO_CTL_INIT_SHIFT; 293 nps_enet_reg_set(priv, NPS_ENET_REG_PHASE_FIFO_CTL, 294 phase_fifo_ctl_value); 295 usleep_range(10, 20); 296 phase_fifo_ctl_value = 0; 297 nps_enet_reg_set(priv, NPS_ENET_REG_PHASE_FIFO_CTL, 298 phase_fifo_ctl_value); 299 } 300 301 static void nps_enet_hw_enable_control(struct net_device *ndev) 302 { 303 struct nps_enet_priv *priv = netdev_priv(ndev); 304 u32 ge_mac_cfg_0_value = 0, buf_int_enable_value = 0; 305 u32 *ge_mac_cfg_2_value = &priv->ge_mac_cfg_2_value; 306 u32 *ge_mac_cfg_3_value = &priv->ge_mac_cfg_3_value; 307 s32 max_frame_length; 308 309 /* Enable Rx and Tx statistics */ 310 *ge_mac_cfg_2_value = (*ge_mac_cfg_2_value & ~CFG_2_STAT_EN_MASK) 311 | NPS_ENET_GE_MAC_CFG_2_STAT_EN << CFG_2_STAT_EN_SHIFT; 312 313 /* Discard packets with different MAC address */ 314 *ge_mac_cfg_2_value = (*ge_mac_cfg_2_value & ~CFG_2_DISK_DA_MASK) 315 | NPS_ENET_ENABLE << CFG_2_DISK_DA_SHIFT; 316 317 /* Discard multicast packets */ 318 *ge_mac_cfg_2_value = (*ge_mac_cfg_2_value & ~CFG_2_DISK_MC_MASK) 319 | NPS_ENET_ENABLE << CFG_2_DISK_MC_SHIFT; 320 321 nps_enet_reg_set(priv, NPS_ENET_REG_GE_MAC_CFG_2, 322 *ge_mac_cfg_2_value); 323 324 /* Discard Packets bigger than max frame length */ 325 max_frame_length = ETH_HLEN + ndev->mtu + ETH_FCS_LEN; 326 if (max_frame_length <= NPS_ENET_MAX_FRAME_LENGTH) { 327 *ge_mac_cfg_3_value = 328 (*ge_mac_cfg_3_value & ~CFG_3_MAX_LEN_MASK) 329 | max_frame_length << CFG_3_MAX_LEN_SHIFT; 330 } 331 332 /* Enable interrupts */ 333 buf_int_enable_value |= NPS_ENET_ENABLE << RX_RDY_SHIFT; 334 buf_int_enable_value |= NPS_ENET_ENABLE << TX_DONE_SHIFT; 335 nps_enet_reg_set(priv, NPS_ENET_REG_BUF_INT_ENABLE, 336 buf_int_enable_value); 337 338 /* Write device MAC address to HW */ 339 nps_enet_set_hw_mac_address(ndev); 340 341 /* Rx and Tx HW features */ 342 ge_mac_cfg_0_value |= NPS_ENET_ENABLE << CFG_0_TX_PAD_EN_SHIFT; 343 ge_mac_cfg_0_value |= NPS_ENET_ENABLE << CFG_0_TX_CRC_EN_SHIFT; 344 ge_mac_cfg_0_value |= NPS_ENET_ENABLE << CFG_0_RX_CRC_STRIP_SHIFT; 345 346 /* IFG configuration */ 347 ge_mac_cfg_0_value |= 348 NPS_ENET_GE_MAC_CFG_0_RX_IFG << CFG_0_RX_IFG_SHIFT; 349 ge_mac_cfg_0_value |= 350 NPS_ENET_GE_MAC_CFG_0_TX_IFG << CFG_0_TX_IFG_SHIFT; 351 352 /* preamble configuration */ 353 ge_mac_cfg_0_value |= NPS_ENET_ENABLE << CFG_0_RX_PR_CHECK_EN_SHIFT; 354 ge_mac_cfg_0_value |= 355 NPS_ENET_GE_MAC_CFG_0_TX_PR_LEN << CFG_0_TX_PR_LEN_SHIFT; 356 357 /* enable flow control frames */ 358 ge_mac_cfg_0_value |= NPS_ENET_ENABLE << CFG_0_TX_FC_EN_SHIFT; 359 ge_mac_cfg_0_value |= NPS_ENET_ENABLE << CFG_0_RX_FC_EN_SHIFT; 360 ge_mac_cfg_0_value |= 361 NPS_ENET_GE_MAC_CFG_0_TX_FC_RETR << CFG_0_TX_FC_RETR_SHIFT; 362 *ge_mac_cfg_3_value = (*ge_mac_cfg_3_value & ~CFG_3_CF_DROP_MASK) 363 | NPS_ENET_ENABLE << CFG_3_CF_DROP_SHIFT; 364 365 /* Enable Rx and Tx */ 366 ge_mac_cfg_0_value |= NPS_ENET_ENABLE << CFG_0_RX_EN_SHIFT; 367 ge_mac_cfg_0_value |= NPS_ENET_ENABLE << CFG_0_TX_EN_SHIFT; 368 369 nps_enet_reg_set(priv, NPS_ENET_REG_GE_MAC_CFG_3, 370 *ge_mac_cfg_3_value); 371 nps_enet_reg_set(priv, NPS_ENET_REG_GE_MAC_CFG_0, 372 ge_mac_cfg_0_value); 373 } 374 375 static void nps_enet_hw_disable_control(struct net_device *ndev) 376 { 377 struct nps_enet_priv *priv = netdev_priv(ndev); 378 379 /* Disable interrupts */ 380 nps_enet_reg_set(priv, NPS_ENET_REG_BUF_INT_ENABLE, 0); 381 382 /* Disable Rx and Tx */ 383 nps_enet_reg_set(priv, NPS_ENET_REG_GE_MAC_CFG_0, 0); 384 } 385 386 static void nps_enet_send_frame(struct net_device *ndev, 387 struct sk_buff *skb) 388 { 389 struct nps_enet_priv *priv = netdev_priv(ndev); 390 u32 tx_ctrl_value = 0; 391 short length = skb->len; 392 u32 i, len = DIV_ROUND_UP(length, sizeof(u32)); 393 u32 *src = (void *)skb->data; 394 bool src_is_aligned = IS_ALIGNED((unsigned long)src, sizeof(u32)); 395 396 /* In case src is not aligned we need an intermediate buffer */ 397 if (src_is_aligned) 398 iowrite32_rep(priv->regs_base + NPS_ENET_REG_TX_BUF, src, len); 399 else /* !src_is_aligned */ 400 for (i = 0; i < len; i++, src++) 401 nps_enet_reg_set(priv, NPS_ENET_REG_TX_BUF, 402 get_unaligned_be32(src)); 403 404 /* Write the length of the Frame */ 405 tx_ctrl_value |= length << TX_CTL_NT_SHIFT; 406 407 tx_ctrl_value |= NPS_ENET_ENABLE << TX_CTL_CT_SHIFT; 408 /* Send Frame */ 409 nps_enet_reg_set(priv, NPS_ENET_REG_TX_CTL, tx_ctrl_value); 410 } 411 412 /** 413 * nps_enet_set_mac_address - Set the MAC address for this device. 414 * @ndev: Pointer to net_device structure. 415 * @p: 6 byte Address to be written as MAC address. 416 * 417 * This function copies the HW address from the sockaddr structure to the 418 * net_device structure and updates the address in HW. 419 * 420 * returns: -EBUSY if the net device is busy or 0 if the address is set 421 * successfully. 422 */ 423 static s32 nps_enet_set_mac_address(struct net_device *ndev, void *p) 424 { 425 struct sockaddr *addr = p; 426 s32 res; 427 428 if (netif_running(ndev)) 429 return -EBUSY; 430 431 res = eth_mac_addr(ndev, p); 432 if (!res) { 433 ether_addr_copy(ndev->dev_addr, addr->sa_data); 434 nps_enet_set_hw_mac_address(ndev); 435 } 436 437 return res; 438 } 439 440 /** 441 * nps_enet_set_rx_mode - Change the receive filtering mode. 442 * @ndev: Pointer to the network device. 443 * 444 * This function enables/disables promiscuous mode 445 */ 446 static void nps_enet_set_rx_mode(struct net_device *ndev) 447 { 448 struct nps_enet_priv *priv = netdev_priv(ndev); 449 u32 ge_mac_cfg_2_value = priv->ge_mac_cfg_2_value; 450 451 if (ndev->flags & IFF_PROMISC) { 452 ge_mac_cfg_2_value = (ge_mac_cfg_2_value & ~CFG_2_DISK_DA_MASK) 453 | NPS_ENET_DISABLE << CFG_2_DISK_DA_SHIFT; 454 ge_mac_cfg_2_value = (ge_mac_cfg_2_value & ~CFG_2_DISK_MC_MASK) 455 | NPS_ENET_DISABLE << CFG_2_DISK_MC_SHIFT; 456 457 } else { 458 ge_mac_cfg_2_value = (ge_mac_cfg_2_value & ~CFG_2_DISK_DA_MASK) 459 | NPS_ENET_ENABLE << CFG_2_DISK_DA_SHIFT; 460 ge_mac_cfg_2_value = (ge_mac_cfg_2_value & ~CFG_2_DISK_MC_MASK) 461 | NPS_ENET_ENABLE << CFG_2_DISK_MC_SHIFT; 462 463 } 464 465 nps_enet_reg_set(priv, NPS_ENET_REG_GE_MAC_CFG_2, ge_mac_cfg_2_value); 466 } 467 468 /** 469 * nps_enet_open - Open the network device. 470 * @ndev: Pointer to the network device. 471 * 472 * returns: 0, on success or non-zero error value on failure. 473 * 474 * This function sets the MAC address, requests and enables an IRQ 475 * for the ENET device and starts the Tx queue. 476 */ 477 static s32 nps_enet_open(struct net_device *ndev) 478 { 479 struct nps_enet_priv *priv = netdev_priv(ndev); 480 s32 err; 481 482 /* Reset private variables */ 483 priv->tx_skb = NULL; 484 priv->ge_mac_cfg_2_value = 0; 485 priv->ge_mac_cfg_3_value = 0; 486 487 /* ge_mac_cfg_3 default values */ 488 priv->ge_mac_cfg_3_value |= 489 NPS_ENET_GE_MAC_CFG_3_RX_IFG_TH << CFG_3_RX_IFG_TH_SHIFT; 490 491 priv->ge_mac_cfg_3_value |= 492 NPS_ENET_GE_MAC_CFG_3_MAX_LEN << CFG_3_MAX_LEN_SHIFT; 493 494 /* Disable HW device */ 495 nps_enet_hw_disable_control(ndev); 496 497 /* irq Rx allocation */ 498 err = request_irq(priv->irq, nps_enet_irq_handler, 499 0, "enet-rx-tx", ndev); 500 if (err) 501 return err; 502 503 napi_enable(&priv->napi); 504 505 /* Enable HW device */ 506 nps_enet_hw_reset(ndev); 507 nps_enet_hw_enable_control(ndev); 508 509 netif_start_queue(ndev); 510 511 return 0; 512 } 513 514 /** 515 * nps_enet_stop - Close the network device. 516 * @ndev: Pointer to the network device. 517 * 518 * This function stops the Tx queue, disables interrupts for the ENET device. 519 */ 520 static s32 nps_enet_stop(struct net_device *ndev) 521 { 522 struct nps_enet_priv *priv = netdev_priv(ndev); 523 524 napi_disable(&priv->napi); 525 netif_stop_queue(ndev); 526 nps_enet_hw_disable_control(ndev); 527 free_irq(priv->irq, ndev); 528 529 return 0; 530 } 531 532 /** 533 * nps_enet_start_xmit - Starts the data transmission. 534 * @skb: sk_buff pointer that contains data to be Transmitted. 535 * @ndev: Pointer to net_device structure. 536 * 537 * returns: NETDEV_TX_OK, on success 538 * NETDEV_TX_BUSY, if any of the descriptors are not free. 539 * 540 * This function is invoked from upper layers to initiate transmission. 541 */ 542 static netdev_tx_t nps_enet_start_xmit(struct sk_buff *skb, 543 struct net_device *ndev) 544 { 545 struct nps_enet_priv *priv = netdev_priv(ndev); 546 547 /* This driver handles one frame at a time */ 548 netif_stop_queue(ndev); 549 550 priv->tx_skb = skb; 551 552 /* make sure tx_skb is actually written to the memory 553 * before the HW is informed and the IRQ is fired. 554 */ 555 wmb(); 556 557 nps_enet_send_frame(ndev, skb); 558 559 return NETDEV_TX_OK; 560 } 561 562 #ifdef CONFIG_NET_POLL_CONTROLLER 563 static void nps_enet_poll_controller(struct net_device *ndev) 564 { 565 disable_irq(ndev->irq); 566 nps_enet_irq_handler(ndev->irq, ndev); 567 enable_irq(ndev->irq); 568 } 569 #endif 570 571 static const struct net_device_ops nps_netdev_ops = { 572 .ndo_open = nps_enet_open, 573 .ndo_stop = nps_enet_stop, 574 .ndo_start_xmit = nps_enet_start_xmit, 575 .ndo_set_mac_address = nps_enet_set_mac_address, 576 .ndo_set_rx_mode = nps_enet_set_rx_mode, 577 #ifdef CONFIG_NET_POLL_CONTROLLER 578 .ndo_poll_controller = nps_enet_poll_controller, 579 #endif 580 }; 581 582 static s32 nps_enet_probe(struct platform_device *pdev) 583 { 584 struct device *dev = &pdev->dev; 585 struct net_device *ndev; 586 struct nps_enet_priv *priv; 587 s32 err = 0; 588 const char *mac_addr; 589 struct resource *res_regs; 590 591 if (!dev->of_node) 592 return -ENODEV; 593 594 ndev = alloc_etherdev(sizeof(struct nps_enet_priv)); 595 if (!ndev) 596 return -ENOMEM; 597 598 platform_set_drvdata(pdev, ndev); 599 SET_NETDEV_DEV(ndev, dev); 600 priv = netdev_priv(ndev); 601 602 /* The EZ NET specific entries in the device structure. */ 603 ndev->netdev_ops = &nps_netdev_ops; 604 ndev->watchdog_timeo = (400 * HZ / 1000); 605 /* FIXME :: no multicast support yet */ 606 ndev->flags &= ~IFF_MULTICAST; 607 608 res_regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 609 priv->regs_base = devm_ioremap_resource(dev, res_regs); 610 if (IS_ERR(priv->regs_base)) { 611 err = PTR_ERR(priv->regs_base); 612 goto out_netdev; 613 } 614 dev_dbg(dev, "Registers base address is 0x%p\n", priv->regs_base); 615 616 /* set kernel MAC address to dev */ 617 mac_addr = of_get_mac_address(dev->of_node); 618 if (mac_addr) 619 ether_addr_copy(ndev->dev_addr, mac_addr); 620 else 621 eth_hw_addr_random(ndev); 622 623 /* Get IRQ number */ 624 priv->irq = platform_get_irq(pdev, 0); 625 if (!priv->irq) { 626 dev_err(dev, "failed to retrieve <irq Rx-Tx> value from device tree\n"); 627 err = -ENODEV; 628 goto out_netdev; 629 } 630 631 netif_napi_add(ndev, &priv->napi, nps_enet_poll, 632 NPS_ENET_NAPI_POLL_WEIGHT); 633 634 /* Register the driver. Should be the last thing in probe */ 635 err = register_netdev(ndev); 636 if (err) { 637 dev_err(dev, "Failed to register ndev for %s, err = 0x%08x\n", 638 ndev->name, (s32)err); 639 goto out_netif_api; 640 } 641 642 dev_info(dev, "(rx/tx=%d)\n", priv->irq); 643 return 0; 644 645 out_netif_api: 646 netif_napi_del(&priv->napi); 647 out_netdev: 648 if (err) 649 free_netdev(ndev); 650 651 return err; 652 } 653 654 static s32 nps_enet_remove(struct platform_device *pdev) 655 { 656 struct net_device *ndev = platform_get_drvdata(pdev); 657 struct nps_enet_priv *priv = netdev_priv(ndev); 658 659 unregister_netdev(ndev); 660 free_netdev(ndev); 661 netif_napi_del(&priv->napi); 662 663 return 0; 664 } 665 666 static const struct of_device_id nps_enet_dt_ids[] = { 667 { .compatible = "ezchip,nps-mgt-enet" }, 668 { /* Sentinel */ } 669 }; 670 671 static struct platform_driver nps_enet_driver = { 672 .probe = nps_enet_probe, 673 .remove = nps_enet_remove, 674 .driver = { 675 .name = DRV_NAME, 676 .of_match_table = nps_enet_dt_ids, 677 }, 678 }; 679 680 module_platform_driver(nps_enet_driver); 681 682 MODULE_AUTHOR("EZchip Semiconductor"); 683 MODULE_LICENSE("GPL v2"); 684