1 /* 2 * Copyright (C) 2005 - 2015 Emulex 3 * All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License version 2 7 * as published by the Free Software Foundation. The full GNU General 8 * Public License is included in this distribution in the file called COPYING. 9 * 10 * Contact Information: 11 * linux-drivers@emulex.com 12 * 13 * Emulex 14 * 3333 Susan Street 15 * Costa Mesa, CA 92626 16 */ 17 18 /********* Mailbox door bell *************/ 19 /* Used for driver communication with the FW. 20 * The software must write this register twice to post any command. First, 21 * it writes the register with hi=1 and the upper bits of the physical address 22 * for the MAILBOX structure. Software must poll the ready bit until this 23 * is acknowledged. Then, sotware writes the register with hi=0 with the lower 24 * bits in the address. It must poll the ready bit until the command is 25 * complete. Upon completion, the MAILBOX will contain a valid completion 26 * queue entry. 27 */ 28 #define MPU_MAILBOX_DB_OFFSET 0x160 29 #define MPU_MAILBOX_DB_RDY_MASK 0x1 /* bit 0 */ 30 #define MPU_MAILBOX_DB_HI_MASK 0x2 /* bit 1 */ 31 32 #define MPU_EP_CONTROL 0 33 34 /********** MPU semphore: used for SH & BE *************/ 35 #define SLIPORT_SEMAPHORE_OFFSET_BEx 0xac /* CSR BAR offset */ 36 #define SLIPORT_SEMAPHORE_OFFSET_SH 0x94 /* PCI-CFG offset */ 37 #define POST_STAGE_MASK 0x0000FFFF 38 #define POST_ERR_MASK 0x1 39 #define POST_ERR_SHIFT 31 40 41 /* MPU semphore POST stage values */ 42 #define POST_STAGE_AWAITING_HOST_RDY 0x1 /* FW awaiting goahead from host */ 43 #define POST_STAGE_HOST_RDY 0x2 /* Host has given go-ahed to FW */ 44 #define POST_STAGE_BE_RESET 0x3 /* Host wants to reset chip */ 45 #define POST_STAGE_ARMFW_RDY 0xc000 /* FW is done with POST */ 46 47 48 /* Lancer SLIPORT registers */ 49 #define SLIPORT_STATUS_OFFSET 0x404 50 #define SLIPORT_CONTROL_OFFSET 0x408 51 #define SLIPORT_ERROR1_OFFSET 0x40C 52 #define SLIPORT_ERROR2_OFFSET 0x410 53 #define PHYSDEV_CONTROL_OFFSET 0x414 54 55 #define SLIPORT_STATUS_ERR_MASK 0x80000000 56 #define SLIPORT_STATUS_DIP_MASK 0x02000000 57 #define SLIPORT_STATUS_RN_MASK 0x01000000 58 #define SLIPORT_STATUS_RDY_MASK 0x00800000 59 #define SLI_PORT_CONTROL_IP_MASK 0x08000000 60 #define PHYSDEV_CONTROL_FW_RESET_MASK 0x00000002 61 #define PHYSDEV_CONTROL_DD_MASK 0x00000004 62 #define PHYSDEV_CONTROL_INP_MASK 0x40000000 63 64 #define SLIPORT_ERROR_NO_RESOURCE1 0x2 65 #define SLIPORT_ERROR_NO_RESOURCE2 0x9 66 67 #define SLIPORT_ERROR_FW_RESET1 0x2 68 #define SLIPORT_ERROR_FW_RESET2 0x0 69 70 /********* Memory BAR register ************/ 71 #define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET 0xfc 72 /* Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt 73 * Disable" may still globally block interrupts in addition to individual 74 * interrupt masks; a mechanism for the device driver to block all interrupts 75 * atomically without having to arbitrate for the PCI Interrupt Disable bit 76 * with the OS. 77 */ 78 #define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK BIT(29) /* bit 29 */ 79 80 /********* PCI Function Capability *********/ 81 #define BE_FUNCTION_CAPS_RSS 0x2 82 #define BE_FUNCTION_CAPS_SUPER_NIC 0x40 83 84 /********* Power management (WOL) **********/ 85 #define PCICFG_PM_CONTROL_OFFSET 0x44 86 #define PCICFG_PM_CONTROL_MASK 0x108 /* bits 3 & 8 */ 87 88 /********* Online Control Registers *******/ 89 #define PCICFG_ONLINE0 0xB0 90 #define PCICFG_ONLINE1 0xB4 91 92 /********* UE Status and Mask Registers ***/ 93 #define PCICFG_UE_STATUS_LOW 0xA0 94 #define PCICFG_UE_STATUS_HIGH 0xA4 95 #define PCICFG_UE_STATUS_LOW_MASK 0xA8 96 #define PCICFG_UE_STATUS_HI_MASK 0xAC 97 98 /******** SLI_INTF ***********************/ 99 #define SLI_INTF_REG_OFFSET 0x58 100 #define SLI_INTF_VALID_MASK 0xE0000000 101 #define SLI_INTF_VALID 0xC0000000 102 #define SLI_INTF_HINT2_MASK 0x1F000000 103 #define SLI_INTF_HINT2_SHIFT 24 104 #define SLI_INTF_HINT1_MASK 0x00FF0000 105 #define SLI_INTF_HINT1_SHIFT 16 106 #define SLI_INTF_FAMILY_MASK 0x00000F00 107 #define SLI_INTF_FAMILY_SHIFT 8 108 #define SLI_INTF_IF_TYPE_MASK 0x0000F000 109 #define SLI_INTF_IF_TYPE_SHIFT 12 110 #define SLI_INTF_REV_MASK 0x000000F0 111 #define SLI_INTF_REV_SHIFT 4 112 #define SLI_INTF_FT_MASK 0x00000001 113 114 #define SLI_INTF_TYPE_2 2 115 #define SLI_INTF_TYPE_3 3 116 117 /********* ISR0 Register offset **********/ 118 #define CEV_ISR0_OFFSET 0xC18 119 #define CEV_ISR_SIZE 4 120 121 /********* Event Q door bell *************/ 122 #define DB_EQ_OFFSET DB_CQ_OFFSET 123 #define DB_EQ_RING_ID_MASK 0x1FF /* bits 0 - 8 */ 124 #define DB_EQ_RING_ID_EXT_MASK 0x3e00 /* bits 9-13 */ 125 #define DB_EQ_RING_ID_EXT_MASK_SHIFT (2) /* qid bits 9-13 placing at 11-15 */ 126 127 /* Clear the interrupt for this eq */ 128 #define DB_EQ_CLR_SHIFT (9) /* bit 9 */ 129 /* Must be 1 */ 130 #define DB_EQ_EVNT_SHIFT (10) /* bit 10 */ 131 /* Number of event entries processed */ 132 #define DB_EQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */ 133 /* Rearm bit */ 134 #define DB_EQ_REARM_SHIFT (29) /* bit 29 */ 135 /* Rearm to interrupt delay encoding */ 136 #define DB_EQ_R2I_DLY_SHIFT (30) /* bits 30 - 31 */ 137 138 /* Rearm to interrupt (R2I) delay multiplier encoding represents 3 different 139 * values configured in CEV_REARM2IRPT_DLY_MULT_CSR register. This value is 140 * programmed by host driver while ringing an EQ doorbell(EQ_DB) if a delay 141 * between rearming the EQ and next interrupt on this EQ is desired. 142 */ 143 #define R2I_DLY_ENC_0 0 /* No delay */ 144 #define R2I_DLY_ENC_1 1 /* maps to 160us EQ delay */ 145 #define R2I_DLY_ENC_2 2 /* maps to 96us EQ delay */ 146 #define R2I_DLY_ENC_3 3 /* maps to 48us EQ delay */ 147 148 /********* Compl Q door bell *************/ 149 #define DB_CQ_OFFSET 0x120 150 #define DB_CQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */ 151 #define DB_CQ_RING_ID_EXT_MASK 0x7C00 /* bits 10-14 */ 152 #define DB_CQ_RING_ID_EXT_MASK_SHIFT (1) /* qid bits 10-14 153 placing at 11-15 */ 154 155 /* Number of event entries processed */ 156 #define DB_CQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */ 157 /* Rearm bit */ 158 #define DB_CQ_REARM_SHIFT (29) /* bit 29 */ 159 160 /********** TX ULP door bell *************/ 161 #define DB_TXULP1_OFFSET 0x60 162 #define DB_TXULP_RING_ID_MASK 0x7FF /* bits 0 - 10 */ 163 /* Number of tx entries posted */ 164 #define DB_TXULP_NUM_POSTED_SHIFT (16) /* bits 16 - 29 */ 165 #define DB_TXULP_NUM_POSTED_MASK 0x3FFF /* bits 16 - 29 */ 166 167 /********** RQ(erx) door bell ************/ 168 #define DB_RQ_OFFSET 0x100 169 #define DB_RQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */ 170 /* Number of rx frags posted */ 171 #define DB_RQ_NUM_POSTED_SHIFT (24) /* bits 24 - 31 */ 172 173 /********** MCC door bell ************/ 174 #define DB_MCCQ_OFFSET 0x140 175 #define DB_MCCQ_RING_ID_MASK 0x7FF /* bits 0 - 10 */ 176 /* Number of entries posted */ 177 #define DB_MCCQ_NUM_POSTED_SHIFT (16) /* bits 16 - 29 */ 178 179 /********** SRIOV VF PCICFG OFFSET ********/ 180 #define SRIOV_VF_PCICFG_OFFSET (4096) 181 182 /********** FAT TABLE ********/ 183 #define RETRIEVE_FAT 0 184 #define QUERY_FAT 1 185 186 /************* Rx Packet Type Encoding **************/ 187 #define BE_UNICAST_PACKET 0 188 #define BE_MULTICAST_PACKET 1 189 #define BE_BROADCAST_PACKET 2 190 #define BE_RSVD_PACKET 3 191 192 /* 193 * BE descriptors: host memory data structures whose formats 194 * are hardwired in BE silicon. 195 */ 196 /* Event Queue Descriptor */ 197 #define EQ_ENTRY_VALID_MASK 0x1 /* bit 0 */ 198 #define EQ_ENTRY_RES_ID_MASK 0xFFFF /* bits 16 - 31 */ 199 #define EQ_ENTRY_RES_ID_SHIFT 16 200 201 struct be_eq_entry { 202 u32 evt; 203 }; 204 205 /* TX Queue Descriptor */ 206 #define ETH_WRB_FRAG_LEN_MASK 0xFFFF 207 struct be_eth_wrb { 208 __le32 frag_pa_hi; /* dword 0 */ 209 __le32 frag_pa_lo; /* dword 1 */ 210 u32 rsvd0; /* dword 2 */ 211 __le32 frag_len; /* dword 3: bits 0 - 15 */ 212 } __packed; 213 214 /* Pseudo amap definition for eth_hdr_wrb in which each bit of the 215 * actual structure is defined as a byte : used to calculate 216 * offset/shift/mask of each field */ 217 struct amap_eth_hdr_wrb { 218 u8 rsvd0[32]; /* dword 0 */ 219 u8 rsvd1[32]; /* dword 1 */ 220 u8 complete; /* dword 2 */ 221 u8 event; 222 u8 crc; 223 u8 forward; 224 u8 lso6; 225 u8 mgmt; 226 u8 ipcs; 227 u8 udpcs; 228 u8 tcpcs; 229 u8 lso; 230 u8 vlan; 231 u8 gso[2]; 232 u8 num_wrb[5]; 233 u8 lso_mss[14]; 234 u8 len[16]; /* dword 3 */ 235 u8 vlan_tag[16]; 236 } __packed; 237 238 #define TX_HDR_WRB_COMPL 1 /* word 2 */ 239 #define TX_HDR_WRB_EVT BIT(1) /* word 2 */ 240 #define TX_HDR_WRB_NUM_SHIFT 13 /* word 2: bits 13:17 */ 241 #define TX_HDR_WRB_NUM_MASK 0x1F /* word 2: bits 13:17 */ 242 243 struct be_eth_hdr_wrb { 244 __le32 dw[4]; 245 }; 246 247 /********* Tx Compl Status Encoding *********/ 248 #define BE_TX_COMP_HDR_PARSE_ERR 0x2 249 #define BE_TX_COMP_NDMA_ERR 0x3 250 #define BE_TX_COMP_ACL_ERR 0x5 251 252 #define LANCER_TX_COMP_LSO_ERR 0x1 253 #define LANCER_TX_COMP_HSW_DROP_MAC_ERR 0x3 254 #define LANCER_TX_COMP_HSW_DROP_VLAN_ERR 0x5 255 #define LANCER_TX_COMP_QINQ_ERR 0x7 256 #define LANCER_TX_COMP_PARITY_ERR 0xb 257 #define LANCER_TX_COMP_DMA_ERR 0xd 258 259 /* TX Compl Queue Descriptor */ 260 261 /* Pseudo amap definition for eth_tx_compl in which each bit of the 262 * actual structure is defined as a byte: used to calculate 263 * offset/shift/mask of each field */ 264 struct amap_eth_tx_compl { 265 u8 wrb_index[16]; /* dword 0 */ 266 u8 ct[2]; /* dword 0 */ 267 u8 port[2]; /* dword 0 */ 268 u8 rsvd0[8]; /* dword 0 */ 269 u8 status[4]; /* dword 0 */ 270 u8 user_bytes[16]; /* dword 1 */ 271 u8 nwh_bytes[8]; /* dword 1 */ 272 u8 lso; /* dword 1 */ 273 u8 cast_enc[2]; /* dword 1 */ 274 u8 rsvd1[5]; /* dword 1 */ 275 u8 rsvd2[32]; /* dword 2 */ 276 u8 pkts[16]; /* dword 3 */ 277 u8 ringid[11]; /* dword 3 */ 278 u8 hash_val[4]; /* dword 3 */ 279 u8 valid; /* dword 3 */ 280 } __packed; 281 282 struct be_eth_tx_compl { 283 u32 dw[4]; 284 }; 285 286 /* RX Queue Descriptor */ 287 struct be_eth_rx_d { 288 u32 fragpa_hi; 289 u32 fragpa_lo; 290 }; 291 292 /* RX Compl Queue Descriptor */ 293 294 /* Pseudo amap definition for BE2 and BE3 legacy mode eth_rx_compl in which 295 * each bit of the actual structure is defined as a byte: used to calculate 296 * offset/shift/mask of each field */ 297 struct amap_eth_rx_compl_v0 { 298 u8 vlan_tag[16]; /* dword 0 */ 299 u8 pktsize[14]; /* dword 0 */ 300 u8 port; /* dword 0 */ 301 u8 ip_opt; /* dword 0 */ 302 u8 err; /* dword 1 */ 303 u8 rsshp; /* dword 1 */ 304 u8 ipf; /* dword 1 */ 305 u8 tcpf; /* dword 1 */ 306 u8 udpf; /* dword 1 */ 307 u8 ipcksm; /* dword 1 */ 308 u8 l4_cksm; /* dword 1 */ 309 u8 ip_version; /* dword 1 */ 310 u8 macdst[6]; /* dword 1 */ 311 u8 vtp; /* dword 1 */ 312 u8 ip_frag; /* dword 1 */ 313 u8 fragndx[10]; /* dword 1 */ 314 u8 ct[2]; /* dword 1 */ 315 u8 sw; /* dword 1 */ 316 u8 numfrags[3]; /* dword 1 */ 317 u8 rss_flush; /* dword 2 */ 318 u8 cast_enc[2]; /* dword 2 */ 319 u8 qnq; /* dword 2 */ 320 u8 rss_bank; /* dword 2 */ 321 u8 rsvd1[23]; /* dword 2 */ 322 u8 lro_pkt; /* dword 2 */ 323 u8 rsvd2[2]; /* dword 2 */ 324 u8 valid; /* dword 2 */ 325 u8 rsshash[32]; /* dword 3 */ 326 } __packed; 327 328 /* Pseudo amap definition for BE3 native mode eth_rx_compl in which 329 * each bit of the actual structure is defined as a byte: used to calculate 330 * offset/shift/mask of each field */ 331 struct amap_eth_rx_compl_v1 { 332 u8 vlan_tag[16]; /* dword 0 */ 333 u8 pktsize[14]; /* dword 0 */ 334 u8 vtp; /* dword 0 */ 335 u8 ip_opt; /* dword 0 */ 336 u8 err; /* dword 1 */ 337 u8 rsshp; /* dword 1 */ 338 u8 ipf; /* dword 1 */ 339 u8 tcpf; /* dword 1 */ 340 u8 udpf; /* dword 1 */ 341 u8 ipcksm; /* dword 1 */ 342 u8 l4_cksm; /* dword 1 */ 343 u8 ip_version; /* dword 1 */ 344 u8 macdst[7]; /* dword 1 */ 345 u8 rsvd0; /* dword 1 */ 346 u8 fragndx[10]; /* dword 1 */ 347 u8 ct[2]; /* dword 1 */ 348 u8 sw; /* dword 1 */ 349 u8 numfrags[3]; /* dword 1 */ 350 u8 rss_flush; /* dword 2 */ 351 u8 cast_enc[2]; /* dword 2 */ 352 u8 qnq; /* dword 2 */ 353 u8 rss_bank; /* dword 2 */ 354 u8 port[2]; /* dword 2 */ 355 u8 vntagp; /* dword 2 */ 356 u8 header_len[8]; /* dword 2 */ 357 u8 header_split[2]; /* dword 2 */ 358 u8 rsvd1[12]; /* dword 2 */ 359 u8 tunneled; 360 u8 valid; /* dword 2 */ 361 u8 rsshash[32]; /* dword 3 */ 362 } __packed; 363 364 struct be_eth_rx_compl { 365 u32 dw[4]; 366 }; 367