1 /* 2 * Copyright (C) 2005 - 2011 Emulex 3 * All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License version 2 7 * as published by the Free Software Foundation. The full GNU General 8 * Public License is included in this distribution in the file called COPYING. 9 * 10 * Contact Information: 11 * linux-drivers@emulex.com 12 * 13 * Emulex 14 * 3333 Susan Street 15 * Costa Mesa, CA 92626 16 */ 17 18 /********* Mailbox door bell *************/ 19 /* Used for driver communication with the FW. 20 * The software must write this register twice to post any command. First, 21 * it writes the register with hi=1 and the upper bits of the physical address 22 * for the MAILBOX structure. Software must poll the ready bit until this 23 * is acknowledged. Then, sotware writes the register with hi=0 with the lower 24 * bits in the address. It must poll the ready bit until the command is 25 * complete. Upon completion, the MAILBOX will contain a valid completion 26 * queue entry. 27 */ 28 #define MPU_MAILBOX_DB_OFFSET 0x160 29 #define MPU_MAILBOX_DB_RDY_MASK 0x1 /* bit 0 */ 30 #define MPU_MAILBOX_DB_HI_MASK 0x2 /* bit 1 */ 31 32 #define MPU_EP_CONTROL 0 33 34 /********** MPU semphore: used for SH & BE *************/ 35 #define SLIPORT_SEMAPHORE_OFFSET_BE 0x7c 36 #define SLIPORT_SEMAPHORE_OFFSET_SH 0x94 37 #define POST_STAGE_MASK 0x0000FFFF 38 #define POST_ERR_MASK 0x1 39 #define POST_ERR_SHIFT 31 40 41 /* MPU semphore POST stage values */ 42 #define POST_STAGE_AWAITING_HOST_RDY 0x1 /* FW awaiting goahead from host */ 43 #define POST_STAGE_HOST_RDY 0x2 /* Host has given go-ahed to FW */ 44 #define POST_STAGE_BE_RESET 0x3 /* Host wants to reset chip */ 45 #define POST_STAGE_ARMFW_RDY 0xc000 /* FW is done with POST */ 46 47 48 /* Lancer SLIPORT registers */ 49 #define SLIPORT_STATUS_OFFSET 0x404 50 #define SLIPORT_CONTROL_OFFSET 0x408 51 #define SLIPORT_ERROR1_OFFSET 0x40C 52 #define SLIPORT_ERROR2_OFFSET 0x410 53 #define PHYSDEV_CONTROL_OFFSET 0x414 54 55 #define SLIPORT_STATUS_ERR_MASK 0x80000000 56 #define SLIPORT_STATUS_RN_MASK 0x01000000 57 #define SLIPORT_STATUS_RDY_MASK 0x00800000 58 #define SLI_PORT_CONTROL_IP_MASK 0x08000000 59 #define PHYSDEV_CONTROL_FW_RESET_MASK 0x00000002 60 #define PHYSDEV_CONTROL_INP_MASK 0x40000000 61 62 #define SLIPORT_ERROR_NO_RESOURCE1 0x2 63 #define SLIPORT_ERROR_NO_RESOURCE2 0x9 64 65 /********* Memory BAR register ************/ 66 #define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET 0xfc 67 /* Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt 68 * Disable" may still globally block interrupts in addition to individual 69 * interrupt masks; a mechanism for the device driver to block all interrupts 70 * atomically without having to arbitrate for the PCI Interrupt Disable bit 71 * with the OS. 72 */ 73 #define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK (1 << 29) /* bit 29 */ 74 75 /********* Power management (WOL) **********/ 76 #define PCICFG_PM_CONTROL_OFFSET 0x44 77 #define PCICFG_PM_CONTROL_MASK 0x108 /* bits 3 & 8 */ 78 79 /********* Online Control Registers *******/ 80 #define PCICFG_ONLINE0 0xB0 81 #define PCICFG_ONLINE1 0xB4 82 83 /********* UE Status and Mask Registers ***/ 84 #define PCICFG_UE_STATUS_LOW 0xA0 85 #define PCICFG_UE_STATUS_HIGH 0xA4 86 #define PCICFG_UE_STATUS_LOW_MASK 0xA8 87 #define PCICFG_UE_STATUS_HI_MASK 0xAC 88 89 /******** SLI_INTF ***********************/ 90 #define SLI_INTF_REG_OFFSET 0x58 91 #define SLI_INTF_VALID_MASK 0xE0000000 92 #define SLI_INTF_VALID 0xC0000000 93 #define SLI_INTF_HINT2_MASK 0x1F000000 94 #define SLI_INTF_HINT2_SHIFT 24 95 #define SLI_INTF_HINT1_MASK 0x00FF0000 96 #define SLI_INTF_HINT1_SHIFT 16 97 #define SLI_INTF_FAMILY_MASK 0x00000F00 98 #define SLI_INTF_FAMILY_SHIFT 8 99 #define SLI_INTF_IF_TYPE_MASK 0x0000F000 100 #define SLI_INTF_IF_TYPE_SHIFT 12 101 #define SLI_INTF_REV_MASK 0x000000F0 102 #define SLI_INTF_REV_SHIFT 4 103 #define SLI_INTF_FT_MASK 0x00000001 104 105 #define SLI_INTF_TYPE_2 2 106 #define SLI_INTF_TYPE_3 3 107 108 /********* ISR0 Register offset **********/ 109 #define CEV_ISR0_OFFSET 0xC18 110 #define CEV_ISR_SIZE 4 111 112 /********* Event Q door bell *************/ 113 #define DB_EQ_OFFSET DB_CQ_OFFSET 114 #define DB_EQ_RING_ID_MASK 0x1FF /* bits 0 - 8 */ 115 #define DB_EQ_RING_ID_EXT_MASK 0x3e00 /* bits 9-13 */ 116 #define DB_EQ_RING_ID_EXT_MASK_SHIFT (2) /* qid bits 9-13 placing at 11-15 */ 117 118 /* Clear the interrupt for this eq */ 119 #define DB_EQ_CLR_SHIFT (9) /* bit 9 */ 120 /* Must be 1 */ 121 #define DB_EQ_EVNT_SHIFT (10) /* bit 10 */ 122 /* Number of event entries processed */ 123 #define DB_EQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */ 124 /* Rearm bit */ 125 #define DB_EQ_REARM_SHIFT (29) /* bit 29 */ 126 127 /********* Compl Q door bell *************/ 128 #define DB_CQ_OFFSET 0x120 129 #define DB_CQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */ 130 #define DB_CQ_RING_ID_EXT_MASK 0x7C00 /* bits 10-14 */ 131 #define DB_CQ_RING_ID_EXT_MASK_SHIFT (1) /* qid bits 10-14 132 placing at 11-15 */ 133 134 /* Number of event entries processed */ 135 #define DB_CQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */ 136 /* Rearm bit */ 137 #define DB_CQ_REARM_SHIFT (29) /* bit 29 */ 138 139 /********** TX ULP door bell *************/ 140 #define DB_TXULP1_OFFSET 0x60 141 #define DB_TXULP_RING_ID_MASK 0x7FF /* bits 0 - 10 */ 142 /* Number of tx entries posted */ 143 #define DB_TXULP_NUM_POSTED_SHIFT (16) /* bits 16 - 29 */ 144 #define DB_TXULP_NUM_POSTED_MASK 0x3FFF /* bits 16 - 29 */ 145 146 /********** RQ(erx) door bell ************/ 147 #define DB_RQ_OFFSET 0x100 148 #define DB_RQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */ 149 /* Number of rx frags posted */ 150 #define DB_RQ_NUM_POSTED_SHIFT (24) /* bits 24 - 31 */ 151 152 /********** MCC door bell ************/ 153 #define DB_MCCQ_OFFSET 0x140 154 #define DB_MCCQ_RING_ID_MASK 0x7FF /* bits 0 - 10 */ 155 /* Number of entries posted */ 156 #define DB_MCCQ_NUM_POSTED_SHIFT (16) /* bits 16 - 29 */ 157 158 /********** SRIOV VF PCICFG OFFSET ********/ 159 #define SRIOV_VF_PCICFG_OFFSET (4096) 160 161 /********** FAT TABLE ********/ 162 #define RETRIEVE_FAT 0 163 #define QUERY_FAT 1 164 165 /* Flashrom related descriptors */ 166 #define MAX_FLASH_COMP 32 167 #define IMAGE_TYPE_FIRMWARE 160 168 #define IMAGE_TYPE_BOOTCODE 224 169 #define IMAGE_TYPE_OPTIONROM 32 170 171 #define NUM_FLASHDIR_ENTRIES 32 172 173 #define OPTYPE_ISCSI_ACTIVE 0 174 #define OPTYPE_REDBOOT 1 175 #define OPTYPE_BIOS 2 176 #define OPTYPE_PXE_BIOS 3 177 #define OPTYPE_FCOE_BIOS 8 178 #define OPTYPE_ISCSI_BACKUP 9 179 #define OPTYPE_FCOE_FW_ACTIVE 10 180 #define OPTYPE_FCOE_FW_BACKUP 11 181 #define OPTYPE_NCSI_FW 13 182 #define OPTYPE_PHY_FW 99 183 #define TN_8022 13 184 185 #define ILLEGAL_IOCTL_REQ 2 186 #define FLASHROM_OPER_PHY_FLASH 9 187 #define FLASHROM_OPER_PHY_SAVE 10 188 #define FLASHROM_OPER_FLASH 1 189 #define FLASHROM_OPER_SAVE 2 190 #define FLASHROM_OPER_REPORT 4 191 192 #define FLASH_IMAGE_MAX_SIZE_g2 (1310720) /* Max firmware image size */ 193 #define FLASH_BIOS_IMAGE_MAX_SIZE_g2 (262144) /* Max OPTION ROM image sz */ 194 #define FLASH_REDBOOT_IMAGE_MAX_SIZE_g2 (262144) /* Max Redboot image sz */ 195 #define FLASH_IMAGE_MAX_SIZE_g3 (2097152) /* Max firmware image size */ 196 #define FLASH_BIOS_IMAGE_MAX_SIZE_g3 (524288) /* Max OPTION ROM image sz */ 197 #define FLASH_REDBOOT_IMAGE_MAX_SIZE_g3 (1048576) /* Max Redboot image sz */ 198 #define FLASH_NCSI_IMAGE_MAX_SIZE_g3 (262144) 199 #define FLASH_PHY_FW_IMAGE_MAX_SIZE_g3 262144 200 201 #define FLASH_NCSI_MAGIC (0x16032009) 202 #define FLASH_NCSI_DISABLED (0) 203 #define FLASH_NCSI_ENABLED (1) 204 205 #define FLASH_NCSI_BITFILE_HDR_OFFSET (0x600000) 206 207 /* Offsets for components on Flash. */ 208 #define FLASH_iSCSI_PRIMARY_IMAGE_START_g2 (1048576) 209 #define FLASH_iSCSI_BACKUP_IMAGE_START_g2 (2359296) 210 #define FLASH_FCoE_PRIMARY_IMAGE_START_g2 (3670016) 211 #define FLASH_FCoE_BACKUP_IMAGE_START_g2 (4980736) 212 #define FLASH_iSCSI_BIOS_START_g2 (7340032) 213 #define FLASH_PXE_BIOS_START_g2 (7864320) 214 #define FLASH_FCoE_BIOS_START_g2 (524288) 215 #define FLASH_REDBOOT_START_g2 (0) 216 217 #define FLASH_NCSI_START_g3 (15990784) 218 #define FLASH_iSCSI_PRIMARY_IMAGE_START_g3 (2097152) 219 #define FLASH_iSCSI_BACKUP_IMAGE_START_g3 (4194304) 220 #define FLASH_FCoE_PRIMARY_IMAGE_START_g3 (6291456) 221 #define FLASH_FCoE_BACKUP_IMAGE_START_g3 (8388608) 222 #define FLASH_iSCSI_BIOS_START_g3 (12582912) 223 #define FLASH_PXE_BIOS_START_g3 (13107200) 224 #define FLASH_FCoE_BIOS_START_g3 (13631488) 225 #define FLASH_REDBOOT_START_g3 (262144) 226 #define FLASH_PHY_FW_START_g3 1310720 227 228 #define IMAGE_NCSI 16 229 #define IMAGE_OPTION_ROM_PXE 32 230 #define IMAGE_OPTION_ROM_FCoE 33 231 #define IMAGE_OPTION_ROM_ISCSI 34 232 #define IMAGE_FLASHISM_JUMPVECTOR 48 233 #define IMAGE_FLASH_ISM 49 234 #define IMAGE_JUMP_VECTOR 50 235 #define IMAGE_FIRMWARE_iSCSI 160 236 #define IMAGE_FIRMWARE_COMP_iSCSI 161 237 #define IMAGE_FIRMWARE_FCoE 162 238 #define IMAGE_FIRMWARE_COMP_FCoE 163 239 #define IMAGE_FIRMWARE_BACKUP_iSCSI 176 240 #define IMAGE_FIRMWARE_BACKUP_COMP_iSCSI 177 241 #define IMAGE_FIRMWARE_BACKUP_FCoE 178 242 #define IMAGE_FIRMWARE_BACKUP_COMP_FCoE 179 243 #define IMAGE_FIRMWARE_PHY 192 244 #define IMAGE_BOOT_CODE 224 245 246 /************* Rx Packet Type Encoding **************/ 247 #define BE_UNICAST_PACKET 0 248 #define BE_MULTICAST_PACKET 1 249 #define BE_BROADCAST_PACKET 2 250 #define BE_RSVD_PACKET 3 251 252 /* 253 * BE descriptors: host memory data structures whose formats 254 * are hardwired in BE silicon. 255 */ 256 /* Event Queue Descriptor */ 257 #define EQ_ENTRY_VALID_MASK 0x1 /* bit 0 */ 258 #define EQ_ENTRY_RES_ID_MASK 0xFFFF /* bits 16 - 31 */ 259 #define EQ_ENTRY_RES_ID_SHIFT 16 260 261 struct be_eq_entry { 262 u32 evt; 263 }; 264 265 /* TX Queue Descriptor */ 266 #define ETH_WRB_FRAG_LEN_MASK 0xFFFF 267 struct be_eth_wrb { 268 u32 frag_pa_hi; /* dword 0 */ 269 u32 frag_pa_lo; /* dword 1 */ 270 u32 rsvd0; /* dword 2 */ 271 u32 frag_len; /* dword 3: bits 0 - 15 */ 272 } __packed; 273 274 /* Pseudo amap definition for eth_hdr_wrb in which each bit of the 275 * actual structure is defined as a byte : used to calculate 276 * offset/shift/mask of each field */ 277 struct amap_eth_hdr_wrb { 278 u8 rsvd0[32]; /* dword 0 */ 279 u8 rsvd1[32]; /* dword 1 */ 280 u8 complete; /* dword 2 */ 281 u8 event; 282 u8 crc; 283 u8 forward; 284 u8 lso6; 285 u8 mgmt; 286 u8 ipcs; 287 u8 udpcs; 288 u8 tcpcs; 289 u8 lso; 290 u8 vlan; 291 u8 gso[2]; 292 u8 num_wrb[5]; 293 u8 lso_mss[14]; 294 u8 len[16]; /* dword 3 */ 295 u8 vlan_tag[16]; 296 } __packed; 297 298 struct be_eth_hdr_wrb { 299 u32 dw[4]; 300 }; 301 302 /* TX Compl Queue Descriptor */ 303 304 /* Pseudo amap definition for eth_tx_compl in which each bit of the 305 * actual structure is defined as a byte: used to calculate 306 * offset/shift/mask of each field */ 307 struct amap_eth_tx_compl { 308 u8 wrb_index[16]; /* dword 0 */ 309 u8 ct[2]; /* dword 0 */ 310 u8 port[2]; /* dword 0 */ 311 u8 rsvd0[8]; /* dword 0 */ 312 u8 status[4]; /* dword 0 */ 313 u8 user_bytes[16]; /* dword 1 */ 314 u8 nwh_bytes[8]; /* dword 1 */ 315 u8 lso; /* dword 1 */ 316 u8 cast_enc[2]; /* dword 1 */ 317 u8 rsvd1[5]; /* dword 1 */ 318 u8 rsvd2[32]; /* dword 2 */ 319 u8 pkts[16]; /* dword 3 */ 320 u8 ringid[11]; /* dword 3 */ 321 u8 hash_val[4]; /* dword 3 */ 322 u8 valid; /* dword 3 */ 323 } __packed; 324 325 struct be_eth_tx_compl { 326 u32 dw[4]; 327 }; 328 329 /* RX Queue Descriptor */ 330 struct be_eth_rx_d { 331 u32 fragpa_hi; 332 u32 fragpa_lo; 333 }; 334 335 /* RX Compl Queue Descriptor */ 336 337 /* Pseudo amap definition for BE2 and BE3 legacy mode eth_rx_compl in which 338 * each bit of the actual structure is defined as a byte: used to calculate 339 * offset/shift/mask of each field */ 340 struct amap_eth_rx_compl_v0 { 341 u8 vlan_tag[16]; /* dword 0 */ 342 u8 pktsize[14]; /* dword 0 */ 343 u8 port; /* dword 0 */ 344 u8 ip_opt; /* dword 0 */ 345 u8 err; /* dword 1 */ 346 u8 rsshp; /* dword 1 */ 347 u8 ipf; /* dword 1 */ 348 u8 tcpf; /* dword 1 */ 349 u8 udpf; /* dword 1 */ 350 u8 ipcksm; /* dword 1 */ 351 u8 l4_cksm; /* dword 1 */ 352 u8 ip_version; /* dword 1 */ 353 u8 macdst[6]; /* dword 1 */ 354 u8 vtp; /* dword 1 */ 355 u8 rsvd0; /* dword 1 */ 356 u8 fragndx[10]; /* dword 1 */ 357 u8 ct[2]; /* dword 1 */ 358 u8 sw; /* dword 1 */ 359 u8 numfrags[3]; /* dword 1 */ 360 u8 rss_flush; /* dword 2 */ 361 u8 cast_enc[2]; /* dword 2 */ 362 u8 vtm; /* dword 2 */ 363 u8 rss_bank; /* dword 2 */ 364 u8 rsvd1[23]; /* dword 2 */ 365 u8 lro_pkt; /* dword 2 */ 366 u8 rsvd2[2]; /* dword 2 */ 367 u8 valid; /* dword 2 */ 368 u8 rsshash[32]; /* dword 3 */ 369 } __packed; 370 371 /* Pseudo amap definition for BE3 native mode eth_rx_compl in which 372 * each bit of the actual structure is defined as a byte: used to calculate 373 * offset/shift/mask of each field */ 374 struct amap_eth_rx_compl_v1 { 375 u8 vlan_tag[16]; /* dword 0 */ 376 u8 pktsize[14]; /* dword 0 */ 377 u8 vtp; /* dword 0 */ 378 u8 ip_opt; /* dword 0 */ 379 u8 err; /* dword 1 */ 380 u8 rsshp; /* dword 1 */ 381 u8 ipf; /* dword 1 */ 382 u8 tcpf; /* dword 1 */ 383 u8 udpf; /* dword 1 */ 384 u8 ipcksm; /* dword 1 */ 385 u8 l4_cksm; /* dword 1 */ 386 u8 ip_version; /* dword 1 */ 387 u8 macdst[7]; /* dword 1 */ 388 u8 rsvd0; /* dword 1 */ 389 u8 fragndx[10]; /* dword 1 */ 390 u8 ct[2]; /* dword 1 */ 391 u8 sw; /* dword 1 */ 392 u8 numfrags[3]; /* dword 1 */ 393 u8 rss_flush; /* dword 2 */ 394 u8 cast_enc[2]; /* dword 2 */ 395 u8 vtm; /* dword 2 */ 396 u8 rss_bank; /* dword 2 */ 397 u8 port[2]; /* dword 2 */ 398 u8 vntagp; /* dword 2 */ 399 u8 header_len[8]; /* dword 2 */ 400 u8 header_split[2]; /* dword 2 */ 401 u8 rsvd1[13]; /* dword 2 */ 402 u8 valid; /* dword 2 */ 403 u8 rsshash[32]; /* dword 3 */ 404 } __packed; 405 406 struct be_eth_rx_compl { 407 u32 dw[4]; 408 }; 409 410 struct mgmt_hba_attribs { 411 u8 flashrom_version_string[32]; 412 u8 manufacturer_name[32]; 413 u32 supported_modes; 414 u32 rsvd0[3]; 415 u8 ncsi_ver_string[12]; 416 u32 default_extended_timeout; 417 u8 controller_model_number[32]; 418 u8 controller_description[64]; 419 u8 controller_serial_number[32]; 420 u8 ip_version_string[32]; 421 u8 firmware_version_string[32]; 422 u8 bios_version_string[32]; 423 u8 redboot_version_string[32]; 424 u8 driver_version_string[32]; 425 u8 fw_on_flash_version_string[32]; 426 u32 functionalities_supported; 427 u16 max_cdblength; 428 u8 asic_revision; 429 u8 generational_guid[16]; 430 u8 hba_port_count; 431 u16 default_link_down_timeout; 432 u8 iscsi_ver_min_max; 433 u8 multifunction_device; 434 u8 cache_valid; 435 u8 hba_status; 436 u8 max_domains_supported; 437 u8 phy_port; 438 u32 firmware_post_status; 439 u32 hba_mtu[8]; 440 u32 rsvd1[4]; 441 }; 442 443 struct mgmt_controller_attrib { 444 struct mgmt_hba_attribs hba_attribs; 445 u16 pci_vendor_id; 446 u16 pci_device_id; 447 u16 pci_sub_vendor_id; 448 u16 pci_sub_system_id; 449 u8 pci_bus_number; 450 u8 pci_device_number; 451 u8 pci_function_number; 452 u8 interface_type; 453 u64 unique_identifier; 454 u32 rsvd0[5]; 455 }; 456 457 struct controller_id { 458 u32 vendor; 459 u32 device; 460 u32 subvendor; 461 u32 subdevice; 462 }; 463 464 struct flash_comp { 465 unsigned long offset; 466 int optype; 467 int size; 468 int img_type; 469 }; 470 471 struct image_hdr { 472 u32 imageid; 473 u32 imageoffset; 474 u32 imagelength; 475 u32 image_checksum; 476 u8 image_version[32]; 477 }; 478 struct flash_file_hdr_g2 { 479 u8 sign[32]; 480 u32 cksum; 481 u32 antidote; 482 struct controller_id cont_id; 483 u32 file_len; 484 u32 chunk_num; 485 u32 total_chunks; 486 u32 num_imgs; 487 u8 build[24]; 488 }; 489 490 struct flash_file_hdr_g3 { 491 u8 sign[52]; 492 u8 ufi_version[4]; 493 u32 file_len; 494 u32 cksum; 495 u32 antidote; 496 u32 num_imgs; 497 u8 build[24]; 498 u8 rsvd[32]; 499 }; 500 501 struct flash_section_hdr { 502 u32 format_rev; 503 u32 cksum; 504 u32 antidote; 505 u32 num_images; 506 u8 id_string[128]; 507 u32 rsvd[4]; 508 } __packed; 509 510 struct flash_section_hdr_g2 { 511 u32 format_rev; 512 u32 cksum; 513 u32 antidote; 514 u32 build_num; 515 u8 id_string[128]; 516 u32 rsvd[8]; 517 } __packed; 518 519 struct flash_section_entry { 520 u32 type; 521 u32 offset; 522 u32 pad_size; 523 u32 image_size; 524 u32 cksum; 525 u32 entry_point; 526 u32 rsvd0; 527 u32 rsvd1; 528 u8 ver_data[32]; 529 } __packed; 530 531 struct flash_section_info { 532 u8 cookie[32]; 533 struct flash_section_hdr fsec_hdr; 534 struct flash_section_entry fsec_entry[32]; 535 } __packed; 536 537 struct flash_section_info_g2 { 538 u8 cookie[32]; 539 struct flash_section_hdr_g2 fsec_hdr; 540 struct flash_section_entry fsec_entry[32]; 541 } __packed; 542