1 /* 2 * Copyright (C) 2005 - 2011 Emulex 3 * All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License version 2 7 * as published by the Free Software Foundation. The full GNU General 8 * Public License is included in this distribution in the file called COPYING. 9 * 10 * Contact Information: 11 * linux-drivers@emulex.com 12 * 13 * Emulex 14 * 3333 Susan Street 15 * Costa Mesa, CA 92626 16 */ 17 18 /* 19 * The driver sends configuration and managements command requests to the 20 * firmware in the BE. These requests are communicated to the processor 21 * using Work Request Blocks (WRBs) submitted to the MCC-WRB ring or via one 22 * WRB inside a MAILBOX. 23 * The commands are serviced by the ARM processor in the BladeEngine's MPU. 24 */ 25 26 struct be_sge { 27 u32 pa_lo; 28 u32 pa_hi; 29 u32 len; 30 }; 31 32 #define MCC_WRB_EMBEDDED_MASK 1 /* bit 0 of dword 0*/ 33 #define MCC_WRB_SGE_CNT_SHIFT 3 /* bits 3 - 7 of dword 0 */ 34 #define MCC_WRB_SGE_CNT_MASK 0x1F /* bits 3 - 7 of dword 0 */ 35 struct be_mcc_wrb { 36 u32 embedded; /* dword 0 */ 37 u32 payload_length; /* dword 1 */ 38 u32 tag0; /* dword 2 */ 39 u32 tag1; /* dword 3 */ 40 u32 rsvd; /* dword 4 */ 41 union { 42 u8 embedded_payload[236]; /* used by embedded cmds */ 43 struct be_sge sgl[19]; /* used by non-embedded cmds */ 44 } payload; 45 }; 46 47 #define CQE_FLAGS_VALID_MASK (1 << 31) 48 #define CQE_FLAGS_ASYNC_MASK (1 << 30) 49 #define CQE_FLAGS_COMPLETED_MASK (1 << 28) 50 #define CQE_FLAGS_CONSUMED_MASK (1 << 27) 51 52 /* Completion Status */ 53 enum { 54 MCC_STATUS_SUCCESS = 0, 55 MCC_STATUS_FAILED = 1, 56 MCC_STATUS_ILLEGAL_REQUEST = 2, 57 MCC_STATUS_ILLEGAL_FIELD = 3, 58 MCC_STATUS_INSUFFICIENT_BUFFER = 4, 59 MCC_STATUS_UNAUTHORIZED_REQUEST = 5, 60 MCC_STATUS_NOT_SUPPORTED = 66 61 }; 62 63 #define CQE_STATUS_COMPL_MASK 0xFFFF 64 #define CQE_STATUS_COMPL_SHIFT 0 /* bits 0 - 15 */ 65 #define CQE_STATUS_EXTD_MASK 0xFFFF 66 #define CQE_STATUS_EXTD_SHIFT 16 /* bits 16 - 31 */ 67 68 struct be_mcc_compl { 69 u32 status; /* dword 0 */ 70 u32 tag0; /* dword 1 */ 71 u32 tag1; /* dword 2 */ 72 u32 flags; /* dword 3 */ 73 }; 74 75 /* When the async bit of mcc_compl is set, the last 4 bytes of 76 * mcc_compl is interpreted as follows: 77 */ 78 #define ASYNC_TRAILER_EVENT_CODE_SHIFT 8 /* bits 8 - 15 */ 79 #define ASYNC_TRAILER_EVENT_CODE_MASK 0xFF 80 #define ASYNC_TRAILER_EVENT_TYPE_SHIFT 16 81 #define ASYNC_TRAILER_EVENT_TYPE_MASK 0xFF 82 #define ASYNC_EVENT_CODE_LINK_STATE 0x1 83 #define ASYNC_EVENT_CODE_GRP_5 0x5 84 #define ASYNC_EVENT_QOS_SPEED 0x1 85 #define ASYNC_EVENT_COS_PRIORITY 0x2 86 #define ASYNC_EVENT_PVID_STATE 0x3 87 struct be_async_event_trailer { 88 u32 code; 89 }; 90 91 enum { 92 LINK_DOWN = 0x0, 93 LINK_UP = 0x1 94 }; 95 #define LINK_STATUS_MASK 0x1 96 97 /* When the event code of an async trailer is link-state, the mcc_compl 98 * must be interpreted as follows 99 */ 100 struct be_async_event_link_state { 101 u8 physical_port; 102 u8 port_link_status; 103 u8 port_duplex; 104 u8 port_speed; 105 u8 port_fault; 106 u8 rsvd0[7]; 107 struct be_async_event_trailer trailer; 108 } __packed; 109 110 /* When the event code of an async trailer is GRP-5 and event_type is QOS_SPEED 111 * the mcc_compl must be interpreted as follows 112 */ 113 struct be_async_event_grp5_qos_link_speed { 114 u8 physical_port; 115 u8 rsvd[5]; 116 u16 qos_link_speed; 117 u32 event_tag; 118 struct be_async_event_trailer trailer; 119 } __packed; 120 121 /* When the event code of an async trailer is GRP5 and event type is 122 * CoS-Priority, the mcc_compl must be interpreted as follows 123 */ 124 struct be_async_event_grp5_cos_priority { 125 u8 physical_port; 126 u8 available_priority_bmap; 127 u8 reco_default_priority; 128 u8 valid; 129 u8 rsvd0; 130 u8 event_tag; 131 struct be_async_event_trailer trailer; 132 } __packed; 133 134 /* When the event code of an async trailer is GRP5 and event type is 135 * PVID state, the mcc_compl must be interpreted as follows 136 */ 137 struct be_async_event_grp5_pvid_state { 138 u8 enabled; 139 u8 rsvd0; 140 u16 tag; 141 u32 event_tag; 142 u32 rsvd1; 143 struct be_async_event_trailer trailer; 144 } __packed; 145 146 struct be_mcc_mailbox { 147 struct be_mcc_wrb wrb; 148 struct be_mcc_compl compl; 149 }; 150 151 #define CMD_SUBSYSTEM_COMMON 0x1 152 #define CMD_SUBSYSTEM_ETH 0x3 153 #define CMD_SUBSYSTEM_LOWLEVEL 0xb 154 155 #define OPCODE_COMMON_NTWK_MAC_QUERY 1 156 #define OPCODE_COMMON_NTWK_MAC_SET 2 157 #define OPCODE_COMMON_NTWK_MULTICAST_SET 3 158 #define OPCODE_COMMON_NTWK_VLAN_CONFIG 4 159 #define OPCODE_COMMON_NTWK_LINK_STATUS_QUERY 5 160 #define OPCODE_COMMON_READ_FLASHROM 6 161 #define OPCODE_COMMON_WRITE_FLASHROM 7 162 #define OPCODE_COMMON_CQ_CREATE 12 163 #define OPCODE_COMMON_EQ_CREATE 13 164 #define OPCODE_COMMON_MCC_CREATE 21 165 #define OPCODE_COMMON_SET_QOS 28 166 #define OPCODE_COMMON_MCC_CREATE_EXT 90 167 #define OPCODE_COMMON_SEEPROM_READ 30 168 #define OPCODE_COMMON_GET_CNTL_ATTRIBUTES 32 169 #define OPCODE_COMMON_NTWK_RX_FILTER 34 170 #define OPCODE_COMMON_GET_FW_VERSION 35 171 #define OPCODE_COMMON_SET_FLOW_CONTROL 36 172 #define OPCODE_COMMON_GET_FLOW_CONTROL 37 173 #define OPCODE_COMMON_SET_FRAME_SIZE 39 174 #define OPCODE_COMMON_MODIFY_EQ_DELAY 41 175 #define OPCODE_COMMON_FIRMWARE_CONFIG 42 176 #define OPCODE_COMMON_NTWK_INTERFACE_CREATE 50 177 #define OPCODE_COMMON_NTWK_INTERFACE_DESTROY 51 178 #define OPCODE_COMMON_MCC_DESTROY 53 179 #define OPCODE_COMMON_CQ_DESTROY 54 180 #define OPCODE_COMMON_EQ_DESTROY 55 181 #define OPCODE_COMMON_QUERY_FIRMWARE_CONFIG 58 182 #define OPCODE_COMMON_NTWK_PMAC_ADD 59 183 #define OPCODE_COMMON_NTWK_PMAC_DEL 60 184 #define OPCODE_COMMON_FUNCTION_RESET 61 185 #define OPCODE_COMMON_MANAGE_FAT 68 186 #define OPCODE_COMMON_ENABLE_DISABLE_BEACON 69 187 #define OPCODE_COMMON_GET_BEACON_STATE 70 188 #define OPCODE_COMMON_READ_TRANSRECV_DATA 73 189 #define OPCODE_COMMON_GET_PHY_DETAILS 102 190 #define OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP 103 191 #define OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES 121 192 #define OPCODE_COMMON_GET_MAC_LIST 147 193 #define OPCODE_COMMON_SET_MAC_LIST 148 194 #define OPCODE_COMMON_GET_HSW_CONFIG 152 195 #define OPCODE_COMMON_SET_HSW_CONFIG 153 196 #define OPCODE_COMMON_READ_OBJECT 171 197 #define OPCODE_COMMON_WRITE_OBJECT 172 198 199 #define OPCODE_ETH_RSS_CONFIG 1 200 #define OPCODE_ETH_ACPI_CONFIG 2 201 #define OPCODE_ETH_PROMISCUOUS 3 202 #define OPCODE_ETH_GET_STATISTICS 4 203 #define OPCODE_ETH_TX_CREATE 7 204 #define OPCODE_ETH_RX_CREATE 8 205 #define OPCODE_ETH_TX_DESTROY 9 206 #define OPCODE_ETH_RX_DESTROY 10 207 #define OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG 12 208 #define OPCODE_ETH_GET_PPORT_STATS 18 209 210 #define OPCODE_LOWLEVEL_HOST_DDR_DMA 17 211 #define OPCODE_LOWLEVEL_LOOPBACK_TEST 18 212 #define OPCODE_LOWLEVEL_SET_LOOPBACK_MODE 19 213 214 struct be_cmd_req_hdr { 215 u8 opcode; /* dword 0 */ 216 u8 subsystem; /* dword 0 */ 217 u8 port_number; /* dword 0 */ 218 u8 domain; /* dword 0 */ 219 u32 timeout; /* dword 1 */ 220 u32 request_length; /* dword 2 */ 221 u8 version; /* dword 3 */ 222 u8 rsvd[3]; /* dword 3 */ 223 }; 224 225 #define RESP_HDR_INFO_OPCODE_SHIFT 0 /* bits 0 - 7 */ 226 #define RESP_HDR_INFO_SUBSYS_SHIFT 8 /* bits 8 - 15 */ 227 struct be_cmd_resp_hdr { 228 u8 opcode; /* dword 0 */ 229 u8 subsystem; /* dword 0 */ 230 u8 rsvd[2]; /* dword 0 */ 231 u8 status; /* dword 1 */ 232 u8 add_status; /* dword 1 */ 233 u8 rsvd1[2]; /* dword 1 */ 234 u32 response_length; /* dword 2 */ 235 u32 actual_resp_len; /* dword 3 */ 236 }; 237 238 struct phys_addr { 239 u32 lo; 240 u32 hi; 241 }; 242 243 /************************** 244 * BE Command definitions * 245 **************************/ 246 247 /* Pseudo amap definition in which each bit of the actual structure is defined 248 * as a byte: used to calculate offset/shift/mask of each field */ 249 struct amap_eq_context { 250 u8 cidx[13]; /* dword 0*/ 251 u8 rsvd0[3]; /* dword 0*/ 252 u8 epidx[13]; /* dword 0*/ 253 u8 valid; /* dword 0*/ 254 u8 rsvd1; /* dword 0*/ 255 u8 size; /* dword 0*/ 256 u8 pidx[13]; /* dword 1*/ 257 u8 rsvd2[3]; /* dword 1*/ 258 u8 pd[10]; /* dword 1*/ 259 u8 count[3]; /* dword 1*/ 260 u8 solevent; /* dword 1*/ 261 u8 stalled; /* dword 1*/ 262 u8 armed; /* dword 1*/ 263 u8 rsvd3[4]; /* dword 2*/ 264 u8 func[8]; /* dword 2*/ 265 u8 rsvd4; /* dword 2*/ 266 u8 delaymult[10]; /* dword 2*/ 267 u8 rsvd5[2]; /* dword 2*/ 268 u8 phase[2]; /* dword 2*/ 269 u8 nodelay; /* dword 2*/ 270 u8 rsvd6[4]; /* dword 2*/ 271 u8 rsvd7[32]; /* dword 3*/ 272 } __packed; 273 274 struct be_cmd_req_eq_create { 275 struct be_cmd_req_hdr hdr; 276 u16 num_pages; /* sword */ 277 u16 rsvd0; /* sword */ 278 u8 context[sizeof(struct amap_eq_context) / 8]; 279 struct phys_addr pages[8]; 280 } __packed; 281 282 struct be_cmd_resp_eq_create { 283 struct be_cmd_resp_hdr resp_hdr; 284 u16 eq_id; /* sword */ 285 u16 rsvd0; /* sword */ 286 } __packed; 287 288 /******************** Mac query ***************************/ 289 enum { 290 MAC_ADDRESS_TYPE_STORAGE = 0x0, 291 MAC_ADDRESS_TYPE_NETWORK = 0x1, 292 MAC_ADDRESS_TYPE_PD = 0x2, 293 MAC_ADDRESS_TYPE_MANAGEMENT = 0x3 294 }; 295 296 struct mac_addr { 297 u16 size_of_struct; 298 u8 addr[ETH_ALEN]; 299 } __packed; 300 301 struct be_cmd_req_mac_query { 302 struct be_cmd_req_hdr hdr; 303 u8 type; 304 u8 permanent; 305 u16 if_id; 306 u32 pmac_id; 307 } __packed; 308 309 struct be_cmd_resp_mac_query { 310 struct be_cmd_resp_hdr hdr; 311 struct mac_addr mac; 312 }; 313 314 /******************** PMac Add ***************************/ 315 struct be_cmd_req_pmac_add { 316 struct be_cmd_req_hdr hdr; 317 u32 if_id; 318 u8 mac_address[ETH_ALEN]; 319 u8 rsvd0[2]; 320 } __packed; 321 322 struct be_cmd_resp_pmac_add { 323 struct be_cmd_resp_hdr hdr; 324 u32 pmac_id; 325 }; 326 327 /******************** PMac Del ***************************/ 328 struct be_cmd_req_pmac_del { 329 struct be_cmd_req_hdr hdr; 330 u32 if_id; 331 u32 pmac_id; 332 }; 333 334 /******************** Create CQ ***************************/ 335 /* Pseudo amap definition in which each bit of the actual structure is defined 336 * as a byte: used to calculate offset/shift/mask of each field */ 337 struct amap_cq_context_be { 338 u8 cidx[11]; /* dword 0*/ 339 u8 rsvd0; /* dword 0*/ 340 u8 coalescwm[2]; /* dword 0*/ 341 u8 nodelay; /* dword 0*/ 342 u8 epidx[11]; /* dword 0*/ 343 u8 rsvd1; /* dword 0*/ 344 u8 count[2]; /* dword 0*/ 345 u8 valid; /* dword 0*/ 346 u8 solevent; /* dword 0*/ 347 u8 eventable; /* dword 0*/ 348 u8 pidx[11]; /* dword 1*/ 349 u8 rsvd2; /* dword 1*/ 350 u8 pd[10]; /* dword 1*/ 351 u8 eqid[8]; /* dword 1*/ 352 u8 stalled; /* dword 1*/ 353 u8 armed; /* dword 1*/ 354 u8 rsvd3[4]; /* dword 2*/ 355 u8 func[8]; /* dword 2*/ 356 u8 rsvd4[20]; /* dword 2*/ 357 u8 rsvd5[32]; /* dword 3*/ 358 } __packed; 359 360 struct amap_cq_context_lancer { 361 u8 rsvd0[12]; /* dword 0*/ 362 u8 coalescwm[2]; /* dword 0*/ 363 u8 nodelay; /* dword 0*/ 364 u8 rsvd1[12]; /* dword 0*/ 365 u8 count[2]; /* dword 0*/ 366 u8 valid; /* dword 0*/ 367 u8 rsvd2; /* dword 0*/ 368 u8 eventable; /* dword 0*/ 369 u8 eqid[16]; /* dword 1*/ 370 u8 rsvd3[15]; /* dword 1*/ 371 u8 armed; /* dword 1*/ 372 u8 rsvd4[32]; /* dword 2*/ 373 u8 rsvd5[32]; /* dword 3*/ 374 } __packed; 375 376 struct be_cmd_req_cq_create { 377 struct be_cmd_req_hdr hdr; 378 u16 num_pages; 379 u8 page_size; 380 u8 rsvd0; 381 u8 context[sizeof(struct amap_cq_context_be) / 8]; 382 struct phys_addr pages[8]; 383 } __packed; 384 385 386 struct be_cmd_resp_cq_create { 387 struct be_cmd_resp_hdr hdr; 388 u16 cq_id; 389 u16 rsvd0; 390 } __packed; 391 392 struct be_cmd_req_get_fat { 393 struct be_cmd_req_hdr hdr; 394 u32 fat_operation; 395 u32 read_log_offset; 396 u32 read_log_length; 397 u32 data_buffer_size; 398 u32 data_buffer[1]; 399 } __packed; 400 401 struct be_cmd_resp_get_fat { 402 struct be_cmd_resp_hdr hdr; 403 u32 log_size; 404 u32 read_log_length; 405 u32 rsvd[2]; 406 u32 data_buffer[1]; 407 } __packed; 408 409 410 /******************** Create MCCQ ***************************/ 411 /* Pseudo amap definition in which each bit of the actual structure is defined 412 * as a byte: used to calculate offset/shift/mask of each field */ 413 struct amap_mcc_context_be { 414 u8 con_index[14]; 415 u8 rsvd0[2]; 416 u8 ring_size[4]; 417 u8 fetch_wrb; 418 u8 fetch_r2t; 419 u8 cq_id[10]; 420 u8 prod_index[14]; 421 u8 fid[8]; 422 u8 pdid[9]; 423 u8 valid; 424 u8 rsvd1[32]; 425 u8 rsvd2[32]; 426 } __packed; 427 428 struct amap_mcc_context_lancer { 429 u8 async_cq_id[16]; 430 u8 ring_size[4]; 431 u8 rsvd0[12]; 432 u8 rsvd1[31]; 433 u8 valid; 434 u8 async_cq_valid[1]; 435 u8 rsvd2[31]; 436 u8 rsvd3[32]; 437 } __packed; 438 439 struct be_cmd_req_mcc_create { 440 struct be_cmd_req_hdr hdr; 441 u16 num_pages; 442 u16 cq_id; 443 u8 context[sizeof(struct amap_mcc_context_be) / 8]; 444 struct phys_addr pages[8]; 445 } __packed; 446 447 struct be_cmd_req_mcc_ext_create { 448 struct be_cmd_req_hdr hdr; 449 u16 num_pages; 450 u16 cq_id; 451 u32 async_event_bitmap[1]; 452 u8 context[sizeof(struct amap_mcc_context_be) / 8]; 453 struct phys_addr pages[8]; 454 } __packed; 455 456 struct be_cmd_resp_mcc_create { 457 struct be_cmd_resp_hdr hdr; 458 u16 id; 459 u16 rsvd0; 460 } __packed; 461 462 /******************** Create TxQ ***************************/ 463 #define BE_ETH_TX_RING_TYPE_STANDARD 2 464 #define BE_ULP1_NUM 1 465 466 /* Pseudo amap definition in which each bit of the actual structure is defined 467 * as a byte: used to calculate offset/shift/mask of each field */ 468 struct amap_tx_context { 469 u8 if_id[16]; /* dword 0 */ 470 u8 tx_ring_size[4]; /* dword 0 */ 471 u8 rsvd1[26]; /* dword 0 */ 472 u8 pci_func_id[8]; /* dword 1 */ 473 u8 rsvd2[9]; /* dword 1 */ 474 u8 ctx_valid; /* dword 1 */ 475 u8 cq_id_send[16]; /* dword 2 */ 476 u8 rsvd3[16]; /* dword 2 */ 477 u8 rsvd4[32]; /* dword 3 */ 478 u8 rsvd5[32]; /* dword 4 */ 479 u8 rsvd6[32]; /* dword 5 */ 480 u8 rsvd7[32]; /* dword 6 */ 481 u8 rsvd8[32]; /* dword 7 */ 482 u8 rsvd9[32]; /* dword 8 */ 483 u8 rsvd10[32]; /* dword 9 */ 484 u8 rsvd11[32]; /* dword 10 */ 485 u8 rsvd12[32]; /* dword 11 */ 486 u8 rsvd13[32]; /* dword 12 */ 487 u8 rsvd14[32]; /* dword 13 */ 488 u8 rsvd15[32]; /* dword 14 */ 489 u8 rsvd16[32]; /* dword 15 */ 490 } __packed; 491 492 struct be_cmd_req_eth_tx_create { 493 struct be_cmd_req_hdr hdr; 494 u8 num_pages; 495 u8 ulp_num; 496 u8 type; 497 u8 bound_port; 498 u8 context[sizeof(struct amap_tx_context) / 8]; 499 struct phys_addr pages[8]; 500 } __packed; 501 502 struct be_cmd_resp_eth_tx_create { 503 struct be_cmd_resp_hdr hdr; 504 u16 cid; 505 u16 rsvd0; 506 } __packed; 507 508 /******************** Create RxQ ***************************/ 509 struct be_cmd_req_eth_rx_create { 510 struct be_cmd_req_hdr hdr; 511 u16 cq_id; 512 u8 frag_size; 513 u8 num_pages; 514 struct phys_addr pages[2]; 515 u32 interface_id; 516 u16 max_frame_size; 517 u16 rsvd0; 518 u32 rss_queue; 519 } __packed; 520 521 struct be_cmd_resp_eth_rx_create { 522 struct be_cmd_resp_hdr hdr; 523 u16 id; 524 u8 rss_id; 525 u8 rsvd0; 526 } __packed; 527 528 /******************** Q Destroy ***************************/ 529 /* Type of Queue to be destroyed */ 530 enum { 531 QTYPE_EQ = 1, 532 QTYPE_CQ, 533 QTYPE_TXQ, 534 QTYPE_RXQ, 535 QTYPE_MCCQ 536 }; 537 538 struct be_cmd_req_q_destroy { 539 struct be_cmd_req_hdr hdr; 540 u16 id; 541 u16 bypass_flush; /* valid only for rx q destroy */ 542 } __packed; 543 544 /************ I/f Create (it's actually I/f Config Create)**********/ 545 546 /* Capability flags for the i/f */ 547 enum be_if_flags { 548 BE_IF_FLAGS_RSS = 0x4, 549 BE_IF_FLAGS_PROMISCUOUS = 0x8, 550 BE_IF_FLAGS_BROADCAST = 0x10, 551 BE_IF_FLAGS_UNTAGGED = 0x20, 552 BE_IF_FLAGS_ULP = 0x40, 553 BE_IF_FLAGS_VLAN_PROMISCUOUS = 0x80, 554 BE_IF_FLAGS_VLAN = 0x100, 555 BE_IF_FLAGS_MCAST_PROMISCUOUS = 0x200, 556 BE_IF_FLAGS_PASS_L2_ERRORS = 0x400, 557 BE_IF_FLAGS_PASS_L3L4_ERRORS = 0x800, 558 BE_IF_FLAGS_MULTICAST = 0x1000 559 }; 560 561 /* An RX interface is an object with one or more MAC addresses and 562 * filtering capabilities. */ 563 struct be_cmd_req_if_create { 564 struct be_cmd_req_hdr hdr; 565 u32 version; /* ignore currently */ 566 u32 capability_flags; 567 u32 enable_flags; 568 u8 mac_addr[ETH_ALEN]; 569 u8 rsvd0; 570 u8 pmac_invalid; /* if set, don't attach the mac addr to the i/f */ 571 u32 vlan_tag; /* not used currently */ 572 } __packed; 573 574 struct be_cmd_resp_if_create { 575 struct be_cmd_resp_hdr hdr; 576 u32 interface_id; 577 u32 pmac_id; 578 }; 579 580 /****** I/f Destroy(it's actually I/f Config Destroy )**********/ 581 struct be_cmd_req_if_destroy { 582 struct be_cmd_req_hdr hdr; 583 u32 interface_id; 584 }; 585 586 /*************** HW Stats Get **********************************/ 587 struct be_port_rxf_stats_v0 { 588 u32 rx_bytes_lsd; /* dword 0*/ 589 u32 rx_bytes_msd; /* dword 1*/ 590 u32 rx_total_frames; /* dword 2*/ 591 u32 rx_unicast_frames; /* dword 3*/ 592 u32 rx_multicast_frames; /* dword 4*/ 593 u32 rx_broadcast_frames; /* dword 5*/ 594 u32 rx_crc_errors; /* dword 6*/ 595 u32 rx_alignment_symbol_errors; /* dword 7*/ 596 u32 rx_pause_frames; /* dword 8*/ 597 u32 rx_control_frames; /* dword 9*/ 598 u32 rx_in_range_errors; /* dword 10*/ 599 u32 rx_out_range_errors; /* dword 11*/ 600 u32 rx_frame_too_long; /* dword 12*/ 601 u32 rx_address_mismatch_drops; /* dword 13*/ 602 u32 rx_vlan_mismatch_drops; /* dword 14*/ 603 u32 rx_dropped_too_small; /* dword 15*/ 604 u32 rx_dropped_too_short; /* dword 16*/ 605 u32 rx_dropped_header_too_small; /* dword 17*/ 606 u32 rx_dropped_tcp_length; /* dword 18*/ 607 u32 rx_dropped_runt; /* dword 19*/ 608 u32 rx_64_byte_packets; /* dword 20*/ 609 u32 rx_65_127_byte_packets; /* dword 21*/ 610 u32 rx_128_256_byte_packets; /* dword 22*/ 611 u32 rx_256_511_byte_packets; /* dword 23*/ 612 u32 rx_512_1023_byte_packets; /* dword 24*/ 613 u32 rx_1024_1518_byte_packets; /* dword 25*/ 614 u32 rx_1519_2047_byte_packets; /* dword 26*/ 615 u32 rx_2048_4095_byte_packets; /* dword 27*/ 616 u32 rx_4096_8191_byte_packets; /* dword 28*/ 617 u32 rx_8192_9216_byte_packets; /* dword 29*/ 618 u32 rx_ip_checksum_errs; /* dword 30*/ 619 u32 rx_tcp_checksum_errs; /* dword 31*/ 620 u32 rx_udp_checksum_errs; /* dword 32*/ 621 u32 rx_non_rss_packets; /* dword 33*/ 622 u32 rx_ipv4_packets; /* dword 34*/ 623 u32 rx_ipv6_packets; /* dword 35*/ 624 u32 rx_ipv4_bytes_lsd; /* dword 36*/ 625 u32 rx_ipv4_bytes_msd; /* dword 37*/ 626 u32 rx_ipv6_bytes_lsd; /* dword 38*/ 627 u32 rx_ipv6_bytes_msd; /* dword 39*/ 628 u32 rx_chute1_packets; /* dword 40*/ 629 u32 rx_chute2_packets; /* dword 41*/ 630 u32 rx_chute3_packets; /* dword 42*/ 631 u32 rx_management_packets; /* dword 43*/ 632 u32 rx_switched_unicast_packets; /* dword 44*/ 633 u32 rx_switched_multicast_packets; /* dword 45*/ 634 u32 rx_switched_broadcast_packets; /* dword 46*/ 635 u32 tx_bytes_lsd; /* dword 47*/ 636 u32 tx_bytes_msd; /* dword 48*/ 637 u32 tx_unicastframes; /* dword 49*/ 638 u32 tx_multicastframes; /* dword 50*/ 639 u32 tx_broadcastframes; /* dword 51*/ 640 u32 tx_pauseframes; /* dword 52*/ 641 u32 tx_controlframes; /* dword 53*/ 642 u32 tx_64_byte_packets; /* dword 54*/ 643 u32 tx_65_127_byte_packets; /* dword 55*/ 644 u32 tx_128_256_byte_packets; /* dword 56*/ 645 u32 tx_256_511_byte_packets; /* dword 57*/ 646 u32 tx_512_1023_byte_packets; /* dword 58*/ 647 u32 tx_1024_1518_byte_packets; /* dword 59*/ 648 u32 tx_1519_2047_byte_packets; /* dword 60*/ 649 u32 tx_2048_4095_byte_packets; /* dword 61*/ 650 u32 tx_4096_8191_byte_packets; /* dword 62*/ 651 u32 tx_8192_9216_byte_packets; /* dword 63*/ 652 u32 rx_fifo_overflow; /* dword 64*/ 653 u32 rx_input_fifo_overflow; /* dword 65*/ 654 }; 655 656 struct be_rxf_stats_v0 { 657 struct be_port_rxf_stats_v0 port[2]; 658 u32 rx_drops_no_pbuf; /* dword 132*/ 659 u32 rx_drops_no_txpb; /* dword 133*/ 660 u32 rx_drops_no_erx_descr; /* dword 134*/ 661 u32 rx_drops_no_tpre_descr; /* dword 135*/ 662 u32 management_rx_port_packets; /* dword 136*/ 663 u32 management_rx_port_bytes; /* dword 137*/ 664 u32 management_rx_port_pause_frames; /* dword 138*/ 665 u32 management_rx_port_errors; /* dword 139*/ 666 u32 management_tx_port_packets; /* dword 140*/ 667 u32 management_tx_port_bytes; /* dword 141*/ 668 u32 management_tx_port_pause; /* dword 142*/ 669 u32 management_rx_port_rxfifo_overflow; /* dword 143*/ 670 u32 rx_drops_too_many_frags; /* dword 144*/ 671 u32 rx_drops_invalid_ring; /* dword 145*/ 672 u32 forwarded_packets; /* dword 146*/ 673 u32 rx_drops_mtu; /* dword 147*/ 674 u32 rsvd0[7]; 675 u32 port0_jabber_events; 676 u32 port1_jabber_events; 677 u32 rsvd1[6]; 678 }; 679 680 struct be_erx_stats_v0 { 681 u32 rx_drops_no_fragments[44]; /* dwordS 0 to 43*/ 682 u32 rsvd[4]; 683 }; 684 685 struct be_pmem_stats { 686 u32 eth_red_drops; 687 u32 rsvd[5]; 688 }; 689 690 struct be_hw_stats_v0 { 691 struct be_rxf_stats_v0 rxf; 692 u32 rsvd[48]; 693 struct be_erx_stats_v0 erx; 694 struct be_pmem_stats pmem; 695 }; 696 697 struct be_cmd_req_get_stats_v0 { 698 struct be_cmd_req_hdr hdr; 699 u8 rsvd[sizeof(struct be_hw_stats_v0)]; 700 }; 701 702 struct be_cmd_resp_get_stats_v0 { 703 struct be_cmd_resp_hdr hdr; 704 struct be_hw_stats_v0 hw_stats; 705 }; 706 707 struct lancer_pport_stats { 708 u32 tx_packets_lo; 709 u32 tx_packets_hi; 710 u32 tx_unicast_packets_lo; 711 u32 tx_unicast_packets_hi; 712 u32 tx_multicast_packets_lo; 713 u32 tx_multicast_packets_hi; 714 u32 tx_broadcast_packets_lo; 715 u32 tx_broadcast_packets_hi; 716 u32 tx_bytes_lo; 717 u32 tx_bytes_hi; 718 u32 tx_unicast_bytes_lo; 719 u32 tx_unicast_bytes_hi; 720 u32 tx_multicast_bytes_lo; 721 u32 tx_multicast_bytes_hi; 722 u32 tx_broadcast_bytes_lo; 723 u32 tx_broadcast_bytes_hi; 724 u32 tx_discards_lo; 725 u32 tx_discards_hi; 726 u32 tx_errors_lo; 727 u32 tx_errors_hi; 728 u32 tx_pause_frames_lo; 729 u32 tx_pause_frames_hi; 730 u32 tx_pause_on_frames_lo; 731 u32 tx_pause_on_frames_hi; 732 u32 tx_pause_off_frames_lo; 733 u32 tx_pause_off_frames_hi; 734 u32 tx_internal_mac_errors_lo; 735 u32 tx_internal_mac_errors_hi; 736 u32 tx_control_frames_lo; 737 u32 tx_control_frames_hi; 738 u32 tx_packets_64_bytes_lo; 739 u32 tx_packets_64_bytes_hi; 740 u32 tx_packets_65_to_127_bytes_lo; 741 u32 tx_packets_65_to_127_bytes_hi; 742 u32 tx_packets_128_to_255_bytes_lo; 743 u32 tx_packets_128_to_255_bytes_hi; 744 u32 tx_packets_256_to_511_bytes_lo; 745 u32 tx_packets_256_to_511_bytes_hi; 746 u32 tx_packets_512_to_1023_bytes_lo; 747 u32 tx_packets_512_to_1023_bytes_hi; 748 u32 tx_packets_1024_to_1518_bytes_lo; 749 u32 tx_packets_1024_to_1518_bytes_hi; 750 u32 tx_packets_1519_to_2047_bytes_lo; 751 u32 tx_packets_1519_to_2047_bytes_hi; 752 u32 tx_packets_2048_to_4095_bytes_lo; 753 u32 tx_packets_2048_to_4095_bytes_hi; 754 u32 tx_packets_4096_to_8191_bytes_lo; 755 u32 tx_packets_4096_to_8191_bytes_hi; 756 u32 tx_packets_8192_to_9216_bytes_lo; 757 u32 tx_packets_8192_to_9216_bytes_hi; 758 u32 tx_lso_packets_lo; 759 u32 tx_lso_packets_hi; 760 u32 rx_packets_lo; 761 u32 rx_packets_hi; 762 u32 rx_unicast_packets_lo; 763 u32 rx_unicast_packets_hi; 764 u32 rx_multicast_packets_lo; 765 u32 rx_multicast_packets_hi; 766 u32 rx_broadcast_packets_lo; 767 u32 rx_broadcast_packets_hi; 768 u32 rx_bytes_lo; 769 u32 rx_bytes_hi; 770 u32 rx_unicast_bytes_lo; 771 u32 rx_unicast_bytes_hi; 772 u32 rx_multicast_bytes_lo; 773 u32 rx_multicast_bytes_hi; 774 u32 rx_broadcast_bytes_lo; 775 u32 rx_broadcast_bytes_hi; 776 u32 rx_unknown_protos; 777 u32 rsvd_69; /* Word 69 is reserved */ 778 u32 rx_discards_lo; 779 u32 rx_discards_hi; 780 u32 rx_errors_lo; 781 u32 rx_errors_hi; 782 u32 rx_crc_errors_lo; 783 u32 rx_crc_errors_hi; 784 u32 rx_alignment_errors_lo; 785 u32 rx_alignment_errors_hi; 786 u32 rx_symbol_errors_lo; 787 u32 rx_symbol_errors_hi; 788 u32 rx_pause_frames_lo; 789 u32 rx_pause_frames_hi; 790 u32 rx_pause_on_frames_lo; 791 u32 rx_pause_on_frames_hi; 792 u32 rx_pause_off_frames_lo; 793 u32 rx_pause_off_frames_hi; 794 u32 rx_frames_too_long_lo; 795 u32 rx_frames_too_long_hi; 796 u32 rx_internal_mac_errors_lo; 797 u32 rx_internal_mac_errors_hi; 798 u32 rx_undersize_packets; 799 u32 rx_oversize_packets; 800 u32 rx_fragment_packets; 801 u32 rx_jabbers; 802 u32 rx_control_frames_lo; 803 u32 rx_control_frames_hi; 804 u32 rx_control_frames_unknown_opcode_lo; 805 u32 rx_control_frames_unknown_opcode_hi; 806 u32 rx_in_range_errors; 807 u32 rx_out_of_range_errors; 808 u32 rx_address_mismatch_drops; 809 u32 rx_vlan_mismatch_drops; 810 u32 rx_dropped_too_small; 811 u32 rx_dropped_too_short; 812 u32 rx_dropped_header_too_small; 813 u32 rx_dropped_invalid_tcp_length; 814 u32 rx_dropped_runt; 815 u32 rx_ip_checksum_errors; 816 u32 rx_tcp_checksum_errors; 817 u32 rx_udp_checksum_errors; 818 u32 rx_non_rss_packets; 819 u32 rsvd_111; 820 u32 rx_ipv4_packets_lo; 821 u32 rx_ipv4_packets_hi; 822 u32 rx_ipv6_packets_lo; 823 u32 rx_ipv6_packets_hi; 824 u32 rx_ipv4_bytes_lo; 825 u32 rx_ipv4_bytes_hi; 826 u32 rx_ipv6_bytes_lo; 827 u32 rx_ipv6_bytes_hi; 828 u32 rx_nic_packets_lo; 829 u32 rx_nic_packets_hi; 830 u32 rx_tcp_packets_lo; 831 u32 rx_tcp_packets_hi; 832 u32 rx_iscsi_packets_lo; 833 u32 rx_iscsi_packets_hi; 834 u32 rx_management_packets_lo; 835 u32 rx_management_packets_hi; 836 u32 rx_switched_unicast_packets_lo; 837 u32 rx_switched_unicast_packets_hi; 838 u32 rx_switched_multicast_packets_lo; 839 u32 rx_switched_multicast_packets_hi; 840 u32 rx_switched_broadcast_packets_lo; 841 u32 rx_switched_broadcast_packets_hi; 842 u32 num_forwards_lo; 843 u32 num_forwards_hi; 844 u32 rx_fifo_overflow; 845 u32 rx_input_fifo_overflow; 846 u32 rx_drops_too_many_frags_lo; 847 u32 rx_drops_too_many_frags_hi; 848 u32 rx_drops_invalid_queue; 849 u32 rsvd_141; 850 u32 rx_drops_mtu_lo; 851 u32 rx_drops_mtu_hi; 852 u32 rx_packets_64_bytes_lo; 853 u32 rx_packets_64_bytes_hi; 854 u32 rx_packets_65_to_127_bytes_lo; 855 u32 rx_packets_65_to_127_bytes_hi; 856 u32 rx_packets_128_to_255_bytes_lo; 857 u32 rx_packets_128_to_255_bytes_hi; 858 u32 rx_packets_256_to_511_bytes_lo; 859 u32 rx_packets_256_to_511_bytes_hi; 860 u32 rx_packets_512_to_1023_bytes_lo; 861 u32 rx_packets_512_to_1023_bytes_hi; 862 u32 rx_packets_1024_to_1518_bytes_lo; 863 u32 rx_packets_1024_to_1518_bytes_hi; 864 u32 rx_packets_1519_to_2047_bytes_lo; 865 u32 rx_packets_1519_to_2047_bytes_hi; 866 u32 rx_packets_2048_to_4095_bytes_lo; 867 u32 rx_packets_2048_to_4095_bytes_hi; 868 u32 rx_packets_4096_to_8191_bytes_lo; 869 u32 rx_packets_4096_to_8191_bytes_hi; 870 u32 rx_packets_8192_to_9216_bytes_lo; 871 u32 rx_packets_8192_to_9216_bytes_hi; 872 }; 873 874 struct pport_stats_params { 875 u16 pport_num; 876 u8 rsvd; 877 u8 reset_stats; 878 }; 879 880 struct lancer_cmd_req_pport_stats { 881 struct be_cmd_req_hdr hdr; 882 union { 883 struct pport_stats_params params; 884 u8 rsvd[sizeof(struct lancer_pport_stats)]; 885 } cmd_params; 886 }; 887 888 struct lancer_cmd_resp_pport_stats { 889 struct be_cmd_resp_hdr hdr; 890 struct lancer_pport_stats pport_stats; 891 }; 892 893 static inline struct lancer_pport_stats* 894 pport_stats_from_cmd(struct be_adapter *adapter) 895 { 896 struct lancer_cmd_resp_pport_stats *cmd = adapter->stats_cmd.va; 897 return &cmd->pport_stats; 898 } 899 900 struct be_cmd_req_get_cntl_addnl_attribs { 901 struct be_cmd_req_hdr hdr; 902 u8 rsvd[8]; 903 }; 904 905 struct be_cmd_resp_get_cntl_addnl_attribs { 906 struct be_cmd_resp_hdr hdr; 907 u16 ipl_file_number; 908 u8 ipl_file_version; 909 u8 rsvd0; 910 u8 on_die_temperature; /* in degrees centigrade*/ 911 u8 rsvd1[3]; 912 }; 913 914 struct be_cmd_req_vlan_config { 915 struct be_cmd_req_hdr hdr; 916 u8 interface_id; 917 u8 promiscuous; 918 u8 untagged; 919 u8 num_vlan; 920 u16 normal_vlan[64]; 921 } __packed; 922 923 /******************* RX FILTER ******************************/ 924 #define BE_MAX_MC 64 /* set mcast promisc if > 64 */ 925 struct macaddr { 926 u8 byte[ETH_ALEN]; 927 }; 928 929 struct be_cmd_req_rx_filter { 930 struct be_cmd_req_hdr hdr; 931 u32 global_flags_mask; 932 u32 global_flags; 933 u32 if_flags_mask; 934 u32 if_flags; 935 u32 if_id; 936 u32 mcast_num; 937 struct macaddr mcast_mac[BE_MAX_MC]; 938 }; 939 940 /******************** Link Status Query *******************/ 941 struct be_cmd_req_link_status { 942 struct be_cmd_req_hdr hdr; 943 u32 rsvd; 944 }; 945 946 enum { 947 PHY_LINK_DUPLEX_NONE = 0x0, 948 PHY_LINK_DUPLEX_HALF = 0x1, 949 PHY_LINK_DUPLEX_FULL = 0x2 950 }; 951 952 enum { 953 PHY_LINK_SPEED_ZERO = 0x0, /* => No link */ 954 PHY_LINK_SPEED_10MBPS = 0x1, 955 PHY_LINK_SPEED_100MBPS = 0x2, 956 PHY_LINK_SPEED_1GBPS = 0x3, 957 PHY_LINK_SPEED_10GBPS = 0x4 958 }; 959 960 struct be_cmd_resp_link_status { 961 struct be_cmd_resp_hdr hdr; 962 u8 physical_port; 963 u8 mac_duplex; 964 u8 mac_speed; 965 u8 mac_fault; 966 u8 mgmt_mac_duplex; 967 u8 mgmt_mac_speed; 968 u16 link_speed; 969 u8 logical_link_status; 970 u8 rsvd1[3]; 971 } __packed; 972 973 /******************** Port Identification ***************************/ 974 /* Identifies the type of port attached to NIC */ 975 struct be_cmd_req_port_type { 976 struct be_cmd_req_hdr hdr; 977 u32 page_num; 978 u32 port; 979 }; 980 981 enum { 982 TR_PAGE_A0 = 0xa0, 983 TR_PAGE_A2 = 0xa2 984 }; 985 986 struct be_cmd_resp_port_type { 987 struct be_cmd_resp_hdr hdr; 988 u32 page_num; 989 u32 port; 990 struct data { 991 u8 identifier; 992 u8 identifier_ext; 993 u8 connector; 994 u8 transceiver[8]; 995 u8 rsvd0[3]; 996 u8 length_km; 997 u8 length_hm; 998 u8 length_om1; 999 u8 length_om2; 1000 u8 length_cu; 1001 u8 length_cu_m; 1002 u8 vendor_name[16]; 1003 u8 rsvd; 1004 u8 vendor_oui[3]; 1005 u8 vendor_pn[16]; 1006 u8 vendor_rev[4]; 1007 } data; 1008 }; 1009 1010 /******************** Get FW Version *******************/ 1011 struct be_cmd_req_get_fw_version { 1012 struct be_cmd_req_hdr hdr; 1013 u8 rsvd0[FW_VER_LEN]; 1014 u8 rsvd1[FW_VER_LEN]; 1015 } __packed; 1016 1017 struct be_cmd_resp_get_fw_version { 1018 struct be_cmd_resp_hdr hdr; 1019 u8 firmware_version_string[FW_VER_LEN]; 1020 u8 fw_on_flash_version_string[FW_VER_LEN]; 1021 } __packed; 1022 1023 /******************** Set Flow Contrl *******************/ 1024 struct be_cmd_req_set_flow_control { 1025 struct be_cmd_req_hdr hdr; 1026 u16 tx_flow_control; 1027 u16 rx_flow_control; 1028 } __packed; 1029 1030 /******************** Get Flow Contrl *******************/ 1031 struct be_cmd_req_get_flow_control { 1032 struct be_cmd_req_hdr hdr; 1033 u32 rsvd; 1034 }; 1035 1036 struct be_cmd_resp_get_flow_control { 1037 struct be_cmd_resp_hdr hdr; 1038 u16 tx_flow_control; 1039 u16 rx_flow_control; 1040 } __packed; 1041 1042 /******************** Modify EQ Delay *******************/ 1043 struct be_cmd_req_modify_eq_delay { 1044 struct be_cmd_req_hdr hdr; 1045 u32 num_eq; 1046 struct { 1047 u32 eq_id; 1048 u32 phase; 1049 u32 delay_multiplier; 1050 } delay[8]; 1051 } __packed; 1052 1053 struct be_cmd_resp_modify_eq_delay { 1054 struct be_cmd_resp_hdr hdr; 1055 u32 rsvd0; 1056 } __packed; 1057 1058 /******************** Get FW Config *******************/ 1059 #define BE_FUNCTION_CAPS_RSS 0x2 1060 /* The HW can come up in either of the following multi-channel modes 1061 * based on the skew/IPL. 1062 */ 1063 #define FLEX10_MODE 0x400 1064 #define VNIC_MODE 0x20000 1065 #define UMC_ENABLED 0x1000000 1066 struct be_cmd_req_query_fw_cfg { 1067 struct be_cmd_req_hdr hdr; 1068 u32 rsvd[31]; 1069 }; 1070 1071 struct be_cmd_resp_query_fw_cfg { 1072 struct be_cmd_resp_hdr hdr; 1073 u32 be_config_number; 1074 u32 asic_revision; 1075 u32 phys_port; 1076 u32 function_mode; 1077 u32 rsvd[26]; 1078 u32 function_caps; 1079 }; 1080 1081 /******************** RSS Config *******************/ 1082 /* RSS types */ 1083 #define RSS_ENABLE_NONE 0x0 1084 #define RSS_ENABLE_IPV4 0x1 1085 #define RSS_ENABLE_TCP_IPV4 0x2 1086 #define RSS_ENABLE_IPV6 0x4 1087 #define RSS_ENABLE_TCP_IPV6 0x8 1088 1089 struct be_cmd_req_rss_config { 1090 struct be_cmd_req_hdr hdr; 1091 u32 if_id; 1092 u16 enable_rss; 1093 u16 cpu_table_size_log2; 1094 u32 hash[10]; 1095 u8 cpu_table[128]; 1096 u8 flush; 1097 u8 rsvd0[3]; 1098 }; 1099 1100 /******************** Port Beacon ***************************/ 1101 1102 #define BEACON_STATE_ENABLED 0x1 1103 #define BEACON_STATE_DISABLED 0x0 1104 1105 struct be_cmd_req_enable_disable_beacon { 1106 struct be_cmd_req_hdr hdr; 1107 u8 port_num; 1108 u8 beacon_state; 1109 u8 beacon_duration; 1110 u8 status_duration; 1111 } __packed; 1112 1113 struct be_cmd_resp_enable_disable_beacon { 1114 struct be_cmd_resp_hdr resp_hdr; 1115 u32 rsvd0; 1116 } __packed; 1117 1118 struct be_cmd_req_get_beacon_state { 1119 struct be_cmd_req_hdr hdr; 1120 u8 port_num; 1121 u8 rsvd0; 1122 u16 rsvd1; 1123 } __packed; 1124 1125 struct be_cmd_resp_get_beacon_state { 1126 struct be_cmd_resp_hdr resp_hdr; 1127 u8 beacon_state; 1128 u8 rsvd0[3]; 1129 } __packed; 1130 1131 /****************** Firmware Flash ******************/ 1132 struct flashrom_params { 1133 u32 op_code; 1134 u32 op_type; 1135 u32 data_buf_size; 1136 u32 offset; 1137 u8 data_buf[4]; 1138 }; 1139 1140 struct be_cmd_write_flashrom { 1141 struct be_cmd_req_hdr hdr; 1142 struct flashrom_params params; 1143 }; 1144 1145 /**************** Lancer Firmware Flash ************/ 1146 struct amap_lancer_write_obj_context { 1147 u8 write_length[24]; 1148 u8 reserved1[7]; 1149 u8 eof; 1150 } __packed; 1151 1152 struct lancer_cmd_req_write_object { 1153 struct be_cmd_req_hdr hdr; 1154 u8 context[sizeof(struct amap_lancer_write_obj_context) / 8]; 1155 u32 write_offset; 1156 u8 object_name[104]; 1157 u32 descriptor_count; 1158 u32 buf_len; 1159 u32 addr_low; 1160 u32 addr_high; 1161 }; 1162 1163 struct lancer_cmd_resp_write_object { 1164 u8 opcode; 1165 u8 subsystem; 1166 u8 rsvd1[2]; 1167 u8 status; 1168 u8 additional_status; 1169 u8 rsvd2[2]; 1170 u32 resp_len; 1171 u32 actual_resp_len; 1172 u32 actual_write_len; 1173 }; 1174 1175 /************************ Lancer Read FW info **************/ 1176 #define LANCER_READ_FILE_CHUNK (32*1024) 1177 #define LANCER_READ_FILE_EOF_MASK 0x80000000 1178 1179 #define LANCER_FW_DUMP_FILE "/dbg/dump.bin" 1180 #define LANCER_VPD_PF_FILE "/vpd/ntr_pf.vpd" 1181 #define LANCER_VPD_VF_FILE "/vpd/ntr_vf.vpd" 1182 1183 struct lancer_cmd_req_read_object { 1184 struct be_cmd_req_hdr hdr; 1185 u32 desired_read_len; 1186 u32 read_offset; 1187 u8 object_name[104]; 1188 u32 descriptor_count; 1189 u32 buf_len; 1190 u32 addr_low; 1191 u32 addr_high; 1192 }; 1193 1194 struct lancer_cmd_resp_read_object { 1195 u8 opcode; 1196 u8 subsystem; 1197 u8 rsvd1[2]; 1198 u8 status; 1199 u8 additional_status; 1200 u8 rsvd2[2]; 1201 u32 resp_len; 1202 u32 actual_resp_len; 1203 u32 actual_read_len; 1204 u32 eof; 1205 }; 1206 1207 /************************ WOL *******************************/ 1208 struct be_cmd_req_acpi_wol_magic_config{ 1209 struct be_cmd_req_hdr hdr; 1210 u32 rsvd0[145]; 1211 u8 magic_mac[6]; 1212 u8 rsvd2[2]; 1213 } __packed; 1214 1215 struct be_cmd_req_acpi_wol_magic_config_v1 { 1216 struct be_cmd_req_hdr hdr; 1217 u8 rsvd0[2]; 1218 u8 query_options; 1219 u8 rsvd1[5]; 1220 u32 rsvd2[288]; 1221 u8 magic_mac[6]; 1222 u8 rsvd3[22]; 1223 } __packed; 1224 1225 struct be_cmd_resp_acpi_wol_magic_config_v1 { 1226 struct be_cmd_resp_hdr hdr; 1227 u8 rsvd0[2]; 1228 u8 wol_settings; 1229 u8 rsvd1[5]; 1230 u32 rsvd2[295]; 1231 } __packed; 1232 1233 #define BE_GET_WOL_CAP 2 1234 1235 #define BE_WOL_CAP 0x1 1236 #define BE_PME_D0_CAP 0x8 1237 #define BE_PME_D1_CAP 0x10 1238 #define BE_PME_D2_CAP 0x20 1239 #define BE_PME_D3HOT_CAP 0x40 1240 #define BE_PME_D3COLD_CAP 0x80 1241 1242 /********************** LoopBack test *********************/ 1243 struct be_cmd_req_loopback_test { 1244 struct be_cmd_req_hdr hdr; 1245 u32 loopback_type; 1246 u32 num_pkts; 1247 u64 pattern; 1248 u32 src_port; 1249 u32 dest_port; 1250 u32 pkt_size; 1251 }; 1252 1253 struct be_cmd_resp_loopback_test { 1254 struct be_cmd_resp_hdr resp_hdr; 1255 u32 status; 1256 u32 num_txfer; 1257 u32 num_rx; 1258 u32 miscomp_off; 1259 u32 ticks_compl; 1260 }; 1261 1262 struct be_cmd_req_set_lmode { 1263 struct be_cmd_req_hdr hdr; 1264 u8 src_port; 1265 u8 dest_port; 1266 u8 loopback_type; 1267 u8 loopback_state; 1268 }; 1269 1270 struct be_cmd_resp_set_lmode { 1271 struct be_cmd_resp_hdr resp_hdr; 1272 u8 rsvd0[4]; 1273 }; 1274 1275 /********************** DDR DMA test *********************/ 1276 struct be_cmd_req_ddrdma_test { 1277 struct be_cmd_req_hdr hdr; 1278 u64 pattern; 1279 u32 byte_count; 1280 u32 rsvd0; 1281 u8 snd_buff[4096]; 1282 u8 rsvd1[4096]; 1283 }; 1284 1285 struct be_cmd_resp_ddrdma_test { 1286 struct be_cmd_resp_hdr hdr; 1287 u64 pattern; 1288 u32 byte_cnt; 1289 u32 snd_err; 1290 u8 rsvd0[4096]; 1291 u8 rcv_buff[4096]; 1292 }; 1293 1294 /*********************** SEEPROM Read ***********************/ 1295 1296 #define BE_READ_SEEPROM_LEN 1024 1297 struct be_cmd_req_seeprom_read { 1298 struct be_cmd_req_hdr hdr; 1299 u8 rsvd0[BE_READ_SEEPROM_LEN]; 1300 }; 1301 1302 struct be_cmd_resp_seeprom_read { 1303 struct be_cmd_req_hdr hdr; 1304 u8 seeprom_data[BE_READ_SEEPROM_LEN]; 1305 }; 1306 1307 enum { 1308 PHY_TYPE_CX4_10GB = 0, 1309 PHY_TYPE_XFP_10GB, 1310 PHY_TYPE_SFP_1GB, 1311 PHY_TYPE_SFP_PLUS_10GB, 1312 PHY_TYPE_KR_10GB, 1313 PHY_TYPE_KX4_10GB, 1314 PHY_TYPE_BASET_10GB, 1315 PHY_TYPE_BASET_1GB, 1316 PHY_TYPE_BASEX_1GB, 1317 PHY_TYPE_SGMII, 1318 PHY_TYPE_DISABLED = 255 1319 }; 1320 1321 #define BE_SUPPORTED_SPEED_NONE 0 1322 #define BE_SUPPORTED_SPEED_10MBPS 1 1323 #define BE_SUPPORTED_SPEED_100MBPS 2 1324 #define BE_SUPPORTED_SPEED_1GBPS 4 1325 #define BE_SUPPORTED_SPEED_10GBPS 8 1326 1327 #define BE_AN_EN 0x2 1328 #define BE_PAUSE_SYM_EN 0x80 1329 1330 /* MAC speed valid values */ 1331 #define SPEED_DEFAULT 0x0 1332 #define SPEED_FORCED_10GB 0x1 1333 #define SPEED_FORCED_1GB 0x2 1334 #define SPEED_AUTONEG_10GB 0x3 1335 #define SPEED_AUTONEG_1GB 0x4 1336 #define SPEED_AUTONEG_100MB 0x5 1337 #define SPEED_AUTONEG_10GB_1GB 0x6 1338 #define SPEED_AUTONEG_10GB_1GB_100MB 0x7 1339 #define SPEED_AUTONEG_1GB_100MB 0x8 1340 #define SPEED_AUTONEG_10MB 0x9 1341 #define SPEED_AUTONEG_1GB_100MB_10MB 0xa 1342 #define SPEED_AUTONEG_100MB_10MB 0xb 1343 #define SPEED_FORCED_100MB 0xc 1344 #define SPEED_FORCED_10MB 0xd 1345 1346 struct be_cmd_req_get_phy_info { 1347 struct be_cmd_req_hdr hdr; 1348 u8 rsvd0[24]; 1349 }; 1350 1351 struct be_phy_info { 1352 u16 phy_type; 1353 u16 interface_type; 1354 u32 misc_params; 1355 u16 ext_phy_details; 1356 u16 rsvd; 1357 u16 auto_speeds_supported; 1358 u16 fixed_speeds_supported; 1359 u32 future_use[2]; 1360 }; 1361 1362 struct be_cmd_resp_get_phy_info { 1363 struct be_cmd_req_hdr hdr; 1364 struct be_phy_info phy_info; 1365 }; 1366 1367 /*********************** Set QOS ***********************/ 1368 1369 #define BE_QOS_BITS_NIC 1 1370 1371 struct be_cmd_req_set_qos { 1372 struct be_cmd_req_hdr hdr; 1373 u32 valid_bits; 1374 u32 max_bps_nic; 1375 u32 rsvd[7]; 1376 }; 1377 1378 struct be_cmd_resp_set_qos { 1379 struct be_cmd_resp_hdr hdr; 1380 u32 rsvd; 1381 }; 1382 1383 /*********************** Controller Attributes ***********************/ 1384 struct be_cmd_req_cntl_attribs { 1385 struct be_cmd_req_hdr hdr; 1386 }; 1387 1388 struct be_cmd_resp_cntl_attribs { 1389 struct be_cmd_resp_hdr hdr; 1390 struct mgmt_controller_attrib attribs; 1391 }; 1392 1393 /*********************** Set driver function ***********************/ 1394 #define CAPABILITY_SW_TIMESTAMPS 2 1395 #define CAPABILITY_BE3_NATIVE_ERX_API 4 1396 1397 struct be_cmd_req_set_func_cap { 1398 struct be_cmd_req_hdr hdr; 1399 u32 valid_cap_flags; 1400 u32 cap_flags; 1401 u8 rsvd[212]; 1402 }; 1403 1404 struct be_cmd_resp_set_func_cap { 1405 struct be_cmd_resp_hdr hdr; 1406 u32 valid_cap_flags; 1407 u32 cap_flags; 1408 u8 rsvd[212]; 1409 }; 1410 1411 /******************** GET/SET_MACLIST **************************/ 1412 #define BE_MAX_MAC 64 1413 struct be_cmd_req_get_mac_list { 1414 struct be_cmd_req_hdr hdr; 1415 u8 mac_type; 1416 u8 perm_override; 1417 u16 iface_id; 1418 u32 mac_id; 1419 u32 rsvd[3]; 1420 } __packed; 1421 1422 struct get_list_macaddr { 1423 u16 mac_addr_size; 1424 union { 1425 u8 macaddr[6]; 1426 struct { 1427 u8 rsvd[2]; 1428 u32 mac_id; 1429 } __packed s_mac_id; 1430 } __packed mac_addr_id; 1431 } __packed; 1432 1433 struct be_cmd_resp_get_mac_list { 1434 struct be_cmd_resp_hdr hdr; 1435 struct get_list_macaddr fd_macaddr; /* Factory default mac */ 1436 struct get_list_macaddr macid_macaddr; /* soft mac */ 1437 u8 true_mac_count; 1438 u8 pseudo_mac_count; 1439 u8 mac_list_size; 1440 u8 rsvd; 1441 /* perm override mac */ 1442 struct get_list_macaddr macaddr_list[BE_MAX_MAC]; 1443 } __packed; 1444 1445 struct be_cmd_req_set_mac_list { 1446 struct be_cmd_req_hdr hdr; 1447 u8 mac_count; 1448 u8 rsvd1; 1449 u16 rsvd2; 1450 struct macaddr mac[BE_MAX_MAC]; 1451 } __packed; 1452 1453 /*********************** HSW Config ***********************/ 1454 struct amap_set_hsw_context { 1455 u8 interface_id[16]; 1456 u8 rsvd0[14]; 1457 u8 pvid_valid; 1458 u8 rsvd1; 1459 u8 rsvd2[16]; 1460 u8 pvid[16]; 1461 u8 rsvd3[32]; 1462 u8 rsvd4[32]; 1463 u8 rsvd5[32]; 1464 } __packed; 1465 1466 struct be_cmd_req_set_hsw_config { 1467 struct be_cmd_req_hdr hdr; 1468 u8 context[sizeof(struct amap_set_hsw_context) / 8]; 1469 } __packed; 1470 1471 struct be_cmd_resp_set_hsw_config { 1472 struct be_cmd_resp_hdr hdr; 1473 u32 rsvd; 1474 }; 1475 1476 struct amap_get_hsw_req_context { 1477 u8 interface_id[16]; 1478 u8 rsvd0[14]; 1479 u8 pvid_valid; 1480 u8 pport; 1481 } __packed; 1482 1483 struct amap_get_hsw_resp_context { 1484 u8 rsvd1[16]; 1485 u8 pvid[16]; 1486 u8 rsvd2[32]; 1487 u8 rsvd3[32]; 1488 u8 rsvd4[32]; 1489 } __packed; 1490 1491 struct be_cmd_req_get_hsw_config { 1492 struct be_cmd_req_hdr hdr; 1493 u8 context[sizeof(struct amap_get_hsw_req_context) / 8]; 1494 } __packed; 1495 1496 struct be_cmd_resp_get_hsw_config { 1497 struct be_cmd_resp_hdr hdr; 1498 u8 context[sizeof(struct amap_get_hsw_resp_context) / 8]; 1499 u32 rsvd; 1500 }; 1501 1502 /*************** HW Stats Get v1 **********************************/ 1503 #define BE_TXP_SW_SZ 48 1504 struct be_port_rxf_stats_v1 { 1505 u32 rsvd0[12]; 1506 u32 rx_crc_errors; 1507 u32 rx_alignment_symbol_errors; 1508 u32 rx_pause_frames; 1509 u32 rx_priority_pause_frames; 1510 u32 rx_control_frames; 1511 u32 rx_in_range_errors; 1512 u32 rx_out_range_errors; 1513 u32 rx_frame_too_long; 1514 u32 rx_address_mismatch_drops; 1515 u32 rx_dropped_too_small; 1516 u32 rx_dropped_too_short; 1517 u32 rx_dropped_header_too_small; 1518 u32 rx_dropped_tcp_length; 1519 u32 rx_dropped_runt; 1520 u32 rsvd1[10]; 1521 u32 rx_ip_checksum_errs; 1522 u32 rx_tcp_checksum_errs; 1523 u32 rx_udp_checksum_errs; 1524 u32 rsvd2[7]; 1525 u32 rx_switched_unicast_packets; 1526 u32 rx_switched_multicast_packets; 1527 u32 rx_switched_broadcast_packets; 1528 u32 rsvd3[3]; 1529 u32 tx_pauseframes; 1530 u32 tx_priority_pauseframes; 1531 u32 tx_controlframes; 1532 u32 rsvd4[10]; 1533 u32 rxpp_fifo_overflow_drop; 1534 u32 rx_input_fifo_overflow_drop; 1535 u32 pmem_fifo_overflow_drop; 1536 u32 jabber_events; 1537 u32 rsvd5[3]; 1538 }; 1539 1540 1541 struct be_rxf_stats_v1 { 1542 struct be_port_rxf_stats_v1 port[4]; 1543 u32 rsvd0[2]; 1544 u32 rx_drops_no_pbuf; 1545 u32 rx_drops_no_txpb; 1546 u32 rx_drops_no_erx_descr; 1547 u32 rx_drops_no_tpre_descr; 1548 u32 rsvd1[6]; 1549 u32 rx_drops_too_many_frags; 1550 u32 rx_drops_invalid_ring; 1551 u32 forwarded_packets; 1552 u32 rx_drops_mtu; 1553 u32 rsvd2[14]; 1554 }; 1555 1556 struct be_erx_stats_v1 { 1557 u32 rx_drops_no_fragments[68]; /* dwordS 0 to 67*/ 1558 u32 rsvd[4]; 1559 }; 1560 1561 struct be_hw_stats_v1 { 1562 struct be_rxf_stats_v1 rxf; 1563 u32 rsvd0[BE_TXP_SW_SZ]; 1564 struct be_erx_stats_v1 erx; 1565 struct be_pmem_stats pmem; 1566 u32 rsvd1[3]; 1567 }; 1568 1569 struct be_cmd_req_get_stats_v1 { 1570 struct be_cmd_req_hdr hdr; 1571 u8 rsvd[sizeof(struct be_hw_stats_v1)]; 1572 }; 1573 1574 struct be_cmd_resp_get_stats_v1 { 1575 struct be_cmd_resp_hdr hdr; 1576 struct be_hw_stats_v1 hw_stats; 1577 }; 1578 1579 static inline void *hw_stats_from_cmd(struct be_adapter *adapter) 1580 { 1581 if (adapter->generation == BE_GEN3) { 1582 struct be_cmd_resp_get_stats_v1 *cmd = adapter->stats_cmd.va; 1583 1584 return &cmd->hw_stats; 1585 } else { 1586 struct be_cmd_resp_get_stats_v0 *cmd = adapter->stats_cmd.va; 1587 1588 return &cmd->hw_stats; 1589 } 1590 } 1591 1592 static inline void *be_erx_stats_from_cmd(struct be_adapter *adapter) 1593 { 1594 if (adapter->generation == BE_GEN3) { 1595 struct be_hw_stats_v1 *hw_stats = hw_stats_from_cmd(adapter); 1596 1597 return &hw_stats->erx; 1598 } else { 1599 struct be_hw_stats_v0 *hw_stats = hw_stats_from_cmd(adapter); 1600 1601 return &hw_stats->erx; 1602 } 1603 } 1604 1605 extern int be_pci_fnum_get(struct be_adapter *adapter); 1606 extern int be_cmd_POST(struct be_adapter *adapter); 1607 extern int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr, 1608 u8 type, bool permanent, u32 if_handle, u32 pmac_id); 1609 extern int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr, 1610 u32 if_id, u32 *pmac_id, u32 domain); 1611 extern int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, 1612 int pmac_id, u32 domain); 1613 extern int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, 1614 u32 en_flags, u8 *mac, u32 *if_handle, u32 *pmac_id, 1615 u32 domain); 1616 extern int be_cmd_if_destroy(struct be_adapter *adapter, int if_handle, 1617 u32 domain); 1618 extern int be_cmd_eq_create(struct be_adapter *adapter, 1619 struct be_queue_info *eq, int eq_delay); 1620 extern int be_cmd_cq_create(struct be_adapter *adapter, 1621 struct be_queue_info *cq, struct be_queue_info *eq, 1622 bool no_delay, int num_cqe_dma_coalesce); 1623 extern int be_cmd_mccq_create(struct be_adapter *adapter, 1624 struct be_queue_info *mccq, 1625 struct be_queue_info *cq); 1626 extern int be_cmd_txq_create(struct be_adapter *adapter, 1627 struct be_queue_info *txq, 1628 struct be_queue_info *cq); 1629 extern int be_cmd_rxq_create(struct be_adapter *adapter, 1630 struct be_queue_info *rxq, u16 cq_id, 1631 u16 frag_size, u32 if_id, u32 rss, u8 *rss_id); 1632 extern int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q, 1633 int type); 1634 extern int be_cmd_rxq_destroy(struct be_adapter *adapter, 1635 struct be_queue_info *q); 1636 extern int be_cmd_link_status_query(struct be_adapter *adapter, u8 *mac_speed, 1637 u16 *link_speed, u8 *link_status, u32 dom); 1638 extern int be_cmd_reset(struct be_adapter *adapter); 1639 extern int be_cmd_get_stats(struct be_adapter *adapter, 1640 struct be_dma_mem *nonemb_cmd); 1641 extern int lancer_cmd_get_pport_stats(struct be_adapter *adapter, 1642 struct be_dma_mem *nonemb_cmd); 1643 extern int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver, 1644 char *fw_on_flash); 1645 1646 extern int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd); 1647 extern int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, 1648 u16 *vtag_array, u32 num, bool untagged, 1649 bool promiscuous); 1650 extern int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 status); 1651 extern int be_cmd_set_flow_control(struct be_adapter *adapter, 1652 u32 tx_fc, u32 rx_fc); 1653 extern int be_cmd_get_flow_control(struct be_adapter *adapter, 1654 u32 *tx_fc, u32 *rx_fc); 1655 extern int be_cmd_query_fw_cfg(struct be_adapter *adapter, 1656 u32 *port_num, u32 *function_mode, u32 *function_caps); 1657 extern int be_cmd_reset_function(struct be_adapter *adapter); 1658 extern int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable, 1659 u16 table_size); 1660 extern int be_process_mcc(struct be_adapter *adapter); 1661 extern int be_cmd_set_beacon_state(struct be_adapter *adapter, 1662 u8 port_num, u8 beacon, u8 status, u8 state); 1663 extern int be_cmd_get_beacon_state(struct be_adapter *adapter, 1664 u8 port_num, u32 *state); 1665 extern int be_cmd_write_flashrom(struct be_adapter *adapter, 1666 struct be_dma_mem *cmd, u32 flash_oper, 1667 u32 flash_opcode, u32 buf_size); 1668 extern int lancer_cmd_write_object(struct be_adapter *adapter, 1669 struct be_dma_mem *cmd, 1670 u32 data_size, u32 data_offset, 1671 const char *obj_name, 1672 u32 *data_written, u8 *addn_status); 1673 int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd, 1674 u32 data_size, u32 data_offset, const char *obj_name, 1675 u32 *data_read, u32 *eof, u8 *addn_status); 1676 int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc, 1677 int offset); 1678 extern int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac, 1679 struct be_dma_mem *nonemb_cmd); 1680 extern int be_cmd_fw_init(struct be_adapter *adapter); 1681 extern int be_cmd_fw_clean(struct be_adapter *adapter); 1682 extern void be_async_mcc_enable(struct be_adapter *adapter); 1683 extern void be_async_mcc_disable(struct be_adapter *adapter); 1684 extern int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num, 1685 u32 loopback_type, u32 pkt_size, 1686 u32 num_pkts, u64 pattern); 1687 extern int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern, 1688 u32 byte_cnt, struct be_dma_mem *cmd); 1689 extern int be_cmd_get_seeprom_data(struct be_adapter *adapter, 1690 struct be_dma_mem *nonemb_cmd); 1691 extern int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num, 1692 u8 loopback_type, u8 enable); 1693 extern int be_cmd_get_phy_info(struct be_adapter *adapter); 1694 extern int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain); 1695 extern void be_detect_dump_ue(struct be_adapter *adapter); 1696 extern int be_cmd_get_die_temperature(struct be_adapter *adapter); 1697 extern int be_cmd_get_cntl_attributes(struct be_adapter *adapter); 1698 extern int be_cmd_req_native_mode(struct be_adapter *adapter); 1699 extern int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size); 1700 extern void be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf); 1701 extern int be_cmd_get_mac_from_list(struct be_adapter *adapter, u32 domain, 1702 bool *pmac_id_active, u32 *pmac_id, u8 *mac); 1703 extern int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array, 1704 u8 mac_count, u32 domain); 1705 extern int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid, 1706 u32 domain, u16 intf_id); 1707 extern int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid, 1708 u32 domain, u16 intf_id); 1709 extern int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter); 1710 1711