1 /* 2 * Copyright (C) 2005 - 2011 Emulex 3 * All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License version 2 7 * as published by the Free Software Foundation. The full GNU General 8 * Public License is included in this distribution in the file called COPYING. 9 * 10 * Contact Information: 11 * linux-drivers@emulex.com 12 * 13 * Emulex 14 * 3333 Susan Street 15 * Costa Mesa, CA 92626 16 */ 17 18 /* 19 * The driver sends configuration and managements command requests to the 20 * firmware in the BE. These requests are communicated to the processor 21 * using Work Request Blocks (WRBs) submitted to the MCC-WRB ring or via one 22 * WRB inside a MAILBOX. 23 * The commands are serviced by the ARM processor in the BladeEngine's MPU. 24 */ 25 26 struct be_sge { 27 u32 pa_lo; 28 u32 pa_hi; 29 u32 len; 30 }; 31 32 #define MCC_WRB_EMBEDDED_MASK 1 /* bit 0 of dword 0*/ 33 #define MCC_WRB_SGE_CNT_SHIFT 3 /* bits 3 - 7 of dword 0 */ 34 #define MCC_WRB_SGE_CNT_MASK 0x1F /* bits 3 - 7 of dword 0 */ 35 struct be_mcc_wrb { 36 u32 embedded; /* dword 0 */ 37 u32 payload_length; /* dword 1 */ 38 u32 tag0; /* dword 2 */ 39 u32 tag1; /* dword 3 */ 40 u32 rsvd; /* dword 4 */ 41 union { 42 u8 embedded_payload[236]; /* used by embedded cmds */ 43 struct be_sge sgl[19]; /* used by non-embedded cmds */ 44 } payload; 45 }; 46 47 #define CQE_FLAGS_VALID_MASK (1 << 31) 48 #define CQE_FLAGS_ASYNC_MASK (1 << 30) 49 #define CQE_FLAGS_COMPLETED_MASK (1 << 28) 50 #define CQE_FLAGS_CONSUMED_MASK (1 << 27) 51 52 /* Completion Status */ 53 enum { 54 MCC_STATUS_SUCCESS = 0, 55 MCC_STATUS_FAILED = 1, 56 MCC_STATUS_ILLEGAL_REQUEST = 2, 57 MCC_STATUS_ILLEGAL_FIELD = 3, 58 MCC_STATUS_INSUFFICIENT_BUFFER = 4, 59 MCC_STATUS_UNAUTHORIZED_REQUEST = 5, 60 MCC_STATUS_NOT_SUPPORTED = 66 61 }; 62 63 #define CQE_STATUS_COMPL_MASK 0xFFFF 64 #define CQE_STATUS_COMPL_SHIFT 0 /* bits 0 - 15 */ 65 #define CQE_STATUS_EXTD_MASK 0xFFFF 66 #define CQE_STATUS_EXTD_SHIFT 16 /* bits 16 - 31 */ 67 68 struct be_mcc_compl { 69 u32 status; /* dword 0 */ 70 u32 tag0; /* dword 1 */ 71 u32 tag1; /* dword 2 */ 72 u32 flags; /* dword 3 */ 73 }; 74 75 /* When the async bit of mcc_compl is set, the last 4 bytes of 76 * mcc_compl is interpreted as follows: 77 */ 78 #define ASYNC_TRAILER_EVENT_CODE_SHIFT 8 /* bits 8 - 15 */ 79 #define ASYNC_TRAILER_EVENT_CODE_MASK 0xFF 80 #define ASYNC_TRAILER_EVENT_TYPE_SHIFT 16 81 #define ASYNC_TRAILER_EVENT_TYPE_MASK 0xFF 82 #define ASYNC_EVENT_CODE_LINK_STATE 0x1 83 #define ASYNC_EVENT_CODE_GRP_5 0x5 84 #define ASYNC_EVENT_QOS_SPEED 0x1 85 #define ASYNC_EVENT_COS_PRIORITY 0x2 86 #define ASYNC_EVENT_PVID_STATE 0x3 87 struct be_async_event_trailer { 88 u32 code; 89 }; 90 91 enum { 92 LINK_DOWN = 0x0, 93 LINK_UP = 0x1 94 }; 95 #define LINK_STATUS_MASK 0x1 96 97 /* When the event code of an async trailer is link-state, the mcc_compl 98 * must be interpreted as follows 99 */ 100 struct be_async_event_link_state { 101 u8 physical_port; 102 u8 port_link_status; 103 u8 port_duplex; 104 u8 port_speed; 105 u8 port_fault; 106 u8 rsvd0[7]; 107 struct be_async_event_trailer trailer; 108 } __packed; 109 110 /* When the event code of an async trailer is GRP-5 and event_type is QOS_SPEED 111 * the mcc_compl must be interpreted as follows 112 */ 113 struct be_async_event_grp5_qos_link_speed { 114 u8 physical_port; 115 u8 rsvd[5]; 116 u16 qos_link_speed; 117 u32 event_tag; 118 struct be_async_event_trailer trailer; 119 } __packed; 120 121 /* When the event code of an async trailer is GRP5 and event type is 122 * CoS-Priority, the mcc_compl must be interpreted as follows 123 */ 124 struct be_async_event_grp5_cos_priority { 125 u8 physical_port; 126 u8 available_priority_bmap; 127 u8 reco_default_priority; 128 u8 valid; 129 u8 rsvd0; 130 u8 event_tag; 131 struct be_async_event_trailer trailer; 132 } __packed; 133 134 /* When the event code of an async trailer is GRP5 and event type is 135 * PVID state, the mcc_compl must be interpreted as follows 136 */ 137 struct be_async_event_grp5_pvid_state { 138 u8 enabled; 139 u8 rsvd0; 140 u16 tag; 141 u32 event_tag; 142 u32 rsvd1; 143 struct be_async_event_trailer trailer; 144 } __packed; 145 146 struct be_mcc_mailbox { 147 struct be_mcc_wrb wrb; 148 struct be_mcc_compl compl; 149 }; 150 151 #define CMD_SUBSYSTEM_COMMON 0x1 152 #define CMD_SUBSYSTEM_ETH 0x3 153 #define CMD_SUBSYSTEM_LOWLEVEL 0xb 154 155 #define OPCODE_COMMON_NTWK_MAC_QUERY 1 156 #define OPCODE_COMMON_NTWK_MAC_SET 2 157 #define OPCODE_COMMON_NTWK_MULTICAST_SET 3 158 #define OPCODE_COMMON_NTWK_VLAN_CONFIG 4 159 #define OPCODE_COMMON_NTWK_LINK_STATUS_QUERY 5 160 #define OPCODE_COMMON_READ_FLASHROM 6 161 #define OPCODE_COMMON_WRITE_FLASHROM 7 162 #define OPCODE_COMMON_CQ_CREATE 12 163 #define OPCODE_COMMON_EQ_CREATE 13 164 #define OPCODE_COMMON_MCC_CREATE 21 165 #define OPCODE_COMMON_SET_QOS 28 166 #define OPCODE_COMMON_MCC_CREATE_EXT 90 167 #define OPCODE_COMMON_SEEPROM_READ 30 168 #define OPCODE_COMMON_GET_CNTL_ATTRIBUTES 32 169 #define OPCODE_COMMON_NTWK_RX_FILTER 34 170 #define OPCODE_COMMON_GET_FW_VERSION 35 171 #define OPCODE_COMMON_SET_FLOW_CONTROL 36 172 #define OPCODE_COMMON_GET_FLOW_CONTROL 37 173 #define OPCODE_COMMON_SET_FRAME_SIZE 39 174 #define OPCODE_COMMON_MODIFY_EQ_DELAY 41 175 #define OPCODE_COMMON_FIRMWARE_CONFIG 42 176 #define OPCODE_COMMON_NTWK_INTERFACE_CREATE 50 177 #define OPCODE_COMMON_NTWK_INTERFACE_DESTROY 51 178 #define OPCODE_COMMON_MCC_DESTROY 53 179 #define OPCODE_COMMON_CQ_DESTROY 54 180 #define OPCODE_COMMON_EQ_DESTROY 55 181 #define OPCODE_COMMON_QUERY_FIRMWARE_CONFIG 58 182 #define OPCODE_COMMON_NTWK_PMAC_ADD 59 183 #define OPCODE_COMMON_NTWK_PMAC_DEL 60 184 #define OPCODE_COMMON_FUNCTION_RESET 61 185 #define OPCODE_COMMON_MANAGE_FAT 68 186 #define OPCODE_COMMON_ENABLE_DISABLE_BEACON 69 187 #define OPCODE_COMMON_GET_BEACON_STATE 70 188 #define OPCODE_COMMON_READ_TRANSRECV_DATA 73 189 #define OPCODE_COMMON_GET_PHY_DETAILS 102 190 #define OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP 103 191 #define OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES 121 192 #define OPCODE_COMMON_GET_EXT_FAT_CAPABILITES 125 193 #define OPCODE_COMMON_SET_EXT_FAT_CAPABILITES 126 194 #define OPCODE_COMMON_GET_MAC_LIST 147 195 #define OPCODE_COMMON_SET_MAC_LIST 148 196 #define OPCODE_COMMON_GET_HSW_CONFIG 152 197 #define OPCODE_COMMON_SET_HSW_CONFIG 153 198 #define OPCODE_COMMON_READ_OBJECT 171 199 #define OPCODE_COMMON_WRITE_OBJECT 172 200 201 #define OPCODE_ETH_RSS_CONFIG 1 202 #define OPCODE_ETH_ACPI_CONFIG 2 203 #define OPCODE_ETH_PROMISCUOUS 3 204 #define OPCODE_ETH_GET_STATISTICS 4 205 #define OPCODE_ETH_TX_CREATE 7 206 #define OPCODE_ETH_RX_CREATE 8 207 #define OPCODE_ETH_TX_DESTROY 9 208 #define OPCODE_ETH_RX_DESTROY 10 209 #define OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG 12 210 #define OPCODE_ETH_GET_PPORT_STATS 18 211 212 #define OPCODE_LOWLEVEL_HOST_DDR_DMA 17 213 #define OPCODE_LOWLEVEL_LOOPBACK_TEST 18 214 #define OPCODE_LOWLEVEL_SET_LOOPBACK_MODE 19 215 216 struct be_cmd_req_hdr { 217 u8 opcode; /* dword 0 */ 218 u8 subsystem; /* dword 0 */ 219 u8 port_number; /* dword 0 */ 220 u8 domain; /* dword 0 */ 221 u32 timeout; /* dword 1 */ 222 u32 request_length; /* dword 2 */ 223 u8 version; /* dword 3 */ 224 u8 rsvd[3]; /* dword 3 */ 225 }; 226 227 #define RESP_HDR_INFO_OPCODE_SHIFT 0 /* bits 0 - 7 */ 228 #define RESP_HDR_INFO_SUBSYS_SHIFT 8 /* bits 8 - 15 */ 229 struct be_cmd_resp_hdr { 230 u8 opcode; /* dword 0 */ 231 u8 subsystem; /* dword 0 */ 232 u8 rsvd[2]; /* dword 0 */ 233 u8 status; /* dword 1 */ 234 u8 add_status; /* dword 1 */ 235 u8 rsvd1[2]; /* dword 1 */ 236 u32 response_length; /* dword 2 */ 237 u32 actual_resp_len; /* dword 3 */ 238 }; 239 240 struct phys_addr { 241 u32 lo; 242 u32 hi; 243 }; 244 245 /************************** 246 * BE Command definitions * 247 **************************/ 248 249 /* Pseudo amap definition in which each bit of the actual structure is defined 250 * as a byte: used to calculate offset/shift/mask of each field */ 251 struct amap_eq_context { 252 u8 cidx[13]; /* dword 0*/ 253 u8 rsvd0[3]; /* dword 0*/ 254 u8 epidx[13]; /* dword 0*/ 255 u8 valid; /* dword 0*/ 256 u8 rsvd1; /* dword 0*/ 257 u8 size; /* dword 0*/ 258 u8 pidx[13]; /* dword 1*/ 259 u8 rsvd2[3]; /* dword 1*/ 260 u8 pd[10]; /* dword 1*/ 261 u8 count[3]; /* dword 1*/ 262 u8 solevent; /* dword 1*/ 263 u8 stalled; /* dword 1*/ 264 u8 armed; /* dword 1*/ 265 u8 rsvd3[4]; /* dword 2*/ 266 u8 func[8]; /* dword 2*/ 267 u8 rsvd4; /* dword 2*/ 268 u8 delaymult[10]; /* dword 2*/ 269 u8 rsvd5[2]; /* dword 2*/ 270 u8 phase[2]; /* dword 2*/ 271 u8 nodelay; /* dword 2*/ 272 u8 rsvd6[4]; /* dword 2*/ 273 u8 rsvd7[32]; /* dword 3*/ 274 } __packed; 275 276 struct be_cmd_req_eq_create { 277 struct be_cmd_req_hdr hdr; 278 u16 num_pages; /* sword */ 279 u16 rsvd0; /* sword */ 280 u8 context[sizeof(struct amap_eq_context) / 8]; 281 struct phys_addr pages[8]; 282 } __packed; 283 284 struct be_cmd_resp_eq_create { 285 struct be_cmd_resp_hdr resp_hdr; 286 u16 eq_id; /* sword */ 287 u16 rsvd0; /* sword */ 288 } __packed; 289 290 /******************** Mac query ***************************/ 291 enum { 292 MAC_ADDRESS_TYPE_STORAGE = 0x0, 293 MAC_ADDRESS_TYPE_NETWORK = 0x1, 294 MAC_ADDRESS_TYPE_PD = 0x2, 295 MAC_ADDRESS_TYPE_MANAGEMENT = 0x3 296 }; 297 298 struct mac_addr { 299 u16 size_of_struct; 300 u8 addr[ETH_ALEN]; 301 } __packed; 302 303 struct be_cmd_req_mac_query { 304 struct be_cmd_req_hdr hdr; 305 u8 type; 306 u8 permanent; 307 u16 if_id; 308 u32 pmac_id; 309 } __packed; 310 311 struct be_cmd_resp_mac_query { 312 struct be_cmd_resp_hdr hdr; 313 struct mac_addr mac; 314 }; 315 316 /******************** PMac Add ***************************/ 317 struct be_cmd_req_pmac_add { 318 struct be_cmd_req_hdr hdr; 319 u32 if_id; 320 u8 mac_address[ETH_ALEN]; 321 u8 rsvd0[2]; 322 } __packed; 323 324 struct be_cmd_resp_pmac_add { 325 struct be_cmd_resp_hdr hdr; 326 u32 pmac_id; 327 }; 328 329 /******************** PMac Del ***************************/ 330 struct be_cmd_req_pmac_del { 331 struct be_cmd_req_hdr hdr; 332 u32 if_id; 333 u32 pmac_id; 334 }; 335 336 /******************** Create CQ ***************************/ 337 /* Pseudo amap definition in which each bit of the actual structure is defined 338 * as a byte: used to calculate offset/shift/mask of each field */ 339 struct amap_cq_context_be { 340 u8 cidx[11]; /* dword 0*/ 341 u8 rsvd0; /* dword 0*/ 342 u8 coalescwm[2]; /* dword 0*/ 343 u8 nodelay; /* dword 0*/ 344 u8 epidx[11]; /* dword 0*/ 345 u8 rsvd1; /* dword 0*/ 346 u8 count[2]; /* dword 0*/ 347 u8 valid; /* dword 0*/ 348 u8 solevent; /* dword 0*/ 349 u8 eventable; /* dword 0*/ 350 u8 pidx[11]; /* dword 1*/ 351 u8 rsvd2; /* dword 1*/ 352 u8 pd[10]; /* dword 1*/ 353 u8 eqid[8]; /* dword 1*/ 354 u8 stalled; /* dword 1*/ 355 u8 armed; /* dword 1*/ 356 u8 rsvd3[4]; /* dword 2*/ 357 u8 func[8]; /* dword 2*/ 358 u8 rsvd4[20]; /* dword 2*/ 359 u8 rsvd5[32]; /* dword 3*/ 360 } __packed; 361 362 struct amap_cq_context_lancer { 363 u8 rsvd0[12]; /* dword 0*/ 364 u8 coalescwm[2]; /* dword 0*/ 365 u8 nodelay; /* dword 0*/ 366 u8 rsvd1[12]; /* dword 0*/ 367 u8 count[2]; /* dword 0*/ 368 u8 valid; /* dword 0*/ 369 u8 rsvd2; /* dword 0*/ 370 u8 eventable; /* dword 0*/ 371 u8 eqid[16]; /* dword 1*/ 372 u8 rsvd3[15]; /* dword 1*/ 373 u8 armed; /* dword 1*/ 374 u8 rsvd4[32]; /* dword 2*/ 375 u8 rsvd5[32]; /* dword 3*/ 376 } __packed; 377 378 struct be_cmd_req_cq_create { 379 struct be_cmd_req_hdr hdr; 380 u16 num_pages; 381 u8 page_size; 382 u8 rsvd0; 383 u8 context[sizeof(struct amap_cq_context_be) / 8]; 384 struct phys_addr pages[8]; 385 } __packed; 386 387 388 struct be_cmd_resp_cq_create { 389 struct be_cmd_resp_hdr hdr; 390 u16 cq_id; 391 u16 rsvd0; 392 } __packed; 393 394 struct be_cmd_req_get_fat { 395 struct be_cmd_req_hdr hdr; 396 u32 fat_operation; 397 u32 read_log_offset; 398 u32 read_log_length; 399 u32 data_buffer_size; 400 u32 data_buffer[1]; 401 } __packed; 402 403 struct be_cmd_resp_get_fat { 404 struct be_cmd_resp_hdr hdr; 405 u32 log_size; 406 u32 read_log_length; 407 u32 rsvd[2]; 408 u32 data_buffer[1]; 409 } __packed; 410 411 412 /******************** Create MCCQ ***************************/ 413 /* Pseudo amap definition in which each bit of the actual structure is defined 414 * as a byte: used to calculate offset/shift/mask of each field */ 415 struct amap_mcc_context_be { 416 u8 con_index[14]; 417 u8 rsvd0[2]; 418 u8 ring_size[4]; 419 u8 fetch_wrb; 420 u8 fetch_r2t; 421 u8 cq_id[10]; 422 u8 prod_index[14]; 423 u8 fid[8]; 424 u8 pdid[9]; 425 u8 valid; 426 u8 rsvd1[32]; 427 u8 rsvd2[32]; 428 } __packed; 429 430 struct amap_mcc_context_lancer { 431 u8 async_cq_id[16]; 432 u8 ring_size[4]; 433 u8 rsvd0[12]; 434 u8 rsvd1[31]; 435 u8 valid; 436 u8 async_cq_valid[1]; 437 u8 rsvd2[31]; 438 u8 rsvd3[32]; 439 } __packed; 440 441 struct be_cmd_req_mcc_create { 442 struct be_cmd_req_hdr hdr; 443 u16 num_pages; 444 u16 cq_id; 445 u8 context[sizeof(struct amap_mcc_context_be) / 8]; 446 struct phys_addr pages[8]; 447 } __packed; 448 449 struct be_cmd_req_mcc_ext_create { 450 struct be_cmd_req_hdr hdr; 451 u16 num_pages; 452 u16 cq_id; 453 u32 async_event_bitmap[1]; 454 u8 context[sizeof(struct amap_mcc_context_be) / 8]; 455 struct phys_addr pages[8]; 456 } __packed; 457 458 struct be_cmd_resp_mcc_create { 459 struct be_cmd_resp_hdr hdr; 460 u16 id; 461 u16 rsvd0; 462 } __packed; 463 464 /******************** Create TxQ ***************************/ 465 #define BE_ETH_TX_RING_TYPE_STANDARD 2 466 #define BE_ULP1_NUM 1 467 468 /* Pseudo amap definition in which each bit of the actual structure is defined 469 * as a byte: used to calculate offset/shift/mask of each field */ 470 struct amap_tx_context { 471 u8 if_id[16]; /* dword 0 */ 472 u8 tx_ring_size[4]; /* dword 0 */ 473 u8 rsvd1[26]; /* dword 0 */ 474 u8 pci_func_id[8]; /* dword 1 */ 475 u8 rsvd2[9]; /* dword 1 */ 476 u8 ctx_valid; /* dword 1 */ 477 u8 cq_id_send[16]; /* dword 2 */ 478 u8 rsvd3[16]; /* dword 2 */ 479 u8 rsvd4[32]; /* dword 3 */ 480 u8 rsvd5[32]; /* dword 4 */ 481 u8 rsvd6[32]; /* dword 5 */ 482 u8 rsvd7[32]; /* dword 6 */ 483 u8 rsvd8[32]; /* dword 7 */ 484 u8 rsvd9[32]; /* dword 8 */ 485 u8 rsvd10[32]; /* dword 9 */ 486 u8 rsvd11[32]; /* dword 10 */ 487 u8 rsvd12[32]; /* dword 11 */ 488 u8 rsvd13[32]; /* dword 12 */ 489 u8 rsvd14[32]; /* dword 13 */ 490 u8 rsvd15[32]; /* dword 14 */ 491 u8 rsvd16[32]; /* dword 15 */ 492 } __packed; 493 494 struct be_cmd_req_eth_tx_create { 495 struct be_cmd_req_hdr hdr; 496 u8 num_pages; 497 u8 ulp_num; 498 u8 type; 499 u8 bound_port; 500 u8 context[sizeof(struct amap_tx_context) / 8]; 501 struct phys_addr pages[8]; 502 } __packed; 503 504 struct be_cmd_resp_eth_tx_create { 505 struct be_cmd_resp_hdr hdr; 506 u16 cid; 507 u16 rsvd0; 508 } __packed; 509 510 /******************** Create RxQ ***************************/ 511 struct be_cmd_req_eth_rx_create { 512 struct be_cmd_req_hdr hdr; 513 u16 cq_id; 514 u8 frag_size; 515 u8 num_pages; 516 struct phys_addr pages[2]; 517 u32 interface_id; 518 u16 max_frame_size; 519 u16 rsvd0; 520 u32 rss_queue; 521 } __packed; 522 523 struct be_cmd_resp_eth_rx_create { 524 struct be_cmd_resp_hdr hdr; 525 u16 id; 526 u8 rss_id; 527 u8 rsvd0; 528 } __packed; 529 530 /******************** Q Destroy ***************************/ 531 /* Type of Queue to be destroyed */ 532 enum { 533 QTYPE_EQ = 1, 534 QTYPE_CQ, 535 QTYPE_TXQ, 536 QTYPE_RXQ, 537 QTYPE_MCCQ 538 }; 539 540 struct be_cmd_req_q_destroy { 541 struct be_cmd_req_hdr hdr; 542 u16 id; 543 u16 bypass_flush; /* valid only for rx q destroy */ 544 } __packed; 545 546 /************ I/f Create (it's actually I/f Config Create)**********/ 547 548 /* Capability flags for the i/f */ 549 enum be_if_flags { 550 BE_IF_FLAGS_RSS = 0x4, 551 BE_IF_FLAGS_PROMISCUOUS = 0x8, 552 BE_IF_FLAGS_BROADCAST = 0x10, 553 BE_IF_FLAGS_UNTAGGED = 0x20, 554 BE_IF_FLAGS_ULP = 0x40, 555 BE_IF_FLAGS_VLAN_PROMISCUOUS = 0x80, 556 BE_IF_FLAGS_VLAN = 0x100, 557 BE_IF_FLAGS_MCAST_PROMISCUOUS = 0x200, 558 BE_IF_FLAGS_PASS_L2_ERRORS = 0x400, 559 BE_IF_FLAGS_PASS_L3L4_ERRORS = 0x800, 560 BE_IF_FLAGS_MULTICAST = 0x1000 561 }; 562 563 /* An RX interface is an object with one or more MAC addresses and 564 * filtering capabilities. */ 565 struct be_cmd_req_if_create { 566 struct be_cmd_req_hdr hdr; 567 u32 version; /* ignore currently */ 568 u32 capability_flags; 569 u32 enable_flags; 570 u8 mac_addr[ETH_ALEN]; 571 u8 rsvd0; 572 u8 pmac_invalid; /* if set, don't attach the mac addr to the i/f */ 573 u32 vlan_tag; /* not used currently */ 574 } __packed; 575 576 struct be_cmd_resp_if_create { 577 struct be_cmd_resp_hdr hdr; 578 u32 interface_id; 579 u32 pmac_id; 580 }; 581 582 /****** I/f Destroy(it's actually I/f Config Destroy )**********/ 583 struct be_cmd_req_if_destroy { 584 struct be_cmd_req_hdr hdr; 585 u32 interface_id; 586 }; 587 588 /*************** HW Stats Get **********************************/ 589 struct be_port_rxf_stats_v0 { 590 u32 rx_bytes_lsd; /* dword 0*/ 591 u32 rx_bytes_msd; /* dword 1*/ 592 u32 rx_total_frames; /* dword 2*/ 593 u32 rx_unicast_frames; /* dword 3*/ 594 u32 rx_multicast_frames; /* dword 4*/ 595 u32 rx_broadcast_frames; /* dword 5*/ 596 u32 rx_crc_errors; /* dword 6*/ 597 u32 rx_alignment_symbol_errors; /* dword 7*/ 598 u32 rx_pause_frames; /* dword 8*/ 599 u32 rx_control_frames; /* dword 9*/ 600 u32 rx_in_range_errors; /* dword 10*/ 601 u32 rx_out_range_errors; /* dword 11*/ 602 u32 rx_frame_too_long; /* dword 12*/ 603 u32 rx_address_mismatch_drops; /* dword 13*/ 604 u32 rx_vlan_mismatch_drops; /* dword 14*/ 605 u32 rx_dropped_too_small; /* dword 15*/ 606 u32 rx_dropped_too_short; /* dword 16*/ 607 u32 rx_dropped_header_too_small; /* dword 17*/ 608 u32 rx_dropped_tcp_length; /* dword 18*/ 609 u32 rx_dropped_runt; /* dword 19*/ 610 u32 rx_64_byte_packets; /* dword 20*/ 611 u32 rx_65_127_byte_packets; /* dword 21*/ 612 u32 rx_128_256_byte_packets; /* dword 22*/ 613 u32 rx_256_511_byte_packets; /* dword 23*/ 614 u32 rx_512_1023_byte_packets; /* dword 24*/ 615 u32 rx_1024_1518_byte_packets; /* dword 25*/ 616 u32 rx_1519_2047_byte_packets; /* dword 26*/ 617 u32 rx_2048_4095_byte_packets; /* dword 27*/ 618 u32 rx_4096_8191_byte_packets; /* dword 28*/ 619 u32 rx_8192_9216_byte_packets; /* dword 29*/ 620 u32 rx_ip_checksum_errs; /* dword 30*/ 621 u32 rx_tcp_checksum_errs; /* dword 31*/ 622 u32 rx_udp_checksum_errs; /* dword 32*/ 623 u32 rx_non_rss_packets; /* dword 33*/ 624 u32 rx_ipv4_packets; /* dword 34*/ 625 u32 rx_ipv6_packets; /* dword 35*/ 626 u32 rx_ipv4_bytes_lsd; /* dword 36*/ 627 u32 rx_ipv4_bytes_msd; /* dword 37*/ 628 u32 rx_ipv6_bytes_lsd; /* dword 38*/ 629 u32 rx_ipv6_bytes_msd; /* dword 39*/ 630 u32 rx_chute1_packets; /* dword 40*/ 631 u32 rx_chute2_packets; /* dword 41*/ 632 u32 rx_chute3_packets; /* dword 42*/ 633 u32 rx_management_packets; /* dword 43*/ 634 u32 rx_switched_unicast_packets; /* dword 44*/ 635 u32 rx_switched_multicast_packets; /* dword 45*/ 636 u32 rx_switched_broadcast_packets; /* dword 46*/ 637 u32 tx_bytes_lsd; /* dword 47*/ 638 u32 tx_bytes_msd; /* dword 48*/ 639 u32 tx_unicastframes; /* dword 49*/ 640 u32 tx_multicastframes; /* dword 50*/ 641 u32 tx_broadcastframes; /* dword 51*/ 642 u32 tx_pauseframes; /* dword 52*/ 643 u32 tx_controlframes; /* dword 53*/ 644 u32 tx_64_byte_packets; /* dword 54*/ 645 u32 tx_65_127_byte_packets; /* dword 55*/ 646 u32 tx_128_256_byte_packets; /* dword 56*/ 647 u32 tx_256_511_byte_packets; /* dword 57*/ 648 u32 tx_512_1023_byte_packets; /* dword 58*/ 649 u32 tx_1024_1518_byte_packets; /* dword 59*/ 650 u32 tx_1519_2047_byte_packets; /* dword 60*/ 651 u32 tx_2048_4095_byte_packets; /* dword 61*/ 652 u32 tx_4096_8191_byte_packets; /* dword 62*/ 653 u32 tx_8192_9216_byte_packets; /* dword 63*/ 654 u32 rx_fifo_overflow; /* dword 64*/ 655 u32 rx_input_fifo_overflow; /* dword 65*/ 656 }; 657 658 struct be_rxf_stats_v0 { 659 struct be_port_rxf_stats_v0 port[2]; 660 u32 rx_drops_no_pbuf; /* dword 132*/ 661 u32 rx_drops_no_txpb; /* dword 133*/ 662 u32 rx_drops_no_erx_descr; /* dword 134*/ 663 u32 rx_drops_no_tpre_descr; /* dword 135*/ 664 u32 management_rx_port_packets; /* dword 136*/ 665 u32 management_rx_port_bytes; /* dword 137*/ 666 u32 management_rx_port_pause_frames; /* dword 138*/ 667 u32 management_rx_port_errors; /* dword 139*/ 668 u32 management_tx_port_packets; /* dword 140*/ 669 u32 management_tx_port_bytes; /* dword 141*/ 670 u32 management_tx_port_pause; /* dword 142*/ 671 u32 management_rx_port_rxfifo_overflow; /* dword 143*/ 672 u32 rx_drops_too_many_frags; /* dword 144*/ 673 u32 rx_drops_invalid_ring; /* dword 145*/ 674 u32 forwarded_packets; /* dword 146*/ 675 u32 rx_drops_mtu; /* dword 147*/ 676 u32 rsvd0[7]; 677 u32 port0_jabber_events; 678 u32 port1_jabber_events; 679 u32 rsvd1[6]; 680 }; 681 682 struct be_erx_stats_v0 { 683 u32 rx_drops_no_fragments[44]; /* dwordS 0 to 43*/ 684 u32 rsvd[4]; 685 }; 686 687 struct be_pmem_stats { 688 u32 eth_red_drops; 689 u32 rsvd[5]; 690 }; 691 692 struct be_hw_stats_v0 { 693 struct be_rxf_stats_v0 rxf; 694 u32 rsvd[48]; 695 struct be_erx_stats_v0 erx; 696 struct be_pmem_stats pmem; 697 }; 698 699 struct be_cmd_req_get_stats_v0 { 700 struct be_cmd_req_hdr hdr; 701 u8 rsvd[sizeof(struct be_hw_stats_v0)]; 702 }; 703 704 struct be_cmd_resp_get_stats_v0 { 705 struct be_cmd_resp_hdr hdr; 706 struct be_hw_stats_v0 hw_stats; 707 }; 708 709 struct lancer_pport_stats { 710 u32 tx_packets_lo; 711 u32 tx_packets_hi; 712 u32 tx_unicast_packets_lo; 713 u32 tx_unicast_packets_hi; 714 u32 tx_multicast_packets_lo; 715 u32 tx_multicast_packets_hi; 716 u32 tx_broadcast_packets_lo; 717 u32 tx_broadcast_packets_hi; 718 u32 tx_bytes_lo; 719 u32 tx_bytes_hi; 720 u32 tx_unicast_bytes_lo; 721 u32 tx_unicast_bytes_hi; 722 u32 tx_multicast_bytes_lo; 723 u32 tx_multicast_bytes_hi; 724 u32 tx_broadcast_bytes_lo; 725 u32 tx_broadcast_bytes_hi; 726 u32 tx_discards_lo; 727 u32 tx_discards_hi; 728 u32 tx_errors_lo; 729 u32 tx_errors_hi; 730 u32 tx_pause_frames_lo; 731 u32 tx_pause_frames_hi; 732 u32 tx_pause_on_frames_lo; 733 u32 tx_pause_on_frames_hi; 734 u32 tx_pause_off_frames_lo; 735 u32 tx_pause_off_frames_hi; 736 u32 tx_internal_mac_errors_lo; 737 u32 tx_internal_mac_errors_hi; 738 u32 tx_control_frames_lo; 739 u32 tx_control_frames_hi; 740 u32 tx_packets_64_bytes_lo; 741 u32 tx_packets_64_bytes_hi; 742 u32 tx_packets_65_to_127_bytes_lo; 743 u32 tx_packets_65_to_127_bytes_hi; 744 u32 tx_packets_128_to_255_bytes_lo; 745 u32 tx_packets_128_to_255_bytes_hi; 746 u32 tx_packets_256_to_511_bytes_lo; 747 u32 tx_packets_256_to_511_bytes_hi; 748 u32 tx_packets_512_to_1023_bytes_lo; 749 u32 tx_packets_512_to_1023_bytes_hi; 750 u32 tx_packets_1024_to_1518_bytes_lo; 751 u32 tx_packets_1024_to_1518_bytes_hi; 752 u32 tx_packets_1519_to_2047_bytes_lo; 753 u32 tx_packets_1519_to_2047_bytes_hi; 754 u32 tx_packets_2048_to_4095_bytes_lo; 755 u32 tx_packets_2048_to_4095_bytes_hi; 756 u32 tx_packets_4096_to_8191_bytes_lo; 757 u32 tx_packets_4096_to_8191_bytes_hi; 758 u32 tx_packets_8192_to_9216_bytes_lo; 759 u32 tx_packets_8192_to_9216_bytes_hi; 760 u32 tx_lso_packets_lo; 761 u32 tx_lso_packets_hi; 762 u32 rx_packets_lo; 763 u32 rx_packets_hi; 764 u32 rx_unicast_packets_lo; 765 u32 rx_unicast_packets_hi; 766 u32 rx_multicast_packets_lo; 767 u32 rx_multicast_packets_hi; 768 u32 rx_broadcast_packets_lo; 769 u32 rx_broadcast_packets_hi; 770 u32 rx_bytes_lo; 771 u32 rx_bytes_hi; 772 u32 rx_unicast_bytes_lo; 773 u32 rx_unicast_bytes_hi; 774 u32 rx_multicast_bytes_lo; 775 u32 rx_multicast_bytes_hi; 776 u32 rx_broadcast_bytes_lo; 777 u32 rx_broadcast_bytes_hi; 778 u32 rx_unknown_protos; 779 u32 rsvd_69; /* Word 69 is reserved */ 780 u32 rx_discards_lo; 781 u32 rx_discards_hi; 782 u32 rx_errors_lo; 783 u32 rx_errors_hi; 784 u32 rx_crc_errors_lo; 785 u32 rx_crc_errors_hi; 786 u32 rx_alignment_errors_lo; 787 u32 rx_alignment_errors_hi; 788 u32 rx_symbol_errors_lo; 789 u32 rx_symbol_errors_hi; 790 u32 rx_pause_frames_lo; 791 u32 rx_pause_frames_hi; 792 u32 rx_pause_on_frames_lo; 793 u32 rx_pause_on_frames_hi; 794 u32 rx_pause_off_frames_lo; 795 u32 rx_pause_off_frames_hi; 796 u32 rx_frames_too_long_lo; 797 u32 rx_frames_too_long_hi; 798 u32 rx_internal_mac_errors_lo; 799 u32 rx_internal_mac_errors_hi; 800 u32 rx_undersize_packets; 801 u32 rx_oversize_packets; 802 u32 rx_fragment_packets; 803 u32 rx_jabbers; 804 u32 rx_control_frames_lo; 805 u32 rx_control_frames_hi; 806 u32 rx_control_frames_unknown_opcode_lo; 807 u32 rx_control_frames_unknown_opcode_hi; 808 u32 rx_in_range_errors; 809 u32 rx_out_of_range_errors; 810 u32 rx_address_mismatch_drops; 811 u32 rx_vlan_mismatch_drops; 812 u32 rx_dropped_too_small; 813 u32 rx_dropped_too_short; 814 u32 rx_dropped_header_too_small; 815 u32 rx_dropped_invalid_tcp_length; 816 u32 rx_dropped_runt; 817 u32 rx_ip_checksum_errors; 818 u32 rx_tcp_checksum_errors; 819 u32 rx_udp_checksum_errors; 820 u32 rx_non_rss_packets; 821 u32 rsvd_111; 822 u32 rx_ipv4_packets_lo; 823 u32 rx_ipv4_packets_hi; 824 u32 rx_ipv6_packets_lo; 825 u32 rx_ipv6_packets_hi; 826 u32 rx_ipv4_bytes_lo; 827 u32 rx_ipv4_bytes_hi; 828 u32 rx_ipv6_bytes_lo; 829 u32 rx_ipv6_bytes_hi; 830 u32 rx_nic_packets_lo; 831 u32 rx_nic_packets_hi; 832 u32 rx_tcp_packets_lo; 833 u32 rx_tcp_packets_hi; 834 u32 rx_iscsi_packets_lo; 835 u32 rx_iscsi_packets_hi; 836 u32 rx_management_packets_lo; 837 u32 rx_management_packets_hi; 838 u32 rx_switched_unicast_packets_lo; 839 u32 rx_switched_unicast_packets_hi; 840 u32 rx_switched_multicast_packets_lo; 841 u32 rx_switched_multicast_packets_hi; 842 u32 rx_switched_broadcast_packets_lo; 843 u32 rx_switched_broadcast_packets_hi; 844 u32 num_forwards_lo; 845 u32 num_forwards_hi; 846 u32 rx_fifo_overflow; 847 u32 rx_input_fifo_overflow; 848 u32 rx_drops_too_many_frags_lo; 849 u32 rx_drops_too_many_frags_hi; 850 u32 rx_drops_invalid_queue; 851 u32 rsvd_141; 852 u32 rx_drops_mtu_lo; 853 u32 rx_drops_mtu_hi; 854 u32 rx_packets_64_bytes_lo; 855 u32 rx_packets_64_bytes_hi; 856 u32 rx_packets_65_to_127_bytes_lo; 857 u32 rx_packets_65_to_127_bytes_hi; 858 u32 rx_packets_128_to_255_bytes_lo; 859 u32 rx_packets_128_to_255_bytes_hi; 860 u32 rx_packets_256_to_511_bytes_lo; 861 u32 rx_packets_256_to_511_bytes_hi; 862 u32 rx_packets_512_to_1023_bytes_lo; 863 u32 rx_packets_512_to_1023_bytes_hi; 864 u32 rx_packets_1024_to_1518_bytes_lo; 865 u32 rx_packets_1024_to_1518_bytes_hi; 866 u32 rx_packets_1519_to_2047_bytes_lo; 867 u32 rx_packets_1519_to_2047_bytes_hi; 868 u32 rx_packets_2048_to_4095_bytes_lo; 869 u32 rx_packets_2048_to_4095_bytes_hi; 870 u32 rx_packets_4096_to_8191_bytes_lo; 871 u32 rx_packets_4096_to_8191_bytes_hi; 872 u32 rx_packets_8192_to_9216_bytes_lo; 873 u32 rx_packets_8192_to_9216_bytes_hi; 874 }; 875 876 struct pport_stats_params { 877 u16 pport_num; 878 u8 rsvd; 879 u8 reset_stats; 880 }; 881 882 struct lancer_cmd_req_pport_stats { 883 struct be_cmd_req_hdr hdr; 884 union { 885 struct pport_stats_params params; 886 u8 rsvd[sizeof(struct lancer_pport_stats)]; 887 } cmd_params; 888 }; 889 890 struct lancer_cmd_resp_pport_stats { 891 struct be_cmd_resp_hdr hdr; 892 struct lancer_pport_stats pport_stats; 893 }; 894 895 static inline struct lancer_pport_stats* 896 pport_stats_from_cmd(struct be_adapter *adapter) 897 { 898 struct lancer_cmd_resp_pport_stats *cmd = adapter->stats_cmd.va; 899 return &cmd->pport_stats; 900 } 901 902 struct be_cmd_req_get_cntl_addnl_attribs { 903 struct be_cmd_req_hdr hdr; 904 u8 rsvd[8]; 905 }; 906 907 struct be_cmd_resp_get_cntl_addnl_attribs { 908 struct be_cmd_resp_hdr hdr; 909 u16 ipl_file_number; 910 u8 ipl_file_version; 911 u8 rsvd0; 912 u8 on_die_temperature; /* in degrees centigrade*/ 913 u8 rsvd1[3]; 914 }; 915 916 struct be_cmd_req_vlan_config { 917 struct be_cmd_req_hdr hdr; 918 u8 interface_id; 919 u8 promiscuous; 920 u8 untagged; 921 u8 num_vlan; 922 u16 normal_vlan[64]; 923 } __packed; 924 925 /******************* RX FILTER ******************************/ 926 #define BE_MAX_MC 64 /* set mcast promisc if > 64 */ 927 struct macaddr { 928 u8 byte[ETH_ALEN]; 929 }; 930 931 struct be_cmd_req_rx_filter { 932 struct be_cmd_req_hdr hdr; 933 u32 global_flags_mask; 934 u32 global_flags; 935 u32 if_flags_mask; 936 u32 if_flags; 937 u32 if_id; 938 u32 mcast_num; 939 struct macaddr mcast_mac[BE_MAX_MC]; 940 }; 941 942 /******************** Link Status Query *******************/ 943 struct be_cmd_req_link_status { 944 struct be_cmd_req_hdr hdr; 945 u32 rsvd; 946 }; 947 948 enum { 949 PHY_LINK_DUPLEX_NONE = 0x0, 950 PHY_LINK_DUPLEX_HALF = 0x1, 951 PHY_LINK_DUPLEX_FULL = 0x2 952 }; 953 954 enum { 955 PHY_LINK_SPEED_ZERO = 0x0, /* => No link */ 956 PHY_LINK_SPEED_10MBPS = 0x1, 957 PHY_LINK_SPEED_100MBPS = 0x2, 958 PHY_LINK_SPEED_1GBPS = 0x3, 959 PHY_LINK_SPEED_10GBPS = 0x4 960 }; 961 962 struct be_cmd_resp_link_status { 963 struct be_cmd_resp_hdr hdr; 964 u8 physical_port; 965 u8 mac_duplex; 966 u8 mac_speed; 967 u8 mac_fault; 968 u8 mgmt_mac_duplex; 969 u8 mgmt_mac_speed; 970 u16 link_speed; 971 u8 logical_link_status; 972 u8 rsvd1[3]; 973 } __packed; 974 975 /******************** Port Identification ***************************/ 976 /* Identifies the type of port attached to NIC */ 977 struct be_cmd_req_port_type { 978 struct be_cmd_req_hdr hdr; 979 u32 page_num; 980 u32 port; 981 }; 982 983 enum { 984 TR_PAGE_A0 = 0xa0, 985 TR_PAGE_A2 = 0xa2 986 }; 987 988 struct be_cmd_resp_port_type { 989 struct be_cmd_resp_hdr hdr; 990 u32 page_num; 991 u32 port; 992 struct data { 993 u8 identifier; 994 u8 identifier_ext; 995 u8 connector; 996 u8 transceiver[8]; 997 u8 rsvd0[3]; 998 u8 length_km; 999 u8 length_hm; 1000 u8 length_om1; 1001 u8 length_om2; 1002 u8 length_cu; 1003 u8 length_cu_m; 1004 u8 vendor_name[16]; 1005 u8 rsvd; 1006 u8 vendor_oui[3]; 1007 u8 vendor_pn[16]; 1008 u8 vendor_rev[4]; 1009 } data; 1010 }; 1011 1012 /******************** Get FW Version *******************/ 1013 struct be_cmd_req_get_fw_version { 1014 struct be_cmd_req_hdr hdr; 1015 u8 rsvd0[FW_VER_LEN]; 1016 u8 rsvd1[FW_VER_LEN]; 1017 } __packed; 1018 1019 struct be_cmd_resp_get_fw_version { 1020 struct be_cmd_resp_hdr hdr; 1021 u8 firmware_version_string[FW_VER_LEN]; 1022 u8 fw_on_flash_version_string[FW_VER_LEN]; 1023 } __packed; 1024 1025 /******************** Set Flow Contrl *******************/ 1026 struct be_cmd_req_set_flow_control { 1027 struct be_cmd_req_hdr hdr; 1028 u16 tx_flow_control; 1029 u16 rx_flow_control; 1030 } __packed; 1031 1032 /******************** Get Flow Contrl *******************/ 1033 struct be_cmd_req_get_flow_control { 1034 struct be_cmd_req_hdr hdr; 1035 u32 rsvd; 1036 }; 1037 1038 struct be_cmd_resp_get_flow_control { 1039 struct be_cmd_resp_hdr hdr; 1040 u16 tx_flow_control; 1041 u16 rx_flow_control; 1042 } __packed; 1043 1044 /******************** Modify EQ Delay *******************/ 1045 struct be_cmd_req_modify_eq_delay { 1046 struct be_cmd_req_hdr hdr; 1047 u32 num_eq; 1048 struct { 1049 u32 eq_id; 1050 u32 phase; 1051 u32 delay_multiplier; 1052 } delay[8]; 1053 } __packed; 1054 1055 struct be_cmd_resp_modify_eq_delay { 1056 struct be_cmd_resp_hdr hdr; 1057 u32 rsvd0; 1058 } __packed; 1059 1060 /******************** Get FW Config *******************/ 1061 #define BE_FUNCTION_CAPS_RSS 0x2 1062 /* The HW can come up in either of the following multi-channel modes 1063 * based on the skew/IPL. 1064 */ 1065 #define RDMA_ENABLED 0x4 1066 #define FLEX10_MODE 0x400 1067 #define VNIC_MODE 0x20000 1068 #define UMC_ENABLED 0x1000000 1069 struct be_cmd_req_query_fw_cfg { 1070 struct be_cmd_req_hdr hdr; 1071 u32 rsvd[31]; 1072 }; 1073 1074 struct be_cmd_resp_query_fw_cfg { 1075 struct be_cmd_resp_hdr hdr; 1076 u32 be_config_number; 1077 u32 asic_revision; 1078 u32 phys_port; 1079 u32 function_mode; 1080 u32 rsvd[26]; 1081 u32 function_caps; 1082 }; 1083 1084 /******************** RSS Config *******************/ 1085 /* RSS types */ 1086 #define RSS_ENABLE_NONE 0x0 1087 #define RSS_ENABLE_IPV4 0x1 1088 #define RSS_ENABLE_TCP_IPV4 0x2 1089 #define RSS_ENABLE_IPV6 0x4 1090 #define RSS_ENABLE_TCP_IPV6 0x8 1091 1092 struct be_cmd_req_rss_config { 1093 struct be_cmd_req_hdr hdr; 1094 u32 if_id; 1095 u16 enable_rss; 1096 u16 cpu_table_size_log2; 1097 u32 hash[10]; 1098 u8 cpu_table[128]; 1099 u8 flush; 1100 u8 rsvd0[3]; 1101 }; 1102 1103 /******************** Port Beacon ***************************/ 1104 1105 #define BEACON_STATE_ENABLED 0x1 1106 #define BEACON_STATE_DISABLED 0x0 1107 1108 struct be_cmd_req_enable_disable_beacon { 1109 struct be_cmd_req_hdr hdr; 1110 u8 port_num; 1111 u8 beacon_state; 1112 u8 beacon_duration; 1113 u8 status_duration; 1114 } __packed; 1115 1116 struct be_cmd_resp_enable_disable_beacon { 1117 struct be_cmd_resp_hdr resp_hdr; 1118 u32 rsvd0; 1119 } __packed; 1120 1121 struct be_cmd_req_get_beacon_state { 1122 struct be_cmd_req_hdr hdr; 1123 u8 port_num; 1124 u8 rsvd0; 1125 u16 rsvd1; 1126 } __packed; 1127 1128 struct be_cmd_resp_get_beacon_state { 1129 struct be_cmd_resp_hdr resp_hdr; 1130 u8 beacon_state; 1131 u8 rsvd0[3]; 1132 } __packed; 1133 1134 /****************** Firmware Flash ******************/ 1135 struct flashrom_params { 1136 u32 op_code; 1137 u32 op_type; 1138 u32 data_buf_size; 1139 u32 offset; 1140 u8 data_buf[4]; 1141 }; 1142 1143 struct be_cmd_write_flashrom { 1144 struct be_cmd_req_hdr hdr; 1145 struct flashrom_params params; 1146 }; 1147 1148 /**************** Lancer Firmware Flash ************/ 1149 struct amap_lancer_write_obj_context { 1150 u8 write_length[24]; 1151 u8 reserved1[7]; 1152 u8 eof; 1153 } __packed; 1154 1155 struct lancer_cmd_req_write_object { 1156 struct be_cmd_req_hdr hdr; 1157 u8 context[sizeof(struct amap_lancer_write_obj_context) / 8]; 1158 u32 write_offset; 1159 u8 object_name[104]; 1160 u32 descriptor_count; 1161 u32 buf_len; 1162 u32 addr_low; 1163 u32 addr_high; 1164 }; 1165 1166 struct lancer_cmd_resp_write_object { 1167 u8 opcode; 1168 u8 subsystem; 1169 u8 rsvd1[2]; 1170 u8 status; 1171 u8 additional_status; 1172 u8 rsvd2[2]; 1173 u32 resp_len; 1174 u32 actual_resp_len; 1175 u32 actual_write_len; 1176 }; 1177 1178 /************************ Lancer Read FW info **************/ 1179 #define LANCER_READ_FILE_CHUNK (32*1024) 1180 #define LANCER_READ_FILE_EOF_MASK 0x80000000 1181 1182 #define LANCER_FW_DUMP_FILE "/dbg/dump.bin" 1183 #define LANCER_VPD_PF_FILE "/vpd/ntr_pf.vpd" 1184 #define LANCER_VPD_VF_FILE "/vpd/ntr_vf.vpd" 1185 1186 struct lancer_cmd_req_read_object { 1187 struct be_cmd_req_hdr hdr; 1188 u32 desired_read_len; 1189 u32 read_offset; 1190 u8 object_name[104]; 1191 u32 descriptor_count; 1192 u32 buf_len; 1193 u32 addr_low; 1194 u32 addr_high; 1195 }; 1196 1197 struct lancer_cmd_resp_read_object { 1198 u8 opcode; 1199 u8 subsystem; 1200 u8 rsvd1[2]; 1201 u8 status; 1202 u8 additional_status; 1203 u8 rsvd2[2]; 1204 u32 resp_len; 1205 u32 actual_resp_len; 1206 u32 actual_read_len; 1207 u32 eof; 1208 }; 1209 1210 /************************ WOL *******************************/ 1211 struct be_cmd_req_acpi_wol_magic_config{ 1212 struct be_cmd_req_hdr hdr; 1213 u32 rsvd0[145]; 1214 u8 magic_mac[6]; 1215 u8 rsvd2[2]; 1216 } __packed; 1217 1218 struct be_cmd_req_acpi_wol_magic_config_v1 { 1219 struct be_cmd_req_hdr hdr; 1220 u8 rsvd0[2]; 1221 u8 query_options; 1222 u8 rsvd1[5]; 1223 u32 rsvd2[288]; 1224 u8 magic_mac[6]; 1225 u8 rsvd3[22]; 1226 } __packed; 1227 1228 struct be_cmd_resp_acpi_wol_magic_config_v1 { 1229 struct be_cmd_resp_hdr hdr; 1230 u8 rsvd0[2]; 1231 u8 wol_settings; 1232 u8 rsvd1[5]; 1233 u32 rsvd2[295]; 1234 } __packed; 1235 1236 #define BE_GET_WOL_CAP 2 1237 1238 #define BE_WOL_CAP 0x1 1239 #define BE_PME_D0_CAP 0x8 1240 #define BE_PME_D1_CAP 0x10 1241 #define BE_PME_D2_CAP 0x20 1242 #define BE_PME_D3HOT_CAP 0x40 1243 #define BE_PME_D3COLD_CAP 0x80 1244 1245 /********************** LoopBack test *********************/ 1246 struct be_cmd_req_loopback_test { 1247 struct be_cmd_req_hdr hdr; 1248 u32 loopback_type; 1249 u32 num_pkts; 1250 u64 pattern; 1251 u32 src_port; 1252 u32 dest_port; 1253 u32 pkt_size; 1254 }; 1255 1256 struct be_cmd_resp_loopback_test { 1257 struct be_cmd_resp_hdr resp_hdr; 1258 u32 status; 1259 u32 num_txfer; 1260 u32 num_rx; 1261 u32 miscomp_off; 1262 u32 ticks_compl; 1263 }; 1264 1265 struct be_cmd_req_set_lmode { 1266 struct be_cmd_req_hdr hdr; 1267 u8 src_port; 1268 u8 dest_port; 1269 u8 loopback_type; 1270 u8 loopback_state; 1271 }; 1272 1273 struct be_cmd_resp_set_lmode { 1274 struct be_cmd_resp_hdr resp_hdr; 1275 u8 rsvd0[4]; 1276 }; 1277 1278 /********************** DDR DMA test *********************/ 1279 struct be_cmd_req_ddrdma_test { 1280 struct be_cmd_req_hdr hdr; 1281 u64 pattern; 1282 u32 byte_count; 1283 u32 rsvd0; 1284 u8 snd_buff[4096]; 1285 u8 rsvd1[4096]; 1286 }; 1287 1288 struct be_cmd_resp_ddrdma_test { 1289 struct be_cmd_resp_hdr hdr; 1290 u64 pattern; 1291 u32 byte_cnt; 1292 u32 snd_err; 1293 u8 rsvd0[4096]; 1294 u8 rcv_buff[4096]; 1295 }; 1296 1297 /*********************** SEEPROM Read ***********************/ 1298 1299 #define BE_READ_SEEPROM_LEN 1024 1300 struct be_cmd_req_seeprom_read { 1301 struct be_cmd_req_hdr hdr; 1302 u8 rsvd0[BE_READ_SEEPROM_LEN]; 1303 }; 1304 1305 struct be_cmd_resp_seeprom_read { 1306 struct be_cmd_req_hdr hdr; 1307 u8 seeprom_data[BE_READ_SEEPROM_LEN]; 1308 }; 1309 1310 enum { 1311 PHY_TYPE_CX4_10GB = 0, 1312 PHY_TYPE_XFP_10GB, 1313 PHY_TYPE_SFP_1GB, 1314 PHY_TYPE_SFP_PLUS_10GB, 1315 PHY_TYPE_KR_10GB, 1316 PHY_TYPE_KX4_10GB, 1317 PHY_TYPE_BASET_10GB, 1318 PHY_TYPE_BASET_1GB, 1319 PHY_TYPE_BASEX_1GB, 1320 PHY_TYPE_SGMII, 1321 PHY_TYPE_DISABLED = 255 1322 }; 1323 1324 #define BE_SUPPORTED_SPEED_NONE 0 1325 #define BE_SUPPORTED_SPEED_10MBPS 1 1326 #define BE_SUPPORTED_SPEED_100MBPS 2 1327 #define BE_SUPPORTED_SPEED_1GBPS 4 1328 #define BE_SUPPORTED_SPEED_10GBPS 8 1329 1330 #define BE_AN_EN 0x2 1331 #define BE_PAUSE_SYM_EN 0x80 1332 1333 /* MAC speed valid values */ 1334 #define SPEED_DEFAULT 0x0 1335 #define SPEED_FORCED_10GB 0x1 1336 #define SPEED_FORCED_1GB 0x2 1337 #define SPEED_AUTONEG_10GB 0x3 1338 #define SPEED_AUTONEG_1GB 0x4 1339 #define SPEED_AUTONEG_100MB 0x5 1340 #define SPEED_AUTONEG_10GB_1GB 0x6 1341 #define SPEED_AUTONEG_10GB_1GB_100MB 0x7 1342 #define SPEED_AUTONEG_1GB_100MB 0x8 1343 #define SPEED_AUTONEG_10MB 0x9 1344 #define SPEED_AUTONEG_1GB_100MB_10MB 0xa 1345 #define SPEED_AUTONEG_100MB_10MB 0xb 1346 #define SPEED_FORCED_100MB 0xc 1347 #define SPEED_FORCED_10MB 0xd 1348 1349 struct be_cmd_req_get_phy_info { 1350 struct be_cmd_req_hdr hdr; 1351 u8 rsvd0[24]; 1352 }; 1353 1354 struct be_phy_info { 1355 u16 phy_type; 1356 u16 interface_type; 1357 u32 misc_params; 1358 u16 ext_phy_details; 1359 u16 rsvd; 1360 u16 auto_speeds_supported; 1361 u16 fixed_speeds_supported; 1362 u32 future_use[2]; 1363 }; 1364 1365 struct be_cmd_resp_get_phy_info { 1366 struct be_cmd_req_hdr hdr; 1367 struct be_phy_info phy_info; 1368 }; 1369 1370 /*********************** Set QOS ***********************/ 1371 1372 #define BE_QOS_BITS_NIC 1 1373 1374 struct be_cmd_req_set_qos { 1375 struct be_cmd_req_hdr hdr; 1376 u32 valid_bits; 1377 u32 max_bps_nic; 1378 u32 rsvd[7]; 1379 }; 1380 1381 struct be_cmd_resp_set_qos { 1382 struct be_cmd_resp_hdr hdr; 1383 u32 rsvd; 1384 }; 1385 1386 /*********************** Controller Attributes ***********************/ 1387 struct be_cmd_req_cntl_attribs { 1388 struct be_cmd_req_hdr hdr; 1389 }; 1390 1391 struct be_cmd_resp_cntl_attribs { 1392 struct be_cmd_resp_hdr hdr; 1393 struct mgmt_controller_attrib attribs; 1394 }; 1395 1396 /*********************** Set driver function ***********************/ 1397 #define CAPABILITY_SW_TIMESTAMPS 2 1398 #define CAPABILITY_BE3_NATIVE_ERX_API 4 1399 1400 struct be_cmd_req_set_func_cap { 1401 struct be_cmd_req_hdr hdr; 1402 u32 valid_cap_flags; 1403 u32 cap_flags; 1404 u8 rsvd[212]; 1405 }; 1406 1407 struct be_cmd_resp_set_func_cap { 1408 struct be_cmd_resp_hdr hdr; 1409 u32 valid_cap_flags; 1410 u32 cap_flags; 1411 u8 rsvd[212]; 1412 }; 1413 1414 /******************** GET/SET_MACLIST **************************/ 1415 #define BE_MAX_MAC 64 1416 struct be_cmd_req_get_mac_list { 1417 struct be_cmd_req_hdr hdr; 1418 u8 mac_type; 1419 u8 perm_override; 1420 u16 iface_id; 1421 u32 mac_id; 1422 u32 rsvd[3]; 1423 } __packed; 1424 1425 struct get_list_macaddr { 1426 u16 mac_addr_size; 1427 union { 1428 u8 macaddr[6]; 1429 struct { 1430 u8 rsvd[2]; 1431 u32 mac_id; 1432 } __packed s_mac_id; 1433 } __packed mac_addr_id; 1434 } __packed; 1435 1436 struct be_cmd_resp_get_mac_list { 1437 struct be_cmd_resp_hdr hdr; 1438 struct get_list_macaddr fd_macaddr; /* Factory default mac */ 1439 struct get_list_macaddr macid_macaddr; /* soft mac */ 1440 u8 true_mac_count; 1441 u8 pseudo_mac_count; 1442 u8 mac_list_size; 1443 u8 rsvd; 1444 /* perm override mac */ 1445 struct get_list_macaddr macaddr_list[BE_MAX_MAC]; 1446 } __packed; 1447 1448 struct be_cmd_req_set_mac_list { 1449 struct be_cmd_req_hdr hdr; 1450 u8 mac_count; 1451 u8 rsvd1; 1452 u16 rsvd2; 1453 struct macaddr mac[BE_MAX_MAC]; 1454 } __packed; 1455 1456 /*********************** HSW Config ***********************/ 1457 struct amap_set_hsw_context { 1458 u8 interface_id[16]; 1459 u8 rsvd0[14]; 1460 u8 pvid_valid; 1461 u8 rsvd1; 1462 u8 rsvd2[16]; 1463 u8 pvid[16]; 1464 u8 rsvd3[32]; 1465 u8 rsvd4[32]; 1466 u8 rsvd5[32]; 1467 } __packed; 1468 1469 struct be_cmd_req_set_hsw_config { 1470 struct be_cmd_req_hdr hdr; 1471 u8 context[sizeof(struct amap_set_hsw_context) / 8]; 1472 } __packed; 1473 1474 struct be_cmd_resp_set_hsw_config { 1475 struct be_cmd_resp_hdr hdr; 1476 u32 rsvd; 1477 }; 1478 1479 struct amap_get_hsw_req_context { 1480 u8 interface_id[16]; 1481 u8 rsvd0[14]; 1482 u8 pvid_valid; 1483 u8 pport; 1484 } __packed; 1485 1486 struct amap_get_hsw_resp_context { 1487 u8 rsvd1[16]; 1488 u8 pvid[16]; 1489 u8 rsvd2[32]; 1490 u8 rsvd3[32]; 1491 u8 rsvd4[32]; 1492 } __packed; 1493 1494 struct be_cmd_req_get_hsw_config { 1495 struct be_cmd_req_hdr hdr; 1496 u8 context[sizeof(struct amap_get_hsw_req_context) / 8]; 1497 } __packed; 1498 1499 struct be_cmd_resp_get_hsw_config { 1500 struct be_cmd_resp_hdr hdr; 1501 u8 context[sizeof(struct amap_get_hsw_resp_context) / 8]; 1502 u32 rsvd; 1503 }; 1504 1505 /*************** HW Stats Get v1 **********************************/ 1506 #define BE_TXP_SW_SZ 48 1507 struct be_port_rxf_stats_v1 { 1508 u32 rsvd0[12]; 1509 u32 rx_crc_errors; 1510 u32 rx_alignment_symbol_errors; 1511 u32 rx_pause_frames; 1512 u32 rx_priority_pause_frames; 1513 u32 rx_control_frames; 1514 u32 rx_in_range_errors; 1515 u32 rx_out_range_errors; 1516 u32 rx_frame_too_long; 1517 u32 rx_address_mismatch_drops; 1518 u32 rx_dropped_too_small; 1519 u32 rx_dropped_too_short; 1520 u32 rx_dropped_header_too_small; 1521 u32 rx_dropped_tcp_length; 1522 u32 rx_dropped_runt; 1523 u32 rsvd1[10]; 1524 u32 rx_ip_checksum_errs; 1525 u32 rx_tcp_checksum_errs; 1526 u32 rx_udp_checksum_errs; 1527 u32 rsvd2[7]; 1528 u32 rx_switched_unicast_packets; 1529 u32 rx_switched_multicast_packets; 1530 u32 rx_switched_broadcast_packets; 1531 u32 rsvd3[3]; 1532 u32 tx_pauseframes; 1533 u32 tx_priority_pauseframes; 1534 u32 tx_controlframes; 1535 u32 rsvd4[10]; 1536 u32 rxpp_fifo_overflow_drop; 1537 u32 rx_input_fifo_overflow_drop; 1538 u32 pmem_fifo_overflow_drop; 1539 u32 jabber_events; 1540 u32 rsvd5[3]; 1541 }; 1542 1543 1544 struct be_rxf_stats_v1 { 1545 struct be_port_rxf_stats_v1 port[4]; 1546 u32 rsvd0[2]; 1547 u32 rx_drops_no_pbuf; 1548 u32 rx_drops_no_txpb; 1549 u32 rx_drops_no_erx_descr; 1550 u32 rx_drops_no_tpre_descr; 1551 u32 rsvd1[6]; 1552 u32 rx_drops_too_many_frags; 1553 u32 rx_drops_invalid_ring; 1554 u32 forwarded_packets; 1555 u32 rx_drops_mtu; 1556 u32 rsvd2[14]; 1557 }; 1558 1559 struct be_erx_stats_v1 { 1560 u32 rx_drops_no_fragments[68]; /* dwordS 0 to 67*/ 1561 u32 rsvd[4]; 1562 }; 1563 1564 struct be_hw_stats_v1 { 1565 struct be_rxf_stats_v1 rxf; 1566 u32 rsvd0[BE_TXP_SW_SZ]; 1567 struct be_erx_stats_v1 erx; 1568 struct be_pmem_stats pmem; 1569 u32 rsvd1[3]; 1570 }; 1571 1572 struct be_cmd_req_get_stats_v1 { 1573 struct be_cmd_req_hdr hdr; 1574 u8 rsvd[sizeof(struct be_hw_stats_v1)]; 1575 }; 1576 1577 struct be_cmd_resp_get_stats_v1 { 1578 struct be_cmd_resp_hdr hdr; 1579 struct be_hw_stats_v1 hw_stats; 1580 }; 1581 1582 static inline void *hw_stats_from_cmd(struct be_adapter *adapter) 1583 { 1584 if (adapter->generation == BE_GEN3) { 1585 struct be_cmd_resp_get_stats_v1 *cmd = adapter->stats_cmd.va; 1586 1587 return &cmd->hw_stats; 1588 } else { 1589 struct be_cmd_resp_get_stats_v0 *cmd = adapter->stats_cmd.va; 1590 1591 return &cmd->hw_stats; 1592 } 1593 } 1594 1595 static inline void *be_erx_stats_from_cmd(struct be_adapter *adapter) 1596 { 1597 if (adapter->generation == BE_GEN3) { 1598 struct be_hw_stats_v1 *hw_stats = hw_stats_from_cmd(adapter); 1599 1600 return &hw_stats->erx; 1601 } else { 1602 struct be_hw_stats_v0 *hw_stats = hw_stats_from_cmd(adapter); 1603 1604 return &hw_stats->erx; 1605 } 1606 } 1607 1608 1609 /************** get fat capabilites *******************/ 1610 #define MAX_MODULES 27 1611 #define MAX_MODES 4 1612 #define MODE_UART 0 1613 #define FW_LOG_LEVEL_DEFAULT 48 1614 #define FW_LOG_LEVEL_FATAL 64 1615 1616 struct ext_fat_mode { 1617 u8 mode; 1618 u8 rsvd0; 1619 u16 port_mask; 1620 u32 dbg_lvl; 1621 u64 fun_mask; 1622 } __packed; 1623 1624 struct ext_fat_modules { 1625 u8 modules_str[32]; 1626 u32 modules_id; 1627 u32 num_modes; 1628 struct ext_fat_mode trace_lvl[MAX_MODES]; 1629 } __packed; 1630 1631 struct be_fat_conf_params { 1632 u32 max_log_entries; 1633 u32 log_entry_size; 1634 u8 log_type; 1635 u8 max_log_funs; 1636 u8 max_log_ports; 1637 u8 rsvd0; 1638 u32 supp_modes; 1639 u32 num_modules; 1640 struct ext_fat_modules module[MAX_MODULES]; 1641 } __packed; 1642 1643 struct be_cmd_req_get_ext_fat_caps { 1644 struct be_cmd_req_hdr hdr; 1645 u32 parameter_type; 1646 }; 1647 1648 struct be_cmd_resp_get_ext_fat_caps { 1649 struct be_cmd_resp_hdr hdr; 1650 struct be_fat_conf_params get_params; 1651 }; 1652 1653 struct be_cmd_req_set_ext_fat_caps { 1654 struct be_cmd_req_hdr hdr; 1655 struct be_fat_conf_params set_params; 1656 }; 1657 1658 extern int be_pci_fnum_get(struct be_adapter *adapter); 1659 extern int be_cmd_POST(struct be_adapter *adapter); 1660 extern int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr, 1661 u8 type, bool permanent, u32 if_handle, u32 pmac_id); 1662 extern int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr, 1663 u32 if_id, u32 *pmac_id, u32 domain); 1664 extern int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, 1665 int pmac_id, u32 domain); 1666 extern int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, 1667 u32 en_flags, u8 *mac, u32 *if_handle, u32 *pmac_id, 1668 u32 domain); 1669 extern int be_cmd_if_destroy(struct be_adapter *adapter, int if_handle, 1670 u32 domain); 1671 extern int be_cmd_eq_create(struct be_adapter *adapter, 1672 struct be_queue_info *eq, int eq_delay); 1673 extern int be_cmd_cq_create(struct be_adapter *adapter, 1674 struct be_queue_info *cq, struct be_queue_info *eq, 1675 bool no_delay, int num_cqe_dma_coalesce); 1676 extern int be_cmd_mccq_create(struct be_adapter *adapter, 1677 struct be_queue_info *mccq, 1678 struct be_queue_info *cq); 1679 extern int be_cmd_txq_create(struct be_adapter *adapter, 1680 struct be_queue_info *txq, 1681 struct be_queue_info *cq); 1682 extern int be_cmd_rxq_create(struct be_adapter *adapter, 1683 struct be_queue_info *rxq, u16 cq_id, 1684 u16 frag_size, u32 if_id, u32 rss, u8 *rss_id); 1685 extern int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q, 1686 int type); 1687 extern int be_cmd_rxq_destroy(struct be_adapter *adapter, 1688 struct be_queue_info *q); 1689 extern int be_cmd_link_status_query(struct be_adapter *adapter, u8 *mac_speed, 1690 u16 *link_speed, u8 *link_status, u32 dom); 1691 extern int be_cmd_reset(struct be_adapter *adapter); 1692 extern int be_cmd_get_stats(struct be_adapter *adapter, 1693 struct be_dma_mem *nonemb_cmd); 1694 extern int lancer_cmd_get_pport_stats(struct be_adapter *adapter, 1695 struct be_dma_mem *nonemb_cmd); 1696 extern int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver, 1697 char *fw_on_flash); 1698 1699 extern int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd); 1700 extern int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, 1701 u16 *vtag_array, u32 num, bool untagged, 1702 bool promiscuous); 1703 extern int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 status); 1704 extern int be_cmd_set_flow_control(struct be_adapter *adapter, 1705 u32 tx_fc, u32 rx_fc); 1706 extern int be_cmd_get_flow_control(struct be_adapter *adapter, 1707 u32 *tx_fc, u32 *rx_fc); 1708 extern int be_cmd_query_fw_cfg(struct be_adapter *adapter, 1709 u32 *port_num, u32 *function_mode, u32 *function_caps); 1710 extern int be_cmd_reset_function(struct be_adapter *adapter); 1711 extern int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable, 1712 u16 table_size); 1713 extern int be_process_mcc(struct be_adapter *adapter); 1714 extern int be_cmd_set_beacon_state(struct be_adapter *adapter, 1715 u8 port_num, u8 beacon, u8 status, u8 state); 1716 extern int be_cmd_get_beacon_state(struct be_adapter *adapter, 1717 u8 port_num, u32 *state); 1718 extern int be_cmd_write_flashrom(struct be_adapter *adapter, 1719 struct be_dma_mem *cmd, u32 flash_oper, 1720 u32 flash_opcode, u32 buf_size); 1721 extern int lancer_cmd_write_object(struct be_adapter *adapter, 1722 struct be_dma_mem *cmd, 1723 u32 data_size, u32 data_offset, 1724 const char *obj_name, 1725 u32 *data_written, u8 *addn_status); 1726 int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd, 1727 u32 data_size, u32 data_offset, const char *obj_name, 1728 u32 *data_read, u32 *eof, u8 *addn_status); 1729 int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc, 1730 int offset); 1731 extern int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac, 1732 struct be_dma_mem *nonemb_cmd); 1733 extern int be_cmd_fw_init(struct be_adapter *adapter); 1734 extern int be_cmd_fw_clean(struct be_adapter *adapter); 1735 extern void be_async_mcc_enable(struct be_adapter *adapter); 1736 extern void be_async_mcc_disable(struct be_adapter *adapter); 1737 extern int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num, 1738 u32 loopback_type, u32 pkt_size, 1739 u32 num_pkts, u64 pattern); 1740 extern int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern, 1741 u32 byte_cnt, struct be_dma_mem *cmd); 1742 extern int be_cmd_get_seeprom_data(struct be_adapter *adapter, 1743 struct be_dma_mem *nonemb_cmd); 1744 extern int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num, 1745 u8 loopback_type, u8 enable); 1746 extern int be_cmd_get_phy_info(struct be_adapter *adapter); 1747 extern int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain); 1748 extern void be_detect_dump_ue(struct be_adapter *adapter); 1749 extern int be_cmd_get_die_temperature(struct be_adapter *adapter); 1750 extern int be_cmd_get_cntl_attributes(struct be_adapter *adapter); 1751 extern int be_cmd_req_native_mode(struct be_adapter *adapter); 1752 extern int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size); 1753 extern void be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf); 1754 extern int be_cmd_get_mac_from_list(struct be_adapter *adapter, u32 domain, 1755 bool *pmac_id_active, u32 *pmac_id, u8 *mac); 1756 extern int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array, 1757 u8 mac_count, u32 domain); 1758 extern int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid, 1759 u32 domain, u16 intf_id); 1760 extern int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid, 1761 u32 domain, u16 intf_id); 1762 extern int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter); 1763 extern int be_cmd_get_ext_fat_capabilites(struct be_adapter *adapter, 1764 struct be_dma_mem *cmd); 1765 extern int be_cmd_set_ext_fat_capabilites(struct be_adapter *adapter, 1766 struct be_dma_mem *cmd, 1767 struct be_fat_conf_params *cfgs); 1768 1769