1 /* 2 * Copyright (C) 2005 - 2011 Emulex 3 * All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License version 2 7 * as published by the Free Software Foundation. The full GNU General 8 * Public License is included in this distribution in the file called COPYING. 9 * 10 * Contact Information: 11 * linux-drivers@emulex.com 12 * 13 * Emulex 14 * 3333 Susan Street 15 * Costa Mesa, CA 92626 16 */ 17 18 #include <linux/module.h> 19 #include "be.h" 20 #include "be_cmds.h" 21 22 static struct be_cmd_priv_map cmd_priv_map[] = { 23 { 24 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, 25 CMD_SUBSYSTEM_ETH, 26 BE_PRIV_LNKMGMT | BE_PRIV_VHADM | 27 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC 28 }, 29 { 30 OPCODE_COMMON_GET_FLOW_CONTROL, 31 CMD_SUBSYSTEM_COMMON, 32 BE_PRIV_LNKQUERY | BE_PRIV_VHADM | 33 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC 34 }, 35 { 36 OPCODE_COMMON_SET_FLOW_CONTROL, 37 CMD_SUBSYSTEM_COMMON, 38 BE_PRIV_LNKMGMT | BE_PRIV_VHADM | 39 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC 40 }, 41 { 42 OPCODE_ETH_GET_PPORT_STATS, 43 CMD_SUBSYSTEM_ETH, 44 BE_PRIV_LNKMGMT | BE_PRIV_VHADM | 45 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC 46 }, 47 { 48 OPCODE_COMMON_GET_PHY_DETAILS, 49 CMD_SUBSYSTEM_COMMON, 50 BE_PRIV_LNKMGMT | BE_PRIV_VHADM | 51 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC 52 } 53 }; 54 55 static bool be_cmd_allowed(struct be_adapter *adapter, u8 opcode, 56 u8 subsystem) 57 { 58 int i; 59 int num_entries = sizeof(cmd_priv_map)/sizeof(struct be_cmd_priv_map); 60 u32 cmd_privileges = adapter->cmd_privileges; 61 62 for (i = 0; i < num_entries; i++) 63 if (opcode == cmd_priv_map[i].opcode && 64 subsystem == cmd_priv_map[i].subsystem) 65 if (!(cmd_privileges & cmd_priv_map[i].priv_mask)) 66 return false; 67 68 return true; 69 } 70 71 static inline void *embedded_payload(struct be_mcc_wrb *wrb) 72 { 73 return wrb->payload.embedded_payload; 74 } 75 76 static void be_mcc_notify(struct be_adapter *adapter) 77 { 78 struct be_queue_info *mccq = &adapter->mcc_obj.q; 79 u32 val = 0; 80 81 if (be_error(adapter)) 82 return; 83 84 val |= mccq->id & DB_MCCQ_RING_ID_MASK; 85 val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT; 86 87 wmb(); 88 iowrite32(val, adapter->db + DB_MCCQ_OFFSET); 89 } 90 91 /* To check if valid bit is set, check the entire word as we don't know 92 * the endianness of the data (old entry is host endian while a new entry is 93 * little endian) */ 94 static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl) 95 { 96 if (compl->flags != 0) { 97 compl->flags = le32_to_cpu(compl->flags); 98 BUG_ON((compl->flags & CQE_FLAGS_VALID_MASK) == 0); 99 return true; 100 } else { 101 return false; 102 } 103 } 104 105 /* Need to reset the entire word that houses the valid bit */ 106 static inline void be_mcc_compl_use(struct be_mcc_compl *compl) 107 { 108 compl->flags = 0; 109 } 110 111 static struct be_cmd_resp_hdr *be_decode_resp_hdr(u32 tag0, u32 tag1) 112 { 113 unsigned long addr; 114 115 addr = tag1; 116 addr = ((addr << 16) << 16) | tag0; 117 return (void *)addr; 118 } 119 120 static int be_mcc_compl_process(struct be_adapter *adapter, 121 struct be_mcc_compl *compl) 122 { 123 u16 compl_status, extd_status; 124 struct be_cmd_resp_hdr *resp_hdr; 125 u8 opcode = 0, subsystem = 0; 126 127 /* Just swap the status to host endian; mcc tag is opaquely copied 128 * from mcc_wrb */ 129 be_dws_le_to_cpu(compl, 4); 130 131 compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) & 132 CQE_STATUS_COMPL_MASK; 133 134 resp_hdr = be_decode_resp_hdr(compl->tag0, compl->tag1); 135 136 if (resp_hdr) { 137 opcode = resp_hdr->opcode; 138 subsystem = resp_hdr->subsystem; 139 } 140 141 if (((opcode == OPCODE_COMMON_WRITE_FLASHROM) || 142 (opcode == OPCODE_COMMON_WRITE_OBJECT)) && 143 (subsystem == CMD_SUBSYSTEM_COMMON)) { 144 adapter->flash_status = compl_status; 145 complete(&adapter->flash_compl); 146 } 147 148 if (compl_status == MCC_STATUS_SUCCESS) { 149 if (((opcode == OPCODE_ETH_GET_STATISTICS) || 150 (opcode == OPCODE_ETH_GET_PPORT_STATS)) && 151 (subsystem == CMD_SUBSYSTEM_ETH)) { 152 be_parse_stats(adapter); 153 adapter->stats_cmd_sent = false; 154 } 155 if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES && 156 subsystem == CMD_SUBSYSTEM_COMMON) { 157 struct be_cmd_resp_get_cntl_addnl_attribs *resp = 158 (void *)resp_hdr; 159 adapter->drv_stats.be_on_die_temperature = 160 resp->on_die_temperature; 161 } 162 } else { 163 if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES) 164 adapter->be_get_temp_freq = 0; 165 166 if (compl_status == MCC_STATUS_NOT_SUPPORTED || 167 compl_status == MCC_STATUS_ILLEGAL_REQUEST) 168 goto done; 169 170 if (compl_status == MCC_STATUS_UNAUTHORIZED_REQUEST) { 171 dev_warn(&adapter->pdev->dev, 172 "VF is not privileged to issue opcode %d-%d\n", 173 opcode, subsystem); 174 } else { 175 extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) & 176 CQE_STATUS_EXTD_MASK; 177 dev_err(&adapter->pdev->dev, 178 "opcode %d-%d failed:status %d-%d\n", 179 opcode, subsystem, compl_status, extd_status); 180 } 181 } 182 done: 183 return compl_status; 184 } 185 186 /* Link state evt is a string of bytes; no need for endian swapping */ 187 static void be_async_link_state_process(struct be_adapter *adapter, 188 struct be_async_event_link_state *evt) 189 { 190 /* When link status changes, link speed must be re-queried from FW */ 191 adapter->phy.link_speed = -1; 192 193 /* Ignore physical link event */ 194 if (lancer_chip(adapter) && 195 !(evt->port_link_status & LOGICAL_LINK_STATUS_MASK)) 196 return; 197 198 /* For the initial link status do not rely on the ASYNC event as 199 * it may not be received in some cases. 200 */ 201 if (adapter->flags & BE_FLAGS_LINK_STATUS_INIT) 202 be_link_status_update(adapter, evt->port_link_status); 203 } 204 205 /* Grp5 CoS Priority evt */ 206 static void be_async_grp5_cos_priority_process(struct be_adapter *adapter, 207 struct be_async_event_grp5_cos_priority *evt) 208 { 209 if (evt->valid) { 210 adapter->vlan_prio_bmap = evt->available_priority_bmap; 211 adapter->recommended_prio &= ~VLAN_PRIO_MASK; 212 adapter->recommended_prio = 213 evt->reco_default_priority << VLAN_PRIO_SHIFT; 214 } 215 } 216 217 /* Grp5 QOS Speed evt: qos_link_speed is in units of 10 Mbps */ 218 static void be_async_grp5_qos_speed_process(struct be_adapter *adapter, 219 struct be_async_event_grp5_qos_link_speed *evt) 220 { 221 if (adapter->phy.link_speed >= 0 && 222 evt->physical_port == adapter->port_num) 223 adapter->phy.link_speed = le16_to_cpu(evt->qos_link_speed) * 10; 224 } 225 226 /*Grp5 PVID evt*/ 227 static void be_async_grp5_pvid_state_process(struct be_adapter *adapter, 228 struct be_async_event_grp5_pvid_state *evt) 229 { 230 if (evt->enabled) 231 adapter->pvid = le16_to_cpu(evt->tag) & VLAN_VID_MASK; 232 else 233 adapter->pvid = 0; 234 } 235 236 static void be_async_grp5_evt_process(struct be_adapter *adapter, 237 u32 trailer, struct be_mcc_compl *evt) 238 { 239 u8 event_type = 0; 240 241 event_type = (trailer >> ASYNC_TRAILER_EVENT_TYPE_SHIFT) & 242 ASYNC_TRAILER_EVENT_TYPE_MASK; 243 244 switch (event_type) { 245 case ASYNC_EVENT_COS_PRIORITY: 246 be_async_grp5_cos_priority_process(adapter, 247 (struct be_async_event_grp5_cos_priority *)evt); 248 break; 249 case ASYNC_EVENT_QOS_SPEED: 250 be_async_grp5_qos_speed_process(adapter, 251 (struct be_async_event_grp5_qos_link_speed *)evt); 252 break; 253 case ASYNC_EVENT_PVID_STATE: 254 be_async_grp5_pvid_state_process(adapter, 255 (struct be_async_event_grp5_pvid_state *)evt); 256 break; 257 default: 258 dev_warn(&adapter->pdev->dev, "Unknown grp5 event!\n"); 259 break; 260 } 261 } 262 263 static inline bool is_link_state_evt(u32 trailer) 264 { 265 return ((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) & 266 ASYNC_TRAILER_EVENT_CODE_MASK) == 267 ASYNC_EVENT_CODE_LINK_STATE; 268 } 269 270 static inline bool is_grp5_evt(u32 trailer) 271 { 272 return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) & 273 ASYNC_TRAILER_EVENT_CODE_MASK) == 274 ASYNC_EVENT_CODE_GRP_5); 275 } 276 277 static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter) 278 { 279 struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq; 280 struct be_mcc_compl *compl = queue_tail_node(mcc_cq); 281 282 if (be_mcc_compl_is_new(compl)) { 283 queue_tail_inc(mcc_cq); 284 return compl; 285 } 286 return NULL; 287 } 288 289 void be_async_mcc_enable(struct be_adapter *adapter) 290 { 291 spin_lock_bh(&adapter->mcc_cq_lock); 292 293 be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0); 294 adapter->mcc_obj.rearm_cq = true; 295 296 spin_unlock_bh(&adapter->mcc_cq_lock); 297 } 298 299 void be_async_mcc_disable(struct be_adapter *adapter) 300 { 301 spin_lock_bh(&adapter->mcc_cq_lock); 302 303 adapter->mcc_obj.rearm_cq = false; 304 be_cq_notify(adapter, adapter->mcc_obj.cq.id, false, 0); 305 306 spin_unlock_bh(&adapter->mcc_cq_lock); 307 } 308 309 int be_process_mcc(struct be_adapter *adapter) 310 { 311 struct be_mcc_compl *compl; 312 int num = 0, status = 0; 313 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj; 314 315 spin_lock(&adapter->mcc_cq_lock); 316 while ((compl = be_mcc_compl_get(adapter))) { 317 if (compl->flags & CQE_FLAGS_ASYNC_MASK) { 318 /* Interpret flags as an async trailer */ 319 if (is_link_state_evt(compl->flags)) 320 be_async_link_state_process(adapter, 321 (struct be_async_event_link_state *) compl); 322 else if (is_grp5_evt(compl->flags)) 323 be_async_grp5_evt_process(adapter, 324 compl->flags, compl); 325 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) { 326 status = be_mcc_compl_process(adapter, compl); 327 atomic_dec(&mcc_obj->q.used); 328 } 329 be_mcc_compl_use(compl); 330 num++; 331 } 332 333 if (num) 334 be_cq_notify(adapter, mcc_obj->cq.id, mcc_obj->rearm_cq, num); 335 336 spin_unlock(&adapter->mcc_cq_lock); 337 return status; 338 } 339 340 /* Wait till no more pending mcc requests are present */ 341 static int be_mcc_wait_compl(struct be_adapter *adapter) 342 { 343 #define mcc_timeout 120000 /* 12s timeout */ 344 int i, status = 0; 345 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj; 346 347 for (i = 0; i < mcc_timeout; i++) { 348 if (be_error(adapter)) 349 return -EIO; 350 351 local_bh_disable(); 352 status = be_process_mcc(adapter); 353 local_bh_enable(); 354 355 if (atomic_read(&mcc_obj->q.used) == 0) 356 break; 357 udelay(100); 358 } 359 if (i == mcc_timeout) { 360 dev_err(&adapter->pdev->dev, "FW not responding\n"); 361 adapter->fw_timeout = true; 362 return -EIO; 363 } 364 return status; 365 } 366 367 /* Notify MCC requests and wait for completion */ 368 static int be_mcc_notify_wait(struct be_adapter *adapter) 369 { 370 int status; 371 struct be_mcc_wrb *wrb; 372 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj; 373 u16 index = mcc_obj->q.head; 374 struct be_cmd_resp_hdr *resp; 375 376 index_dec(&index, mcc_obj->q.len); 377 wrb = queue_index_node(&mcc_obj->q, index); 378 379 resp = be_decode_resp_hdr(wrb->tag0, wrb->tag1); 380 381 be_mcc_notify(adapter); 382 383 status = be_mcc_wait_compl(adapter); 384 if (status == -EIO) 385 goto out; 386 387 status = resp->status; 388 out: 389 return status; 390 } 391 392 static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db) 393 { 394 int msecs = 0; 395 u32 ready; 396 397 do { 398 if (be_error(adapter)) 399 return -EIO; 400 401 ready = ioread32(db); 402 if (ready == 0xffffffff) 403 return -1; 404 405 ready &= MPU_MAILBOX_DB_RDY_MASK; 406 if (ready) 407 break; 408 409 if (msecs > 4000) { 410 dev_err(&adapter->pdev->dev, "FW not responding\n"); 411 adapter->fw_timeout = true; 412 be_detect_error(adapter); 413 return -1; 414 } 415 416 msleep(1); 417 msecs++; 418 } while (true); 419 420 return 0; 421 } 422 423 /* 424 * Insert the mailbox address into the doorbell in two steps 425 * Polls on the mbox doorbell till a command completion (or a timeout) occurs 426 */ 427 static int be_mbox_notify_wait(struct be_adapter *adapter) 428 { 429 int status; 430 u32 val = 0; 431 void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET; 432 struct be_dma_mem *mbox_mem = &adapter->mbox_mem; 433 struct be_mcc_mailbox *mbox = mbox_mem->va; 434 struct be_mcc_compl *compl = &mbox->compl; 435 436 /* wait for ready to be set */ 437 status = be_mbox_db_ready_wait(adapter, db); 438 if (status != 0) 439 return status; 440 441 val |= MPU_MAILBOX_DB_HI_MASK; 442 /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */ 443 val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2; 444 iowrite32(val, db); 445 446 /* wait for ready to be set */ 447 status = be_mbox_db_ready_wait(adapter, db); 448 if (status != 0) 449 return status; 450 451 val = 0; 452 /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */ 453 val |= (u32)(mbox_mem->dma >> 4) << 2; 454 iowrite32(val, db); 455 456 status = be_mbox_db_ready_wait(adapter, db); 457 if (status != 0) 458 return status; 459 460 /* A cq entry has been made now */ 461 if (be_mcc_compl_is_new(compl)) { 462 status = be_mcc_compl_process(adapter, &mbox->compl); 463 be_mcc_compl_use(compl); 464 if (status) 465 return status; 466 } else { 467 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n"); 468 return -1; 469 } 470 return 0; 471 } 472 473 static int be_POST_stage_get(struct be_adapter *adapter, u16 *stage) 474 { 475 u32 sem; 476 u32 reg = skyhawk_chip(adapter) ? SLIPORT_SEMAPHORE_OFFSET_SH : 477 SLIPORT_SEMAPHORE_OFFSET_BE; 478 479 pci_read_config_dword(adapter->pdev, reg, &sem); 480 *stage = sem & POST_STAGE_MASK; 481 482 if ((sem >> POST_ERR_SHIFT) & POST_ERR_MASK) 483 return -1; 484 else 485 return 0; 486 } 487 488 int lancer_wait_ready(struct be_adapter *adapter) 489 { 490 #define SLIPORT_READY_TIMEOUT 30 491 u32 sliport_status; 492 int status = 0, i; 493 494 for (i = 0; i < SLIPORT_READY_TIMEOUT; i++) { 495 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET); 496 if (sliport_status & SLIPORT_STATUS_RDY_MASK) 497 break; 498 499 msleep(1000); 500 } 501 502 if (i == SLIPORT_READY_TIMEOUT) 503 status = -1; 504 505 return status; 506 } 507 508 static bool lancer_provisioning_error(struct be_adapter *adapter) 509 { 510 u32 sliport_status = 0, sliport_err1 = 0, sliport_err2 = 0; 511 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET); 512 if (sliport_status & SLIPORT_STATUS_ERR_MASK) { 513 sliport_err1 = ioread32(adapter->db + 514 SLIPORT_ERROR1_OFFSET); 515 sliport_err2 = ioread32(adapter->db + 516 SLIPORT_ERROR2_OFFSET); 517 518 if (sliport_err1 == SLIPORT_ERROR_NO_RESOURCE1 && 519 sliport_err2 == SLIPORT_ERROR_NO_RESOURCE2) 520 return true; 521 } 522 return false; 523 } 524 525 int lancer_test_and_set_rdy_state(struct be_adapter *adapter) 526 { 527 int status; 528 u32 sliport_status, err, reset_needed; 529 bool resource_error; 530 531 resource_error = lancer_provisioning_error(adapter); 532 if (resource_error) 533 return -1; 534 535 status = lancer_wait_ready(adapter); 536 if (!status) { 537 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET); 538 err = sliport_status & SLIPORT_STATUS_ERR_MASK; 539 reset_needed = sliport_status & SLIPORT_STATUS_RN_MASK; 540 if (err && reset_needed) { 541 iowrite32(SLI_PORT_CONTROL_IP_MASK, 542 adapter->db + SLIPORT_CONTROL_OFFSET); 543 544 /* check adapter has corrected the error */ 545 status = lancer_wait_ready(adapter); 546 sliport_status = ioread32(adapter->db + 547 SLIPORT_STATUS_OFFSET); 548 sliport_status &= (SLIPORT_STATUS_ERR_MASK | 549 SLIPORT_STATUS_RN_MASK); 550 if (status || sliport_status) 551 status = -1; 552 } else if (err || reset_needed) { 553 status = -1; 554 } 555 } 556 /* Stop error recovery if error is not recoverable. 557 * No resource error is temporary errors and will go away 558 * when PF provisions resources. 559 */ 560 resource_error = lancer_provisioning_error(adapter); 561 if (status == -1 && !resource_error) 562 adapter->eeh_error = true; 563 564 return status; 565 } 566 567 int be_fw_wait_ready(struct be_adapter *adapter) 568 { 569 u16 stage; 570 int status, timeout = 0; 571 struct device *dev = &adapter->pdev->dev; 572 573 if (lancer_chip(adapter)) { 574 status = lancer_wait_ready(adapter); 575 return status; 576 } 577 578 do { 579 status = be_POST_stage_get(adapter, &stage); 580 if (status) { 581 dev_err(dev, "POST error; stage=0x%x\n", stage); 582 return -1; 583 } else if (stage != POST_STAGE_ARMFW_RDY) { 584 if (msleep_interruptible(2000)) { 585 dev_err(dev, "Waiting for POST aborted\n"); 586 return -EINTR; 587 } 588 timeout += 2; 589 } else { 590 return 0; 591 } 592 } while (timeout < 60); 593 594 dev_err(dev, "POST timeout; stage=0x%x\n", stage); 595 return -1; 596 } 597 598 599 static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb) 600 { 601 return &wrb->payload.sgl[0]; 602 } 603 604 605 /* Don't touch the hdr after it's prepared */ 606 /* mem will be NULL for embedded commands */ 607 static void be_wrb_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr, 608 u8 subsystem, u8 opcode, int cmd_len, 609 struct be_mcc_wrb *wrb, struct be_dma_mem *mem) 610 { 611 struct be_sge *sge; 612 unsigned long addr = (unsigned long)req_hdr; 613 u64 req_addr = addr; 614 615 req_hdr->opcode = opcode; 616 req_hdr->subsystem = subsystem; 617 req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr)); 618 req_hdr->version = 0; 619 620 wrb->tag0 = req_addr & 0xFFFFFFFF; 621 wrb->tag1 = upper_32_bits(req_addr); 622 623 wrb->payload_length = cmd_len; 624 if (mem) { 625 wrb->embedded |= (1 & MCC_WRB_SGE_CNT_MASK) << 626 MCC_WRB_SGE_CNT_SHIFT; 627 sge = nonembedded_sgl(wrb); 628 sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma)); 629 sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF); 630 sge->len = cpu_to_le32(mem->size); 631 } else 632 wrb->embedded |= MCC_WRB_EMBEDDED_MASK; 633 be_dws_cpu_to_le(wrb, 8); 634 } 635 636 static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages, 637 struct be_dma_mem *mem) 638 { 639 int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages); 640 u64 dma = (u64)mem->dma; 641 642 for (i = 0; i < buf_pages; i++) { 643 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF); 644 pages[i].hi = cpu_to_le32(upper_32_bits(dma)); 645 dma += PAGE_SIZE_4K; 646 } 647 } 648 649 /* Converts interrupt delay in microseconds to multiplier value */ 650 static u32 eq_delay_to_mult(u32 usec_delay) 651 { 652 #define MAX_INTR_RATE 651042 653 const u32 round = 10; 654 u32 multiplier; 655 656 if (usec_delay == 0) 657 multiplier = 0; 658 else { 659 u32 interrupt_rate = 1000000 / usec_delay; 660 /* Max delay, corresponding to the lowest interrupt rate */ 661 if (interrupt_rate == 0) 662 multiplier = 1023; 663 else { 664 multiplier = (MAX_INTR_RATE - interrupt_rate) * round; 665 multiplier /= interrupt_rate; 666 /* Round the multiplier to the closest value.*/ 667 multiplier = (multiplier + round/2) / round; 668 multiplier = min(multiplier, (u32)1023); 669 } 670 } 671 return multiplier; 672 } 673 674 static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter) 675 { 676 struct be_dma_mem *mbox_mem = &adapter->mbox_mem; 677 struct be_mcc_wrb *wrb 678 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb; 679 memset(wrb, 0, sizeof(*wrb)); 680 return wrb; 681 } 682 683 static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter) 684 { 685 struct be_queue_info *mccq = &adapter->mcc_obj.q; 686 struct be_mcc_wrb *wrb; 687 688 if (!mccq->created) 689 return NULL; 690 691 if (atomic_read(&mccq->used) >= mccq->len) { 692 dev_err(&adapter->pdev->dev, "Out of MCCQ wrbs\n"); 693 return NULL; 694 } 695 696 wrb = queue_head_node(mccq); 697 queue_head_inc(mccq); 698 atomic_inc(&mccq->used); 699 memset(wrb, 0, sizeof(*wrb)); 700 return wrb; 701 } 702 703 /* Tell fw we're about to start firing cmds by writing a 704 * special pattern across the wrb hdr; uses mbox 705 */ 706 int be_cmd_fw_init(struct be_adapter *adapter) 707 { 708 u8 *wrb; 709 int status; 710 711 if (lancer_chip(adapter)) 712 return 0; 713 714 if (mutex_lock_interruptible(&adapter->mbox_lock)) 715 return -1; 716 717 wrb = (u8 *)wrb_from_mbox(adapter); 718 *wrb++ = 0xFF; 719 *wrb++ = 0x12; 720 *wrb++ = 0x34; 721 *wrb++ = 0xFF; 722 *wrb++ = 0xFF; 723 *wrb++ = 0x56; 724 *wrb++ = 0x78; 725 *wrb = 0xFF; 726 727 status = be_mbox_notify_wait(adapter); 728 729 mutex_unlock(&adapter->mbox_lock); 730 return status; 731 } 732 733 /* Tell fw we're done with firing cmds by writing a 734 * special pattern across the wrb hdr; uses mbox 735 */ 736 int be_cmd_fw_clean(struct be_adapter *adapter) 737 { 738 u8 *wrb; 739 int status; 740 741 if (lancer_chip(adapter)) 742 return 0; 743 744 if (mutex_lock_interruptible(&adapter->mbox_lock)) 745 return -1; 746 747 wrb = (u8 *)wrb_from_mbox(adapter); 748 *wrb++ = 0xFF; 749 *wrb++ = 0xAA; 750 *wrb++ = 0xBB; 751 *wrb++ = 0xFF; 752 *wrb++ = 0xFF; 753 *wrb++ = 0xCC; 754 *wrb++ = 0xDD; 755 *wrb = 0xFF; 756 757 status = be_mbox_notify_wait(adapter); 758 759 mutex_unlock(&adapter->mbox_lock); 760 return status; 761 } 762 763 int be_cmd_eq_create(struct be_adapter *adapter, 764 struct be_queue_info *eq, int eq_delay) 765 { 766 struct be_mcc_wrb *wrb; 767 struct be_cmd_req_eq_create *req; 768 struct be_dma_mem *q_mem = &eq->dma_mem; 769 int status; 770 771 if (mutex_lock_interruptible(&adapter->mbox_lock)) 772 return -1; 773 774 wrb = wrb_from_mbox(adapter); 775 req = embedded_payload(wrb); 776 777 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 778 OPCODE_COMMON_EQ_CREATE, sizeof(*req), wrb, NULL); 779 780 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size)); 781 782 AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1); 783 /* 4byte eqe*/ 784 AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0); 785 AMAP_SET_BITS(struct amap_eq_context, count, req->context, 786 __ilog2_u32(eq->len/256)); 787 AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context, 788 eq_delay_to_mult(eq_delay)); 789 be_dws_cpu_to_le(req->context, sizeof(req->context)); 790 791 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); 792 793 status = be_mbox_notify_wait(adapter); 794 if (!status) { 795 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb); 796 eq->id = le16_to_cpu(resp->eq_id); 797 eq->created = true; 798 } 799 800 mutex_unlock(&adapter->mbox_lock); 801 return status; 802 } 803 804 /* Use MCC */ 805 int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr, 806 bool permanent, u32 if_handle, u32 pmac_id) 807 { 808 struct be_mcc_wrb *wrb; 809 struct be_cmd_req_mac_query *req; 810 int status; 811 812 spin_lock_bh(&adapter->mcc_lock); 813 814 wrb = wrb_from_mccq(adapter); 815 if (!wrb) { 816 status = -EBUSY; 817 goto err; 818 } 819 req = embedded_payload(wrb); 820 821 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 822 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req), wrb, NULL); 823 req->type = MAC_ADDRESS_TYPE_NETWORK; 824 if (permanent) { 825 req->permanent = 1; 826 } else { 827 req->if_id = cpu_to_le16((u16) if_handle); 828 req->pmac_id = cpu_to_le32(pmac_id); 829 req->permanent = 0; 830 } 831 832 status = be_mcc_notify_wait(adapter); 833 if (!status) { 834 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb); 835 memcpy(mac_addr, resp->mac.addr, ETH_ALEN); 836 } 837 838 err: 839 spin_unlock_bh(&adapter->mcc_lock); 840 return status; 841 } 842 843 /* Uses synchronous MCCQ */ 844 int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr, 845 u32 if_id, u32 *pmac_id, u32 domain) 846 { 847 struct be_mcc_wrb *wrb; 848 struct be_cmd_req_pmac_add *req; 849 int status; 850 851 spin_lock_bh(&adapter->mcc_lock); 852 853 wrb = wrb_from_mccq(adapter); 854 if (!wrb) { 855 status = -EBUSY; 856 goto err; 857 } 858 req = embedded_payload(wrb); 859 860 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 861 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req), wrb, NULL); 862 863 req->hdr.domain = domain; 864 req->if_id = cpu_to_le32(if_id); 865 memcpy(req->mac_address, mac_addr, ETH_ALEN); 866 867 status = be_mcc_notify_wait(adapter); 868 if (!status) { 869 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb); 870 *pmac_id = le32_to_cpu(resp->pmac_id); 871 } 872 873 err: 874 spin_unlock_bh(&adapter->mcc_lock); 875 876 if (status == MCC_STATUS_UNAUTHORIZED_REQUEST) 877 status = -EPERM; 878 879 return status; 880 } 881 882 /* Uses synchronous MCCQ */ 883 int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, int pmac_id, u32 dom) 884 { 885 struct be_mcc_wrb *wrb; 886 struct be_cmd_req_pmac_del *req; 887 int status; 888 889 if (pmac_id == -1) 890 return 0; 891 892 spin_lock_bh(&adapter->mcc_lock); 893 894 wrb = wrb_from_mccq(adapter); 895 if (!wrb) { 896 status = -EBUSY; 897 goto err; 898 } 899 req = embedded_payload(wrb); 900 901 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 902 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req), wrb, NULL); 903 904 req->hdr.domain = dom; 905 req->if_id = cpu_to_le32(if_id); 906 req->pmac_id = cpu_to_le32(pmac_id); 907 908 status = be_mcc_notify_wait(adapter); 909 910 err: 911 spin_unlock_bh(&adapter->mcc_lock); 912 return status; 913 } 914 915 /* Uses Mbox */ 916 int be_cmd_cq_create(struct be_adapter *adapter, struct be_queue_info *cq, 917 struct be_queue_info *eq, bool no_delay, int coalesce_wm) 918 { 919 struct be_mcc_wrb *wrb; 920 struct be_cmd_req_cq_create *req; 921 struct be_dma_mem *q_mem = &cq->dma_mem; 922 void *ctxt; 923 int status; 924 925 if (mutex_lock_interruptible(&adapter->mbox_lock)) 926 return -1; 927 928 wrb = wrb_from_mbox(adapter); 929 req = embedded_payload(wrb); 930 ctxt = &req->context; 931 932 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 933 OPCODE_COMMON_CQ_CREATE, sizeof(*req), wrb, NULL); 934 935 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size)); 936 if (lancer_chip(adapter)) { 937 req->hdr.version = 2; 938 req->page_size = 1; /* 1 for 4K */ 939 AMAP_SET_BITS(struct amap_cq_context_lancer, nodelay, ctxt, 940 no_delay); 941 AMAP_SET_BITS(struct amap_cq_context_lancer, count, ctxt, 942 __ilog2_u32(cq->len/256)); 943 AMAP_SET_BITS(struct amap_cq_context_lancer, valid, ctxt, 1); 944 AMAP_SET_BITS(struct amap_cq_context_lancer, eventable, 945 ctxt, 1); 946 AMAP_SET_BITS(struct amap_cq_context_lancer, eqid, 947 ctxt, eq->id); 948 } else { 949 AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt, 950 coalesce_wm); 951 AMAP_SET_BITS(struct amap_cq_context_be, nodelay, 952 ctxt, no_delay); 953 AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt, 954 __ilog2_u32(cq->len/256)); 955 AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1); 956 AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1); 957 AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id); 958 } 959 960 be_dws_cpu_to_le(ctxt, sizeof(req->context)); 961 962 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); 963 964 status = be_mbox_notify_wait(adapter); 965 if (!status) { 966 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb); 967 cq->id = le16_to_cpu(resp->cq_id); 968 cq->created = true; 969 } 970 971 mutex_unlock(&adapter->mbox_lock); 972 973 return status; 974 } 975 976 static u32 be_encoded_q_len(int q_len) 977 { 978 u32 len_encoded = fls(q_len); /* log2(len) + 1 */ 979 if (len_encoded == 16) 980 len_encoded = 0; 981 return len_encoded; 982 } 983 984 int be_cmd_mccq_ext_create(struct be_adapter *adapter, 985 struct be_queue_info *mccq, 986 struct be_queue_info *cq) 987 { 988 struct be_mcc_wrb *wrb; 989 struct be_cmd_req_mcc_ext_create *req; 990 struct be_dma_mem *q_mem = &mccq->dma_mem; 991 void *ctxt; 992 int status; 993 994 if (mutex_lock_interruptible(&adapter->mbox_lock)) 995 return -1; 996 997 wrb = wrb_from_mbox(adapter); 998 req = embedded_payload(wrb); 999 ctxt = &req->context; 1000 1001 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1002 OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req), wrb, NULL); 1003 1004 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size)); 1005 if (lancer_chip(adapter)) { 1006 req->hdr.version = 1; 1007 req->cq_id = cpu_to_le16(cq->id); 1008 1009 AMAP_SET_BITS(struct amap_mcc_context_lancer, ring_size, ctxt, 1010 be_encoded_q_len(mccq->len)); 1011 AMAP_SET_BITS(struct amap_mcc_context_lancer, valid, ctxt, 1); 1012 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_id, 1013 ctxt, cq->id); 1014 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_valid, 1015 ctxt, 1); 1016 1017 } else { 1018 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1); 1019 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt, 1020 be_encoded_q_len(mccq->len)); 1021 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id); 1022 } 1023 1024 /* Subscribe to Link State and Group 5 Events(bits 1 and 5 set) */ 1025 req->async_event_bitmap[0] = cpu_to_le32(0x00000022); 1026 be_dws_cpu_to_le(ctxt, sizeof(req->context)); 1027 1028 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); 1029 1030 status = be_mbox_notify_wait(adapter); 1031 if (!status) { 1032 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb); 1033 mccq->id = le16_to_cpu(resp->id); 1034 mccq->created = true; 1035 } 1036 mutex_unlock(&adapter->mbox_lock); 1037 1038 return status; 1039 } 1040 1041 int be_cmd_mccq_org_create(struct be_adapter *adapter, 1042 struct be_queue_info *mccq, 1043 struct be_queue_info *cq) 1044 { 1045 struct be_mcc_wrb *wrb; 1046 struct be_cmd_req_mcc_create *req; 1047 struct be_dma_mem *q_mem = &mccq->dma_mem; 1048 void *ctxt; 1049 int status; 1050 1051 if (mutex_lock_interruptible(&adapter->mbox_lock)) 1052 return -1; 1053 1054 wrb = wrb_from_mbox(adapter); 1055 req = embedded_payload(wrb); 1056 ctxt = &req->context; 1057 1058 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1059 OPCODE_COMMON_MCC_CREATE, sizeof(*req), wrb, NULL); 1060 1061 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size)); 1062 1063 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1); 1064 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt, 1065 be_encoded_q_len(mccq->len)); 1066 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id); 1067 1068 be_dws_cpu_to_le(ctxt, sizeof(req->context)); 1069 1070 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); 1071 1072 status = be_mbox_notify_wait(adapter); 1073 if (!status) { 1074 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb); 1075 mccq->id = le16_to_cpu(resp->id); 1076 mccq->created = true; 1077 } 1078 1079 mutex_unlock(&adapter->mbox_lock); 1080 return status; 1081 } 1082 1083 int be_cmd_mccq_create(struct be_adapter *adapter, 1084 struct be_queue_info *mccq, 1085 struct be_queue_info *cq) 1086 { 1087 int status; 1088 1089 status = be_cmd_mccq_ext_create(adapter, mccq, cq); 1090 if (status && !lancer_chip(adapter)) { 1091 dev_warn(&adapter->pdev->dev, "Upgrade to F/W ver 2.102.235.0 " 1092 "or newer to avoid conflicting priorities between NIC " 1093 "and FCoE traffic"); 1094 status = be_cmd_mccq_org_create(adapter, mccq, cq); 1095 } 1096 return status; 1097 } 1098 1099 int be_cmd_txq_create(struct be_adapter *adapter, 1100 struct be_queue_info *txq, 1101 struct be_queue_info *cq) 1102 { 1103 struct be_mcc_wrb *wrb; 1104 struct be_cmd_req_eth_tx_create *req; 1105 struct be_dma_mem *q_mem = &txq->dma_mem; 1106 void *ctxt; 1107 int status; 1108 1109 spin_lock_bh(&adapter->mcc_lock); 1110 1111 wrb = wrb_from_mccq(adapter); 1112 if (!wrb) { 1113 status = -EBUSY; 1114 goto err; 1115 } 1116 1117 req = embedded_payload(wrb); 1118 ctxt = &req->context; 1119 1120 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, 1121 OPCODE_ETH_TX_CREATE, sizeof(*req), wrb, NULL); 1122 1123 if (lancer_chip(adapter)) { 1124 req->hdr.version = 1; 1125 AMAP_SET_BITS(struct amap_tx_context, if_id, ctxt, 1126 adapter->if_handle); 1127 } 1128 1129 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size); 1130 req->ulp_num = BE_ULP1_NUM; 1131 req->type = BE_ETH_TX_RING_TYPE_STANDARD; 1132 1133 AMAP_SET_BITS(struct amap_tx_context, tx_ring_size, ctxt, 1134 be_encoded_q_len(txq->len)); 1135 AMAP_SET_BITS(struct amap_tx_context, ctx_valid, ctxt, 1); 1136 AMAP_SET_BITS(struct amap_tx_context, cq_id_send, ctxt, cq->id); 1137 1138 be_dws_cpu_to_le(ctxt, sizeof(req->context)); 1139 1140 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); 1141 1142 status = be_mcc_notify_wait(adapter); 1143 if (!status) { 1144 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(wrb); 1145 txq->id = le16_to_cpu(resp->cid); 1146 txq->created = true; 1147 } 1148 1149 err: 1150 spin_unlock_bh(&adapter->mcc_lock); 1151 1152 return status; 1153 } 1154 1155 /* Uses MCC */ 1156 int be_cmd_rxq_create(struct be_adapter *adapter, 1157 struct be_queue_info *rxq, u16 cq_id, u16 frag_size, 1158 u32 if_id, u32 rss, u8 *rss_id) 1159 { 1160 struct be_mcc_wrb *wrb; 1161 struct be_cmd_req_eth_rx_create *req; 1162 struct be_dma_mem *q_mem = &rxq->dma_mem; 1163 int status; 1164 1165 spin_lock_bh(&adapter->mcc_lock); 1166 1167 wrb = wrb_from_mccq(adapter); 1168 if (!wrb) { 1169 status = -EBUSY; 1170 goto err; 1171 } 1172 req = embedded_payload(wrb); 1173 1174 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, 1175 OPCODE_ETH_RX_CREATE, sizeof(*req), wrb, NULL); 1176 1177 req->cq_id = cpu_to_le16(cq_id); 1178 req->frag_size = fls(frag_size) - 1; 1179 req->num_pages = 2; 1180 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); 1181 req->interface_id = cpu_to_le32(if_id); 1182 req->max_frame_size = cpu_to_le16(BE_MAX_JUMBO_FRAME_SIZE); 1183 req->rss_queue = cpu_to_le32(rss); 1184 1185 status = be_mcc_notify_wait(adapter); 1186 if (!status) { 1187 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb); 1188 rxq->id = le16_to_cpu(resp->id); 1189 rxq->created = true; 1190 *rss_id = resp->rss_id; 1191 } 1192 1193 err: 1194 spin_unlock_bh(&adapter->mcc_lock); 1195 return status; 1196 } 1197 1198 /* Generic destroyer function for all types of queues 1199 * Uses Mbox 1200 */ 1201 int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q, 1202 int queue_type) 1203 { 1204 struct be_mcc_wrb *wrb; 1205 struct be_cmd_req_q_destroy *req; 1206 u8 subsys = 0, opcode = 0; 1207 int status; 1208 1209 if (mutex_lock_interruptible(&adapter->mbox_lock)) 1210 return -1; 1211 1212 wrb = wrb_from_mbox(adapter); 1213 req = embedded_payload(wrb); 1214 1215 switch (queue_type) { 1216 case QTYPE_EQ: 1217 subsys = CMD_SUBSYSTEM_COMMON; 1218 opcode = OPCODE_COMMON_EQ_DESTROY; 1219 break; 1220 case QTYPE_CQ: 1221 subsys = CMD_SUBSYSTEM_COMMON; 1222 opcode = OPCODE_COMMON_CQ_DESTROY; 1223 break; 1224 case QTYPE_TXQ: 1225 subsys = CMD_SUBSYSTEM_ETH; 1226 opcode = OPCODE_ETH_TX_DESTROY; 1227 break; 1228 case QTYPE_RXQ: 1229 subsys = CMD_SUBSYSTEM_ETH; 1230 opcode = OPCODE_ETH_RX_DESTROY; 1231 break; 1232 case QTYPE_MCCQ: 1233 subsys = CMD_SUBSYSTEM_COMMON; 1234 opcode = OPCODE_COMMON_MCC_DESTROY; 1235 break; 1236 default: 1237 BUG(); 1238 } 1239 1240 be_wrb_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req), wrb, 1241 NULL); 1242 req->id = cpu_to_le16(q->id); 1243 1244 status = be_mbox_notify_wait(adapter); 1245 q->created = false; 1246 1247 mutex_unlock(&adapter->mbox_lock); 1248 return status; 1249 } 1250 1251 /* Uses MCC */ 1252 int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q) 1253 { 1254 struct be_mcc_wrb *wrb; 1255 struct be_cmd_req_q_destroy *req; 1256 int status; 1257 1258 spin_lock_bh(&adapter->mcc_lock); 1259 1260 wrb = wrb_from_mccq(adapter); 1261 if (!wrb) { 1262 status = -EBUSY; 1263 goto err; 1264 } 1265 req = embedded_payload(wrb); 1266 1267 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, 1268 OPCODE_ETH_RX_DESTROY, sizeof(*req), wrb, NULL); 1269 req->id = cpu_to_le16(q->id); 1270 1271 status = be_mcc_notify_wait(adapter); 1272 q->created = false; 1273 1274 err: 1275 spin_unlock_bh(&adapter->mcc_lock); 1276 return status; 1277 } 1278 1279 /* Create an rx filtering policy configuration on an i/f 1280 * Uses MCCQ 1281 */ 1282 int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags, 1283 u32 *if_handle, u32 domain) 1284 { 1285 struct be_mcc_wrb *wrb; 1286 struct be_cmd_req_if_create *req; 1287 int status; 1288 1289 spin_lock_bh(&adapter->mcc_lock); 1290 1291 wrb = wrb_from_mccq(adapter); 1292 if (!wrb) { 1293 status = -EBUSY; 1294 goto err; 1295 } 1296 req = embedded_payload(wrb); 1297 1298 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1299 OPCODE_COMMON_NTWK_INTERFACE_CREATE, sizeof(*req), wrb, NULL); 1300 req->hdr.domain = domain; 1301 req->capability_flags = cpu_to_le32(cap_flags); 1302 req->enable_flags = cpu_to_le32(en_flags); 1303 1304 req->pmac_invalid = true; 1305 1306 status = be_mcc_notify_wait(adapter); 1307 if (!status) { 1308 struct be_cmd_resp_if_create *resp = embedded_payload(wrb); 1309 *if_handle = le32_to_cpu(resp->interface_id); 1310 } 1311 1312 err: 1313 spin_unlock_bh(&adapter->mcc_lock); 1314 return status; 1315 } 1316 1317 /* Uses MCCQ */ 1318 int be_cmd_if_destroy(struct be_adapter *adapter, int interface_id, u32 domain) 1319 { 1320 struct be_mcc_wrb *wrb; 1321 struct be_cmd_req_if_destroy *req; 1322 int status; 1323 1324 if (interface_id == -1) 1325 return 0; 1326 1327 spin_lock_bh(&adapter->mcc_lock); 1328 1329 wrb = wrb_from_mccq(adapter); 1330 if (!wrb) { 1331 status = -EBUSY; 1332 goto err; 1333 } 1334 req = embedded_payload(wrb); 1335 1336 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1337 OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req), wrb, NULL); 1338 req->hdr.domain = domain; 1339 req->interface_id = cpu_to_le32(interface_id); 1340 1341 status = be_mcc_notify_wait(adapter); 1342 err: 1343 spin_unlock_bh(&adapter->mcc_lock); 1344 return status; 1345 } 1346 1347 /* Get stats is a non embedded command: the request is not embedded inside 1348 * WRB but is a separate dma memory block 1349 * Uses asynchronous MCC 1350 */ 1351 int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd) 1352 { 1353 struct be_mcc_wrb *wrb; 1354 struct be_cmd_req_hdr *hdr; 1355 int status = 0; 1356 1357 spin_lock_bh(&adapter->mcc_lock); 1358 1359 wrb = wrb_from_mccq(adapter); 1360 if (!wrb) { 1361 status = -EBUSY; 1362 goto err; 1363 } 1364 hdr = nonemb_cmd->va; 1365 1366 be_wrb_cmd_hdr_prepare(hdr, CMD_SUBSYSTEM_ETH, 1367 OPCODE_ETH_GET_STATISTICS, nonemb_cmd->size, wrb, nonemb_cmd); 1368 1369 /* version 1 of the cmd is not supported only by BE2 */ 1370 if (!BE2_chip(adapter)) 1371 hdr->version = 1; 1372 1373 be_mcc_notify(adapter); 1374 adapter->stats_cmd_sent = true; 1375 1376 err: 1377 spin_unlock_bh(&adapter->mcc_lock); 1378 return status; 1379 } 1380 1381 /* Lancer Stats */ 1382 int lancer_cmd_get_pport_stats(struct be_adapter *adapter, 1383 struct be_dma_mem *nonemb_cmd) 1384 { 1385 1386 struct be_mcc_wrb *wrb; 1387 struct lancer_cmd_req_pport_stats *req; 1388 int status = 0; 1389 1390 if (!be_cmd_allowed(adapter, OPCODE_ETH_GET_PPORT_STATS, 1391 CMD_SUBSYSTEM_ETH)) 1392 return -EPERM; 1393 1394 spin_lock_bh(&adapter->mcc_lock); 1395 1396 wrb = wrb_from_mccq(adapter); 1397 if (!wrb) { 1398 status = -EBUSY; 1399 goto err; 1400 } 1401 req = nonemb_cmd->va; 1402 1403 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, 1404 OPCODE_ETH_GET_PPORT_STATS, nonemb_cmd->size, wrb, 1405 nonemb_cmd); 1406 1407 req->cmd_params.params.pport_num = cpu_to_le16(adapter->hba_port_num); 1408 req->cmd_params.params.reset_stats = 0; 1409 1410 be_mcc_notify(adapter); 1411 adapter->stats_cmd_sent = true; 1412 1413 err: 1414 spin_unlock_bh(&adapter->mcc_lock); 1415 return status; 1416 } 1417 1418 static int be_mac_to_link_speed(int mac_speed) 1419 { 1420 switch (mac_speed) { 1421 case PHY_LINK_SPEED_ZERO: 1422 return 0; 1423 case PHY_LINK_SPEED_10MBPS: 1424 return 10; 1425 case PHY_LINK_SPEED_100MBPS: 1426 return 100; 1427 case PHY_LINK_SPEED_1GBPS: 1428 return 1000; 1429 case PHY_LINK_SPEED_10GBPS: 1430 return 10000; 1431 } 1432 return 0; 1433 } 1434 1435 /* Uses synchronous mcc 1436 * Returns link_speed in Mbps 1437 */ 1438 int be_cmd_link_status_query(struct be_adapter *adapter, u16 *link_speed, 1439 u8 *link_status, u32 dom) 1440 { 1441 struct be_mcc_wrb *wrb; 1442 struct be_cmd_req_link_status *req; 1443 int status; 1444 1445 spin_lock_bh(&adapter->mcc_lock); 1446 1447 if (link_status) 1448 *link_status = LINK_DOWN; 1449 1450 wrb = wrb_from_mccq(adapter); 1451 if (!wrb) { 1452 status = -EBUSY; 1453 goto err; 1454 } 1455 req = embedded_payload(wrb); 1456 1457 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1458 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req), wrb, NULL); 1459 1460 /* version 1 of the cmd is not supported only by BE2 */ 1461 if (!BE2_chip(adapter)) 1462 req->hdr.version = 1; 1463 1464 req->hdr.domain = dom; 1465 1466 status = be_mcc_notify_wait(adapter); 1467 if (!status) { 1468 struct be_cmd_resp_link_status *resp = embedded_payload(wrb); 1469 if (link_speed) { 1470 *link_speed = resp->link_speed ? 1471 le16_to_cpu(resp->link_speed) * 10 : 1472 be_mac_to_link_speed(resp->mac_speed); 1473 1474 if (!resp->logical_link_status) 1475 *link_speed = 0; 1476 } 1477 if (link_status) 1478 *link_status = resp->logical_link_status; 1479 } 1480 1481 err: 1482 spin_unlock_bh(&adapter->mcc_lock); 1483 return status; 1484 } 1485 1486 /* Uses synchronous mcc */ 1487 int be_cmd_get_die_temperature(struct be_adapter *adapter) 1488 { 1489 struct be_mcc_wrb *wrb; 1490 struct be_cmd_req_get_cntl_addnl_attribs *req; 1491 int status; 1492 1493 spin_lock_bh(&adapter->mcc_lock); 1494 1495 wrb = wrb_from_mccq(adapter); 1496 if (!wrb) { 1497 status = -EBUSY; 1498 goto err; 1499 } 1500 req = embedded_payload(wrb); 1501 1502 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1503 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES, sizeof(*req), 1504 wrb, NULL); 1505 1506 be_mcc_notify(adapter); 1507 1508 err: 1509 spin_unlock_bh(&adapter->mcc_lock); 1510 return status; 1511 } 1512 1513 /* Uses synchronous mcc */ 1514 int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size) 1515 { 1516 struct be_mcc_wrb *wrb; 1517 struct be_cmd_req_get_fat *req; 1518 int status; 1519 1520 spin_lock_bh(&adapter->mcc_lock); 1521 1522 wrb = wrb_from_mccq(adapter); 1523 if (!wrb) { 1524 status = -EBUSY; 1525 goto err; 1526 } 1527 req = embedded_payload(wrb); 1528 1529 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1530 OPCODE_COMMON_MANAGE_FAT, sizeof(*req), wrb, NULL); 1531 req->fat_operation = cpu_to_le32(QUERY_FAT); 1532 status = be_mcc_notify_wait(adapter); 1533 if (!status) { 1534 struct be_cmd_resp_get_fat *resp = embedded_payload(wrb); 1535 if (log_size && resp->log_size) 1536 *log_size = le32_to_cpu(resp->log_size) - 1537 sizeof(u32); 1538 } 1539 err: 1540 spin_unlock_bh(&adapter->mcc_lock); 1541 return status; 1542 } 1543 1544 void be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf) 1545 { 1546 struct be_dma_mem get_fat_cmd; 1547 struct be_mcc_wrb *wrb; 1548 struct be_cmd_req_get_fat *req; 1549 u32 offset = 0, total_size, buf_size, 1550 log_offset = sizeof(u32), payload_len; 1551 int status; 1552 1553 if (buf_len == 0) 1554 return; 1555 1556 total_size = buf_len; 1557 1558 get_fat_cmd.size = sizeof(struct be_cmd_req_get_fat) + 60*1024; 1559 get_fat_cmd.va = pci_alloc_consistent(adapter->pdev, 1560 get_fat_cmd.size, 1561 &get_fat_cmd.dma); 1562 if (!get_fat_cmd.va) { 1563 status = -ENOMEM; 1564 dev_err(&adapter->pdev->dev, 1565 "Memory allocation failure while retrieving FAT data\n"); 1566 return; 1567 } 1568 1569 spin_lock_bh(&adapter->mcc_lock); 1570 1571 while (total_size) { 1572 buf_size = min(total_size, (u32)60*1024); 1573 total_size -= buf_size; 1574 1575 wrb = wrb_from_mccq(adapter); 1576 if (!wrb) { 1577 status = -EBUSY; 1578 goto err; 1579 } 1580 req = get_fat_cmd.va; 1581 1582 payload_len = sizeof(struct be_cmd_req_get_fat) + buf_size; 1583 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1584 OPCODE_COMMON_MANAGE_FAT, payload_len, wrb, 1585 &get_fat_cmd); 1586 1587 req->fat_operation = cpu_to_le32(RETRIEVE_FAT); 1588 req->read_log_offset = cpu_to_le32(log_offset); 1589 req->read_log_length = cpu_to_le32(buf_size); 1590 req->data_buffer_size = cpu_to_le32(buf_size); 1591 1592 status = be_mcc_notify_wait(adapter); 1593 if (!status) { 1594 struct be_cmd_resp_get_fat *resp = get_fat_cmd.va; 1595 memcpy(buf + offset, 1596 resp->data_buffer, 1597 le32_to_cpu(resp->read_log_length)); 1598 } else { 1599 dev_err(&adapter->pdev->dev, "FAT Table Retrieve error\n"); 1600 goto err; 1601 } 1602 offset += buf_size; 1603 log_offset += buf_size; 1604 } 1605 err: 1606 pci_free_consistent(adapter->pdev, get_fat_cmd.size, 1607 get_fat_cmd.va, 1608 get_fat_cmd.dma); 1609 spin_unlock_bh(&adapter->mcc_lock); 1610 } 1611 1612 /* Uses synchronous mcc */ 1613 int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver, 1614 char *fw_on_flash) 1615 { 1616 struct be_mcc_wrb *wrb; 1617 struct be_cmd_req_get_fw_version *req; 1618 int status; 1619 1620 spin_lock_bh(&adapter->mcc_lock); 1621 1622 wrb = wrb_from_mccq(adapter); 1623 if (!wrb) { 1624 status = -EBUSY; 1625 goto err; 1626 } 1627 1628 req = embedded_payload(wrb); 1629 1630 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1631 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req), wrb, NULL); 1632 status = be_mcc_notify_wait(adapter); 1633 if (!status) { 1634 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb); 1635 strcpy(fw_ver, resp->firmware_version_string); 1636 if (fw_on_flash) 1637 strcpy(fw_on_flash, resp->fw_on_flash_version_string); 1638 } 1639 err: 1640 spin_unlock_bh(&adapter->mcc_lock); 1641 return status; 1642 } 1643 1644 /* set the EQ delay interval of an EQ to specified value 1645 * Uses async mcc 1646 */ 1647 int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd) 1648 { 1649 struct be_mcc_wrb *wrb; 1650 struct be_cmd_req_modify_eq_delay *req; 1651 int status = 0; 1652 1653 spin_lock_bh(&adapter->mcc_lock); 1654 1655 wrb = wrb_from_mccq(adapter); 1656 if (!wrb) { 1657 status = -EBUSY; 1658 goto err; 1659 } 1660 req = embedded_payload(wrb); 1661 1662 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1663 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req), wrb, NULL); 1664 1665 req->num_eq = cpu_to_le32(1); 1666 req->delay[0].eq_id = cpu_to_le32(eq_id); 1667 req->delay[0].phase = 0; 1668 req->delay[0].delay_multiplier = cpu_to_le32(eqd); 1669 1670 be_mcc_notify(adapter); 1671 1672 err: 1673 spin_unlock_bh(&adapter->mcc_lock); 1674 return status; 1675 } 1676 1677 /* Uses sycnhronous mcc */ 1678 int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array, 1679 u32 num, bool untagged, bool promiscuous) 1680 { 1681 struct be_mcc_wrb *wrb; 1682 struct be_cmd_req_vlan_config *req; 1683 int status; 1684 1685 spin_lock_bh(&adapter->mcc_lock); 1686 1687 wrb = wrb_from_mccq(adapter); 1688 if (!wrb) { 1689 status = -EBUSY; 1690 goto err; 1691 } 1692 req = embedded_payload(wrb); 1693 1694 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1695 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req), wrb, NULL); 1696 1697 req->interface_id = if_id; 1698 req->promiscuous = promiscuous; 1699 req->untagged = untagged; 1700 req->num_vlan = num; 1701 if (!promiscuous) { 1702 memcpy(req->normal_vlan, vtag_array, 1703 req->num_vlan * sizeof(vtag_array[0])); 1704 } 1705 1706 status = be_mcc_notify_wait(adapter); 1707 1708 err: 1709 spin_unlock_bh(&adapter->mcc_lock); 1710 return status; 1711 } 1712 1713 int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value) 1714 { 1715 struct be_mcc_wrb *wrb; 1716 struct be_dma_mem *mem = &adapter->rx_filter; 1717 struct be_cmd_req_rx_filter *req = mem->va; 1718 int status; 1719 1720 spin_lock_bh(&adapter->mcc_lock); 1721 1722 wrb = wrb_from_mccq(adapter); 1723 if (!wrb) { 1724 status = -EBUSY; 1725 goto err; 1726 } 1727 memset(req, 0, sizeof(*req)); 1728 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1729 OPCODE_COMMON_NTWK_RX_FILTER, sizeof(*req), 1730 wrb, mem); 1731 1732 req->if_id = cpu_to_le32(adapter->if_handle); 1733 if (flags & IFF_PROMISC) { 1734 req->if_flags_mask = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS | 1735 BE_IF_FLAGS_VLAN_PROMISCUOUS); 1736 if (value == ON) 1737 req->if_flags = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS | 1738 BE_IF_FLAGS_VLAN_PROMISCUOUS); 1739 } else if (flags & IFF_ALLMULTI) { 1740 req->if_flags_mask = req->if_flags = 1741 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS); 1742 } else { 1743 struct netdev_hw_addr *ha; 1744 int i = 0; 1745 1746 req->if_flags_mask = req->if_flags = 1747 cpu_to_le32(BE_IF_FLAGS_MULTICAST); 1748 1749 /* Reset mcast promisc mode if already set by setting mask 1750 * and not setting flags field 1751 */ 1752 req->if_flags_mask |= 1753 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS & 1754 adapter->if_cap_flags); 1755 1756 req->mcast_num = cpu_to_le32(netdev_mc_count(adapter->netdev)); 1757 netdev_for_each_mc_addr(ha, adapter->netdev) 1758 memcpy(req->mcast_mac[i++].byte, ha->addr, ETH_ALEN); 1759 } 1760 1761 status = be_mcc_notify_wait(adapter); 1762 err: 1763 spin_unlock_bh(&adapter->mcc_lock); 1764 return status; 1765 } 1766 1767 /* Uses synchrounous mcc */ 1768 int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc) 1769 { 1770 struct be_mcc_wrb *wrb; 1771 struct be_cmd_req_set_flow_control *req; 1772 int status; 1773 1774 if (!be_cmd_allowed(adapter, OPCODE_COMMON_SET_FLOW_CONTROL, 1775 CMD_SUBSYSTEM_COMMON)) 1776 return -EPERM; 1777 1778 spin_lock_bh(&adapter->mcc_lock); 1779 1780 wrb = wrb_from_mccq(adapter); 1781 if (!wrb) { 1782 status = -EBUSY; 1783 goto err; 1784 } 1785 req = embedded_payload(wrb); 1786 1787 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1788 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req), wrb, NULL); 1789 1790 req->tx_flow_control = cpu_to_le16((u16)tx_fc); 1791 req->rx_flow_control = cpu_to_le16((u16)rx_fc); 1792 1793 status = be_mcc_notify_wait(adapter); 1794 1795 err: 1796 spin_unlock_bh(&adapter->mcc_lock); 1797 return status; 1798 } 1799 1800 /* Uses sycn mcc */ 1801 int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc) 1802 { 1803 struct be_mcc_wrb *wrb; 1804 struct be_cmd_req_get_flow_control *req; 1805 int status; 1806 1807 if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_FLOW_CONTROL, 1808 CMD_SUBSYSTEM_COMMON)) 1809 return -EPERM; 1810 1811 spin_lock_bh(&adapter->mcc_lock); 1812 1813 wrb = wrb_from_mccq(adapter); 1814 if (!wrb) { 1815 status = -EBUSY; 1816 goto err; 1817 } 1818 req = embedded_payload(wrb); 1819 1820 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1821 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req), wrb, NULL); 1822 1823 status = be_mcc_notify_wait(adapter); 1824 if (!status) { 1825 struct be_cmd_resp_get_flow_control *resp = 1826 embedded_payload(wrb); 1827 *tx_fc = le16_to_cpu(resp->tx_flow_control); 1828 *rx_fc = le16_to_cpu(resp->rx_flow_control); 1829 } 1830 1831 err: 1832 spin_unlock_bh(&adapter->mcc_lock); 1833 return status; 1834 } 1835 1836 /* Uses mbox */ 1837 int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num, 1838 u32 *mode, u32 *caps) 1839 { 1840 struct be_mcc_wrb *wrb; 1841 struct be_cmd_req_query_fw_cfg *req; 1842 int status; 1843 1844 if (mutex_lock_interruptible(&adapter->mbox_lock)) 1845 return -1; 1846 1847 wrb = wrb_from_mbox(adapter); 1848 req = embedded_payload(wrb); 1849 1850 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1851 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req), wrb, NULL); 1852 1853 status = be_mbox_notify_wait(adapter); 1854 if (!status) { 1855 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb); 1856 *port_num = le32_to_cpu(resp->phys_port); 1857 *mode = le32_to_cpu(resp->function_mode); 1858 *caps = le32_to_cpu(resp->function_caps); 1859 } 1860 1861 mutex_unlock(&adapter->mbox_lock); 1862 return status; 1863 } 1864 1865 /* Uses mbox */ 1866 int be_cmd_reset_function(struct be_adapter *adapter) 1867 { 1868 struct be_mcc_wrb *wrb; 1869 struct be_cmd_req_hdr *req; 1870 int status; 1871 1872 if (lancer_chip(adapter)) { 1873 status = lancer_wait_ready(adapter); 1874 if (!status) { 1875 iowrite32(SLI_PORT_CONTROL_IP_MASK, 1876 adapter->db + SLIPORT_CONTROL_OFFSET); 1877 status = lancer_test_and_set_rdy_state(adapter); 1878 } 1879 if (status) { 1880 dev_err(&adapter->pdev->dev, 1881 "Adapter in non recoverable error\n"); 1882 } 1883 return status; 1884 } 1885 1886 if (mutex_lock_interruptible(&adapter->mbox_lock)) 1887 return -1; 1888 1889 wrb = wrb_from_mbox(adapter); 1890 req = embedded_payload(wrb); 1891 1892 be_wrb_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON, 1893 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req), wrb, NULL); 1894 1895 status = be_mbox_notify_wait(adapter); 1896 1897 mutex_unlock(&adapter->mbox_lock); 1898 return status; 1899 } 1900 1901 int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable, u16 table_size) 1902 { 1903 struct be_mcc_wrb *wrb; 1904 struct be_cmd_req_rss_config *req; 1905 u32 myhash[10] = {0x15d43fa5, 0x2534685a, 0x5f87693a, 0x5668494e, 1906 0x33cf6a53, 0x383334c6, 0x76ac4257, 0x59b242b2, 1907 0x3ea83c02, 0x4a110304}; 1908 int status; 1909 1910 if (mutex_lock_interruptible(&adapter->mbox_lock)) 1911 return -1; 1912 1913 wrb = wrb_from_mbox(adapter); 1914 req = embedded_payload(wrb); 1915 1916 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, 1917 OPCODE_ETH_RSS_CONFIG, sizeof(*req), wrb, NULL); 1918 1919 req->if_id = cpu_to_le32(adapter->if_handle); 1920 req->enable_rss = cpu_to_le16(RSS_ENABLE_TCP_IPV4 | RSS_ENABLE_IPV4 | 1921 RSS_ENABLE_TCP_IPV6 | RSS_ENABLE_IPV6); 1922 1923 if (lancer_chip(adapter) || skyhawk_chip(adapter)) { 1924 req->hdr.version = 1; 1925 req->enable_rss |= cpu_to_le16(RSS_ENABLE_UDP_IPV4 | 1926 RSS_ENABLE_UDP_IPV6); 1927 } 1928 1929 req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1); 1930 memcpy(req->cpu_table, rsstable, table_size); 1931 memcpy(req->hash, myhash, sizeof(myhash)); 1932 be_dws_cpu_to_le(req->hash, sizeof(req->hash)); 1933 1934 status = be_mbox_notify_wait(adapter); 1935 1936 mutex_unlock(&adapter->mbox_lock); 1937 return status; 1938 } 1939 1940 /* Uses sync mcc */ 1941 int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num, 1942 u8 bcn, u8 sts, u8 state) 1943 { 1944 struct be_mcc_wrb *wrb; 1945 struct be_cmd_req_enable_disable_beacon *req; 1946 int status; 1947 1948 spin_lock_bh(&adapter->mcc_lock); 1949 1950 wrb = wrb_from_mccq(adapter); 1951 if (!wrb) { 1952 status = -EBUSY; 1953 goto err; 1954 } 1955 req = embedded_payload(wrb); 1956 1957 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1958 OPCODE_COMMON_ENABLE_DISABLE_BEACON, sizeof(*req), wrb, NULL); 1959 1960 req->port_num = port_num; 1961 req->beacon_state = state; 1962 req->beacon_duration = bcn; 1963 req->status_duration = sts; 1964 1965 status = be_mcc_notify_wait(adapter); 1966 1967 err: 1968 spin_unlock_bh(&adapter->mcc_lock); 1969 return status; 1970 } 1971 1972 /* Uses sync mcc */ 1973 int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state) 1974 { 1975 struct be_mcc_wrb *wrb; 1976 struct be_cmd_req_get_beacon_state *req; 1977 int status; 1978 1979 spin_lock_bh(&adapter->mcc_lock); 1980 1981 wrb = wrb_from_mccq(adapter); 1982 if (!wrb) { 1983 status = -EBUSY; 1984 goto err; 1985 } 1986 req = embedded_payload(wrb); 1987 1988 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1989 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req), wrb, NULL); 1990 1991 req->port_num = port_num; 1992 1993 status = be_mcc_notify_wait(adapter); 1994 if (!status) { 1995 struct be_cmd_resp_get_beacon_state *resp = 1996 embedded_payload(wrb); 1997 *state = resp->beacon_state; 1998 } 1999 2000 err: 2001 spin_unlock_bh(&adapter->mcc_lock); 2002 return status; 2003 } 2004 2005 int lancer_cmd_write_object(struct be_adapter *adapter, struct be_dma_mem *cmd, 2006 u32 data_size, u32 data_offset, 2007 const char *obj_name, u32 *data_written, 2008 u8 *change_status, u8 *addn_status) 2009 { 2010 struct be_mcc_wrb *wrb; 2011 struct lancer_cmd_req_write_object *req; 2012 struct lancer_cmd_resp_write_object *resp; 2013 void *ctxt = NULL; 2014 int status; 2015 2016 spin_lock_bh(&adapter->mcc_lock); 2017 adapter->flash_status = 0; 2018 2019 wrb = wrb_from_mccq(adapter); 2020 if (!wrb) { 2021 status = -EBUSY; 2022 goto err_unlock; 2023 } 2024 2025 req = embedded_payload(wrb); 2026 2027 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2028 OPCODE_COMMON_WRITE_OBJECT, 2029 sizeof(struct lancer_cmd_req_write_object), wrb, 2030 NULL); 2031 2032 ctxt = &req->context; 2033 AMAP_SET_BITS(struct amap_lancer_write_obj_context, 2034 write_length, ctxt, data_size); 2035 2036 if (data_size == 0) 2037 AMAP_SET_BITS(struct amap_lancer_write_obj_context, 2038 eof, ctxt, 1); 2039 else 2040 AMAP_SET_BITS(struct amap_lancer_write_obj_context, 2041 eof, ctxt, 0); 2042 2043 be_dws_cpu_to_le(ctxt, sizeof(req->context)); 2044 req->write_offset = cpu_to_le32(data_offset); 2045 strcpy(req->object_name, obj_name); 2046 req->descriptor_count = cpu_to_le32(1); 2047 req->buf_len = cpu_to_le32(data_size); 2048 req->addr_low = cpu_to_le32((cmd->dma + 2049 sizeof(struct lancer_cmd_req_write_object)) 2050 & 0xFFFFFFFF); 2051 req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma + 2052 sizeof(struct lancer_cmd_req_write_object))); 2053 2054 be_mcc_notify(adapter); 2055 spin_unlock_bh(&adapter->mcc_lock); 2056 2057 if (!wait_for_completion_timeout(&adapter->flash_compl, 2058 msecs_to_jiffies(30000))) 2059 status = -1; 2060 else 2061 status = adapter->flash_status; 2062 2063 resp = embedded_payload(wrb); 2064 if (!status) { 2065 *data_written = le32_to_cpu(resp->actual_write_len); 2066 *change_status = resp->change_status; 2067 } else { 2068 *addn_status = resp->additional_status; 2069 } 2070 2071 return status; 2072 2073 err_unlock: 2074 spin_unlock_bh(&adapter->mcc_lock); 2075 return status; 2076 } 2077 2078 int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd, 2079 u32 data_size, u32 data_offset, const char *obj_name, 2080 u32 *data_read, u32 *eof, u8 *addn_status) 2081 { 2082 struct be_mcc_wrb *wrb; 2083 struct lancer_cmd_req_read_object *req; 2084 struct lancer_cmd_resp_read_object *resp; 2085 int status; 2086 2087 spin_lock_bh(&adapter->mcc_lock); 2088 2089 wrb = wrb_from_mccq(adapter); 2090 if (!wrb) { 2091 status = -EBUSY; 2092 goto err_unlock; 2093 } 2094 2095 req = embedded_payload(wrb); 2096 2097 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2098 OPCODE_COMMON_READ_OBJECT, 2099 sizeof(struct lancer_cmd_req_read_object), wrb, 2100 NULL); 2101 2102 req->desired_read_len = cpu_to_le32(data_size); 2103 req->read_offset = cpu_to_le32(data_offset); 2104 strcpy(req->object_name, obj_name); 2105 req->descriptor_count = cpu_to_le32(1); 2106 req->buf_len = cpu_to_le32(data_size); 2107 req->addr_low = cpu_to_le32((cmd->dma & 0xFFFFFFFF)); 2108 req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma)); 2109 2110 status = be_mcc_notify_wait(adapter); 2111 2112 resp = embedded_payload(wrb); 2113 if (!status) { 2114 *data_read = le32_to_cpu(resp->actual_read_len); 2115 *eof = le32_to_cpu(resp->eof); 2116 } else { 2117 *addn_status = resp->additional_status; 2118 } 2119 2120 err_unlock: 2121 spin_unlock_bh(&adapter->mcc_lock); 2122 return status; 2123 } 2124 2125 int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd, 2126 u32 flash_type, u32 flash_opcode, u32 buf_size) 2127 { 2128 struct be_mcc_wrb *wrb; 2129 struct be_cmd_write_flashrom *req; 2130 int status; 2131 2132 spin_lock_bh(&adapter->mcc_lock); 2133 adapter->flash_status = 0; 2134 2135 wrb = wrb_from_mccq(adapter); 2136 if (!wrb) { 2137 status = -EBUSY; 2138 goto err_unlock; 2139 } 2140 req = cmd->va; 2141 2142 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2143 OPCODE_COMMON_WRITE_FLASHROM, cmd->size, wrb, cmd); 2144 2145 req->params.op_type = cpu_to_le32(flash_type); 2146 req->params.op_code = cpu_to_le32(flash_opcode); 2147 req->params.data_buf_size = cpu_to_le32(buf_size); 2148 2149 be_mcc_notify(adapter); 2150 spin_unlock_bh(&adapter->mcc_lock); 2151 2152 if (!wait_for_completion_timeout(&adapter->flash_compl, 2153 msecs_to_jiffies(40000))) 2154 status = -1; 2155 else 2156 status = adapter->flash_status; 2157 2158 return status; 2159 2160 err_unlock: 2161 spin_unlock_bh(&adapter->mcc_lock); 2162 return status; 2163 } 2164 2165 int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc, 2166 int offset) 2167 { 2168 struct be_mcc_wrb *wrb; 2169 struct be_cmd_read_flash_crc *req; 2170 int status; 2171 2172 spin_lock_bh(&adapter->mcc_lock); 2173 2174 wrb = wrb_from_mccq(adapter); 2175 if (!wrb) { 2176 status = -EBUSY; 2177 goto err; 2178 } 2179 req = embedded_payload(wrb); 2180 2181 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2182 OPCODE_COMMON_READ_FLASHROM, sizeof(*req), 2183 wrb, NULL); 2184 2185 req->params.op_type = cpu_to_le32(OPTYPE_REDBOOT); 2186 req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT); 2187 req->params.offset = cpu_to_le32(offset); 2188 req->params.data_buf_size = cpu_to_le32(0x4); 2189 2190 status = be_mcc_notify_wait(adapter); 2191 if (!status) 2192 memcpy(flashed_crc, req->crc, 4); 2193 2194 err: 2195 spin_unlock_bh(&adapter->mcc_lock); 2196 return status; 2197 } 2198 2199 int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac, 2200 struct be_dma_mem *nonemb_cmd) 2201 { 2202 struct be_mcc_wrb *wrb; 2203 struct be_cmd_req_acpi_wol_magic_config *req; 2204 int status; 2205 2206 spin_lock_bh(&adapter->mcc_lock); 2207 2208 wrb = wrb_from_mccq(adapter); 2209 if (!wrb) { 2210 status = -EBUSY; 2211 goto err; 2212 } 2213 req = nonemb_cmd->va; 2214 2215 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, 2216 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req), wrb, 2217 nonemb_cmd); 2218 memcpy(req->magic_mac, mac, ETH_ALEN); 2219 2220 status = be_mcc_notify_wait(adapter); 2221 2222 err: 2223 spin_unlock_bh(&adapter->mcc_lock); 2224 return status; 2225 } 2226 2227 int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num, 2228 u8 loopback_type, u8 enable) 2229 { 2230 struct be_mcc_wrb *wrb; 2231 struct be_cmd_req_set_lmode *req; 2232 int status; 2233 2234 spin_lock_bh(&adapter->mcc_lock); 2235 2236 wrb = wrb_from_mccq(adapter); 2237 if (!wrb) { 2238 status = -EBUSY; 2239 goto err; 2240 } 2241 2242 req = embedded_payload(wrb); 2243 2244 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL, 2245 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE, sizeof(*req), wrb, 2246 NULL); 2247 2248 req->src_port = port_num; 2249 req->dest_port = port_num; 2250 req->loopback_type = loopback_type; 2251 req->loopback_state = enable; 2252 2253 status = be_mcc_notify_wait(adapter); 2254 err: 2255 spin_unlock_bh(&adapter->mcc_lock); 2256 return status; 2257 } 2258 2259 int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num, 2260 u32 loopback_type, u32 pkt_size, u32 num_pkts, u64 pattern) 2261 { 2262 struct be_mcc_wrb *wrb; 2263 struct be_cmd_req_loopback_test *req; 2264 int status; 2265 2266 spin_lock_bh(&adapter->mcc_lock); 2267 2268 wrb = wrb_from_mccq(adapter); 2269 if (!wrb) { 2270 status = -EBUSY; 2271 goto err; 2272 } 2273 2274 req = embedded_payload(wrb); 2275 2276 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL, 2277 OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req), wrb, NULL); 2278 req->hdr.timeout = cpu_to_le32(4); 2279 2280 req->pattern = cpu_to_le64(pattern); 2281 req->src_port = cpu_to_le32(port_num); 2282 req->dest_port = cpu_to_le32(port_num); 2283 req->pkt_size = cpu_to_le32(pkt_size); 2284 req->num_pkts = cpu_to_le32(num_pkts); 2285 req->loopback_type = cpu_to_le32(loopback_type); 2286 2287 status = be_mcc_notify_wait(adapter); 2288 if (!status) { 2289 struct be_cmd_resp_loopback_test *resp = embedded_payload(wrb); 2290 status = le32_to_cpu(resp->status); 2291 } 2292 2293 err: 2294 spin_unlock_bh(&adapter->mcc_lock); 2295 return status; 2296 } 2297 2298 int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern, 2299 u32 byte_cnt, struct be_dma_mem *cmd) 2300 { 2301 struct be_mcc_wrb *wrb; 2302 struct be_cmd_req_ddrdma_test *req; 2303 int status; 2304 int i, j = 0; 2305 2306 spin_lock_bh(&adapter->mcc_lock); 2307 2308 wrb = wrb_from_mccq(adapter); 2309 if (!wrb) { 2310 status = -EBUSY; 2311 goto err; 2312 } 2313 req = cmd->va; 2314 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL, 2315 OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size, wrb, cmd); 2316 2317 req->pattern = cpu_to_le64(pattern); 2318 req->byte_count = cpu_to_le32(byte_cnt); 2319 for (i = 0; i < byte_cnt; i++) { 2320 req->snd_buff[i] = (u8)(pattern >> (j*8)); 2321 j++; 2322 if (j > 7) 2323 j = 0; 2324 } 2325 2326 status = be_mcc_notify_wait(adapter); 2327 2328 if (!status) { 2329 struct be_cmd_resp_ddrdma_test *resp; 2330 resp = cmd->va; 2331 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) || 2332 resp->snd_err) { 2333 status = -1; 2334 } 2335 } 2336 2337 err: 2338 spin_unlock_bh(&adapter->mcc_lock); 2339 return status; 2340 } 2341 2342 int be_cmd_get_seeprom_data(struct be_adapter *adapter, 2343 struct be_dma_mem *nonemb_cmd) 2344 { 2345 struct be_mcc_wrb *wrb; 2346 struct be_cmd_req_seeprom_read *req; 2347 struct be_sge *sge; 2348 int status; 2349 2350 spin_lock_bh(&adapter->mcc_lock); 2351 2352 wrb = wrb_from_mccq(adapter); 2353 if (!wrb) { 2354 status = -EBUSY; 2355 goto err; 2356 } 2357 req = nonemb_cmd->va; 2358 sge = nonembedded_sgl(wrb); 2359 2360 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2361 OPCODE_COMMON_SEEPROM_READ, sizeof(*req), wrb, 2362 nonemb_cmd); 2363 2364 status = be_mcc_notify_wait(adapter); 2365 2366 err: 2367 spin_unlock_bh(&adapter->mcc_lock); 2368 return status; 2369 } 2370 2371 int be_cmd_get_phy_info(struct be_adapter *adapter) 2372 { 2373 struct be_mcc_wrb *wrb; 2374 struct be_cmd_req_get_phy_info *req; 2375 struct be_dma_mem cmd; 2376 int status; 2377 2378 if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_PHY_DETAILS, 2379 CMD_SUBSYSTEM_COMMON)) 2380 return -EPERM; 2381 2382 spin_lock_bh(&adapter->mcc_lock); 2383 2384 wrb = wrb_from_mccq(adapter); 2385 if (!wrb) { 2386 status = -EBUSY; 2387 goto err; 2388 } 2389 cmd.size = sizeof(struct be_cmd_req_get_phy_info); 2390 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, 2391 &cmd.dma); 2392 if (!cmd.va) { 2393 dev_err(&adapter->pdev->dev, "Memory alloc failure\n"); 2394 status = -ENOMEM; 2395 goto err; 2396 } 2397 2398 req = cmd.va; 2399 2400 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2401 OPCODE_COMMON_GET_PHY_DETAILS, sizeof(*req), 2402 wrb, &cmd); 2403 2404 status = be_mcc_notify_wait(adapter); 2405 if (!status) { 2406 struct be_phy_info *resp_phy_info = 2407 cmd.va + sizeof(struct be_cmd_req_hdr); 2408 adapter->phy.phy_type = le16_to_cpu(resp_phy_info->phy_type); 2409 adapter->phy.interface_type = 2410 le16_to_cpu(resp_phy_info->interface_type); 2411 adapter->phy.auto_speeds_supported = 2412 le16_to_cpu(resp_phy_info->auto_speeds_supported); 2413 adapter->phy.fixed_speeds_supported = 2414 le16_to_cpu(resp_phy_info->fixed_speeds_supported); 2415 adapter->phy.misc_params = 2416 le32_to_cpu(resp_phy_info->misc_params); 2417 } 2418 pci_free_consistent(adapter->pdev, cmd.size, 2419 cmd.va, cmd.dma); 2420 err: 2421 spin_unlock_bh(&adapter->mcc_lock); 2422 return status; 2423 } 2424 2425 int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain) 2426 { 2427 struct be_mcc_wrb *wrb; 2428 struct be_cmd_req_set_qos *req; 2429 int status; 2430 2431 spin_lock_bh(&adapter->mcc_lock); 2432 2433 wrb = wrb_from_mccq(adapter); 2434 if (!wrb) { 2435 status = -EBUSY; 2436 goto err; 2437 } 2438 2439 req = embedded_payload(wrb); 2440 2441 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2442 OPCODE_COMMON_SET_QOS, sizeof(*req), wrb, NULL); 2443 2444 req->hdr.domain = domain; 2445 req->valid_bits = cpu_to_le32(BE_QOS_BITS_NIC); 2446 req->max_bps_nic = cpu_to_le32(bps); 2447 2448 status = be_mcc_notify_wait(adapter); 2449 2450 err: 2451 spin_unlock_bh(&adapter->mcc_lock); 2452 return status; 2453 } 2454 2455 int be_cmd_get_cntl_attributes(struct be_adapter *adapter) 2456 { 2457 struct be_mcc_wrb *wrb; 2458 struct be_cmd_req_cntl_attribs *req; 2459 struct be_cmd_resp_cntl_attribs *resp; 2460 int status; 2461 int payload_len = max(sizeof(*req), sizeof(*resp)); 2462 struct mgmt_controller_attrib *attribs; 2463 struct be_dma_mem attribs_cmd; 2464 2465 memset(&attribs_cmd, 0, sizeof(struct be_dma_mem)); 2466 attribs_cmd.size = sizeof(struct be_cmd_resp_cntl_attribs); 2467 attribs_cmd.va = pci_alloc_consistent(adapter->pdev, attribs_cmd.size, 2468 &attribs_cmd.dma); 2469 if (!attribs_cmd.va) { 2470 dev_err(&adapter->pdev->dev, 2471 "Memory allocation failure\n"); 2472 return -ENOMEM; 2473 } 2474 2475 if (mutex_lock_interruptible(&adapter->mbox_lock)) 2476 return -1; 2477 2478 wrb = wrb_from_mbox(adapter); 2479 if (!wrb) { 2480 status = -EBUSY; 2481 goto err; 2482 } 2483 req = attribs_cmd.va; 2484 2485 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2486 OPCODE_COMMON_GET_CNTL_ATTRIBUTES, payload_len, wrb, 2487 &attribs_cmd); 2488 2489 status = be_mbox_notify_wait(adapter); 2490 if (!status) { 2491 attribs = attribs_cmd.va + sizeof(struct be_cmd_resp_hdr); 2492 adapter->hba_port_num = attribs->hba_attribs.phy_port; 2493 } 2494 2495 err: 2496 mutex_unlock(&adapter->mbox_lock); 2497 pci_free_consistent(adapter->pdev, attribs_cmd.size, attribs_cmd.va, 2498 attribs_cmd.dma); 2499 return status; 2500 } 2501 2502 /* Uses mbox */ 2503 int be_cmd_req_native_mode(struct be_adapter *adapter) 2504 { 2505 struct be_mcc_wrb *wrb; 2506 struct be_cmd_req_set_func_cap *req; 2507 int status; 2508 2509 if (mutex_lock_interruptible(&adapter->mbox_lock)) 2510 return -1; 2511 2512 wrb = wrb_from_mbox(adapter); 2513 if (!wrb) { 2514 status = -EBUSY; 2515 goto err; 2516 } 2517 2518 req = embedded_payload(wrb); 2519 2520 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2521 OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP, sizeof(*req), wrb, NULL); 2522 2523 req->valid_cap_flags = cpu_to_le32(CAPABILITY_SW_TIMESTAMPS | 2524 CAPABILITY_BE3_NATIVE_ERX_API); 2525 req->cap_flags = cpu_to_le32(CAPABILITY_BE3_NATIVE_ERX_API); 2526 2527 status = be_mbox_notify_wait(adapter); 2528 if (!status) { 2529 struct be_cmd_resp_set_func_cap *resp = embedded_payload(wrb); 2530 adapter->be3_native = le32_to_cpu(resp->cap_flags) & 2531 CAPABILITY_BE3_NATIVE_ERX_API; 2532 if (!adapter->be3_native) 2533 dev_warn(&adapter->pdev->dev, 2534 "adapter not in advanced mode\n"); 2535 } 2536 err: 2537 mutex_unlock(&adapter->mbox_lock); 2538 return status; 2539 } 2540 2541 /* Get privilege(s) for a function */ 2542 int be_cmd_get_fn_privileges(struct be_adapter *adapter, u32 *privilege, 2543 u32 domain) 2544 { 2545 struct be_mcc_wrb *wrb; 2546 struct be_cmd_req_get_fn_privileges *req; 2547 int status; 2548 2549 spin_lock_bh(&adapter->mcc_lock); 2550 2551 wrb = wrb_from_mccq(adapter); 2552 if (!wrb) { 2553 status = -EBUSY; 2554 goto err; 2555 } 2556 2557 req = embedded_payload(wrb); 2558 2559 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2560 OPCODE_COMMON_GET_FN_PRIVILEGES, sizeof(*req), 2561 wrb, NULL); 2562 2563 req->hdr.domain = domain; 2564 2565 status = be_mcc_notify_wait(adapter); 2566 if (!status) { 2567 struct be_cmd_resp_get_fn_privileges *resp = 2568 embedded_payload(wrb); 2569 *privilege = le32_to_cpu(resp->privilege_mask); 2570 } 2571 2572 err: 2573 spin_unlock_bh(&adapter->mcc_lock); 2574 return status; 2575 } 2576 2577 /* Uses synchronous MCCQ */ 2578 int be_cmd_get_mac_from_list(struct be_adapter *adapter, u8 *mac, 2579 bool *pmac_id_active, u32 *pmac_id, u8 domain) 2580 { 2581 struct be_mcc_wrb *wrb; 2582 struct be_cmd_req_get_mac_list *req; 2583 int status; 2584 int mac_count; 2585 struct be_dma_mem get_mac_list_cmd; 2586 int i; 2587 2588 memset(&get_mac_list_cmd, 0, sizeof(struct be_dma_mem)); 2589 get_mac_list_cmd.size = sizeof(struct be_cmd_resp_get_mac_list); 2590 get_mac_list_cmd.va = pci_alloc_consistent(adapter->pdev, 2591 get_mac_list_cmd.size, 2592 &get_mac_list_cmd.dma); 2593 2594 if (!get_mac_list_cmd.va) { 2595 dev_err(&adapter->pdev->dev, 2596 "Memory allocation failure during GET_MAC_LIST\n"); 2597 return -ENOMEM; 2598 } 2599 2600 spin_lock_bh(&adapter->mcc_lock); 2601 2602 wrb = wrb_from_mccq(adapter); 2603 if (!wrb) { 2604 status = -EBUSY; 2605 goto out; 2606 } 2607 2608 req = get_mac_list_cmd.va; 2609 2610 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2611 OPCODE_COMMON_GET_MAC_LIST, sizeof(*req), 2612 wrb, &get_mac_list_cmd); 2613 2614 req->hdr.domain = domain; 2615 req->mac_type = MAC_ADDRESS_TYPE_NETWORK; 2616 req->perm_override = 1; 2617 2618 status = be_mcc_notify_wait(adapter); 2619 if (!status) { 2620 struct be_cmd_resp_get_mac_list *resp = 2621 get_mac_list_cmd.va; 2622 mac_count = resp->true_mac_count + resp->pseudo_mac_count; 2623 /* Mac list returned could contain one or more active mac_ids 2624 * or one or more true or pseudo permanant mac addresses. 2625 * If an active mac_id is present, return first active mac_id 2626 * found. 2627 */ 2628 for (i = 0; i < mac_count; i++) { 2629 struct get_list_macaddr *mac_entry; 2630 u16 mac_addr_size; 2631 u32 mac_id; 2632 2633 mac_entry = &resp->macaddr_list[i]; 2634 mac_addr_size = le16_to_cpu(mac_entry->mac_addr_size); 2635 /* mac_id is a 32 bit value and mac_addr size 2636 * is 6 bytes 2637 */ 2638 if (mac_addr_size == sizeof(u32)) { 2639 *pmac_id_active = true; 2640 mac_id = mac_entry->mac_addr_id.s_mac_id.mac_id; 2641 *pmac_id = le32_to_cpu(mac_id); 2642 goto out; 2643 } 2644 } 2645 /* If no active mac_id found, return first mac addr */ 2646 *pmac_id_active = false; 2647 memcpy(mac, resp->macaddr_list[0].mac_addr_id.macaddr, 2648 ETH_ALEN); 2649 } 2650 2651 out: 2652 spin_unlock_bh(&adapter->mcc_lock); 2653 pci_free_consistent(adapter->pdev, get_mac_list_cmd.size, 2654 get_mac_list_cmd.va, get_mac_list_cmd.dma); 2655 return status; 2656 } 2657 2658 /* Uses synchronous MCCQ */ 2659 int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array, 2660 u8 mac_count, u32 domain) 2661 { 2662 struct be_mcc_wrb *wrb; 2663 struct be_cmd_req_set_mac_list *req; 2664 int status; 2665 struct be_dma_mem cmd; 2666 2667 memset(&cmd, 0, sizeof(struct be_dma_mem)); 2668 cmd.size = sizeof(struct be_cmd_req_set_mac_list); 2669 cmd.va = dma_alloc_coherent(&adapter->pdev->dev, cmd.size, 2670 &cmd.dma, GFP_KERNEL); 2671 if (!cmd.va) { 2672 dev_err(&adapter->pdev->dev, "Memory alloc failure\n"); 2673 return -ENOMEM; 2674 } 2675 2676 spin_lock_bh(&adapter->mcc_lock); 2677 2678 wrb = wrb_from_mccq(adapter); 2679 if (!wrb) { 2680 status = -EBUSY; 2681 goto err; 2682 } 2683 2684 req = cmd.va; 2685 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2686 OPCODE_COMMON_SET_MAC_LIST, sizeof(*req), 2687 wrb, &cmd); 2688 2689 req->hdr.domain = domain; 2690 req->mac_count = mac_count; 2691 if (mac_count) 2692 memcpy(req->mac, mac_array, ETH_ALEN*mac_count); 2693 2694 status = be_mcc_notify_wait(adapter); 2695 2696 err: 2697 dma_free_coherent(&adapter->pdev->dev, cmd.size, 2698 cmd.va, cmd.dma); 2699 spin_unlock_bh(&adapter->mcc_lock); 2700 return status; 2701 } 2702 2703 int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid, 2704 u32 domain, u16 intf_id) 2705 { 2706 struct be_mcc_wrb *wrb; 2707 struct be_cmd_req_set_hsw_config *req; 2708 void *ctxt; 2709 int status; 2710 2711 spin_lock_bh(&adapter->mcc_lock); 2712 2713 wrb = wrb_from_mccq(adapter); 2714 if (!wrb) { 2715 status = -EBUSY; 2716 goto err; 2717 } 2718 2719 req = embedded_payload(wrb); 2720 ctxt = &req->context; 2721 2722 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2723 OPCODE_COMMON_SET_HSW_CONFIG, sizeof(*req), wrb, NULL); 2724 2725 req->hdr.domain = domain; 2726 AMAP_SET_BITS(struct amap_set_hsw_context, interface_id, ctxt, intf_id); 2727 if (pvid) { 2728 AMAP_SET_BITS(struct amap_set_hsw_context, pvid_valid, ctxt, 1); 2729 AMAP_SET_BITS(struct amap_set_hsw_context, pvid, ctxt, pvid); 2730 } 2731 2732 be_dws_cpu_to_le(req->context, sizeof(req->context)); 2733 status = be_mcc_notify_wait(adapter); 2734 2735 err: 2736 spin_unlock_bh(&adapter->mcc_lock); 2737 return status; 2738 } 2739 2740 /* Get Hyper switch config */ 2741 int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid, 2742 u32 domain, u16 intf_id) 2743 { 2744 struct be_mcc_wrb *wrb; 2745 struct be_cmd_req_get_hsw_config *req; 2746 void *ctxt; 2747 int status; 2748 u16 vid; 2749 2750 spin_lock_bh(&adapter->mcc_lock); 2751 2752 wrb = wrb_from_mccq(adapter); 2753 if (!wrb) { 2754 status = -EBUSY; 2755 goto err; 2756 } 2757 2758 req = embedded_payload(wrb); 2759 ctxt = &req->context; 2760 2761 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2762 OPCODE_COMMON_GET_HSW_CONFIG, sizeof(*req), wrb, NULL); 2763 2764 req->hdr.domain = domain; 2765 AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id, ctxt, 2766 intf_id); 2767 AMAP_SET_BITS(struct amap_get_hsw_req_context, pvid_valid, ctxt, 1); 2768 be_dws_cpu_to_le(req->context, sizeof(req->context)); 2769 2770 status = be_mcc_notify_wait(adapter); 2771 if (!status) { 2772 struct be_cmd_resp_get_hsw_config *resp = 2773 embedded_payload(wrb); 2774 be_dws_le_to_cpu(&resp->context, 2775 sizeof(resp->context)); 2776 vid = AMAP_GET_BITS(struct amap_get_hsw_resp_context, 2777 pvid, &resp->context); 2778 *pvid = le16_to_cpu(vid); 2779 } 2780 2781 err: 2782 spin_unlock_bh(&adapter->mcc_lock); 2783 return status; 2784 } 2785 2786 int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter) 2787 { 2788 struct be_mcc_wrb *wrb; 2789 struct be_cmd_req_acpi_wol_magic_config_v1 *req; 2790 int status; 2791 int payload_len = sizeof(*req); 2792 struct be_dma_mem cmd; 2793 2794 if (!be_cmd_allowed(adapter, OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, 2795 CMD_SUBSYSTEM_ETH)) 2796 return -EPERM; 2797 2798 memset(&cmd, 0, sizeof(struct be_dma_mem)); 2799 cmd.size = sizeof(struct be_cmd_resp_acpi_wol_magic_config_v1); 2800 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, 2801 &cmd.dma); 2802 if (!cmd.va) { 2803 dev_err(&adapter->pdev->dev, 2804 "Memory allocation failure\n"); 2805 return -ENOMEM; 2806 } 2807 2808 if (mutex_lock_interruptible(&adapter->mbox_lock)) 2809 return -1; 2810 2811 wrb = wrb_from_mbox(adapter); 2812 if (!wrb) { 2813 status = -EBUSY; 2814 goto err; 2815 } 2816 2817 req = cmd.va; 2818 2819 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, 2820 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, 2821 payload_len, wrb, &cmd); 2822 2823 req->hdr.version = 1; 2824 req->query_options = BE_GET_WOL_CAP; 2825 2826 status = be_mbox_notify_wait(adapter); 2827 if (!status) { 2828 struct be_cmd_resp_acpi_wol_magic_config_v1 *resp; 2829 resp = (struct be_cmd_resp_acpi_wol_magic_config_v1 *) cmd.va; 2830 2831 /* the command could succeed misleadingly on old f/w 2832 * which is not aware of the V1 version. fake an error. */ 2833 if (resp->hdr.response_length < payload_len) { 2834 status = -1; 2835 goto err; 2836 } 2837 adapter->wol_cap = resp->wol_settings; 2838 } 2839 err: 2840 mutex_unlock(&adapter->mbox_lock); 2841 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma); 2842 return status; 2843 2844 } 2845 int be_cmd_get_ext_fat_capabilites(struct be_adapter *adapter, 2846 struct be_dma_mem *cmd) 2847 { 2848 struct be_mcc_wrb *wrb; 2849 struct be_cmd_req_get_ext_fat_caps *req; 2850 int status; 2851 2852 if (mutex_lock_interruptible(&adapter->mbox_lock)) 2853 return -1; 2854 2855 wrb = wrb_from_mbox(adapter); 2856 if (!wrb) { 2857 status = -EBUSY; 2858 goto err; 2859 } 2860 2861 req = cmd->va; 2862 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2863 OPCODE_COMMON_GET_EXT_FAT_CAPABILITES, 2864 cmd->size, wrb, cmd); 2865 req->parameter_type = cpu_to_le32(1); 2866 2867 status = be_mbox_notify_wait(adapter); 2868 err: 2869 mutex_unlock(&adapter->mbox_lock); 2870 return status; 2871 } 2872 2873 int be_cmd_set_ext_fat_capabilites(struct be_adapter *adapter, 2874 struct be_dma_mem *cmd, 2875 struct be_fat_conf_params *configs) 2876 { 2877 struct be_mcc_wrb *wrb; 2878 struct be_cmd_req_set_ext_fat_caps *req; 2879 int status; 2880 2881 spin_lock_bh(&adapter->mcc_lock); 2882 2883 wrb = wrb_from_mccq(adapter); 2884 if (!wrb) { 2885 status = -EBUSY; 2886 goto err; 2887 } 2888 2889 req = cmd->va; 2890 memcpy(&req->set_params, configs, sizeof(struct be_fat_conf_params)); 2891 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2892 OPCODE_COMMON_SET_EXT_FAT_CAPABILITES, 2893 cmd->size, wrb, cmd); 2894 2895 status = be_mcc_notify_wait(adapter); 2896 err: 2897 spin_unlock_bh(&adapter->mcc_lock); 2898 return status; 2899 } 2900 2901 int be_cmd_query_port_name(struct be_adapter *adapter, u8 *port_name) 2902 { 2903 struct be_mcc_wrb *wrb; 2904 struct be_cmd_req_get_port_name *req; 2905 int status; 2906 2907 if (!lancer_chip(adapter)) { 2908 *port_name = adapter->hba_port_num + '0'; 2909 return 0; 2910 } 2911 2912 spin_lock_bh(&adapter->mcc_lock); 2913 2914 wrb = wrb_from_mccq(adapter); 2915 if (!wrb) { 2916 status = -EBUSY; 2917 goto err; 2918 } 2919 2920 req = embedded_payload(wrb); 2921 2922 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2923 OPCODE_COMMON_GET_PORT_NAME, sizeof(*req), wrb, 2924 NULL); 2925 req->hdr.version = 1; 2926 2927 status = be_mcc_notify_wait(adapter); 2928 if (!status) { 2929 struct be_cmd_resp_get_port_name *resp = embedded_payload(wrb); 2930 *port_name = resp->port_name[adapter->hba_port_num]; 2931 } else { 2932 *port_name = adapter->hba_port_num + '0'; 2933 } 2934 err: 2935 spin_unlock_bh(&adapter->mcc_lock); 2936 return status; 2937 } 2938 2939 static struct be_nic_resource_desc *be_get_nic_desc(u8 *buf, u32 desc_count, 2940 u32 max_buf_size) 2941 { 2942 struct be_nic_resource_desc *desc = (struct be_nic_resource_desc *)buf; 2943 int i; 2944 2945 for (i = 0; i < desc_count; i++) { 2946 desc->desc_len = RESOURCE_DESC_SIZE; 2947 if (((void *)desc + desc->desc_len) > 2948 (void *)(buf + max_buf_size)) { 2949 desc = NULL; 2950 break; 2951 } 2952 2953 if (desc->desc_type == NIC_RESOURCE_DESC_TYPE_ID) 2954 break; 2955 2956 desc = (void *)desc + desc->desc_len; 2957 } 2958 2959 if (!desc || i == MAX_RESOURCE_DESC) 2960 return NULL; 2961 2962 return desc; 2963 } 2964 2965 /* Uses Mbox */ 2966 int be_cmd_get_func_config(struct be_adapter *adapter) 2967 { 2968 struct be_mcc_wrb *wrb; 2969 struct be_cmd_req_get_func_config *req; 2970 int status; 2971 struct be_dma_mem cmd; 2972 2973 memset(&cmd, 0, sizeof(struct be_dma_mem)); 2974 cmd.size = sizeof(struct be_cmd_resp_get_func_config); 2975 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, 2976 &cmd.dma); 2977 if (!cmd.va) { 2978 dev_err(&adapter->pdev->dev, "Memory alloc failure\n"); 2979 return -ENOMEM; 2980 } 2981 if (mutex_lock_interruptible(&adapter->mbox_lock)) 2982 return -1; 2983 2984 wrb = wrb_from_mbox(adapter); 2985 if (!wrb) { 2986 status = -EBUSY; 2987 goto err; 2988 } 2989 2990 req = cmd.va; 2991 2992 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2993 OPCODE_COMMON_GET_FUNC_CONFIG, 2994 cmd.size, wrb, &cmd); 2995 2996 status = be_mbox_notify_wait(adapter); 2997 if (!status) { 2998 struct be_cmd_resp_get_func_config *resp = cmd.va; 2999 u32 desc_count = le32_to_cpu(resp->desc_count); 3000 struct be_nic_resource_desc *desc; 3001 3002 desc = be_get_nic_desc(resp->func_param, desc_count, 3003 sizeof(resp->func_param)); 3004 if (!desc) { 3005 status = -EINVAL; 3006 goto err; 3007 } 3008 3009 adapter->pf_number = desc->pf_num; 3010 adapter->max_pmac_cnt = le16_to_cpu(desc->unicast_mac_count); 3011 adapter->max_vlans = le16_to_cpu(desc->vlan_count); 3012 adapter->max_mcast_mac = le16_to_cpu(desc->mcast_mac_count); 3013 adapter->max_tx_queues = le16_to_cpu(desc->txq_count); 3014 adapter->max_rss_queues = le16_to_cpu(desc->rssq_count); 3015 adapter->max_rx_queues = le16_to_cpu(desc->rq_count); 3016 3017 adapter->max_event_queues = le16_to_cpu(desc->eq_count); 3018 adapter->if_cap_flags = le32_to_cpu(desc->cap_flags); 3019 } 3020 err: 3021 mutex_unlock(&adapter->mbox_lock); 3022 pci_free_consistent(adapter->pdev, cmd.size, 3023 cmd.va, cmd.dma); 3024 return status; 3025 } 3026 3027 /* Uses sync mcc */ 3028 int be_cmd_get_profile_config(struct be_adapter *adapter, u32 *cap_flags, 3029 u8 domain) 3030 { 3031 struct be_mcc_wrb *wrb; 3032 struct be_cmd_req_get_profile_config *req; 3033 int status; 3034 struct be_dma_mem cmd; 3035 3036 memset(&cmd, 0, sizeof(struct be_dma_mem)); 3037 cmd.size = sizeof(struct be_cmd_resp_get_profile_config); 3038 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, 3039 &cmd.dma); 3040 if (!cmd.va) { 3041 dev_err(&adapter->pdev->dev, "Memory alloc failure\n"); 3042 return -ENOMEM; 3043 } 3044 3045 spin_lock_bh(&adapter->mcc_lock); 3046 3047 wrb = wrb_from_mccq(adapter); 3048 if (!wrb) { 3049 status = -EBUSY; 3050 goto err; 3051 } 3052 3053 req = cmd.va; 3054 3055 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 3056 OPCODE_COMMON_GET_PROFILE_CONFIG, 3057 cmd.size, wrb, &cmd); 3058 3059 req->type = ACTIVE_PROFILE_TYPE; 3060 req->hdr.domain = domain; 3061 3062 status = be_mcc_notify_wait(adapter); 3063 if (!status) { 3064 struct be_cmd_resp_get_profile_config *resp = cmd.va; 3065 u32 desc_count = le32_to_cpu(resp->desc_count); 3066 struct be_nic_resource_desc *desc; 3067 3068 desc = be_get_nic_desc(resp->func_param, desc_count, 3069 sizeof(resp->func_param)); 3070 3071 if (!desc) { 3072 status = -EINVAL; 3073 goto err; 3074 } 3075 *cap_flags = le32_to_cpu(desc->cap_flags); 3076 } 3077 err: 3078 spin_unlock_bh(&adapter->mcc_lock); 3079 pci_free_consistent(adapter->pdev, cmd.size, 3080 cmd.va, cmd.dma); 3081 return status; 3082 } 3083 3084 /* Uses sync mcc */ 3085 int be_cmd_set_profile_config(struct be_adapter *adapter, u32 bps, 3086 u8 domain) 3087 { 3088 struct be_mcc_wrb *wrb; 3089 struct be_cmd_req_set_profile_config *req; 3090 int status; 3091 3092 spin_lock_bh(&adapter->mcc_lock); 3093 3094 wrb = wrb_from_mccq(adapter); 3095 if (!wrb) { 3096 status = -EBUSY; 3097 goto err; 3098 } 3099 3100 req = embedded_payload(wrb); 3101 3102 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 3103 OPCODE_COMMON_SET_PROFILE_CONFIG, sizeof(*req), 3104 wrb, NULL); 3105 3106 req->hdr.domain = domain; 3107 req->desc_count = cpu_to_le32(1); 3108 3109 req->nic_desc.desc_type = NIC_RESOURCE_DESC_TYPE_ID; 3110 req->nic_desc.desc_len = RESOURCE_DESC_SIZE; 3111 req->nic_desc.flags = (1 << QUN) | (1 << IMM) | (1 << NOSV); 3112 req->nic_desc.pf_num = adapter->pf_number; 3113 req->nic_desc.vf_num = domain; 3114 3115 /* Mark fields invalid */ 3116 req->nic_desc.unicast_mac_count = 0xFFFF; 3117 req->nic_desc.mcc_count = 0xFFFF; 3118 req->nic_desc.vlan_count = 0xFFFF; 3119 req->nic_desc.mcast_mac_count = 0xFFFF; 3120 req->nic_desc.txq_count = 0xFFFF; 3121 req->nic_desc.rq_count = 0xFFFF; 3122 req->nic_desc.rssq_count = 0xFFFF; 3123 req->nic_desc.lro_count = 0xFFFF; 3124 req->nic_desc.cq_count = 0xFFFF; 3125 req->nic_desc.toe_conn_count = 0xFFFF; 3126 req->nic_desc.eq_count = 0xFFFF; 3127 req->nic_desc.link_param = 0xFF; 3128 req->nic_desc.bw_min = 0xFFFFFFFF; 3129 req->nic_desc.acpi_params = 0xFF; 3130 req->nic_desc.wol_param = 0x0F; 3131 3132 /* Change BW */ 3133 req->nic_desc.bw_min = cpu_to_le32(bps); 3134 req->nic_desc.bw_max = cpu_to_le32(bps); 3135 status = be_mcc_notify_wait(adapter); 3136 err: 3137 spin_unlock_bh(&adapter->mcc_lock); 3138 return status; 3139 } 3140 3141 /* Uses sync mcc */ 3142 int be_cmd_enable_vf(struct be_adapter *adapter, u8 domain) 3143 { 3144 struct be_mcc_wrb *wrb; 3145 struct be_cmd_enable_disable_vf *req; 3146 int status; 3147 3148 if (!lancer_chip(adapter)) 3149 return 0; 3150 3151 spin_lock_bh(&adapter->mcc_lock); 3152 3153 wrb = wrb_from_mccq(adapter); 3154 if (!wrb) { 3155 status = -EBUSY; 3156 goto err; 3157 } 3158 3159 req = embedded_payload(wrb); 3160 3161 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 3162 OPCODE_COMMON_ENABLE_DISABLE_VF, sizeof(*req), 3163 wrb, NULL); 3164 3165 req->hdr.domain = domain; 3166 req->enable = 1; 3167 status = be_mcc_notify_wait(adapter); 3168 err: 3169 spin_unlock_bh(&adapter->mcc_lock); 3170 return status; 3171 } 3172 3173 int be_roce_mcc_cmd(void *netdev_handle, void *wrb_payload, 3174 int wrb_payload_size, u16 *cmd_status, u16 *ext_status) 3175 { 3176 struct be_adapter *adapter = netdev_priv(netdev_handle); 3177 struct be_mcc_wrb *wrb; 3178 struct be_cmd_req_hdr *hdr = (struct be_cmd_req_hdr *) wrb_payload; 3179 struct be_cmd_req_hdr *req; 3180 struct be_cmd_resp_hdr *resp; 3181 int status; 3182 3183 spin_lock_bh(&adapter->mcc_lock); 3184 3185 wrb = wrb_from_mccq(adapter); 3186 if (!wrb) { 3187 status = -EBUSY; 3188 goto err; 3189 } 3190 req = embedded_payload(wrb); 3191 resp = embedded_payload(wrb); 3192 3193 be_wrb_cmd_hdr_prepare(req, hdr->subsystem, 3194 hdr->opcode, wrb_payload_size, wrb, NULL); 3195 memcpy(req, wrb_payload, wrb_payload_size); 3196 be_dws_cpu_to_le(req, wrb_payload_size); 3197 3198 status = be_mcc_notify_wait(adapter); 3199 if (cmd_status) 3200 *cmd_status = (status & 0xffff); 3201 if (ext_status) 3202 *ext_status = 0; 3203 memcpy(wrb_payload, resp, sizeof(*resp) + resp->response_length); 3204 be_dws_le_to_cpu(wrb_payload, sizeof(*resp) + resp->response_length); 3205 err: 3206 spin_unlock_bh(&adapter->mcc_lock); 3207 return status; 3208 } 3209 EXPORT_SYMBOL(be_roce_mcc_cmd); 3210