1 /* 2 * Copyright (C) 2005 - 2013 Emulex 3 * All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License version 2 7 * as published by the Free Software Foundation. The full GNU General 8 * Public License is included in this distribution in the file called COPYING. 9 * 10 * Contact Information: 11 * linux-drivers@emulex.com 12 * 13 * Emulex 14 * 3333 Susan Street 15 * Costa Mesa, CA 92626 16 */ 17 18 #include <linux/module.h> 19 #include "be.h" 20 #include "be_cmds.h" 21 22 static struct be_cmd_priv_map cmd_priv_map[] = { 23 { 24 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, 25 CMD_SUBSYSTEM_ETH, 26 BE_PRIV_LNKMGMT | BE_PRIV_VHADM | 27 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC 28 }, 29 { 30 OPCODE_COMMON_GET_FLOW_CONTROL, 31 CMD_SUBSYSTEM_COMMON, 32 BE_PRIV_LNKQUERY | BE_PRIV_VHADM | 33 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC 34 }, 35 { 36 OPCODE_COMMON_SET_FLOW_CONTROL, 37 CMD_SUBSYSTEM_COMMON, 38 BE_PRIV_LNKMGMT | BE_PRIV_VHADM | 39 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC 40 }, 41 { 42 OPCODE_ETH_GET_PPORT_STATS, 43 CMD_SUBSYSTEM_ETH, 44 BE_PRIV_LNKMGMT | BE_PRIV_VHADM | 45 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC 46 }, 47 { 48 OPCODE_COMMON_GET_PHY_DETAILS, 49 CMD_SUBSYSTEM_COMMON, 50 BE_PRIV_LNKMGMT | BE_PRIV_VHADM | 51 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC 52 } 53 }; 54 55 static bool be_cmd_allowed(struct be_adapter *adapter, u8 opcode, 56 u8 subsystem) 57 { 58 int i; 59 int num_entries = sizeof(cmd_priv_map)/sizeof(struct be_cmd_priv_map); 60 u32 cmd_privileges = adapter->cmd_privileges; 61 62 for (i = 0; i < num_entries; i++) 63 if (opcode == cmd_priv_map[i].opcode && 64 subsystem == cmd_priv_map[i].subsystem) 65 if (!(cmd_privileges & cmd_priv_map[i].priv_mask)) 66 return false; 67 68 return true; 69 } 70 71 static inline void *embedded_payload(struct be_mcc_wrb *wrb) 72 { 73 return wrb->payload.embedded_payload; 74 } 75 76 static void be_mcc_notify(struct be_adapter *adapter) 77 { 78 struct be_queue_info *mccq = &adapter->mcc_obj.q; 79 u32 val = 0; 80 81 if (be_error(adapter)) 82 return; 83 84 val |= mccq->id & DB_MCCQ_RING_ID_MASK; 85 val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT; 86 87 wmb(); 88 iowrite32(val, adapter->db + DB_MCCQ_OFFSET); 89 } 90 91 /* To check if valid bit is set, check the entire word as we don't know 92 * the endianness of the data (old entry is host endian while a new entry is 93 * little endian) */ 94 static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl) 95 { 96 u32 flags; 97 98 if (compl->flags != 0) { 99 flags = le32_to_cpu(compl->flags); 100 if (flags & CQE_FLAGS_VALID_MASK) { 101 compl->flags = flags; 102 return true; 103 } 104 } 105 return false; 106 } 107 108 /* Need to reset the entire word that houses the valid bit */ 109 static inline void be_mcc_compl_use(struct be_mcc_compl *compl) 110 { 111 compl->flags = 0; 112 } 113 114 static struct be_cmd_resp_hdr *be_decode_resp_hdr(u32 tag0, u32 tag1) 115 { 116 unsigned long addr; 117 118 addr = tag1; 119 addr = ((addr << 16) << 16) | tag0; 120 return (void *)addr; 121 } 122 123 static int be_mcc_compl_process(struct be_adapter *adapter, 124 struct be_mcc_compl *compl) 125 { 126 u16 compl_status, extd_status; 127 struct be_cmd_resp_hdr *resp_hdr; 128 u8 opcode = 0, subsystem = 0; 129 130 /* Just swap the status to host endian; mcc tag is opaquely copied 131 * from mcc_wrb */ 132 be_dws_le_to_cpu(compl, 4); 133 134 compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) & 135 CQE_STATUS_COMPL_MASK; 136 137 resp_hdr = be_decode_resp_hdr(compl->tag0, compl->tag1); 138 139 if (resp_hdr) { 140 opcode = resp_hdr->opcode; 141 subsystem = resp_hdr->subsystem; 142 } 143 144 if (((opcode == OPCODE_COMMON_WRITE_FLASHROM) || 145 (opcode == OPCODE_COMMON_WRITE_OBJECT)) && 146 (subsystem == CMD_SUBSYSTEM_COMMON)) { 147 adapter->flash_status = compl_status; 148 complete(&adapter->flash_compl); 149 } 150 151 if (compl_status == MCC_STATUS_SUCCESS) { 152 if (((opcode == OPCODE_ETH_GET_STATISTICS) || 153 (opcode == OPCODE_ETH_GET_PPORT_STATS)) && 154 (subsystem == CMD_SUBSYSTEM_ETH)) { 155 be_parse_stats(adapter); 156 adapter->stats_cmd_sent = false; 157 } 158 if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES && 159 subsystem == CMD_SUBSYSTEM_COMMON) { 160 struct be_cmd_resp_get_cntl_addnl_attribs *resp = 161 (void *)resp_hdr; 162 adapter->drv_stats.be_on_die_temperature = 163 resp->on_die_temperature; 164 } 165 } else { 166 if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES) 167 adapter->be_get_temp_freq = 0; 168 169 if (compl_status == MCC_STATUS_NOT_SUPPORTED || 170 compl_status == MCC_STATUS_ILLEGAL_REQUEST) 171 goto done; 172 173 if (compl_status == MCC_STATUS_UNAUTHORIZED_REQUEST) { 174 dev_warn(&adapter->pdev->dev, 175 "VF is not privileged to issue opcode %d-%d\n", 176 opcode, subsystem); 177 } else { 178 extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) & 179 CQE_STATUS_EXTD_MASK; 180 dev_err(&adapter->pdev->dev, 181 "opcode %d-%d failed:status %d-%d\n", 182 opcode, subsystem, compl_status, extd_status); 183 184 if (extd_status == MCC_ADDL_STS_INSUFFICIENT_RESOURCES) 185 return extd_status; 186 } 187 } 188 done: 189 return compl_status; 190 } 191 192 /* Link state evt is a string of bytes; no need for endian swapping */ 193 static void be_async_link_state_process(struct be_adapter *adapter, 194 struct be_async_event_link_state *evt) 195 { 196 /* When link status changes, link speed must be re-queried from FW */ 197 adapter->phy.link_speed = -1; 198 199 /* Ignore physical link event */ 200 if (lancer_chip(adapter) && 201 !(evt->port_link_status & LOGICAL_LINK_STATUS_MASK)) 202 return; 203 204 /* For the initial link status do not rely on the ASYNC event as 205 * it may not be received in some cases. 206 */ 207 if (adapter->flags & BE_FLAGS_LINK_STATUS_INIT) 208 be_link_status_update(adapter, evt->port_link_status); 209 } 210 211 /* Grp5 CoS Priority evt */ 212 static void be_async_grp5_cos_priority_process(struct be_adapter *adapter, 213 struct be_async_event_grp5_cos_priority *evt) 214 { 215 if (evt->valid) { 216 adapter->vlan_prio_bmap = evt->available_priority_bmap; 217 adapter->recommended_prio &= ~VLAN_PRIO_MASK; 218 adapter->recommended_prio = 219 evt->reco_default_priority << VLAN_PRIO_SHIFT; 220 } 221 } 222 223 /* Grp5 QOS Speed evt: qos_link_speed is in units of 10 Mbps */ 224 static void be_async_grp5_qos_speed_process(struct be_adapter *adapter, 225 struct be_async_event_grp5_qos_link_speed *evt) 226 { 227 if (adapter->phy.link_speed >= 0 && 228 evt->physical_port == adapter->port_num) 229 adapter->phy.link_speed = le16_to_cpu(evt->qos_link_speed) * 10; 230 } 231 232 /*Grp5 PVID evt*/ 233 static void be_async_grp5_pvid_state_process(struct be_adapter *adapter, 234 struct be_async_event_grp5_pvid_state *evt) 235 { 236 if (evt->enabled) 237 adapter->pvid = le16_to_cpu(evt->tag) & VLAN_VID_MASK; 238 else 239 adapter->pvid = 0; 240 } 241 242 static void be_async_grp5_evt_process(struct be_adapter *adapter, 243 u32 trailer, struct be_mcc_compl *evt) 244 { 245 u8 event_type = 0; 246 247 event_type = (trailer >> ASYNC_TRAILER_EVENT_TYPE_SHIFT) & 248 ASYNC_TRAILER_EVENT_TYPE_MASK; 249 250 switch (event_type) { 251 case ASYNC_EVENT_COS_PRIORITY: 252 be_async_grp5_cos_priority_process(adapter, 253 (struct be_async_event_grp5_cos_priority *)evt); 254 break; 255 case ASYNC_EVENT_QOS_SPEED: 256 be_async_grp5_qos_speed_process(adapter, 257 (struct be_async_event_grp5_qos_link_speed *)evt); 258 break; 259 case ASYNC_EVENT_PVID_STATE: 260 be_async_grp5_pvid_state_process(adapter, 261 (struct be_async_event_grp5_pvid_state *)evt); 262 break; 263 default: 264 dev_warn(&adapter->pdev->dev, "Unknown grp5 event 0x%x!\n", 265 event_type); 266 break; 267 } 268 } 269 270 static void be_async_dbg_evt_process(struct be_adapter *adapter, 271 u32 trailer, struct be_mcc_compl *cmp) 272 { 273 u8 event_type = 0; 274 struct be_async_event_qnq *evt = (struct be_async_event_qnq *) cmp; 275 276 event_type = (trailer >> ASYNC_TRAILER_EVENT_TYPE_SHIFT) & 277 ASYNC_TRAILER_EVENT_TYPE_MASK; 278 279 switch (event_type) { 280 case ASYNC_DEBUG_EVENT_TYPE_QNQ: 281 if (evt->valid) 282 adapter->qnq_vid = le16_to_cpu(evt->vlan_tag); 283 adapter->flags |= BE_FLAGS_QNQ_ASYNC_EVT_RCVD; 284 break; 285 default: 286 dev_warn(&adapter->pdev->dev, "Unknown debug event 0x%x!\n", 287 event_type); 288 break; 289 } 290 } 291 292 static inline bool is_link_state_evt(u32 trailer) 293 { 294 return ((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) & 295 ASYNC_TRAILER_EVENT_CODE_MASK) == 296 ASYNC_EVENT_CODE_LINK_STATE; 297 } 298 299 static inline bool is_grp5_evt(u32 trailer) 300 { 301 return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) & 302 ASYNC_TRAILER_EVENT_CODE_MASK) == 303 ASYNC_EVENT_CODE_GRP_5); 304 } 305 306 static inline bool is_dbg_evt(u32 trailer) 307 { 308 return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) & 309 ASYNC_TRAILER_EVENT_CODE_MASK) == 310 ASYNC_EVENT_CODE_QNQ); 311 } 312 313 static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter) 314 { 315 struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq; 316 struct be_mcc_compl *compl = queue_tail_node(mcc_cq); 317 318 if (be_mcc_compl_is_new(compl)) { 319 queue_tail_inc(mcc_cq); 320 return compl; 321 } 322 return NULL; 323 } 324 325 void be_async_mcc_enable(struct be_adapter *adapter) 326 { 327 spin_lock_bh(&adapter->mcc_cq_lock); 328 329 be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0); 330 adapter->mcc_obj.rearm_cq = true; 331 332 spin_unlock_bh(&adapter->mcc_cq_lock); 333 } 334 335 void be_async_mcc_disable(struct be_adapter *adapter) 336 { 337 spin_lock_bh(&adapter->mcc_cq_lock); 338 339 adapter->mcc_obj.rearm_cq = false; 340 be_cq_notify(adapter, adapter->mcc_obj.cq.id, false, 0); 341 342 spin_unlock_bh(&adapter->mcc_cq_lock); 343 } 344 345 int be_process_mcc(struct be_adapter *adapter) 346 { 347 struct be_mcc_compl *compl; 348 int num = 0, status = 0; 349 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj; 350 351 spin_lock(&adapter->mcc_cq_lock); 352 while ((compl = be_mcc_compl_get(adapter))) { 353 if (compl->flags & CQE_FLAGS_ASYNC_MASK) { 354 /* Interpret flags as an async trailer */ 355 if (is_link_state_evt(compl->flags)) 356 be_async_link_state_process(adapter, 357 (struct be_async_event_link_state *) compl); 358 else if (is_grp5_evt(compl->flags)) 359 be_async_grp5_evt_process(adapter, 360 compl->flags, compl); 361 else if (is_dbg_evt(compl->flags)) 362 be_async_dbg_evt_process(adapter, 363 compl->flags, compl); 364 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) { 365 status = be_mcc_compl_process(adapter, compl); 366 atomic_dec(&mcc_obj->q.used); 367 } 368 be_mcc_compl_use(compl); 369 num++; 370 } 371 372 if (num) 373 be_cq_notify(adapter, mcc_obj->cq.id, mcc_obj->rearm_cq, num); 374 375 spin_unlock(&adapter->mcc_cq_lock); 376 return status; 377 } 378 379 /* Wait till no more pending mcc requests are present */ 380 static int be_mcc_wait_compl(struct be_adapter *adapter) 381 { 382 #define mcc_timeout 120000 /* 12s timeout */ 383 int i, status = 0; 384 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj; 385 386 for (i = 0; i < mcc_timeout; i++) { 387 if (be_error(adapter)) 388 return -EIO; 389 390 local_bh_disable(); 391 status = be_process_mcc(adapter); 392 local_bh_enable(); 393 394 if (atomic_read(&mcc_obj->q.used) == 0) 395 break; 396 udelay(100); 397 } 398 if (i == mcc_timeout) { 399 dev_err(&adapter->pdev->dev, "FW not responding\n"); 400 adapter->fw_timeout = true; 401 return -EIO; 402 } 403 return status; 404 } 405 406 /* Notify MCC requests and wait for completion */ 407 static int be_mcc_notify_wait(struct be_adapter *adapter) 408 { 409 int status; 410 struct be_mcc_wrb *wrb; 411 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj; 412 u16 index = mcc_obj->q.head; 413 struct be_cmd_resp_hdr *resp; 414 415 index_dec(&index, mcc_obj->q.len); 416 wrb = queue_index_node(&mcc_obj->q, index); 417 418 resp = be_decode_resp_hdr(wrb->tag0, wrb->tag1); 419 420 be_mcc_notify(adapter); 421 422 status = be_mcc_wait_compl(adapter); 423 if (status == -EIO) 424 goto out; 425 426 status = resp->status; 427 out: 428 return status; 429 } 430 431 static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db) 432 { 433 int msecs = 0; 434 u32 ready; 435 436 do { 437 if (be_error(adapter)) 438 return -EIO; 439 440 ready = ioread32(db); 441 if (ready == 0xffffffff) 442 return -1; 443 444 ready &= MPU_MAILBOX_DB_RDY_MASK; 445 if (ready) 446 break; 447 448 if (msecs > 4000) { 449 dev_err(&adapter->pdev->dev, "FW not responding\n"); 450 adapter->fw_timeout = true; 451 be_detect_error(adapter); 452 return -1; 453 } 454 455 msleep(1); 456 msecs++; 457 } while (true); 458 459 return 0; 460 } 461 462 /* 463 * Insert the mailbox address into the doorbell in two steps 464 * Polls on the mbox doorbell till a command completion (or a timeout) occurs 465 */ 466 static int be_mbox_notify_wait(struct be_adapter *adapter) 467 { 468 int status; 469 u32 val = 0; 470 void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET; 471 struct be_dma_mem *mbox_mem = &adapter->mbox_mem; 472 struct be_mcc_mailbox *mbox = mbox_mem->va; 473 struct be_mcc_compl *compl = &mbox->compl; 474 475 /* wait for ready to be set */ 476 status = be_mbox_db_ready_wait(adapter, db); 477 if (status != 0) 478 return status; 479 480 val |= MPU_MAILBOX_DB_HI_MASK; 481 /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */ 482 val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2; 483 iowrite32(val, db); 484 485 /* wait for ready to be set */ 486 status = be_mbox_db_ready_wait(adapter, db); 487 if (status != 0) 488 return status; 489 490 val = 0; 491 /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */ 492 val |= (u32)(mbox_mem->dma >> 4) << 2; 493 iowrite32(val, db); 494 495 status = be_mbox_db_ready_wait(adapter, db); 496 if (status != 0) 497 return status; 498 499 /* A cq entry has been made now */ 500 if (be_mcc_compl_is_new(compl)) { 501 status = be_mcc_compl_process(adapter, &mbox->compl); 502 be_mcc_compl_use(compl); 503 if (status) 504 return status; 505 } else { 506 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n"); 507 return -1; 508 } 509 return 0; 510 } 511 512 static u16 be_POST_stage_get(struct be_adapter *adapter) 513 { 514 u32 sem; 515 516 if (BEx_chip(adapter)) 517 sem = ioread32(adapter->csr + SLIPORT_SEMAPHORE_OFFSET_BEx); 518 else 519 pci_read_config_dword(adapter->pdev, 520 SLIPORT_SEMAPHORE_OFFSET_SH, &sem); 521 522 return sem & POST_STAGE_MASK; 523 } 524 525 static int lancer_wait_ready(struct be_adapter *adapter) 526 { 527 #define SLIPORT_READY_TIMEOUT 30 528 u32 sliport_status; 529 int status = 0, i; 530 531 for (i = 0; i < SLIPORT_READY_TIMEOUT; i++) { 532 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET); 533 if (sliport_status & SLIPORT_STATUS_RDY_MASK) 534 break; 535 536 msleep(1000); 537 } 538 539 if (i == SLIPORT_READY_TIMEOUT) 540 status = -1; 541 542 return status; 543 } 544 545 static bool lancer_provisioning_error(struct be_adapter *adapter) 546 { 547 u32 sliport_status = 0, sliport_err1 = 0, sliport_err2 = 0; 548 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET); 549 if (sliport_status & SLIPORT_STATUS_ERR_MASK) { 550 sliport_err1 = ioread32(adapter->db + 551 SLIPORT_ERROR1_OFFSET); 552 sliport_err2 = ioread32(adapter->db + 553 SLIPORT_ERROR2_OFFSET); 554 555 if (sliport_err1 == SLIPORT_ERROR_NO_RESOURCE1 && 556 sliport_err2 == SLIPORT_ERROR_NO_RESOURCE2) 557 return true; 558 } 559 return false; 560 } 561 562 int lancer_test_and_set_rdy_state(struct be_adapter *adapter) 563 { 564 int status; 565 u32 sliport_status, err, reset_needed; 566 bool resource_error; 567 568 resource_error = lancer_provisioning_error(adapter); 569 if (resource_error) 570 return -EAGAIN; 571 572 status = lancer_wait_ready(adapter); 573 if (!status) { 574 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET); 575 err = sliport_status & SLIPORT_STATUS_ERR_MASK; 576 reset_needed = sliport_status & SLIPORT_STATUS_RN_MASK; 577 if (err && reset_needed) { 578 iowrite32(SLI_PORT_CONTROL_IP_MASK, 579 adapter->db + SLIPORT_CONTROL_OFFSET); 580 581 /* check adapter has corrected the error */ 582 status = lancer_wait_ready(adapter); 583 sliport_status = ioread32(adapter->db + 584 SLIPORT_STATUS_OFFSET); 585 sliport_status &= (SLIPORT_STATUS_ERR_MASK | 586 SLIPORT_STATUS_RN_MASK); 587 if (status || sliport_status) 588 status = -1; 589 } else if (err || reset_needed) { 590 status = -1; 591 } 592 } 593 /* Stop error recovery if error is not recoverable. 594 * No resource error is temporary errors and will go away 595 * when PF provisions resources. 596 */ 597 resource_error = lancer_provisioning_error(adapter); 598 if (resource_error) 599 status = -EAGAIN; 600 601 return status; 602 } 603 604 int be_fw_wait_ready(struct be_adapter *adapter) 605 { 606 u16 stage; 607 int status, timeout = 0; 608 struct device *dev = &adapter->pdev->dev; 609 610 if (lancer_chip(adapter)) { 611 status = lancer_wait_ready(adapter); 612 return status; 613 } 614 615 do { 616 stage = be_POST_stage_get(adapter); 617 if (stage == POST_STAGE_ARMFW_RDY) 618 return 0; 619 620 dev_info(dev, "Waiting for POST, %ds elapsed\n", 621 timeout); 622 if (msleep_interruptible(2000)) { 623 dev_err(dev, "Waiting for POST aborted\n"); 624 return -EINTR; 625 } 626 timeout += 2; 627 } while (timeout < 60); 628 629 dev_err(dev, "POST timeout; stage=0x%x\n", stage); 630 return -1; 631 } 632 633 634 static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb) 635 { 636 return &wrb->payload.sgl[0]; 637 } 638 639 static inline void fill_wrb_tags(struct be_mcc_wrb *wrb, 640 unsigned long addr) 641 { 642 wrb->tag0 = addr & 0xFFFFFFFF; 643 wrb->tag1 = upper_32_bits(addr); 644 } 645 646 /* Don't touch the hdr after it's prepared */ 647 /* mem will be NULL for embedded commands */ 648 static void be_wrb_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr, 649 u8 subsystem, u8 opcode, int cmd_len, 650 struct be_mcc_wrb *wrb, struct be_dma_mem *mem) 651 { 652 struct be_sge *sge; 653 654 req_hdr->opcode = opcode; 655 req_hdr->subsystem = subsystem; 656 req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr)); 657 req_hdr->version = 0; 658 fill_wrb_tags(wrb, (ulong) req_hdr); 659 wrb->payload_length = cmd_len; 660 if (mem) { 661 wrb->embedded |= (1 & MCC_WRB_SGE_CNT_MASK) << 662 MCC_WRB_SGE_CNT_SHIFT; 663 sge = nonembedded_sgl(wrb); 664 sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma)); 665 sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF); 666 sge->len = cpu_to_le32(mem->size); 667 } else 668 wrb->embedded |= MCC_WRB_EMBEDDED_MASK; 669 be_dws_cpu_to_le(wrb, 8); 670 } 671 672 static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages, 673 struct be_dma_mem *mem) 674 { 675 int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages); 676 u64 dma = (u64)mem->dma; 677 678 for (i = 0; i < buf_pages; i++) { 679 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF); 680 pages[i].hi = cpu_to_le32(upper_32_bits(dma)); 681 dma += PAGE_SIZE_4K; 682 } 683 } 684 685 static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter) 686 { 687 struct be_dma_mem *mbox_mem = &adapter->mbox_mem; 688 struct be_mcc_wrb *wrb 689 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb; 690 memset(wrb, 0, sizeof(*wrb)); 691 return wrb; 692 } 693 694 static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter) 695 { 696 struct be_queue_info *mccq = &adapter->mcc_obj.q; 697 struct be_mcc_wrb *wrb; 698 699 if (!mccq->created) 700 return NULL; 701 702 if (atomic_read(&mccq->used) >= mccq->len) 703 return NULL; 704 705 wrb = queue_head_node(mccq); 706 queue_head_inc(mccq); 707 atomic_inc(&mccq->used); 708 memset(wrb, 0, sizeof(*wrb)); 709 return wrb; 710 } 711 712 static bool use_mcc(struct be_adapter *adapter) 713 { 714 return adapter->mcc_obj.q.created; 715 } 716 717 /* Must be used only in process context */ 718 static int be_cmd_lock(struct be_adapter *adapter) 719 { 720 if (use_mcc(adapter)) { 721 spin_lock_bh(&adapter->mcc_lock); 722 return 0; 723 } else { 724 return mutex_lock_interruptible(&adapter->mbox_lock); 725 } 726 } 727 728 /* Must be used only in process context */ 729 static void be_cmd_unlock(struct be_adapter *adapter) 730 { 731 if (use_mcc(adapter)) 732 spin_unlock_bh(&adapter->mcc_lock); 733 else 734 return mutex_unlock(&adapter->mbox_lock); 735 } 736 737 static struct be_mcc_wrb *be_cmd_copy(struct be_adapter *adapter, 738 struct be_mcc_wrb *wrb) 739 { 740 struct be_mcc_wrb *dest_wrb; 741 742 if (use_mcc(adapter)) { 743 dest_wrb = wrb_from_mccq(adapter); 744 if (!dest_wrb) 745 return NULL; 746 } else { 747 dest_wrb = wrb_from_mbox(adapter); 748 } 749 750 memcpy(dest_wrb, wrb, sizeof(*wrb)); 751 if (wrb->embedded & cpu_to_le32(MCC_WRB_EMBEDDED_MASK)) 752 fill_wrb_tags(dest_wrb, (ulong) embedded_payload(wrb)); 753 754 return dest_wrb; 755 } 756 757 /* Must be used only in process context */ 758 static int be_cmd_notify_wait(struct be_adapter *adapter, 759 struct be_mcc_wrb *wrb) 760 { 761 struct be_mcc_wrb *dest_wrb; 762 int status; 763 764 status = be_cmd_lock(adapter); 765 if (status) 766 return status; 767 768 dest_wrb = be_cmd_copy(adapter, wrb); 769 if (!dest_wrb) 770 return -EBUSY; 771 772 if (use_mcc(adapter)) 773 status = be_mcc_notify_wait(adapter); 774 else 775 status = be_mbox_notify_wait(adapter); 776 777 if (!status) 778 memcpy(wrb, dest_wrb, sizeof(*wrb)); 779 780 be_cmd_unlock(adapter); 781 return status; 782 } 783 784 /* Tell fw we're about to start firing cmds by writing a 785 * special pattern across the wrb hdr; uses mbox 786 */ 787 int be_cmd_fw_init(struct be_adapter *adapter) 788 { 789 u8 *wrb; 790 int status; 791 792 if (lancer_chip(adapter)) 793 return 0; 794 795 if (mutex_lock_interruptible(&adapter->mbox_lock)) 796 return -1; 797 798 wrb = (u8 *)wrb_from_mbox(adapter); 799 *wrb++ = 0xFF; 800 *wrb++ = 0x12; 801 *wrb++ = 0x34; 802 *wrb++ = 0xFF; 803 *wrb++ = 0xFF; 804 *wrb++ = 0x56; 805 *wrb++ = 0x78; 806 *wrb = 0xFF; 807 808 status = be_mbox_notify_wait(adapter); 809 810 mutex_unlock(&adapter->mbox_lock); 811 return status; 812 } 813 814 /* Tell fw we're done with firing cmds by writing a 815 * special pattern across the wrb hdr; uses mbox 816 */ 817 int be_cmd_fw_clean(struct be_adapter *adapter) 818 { 819 u8 *wrb; 820 int status; 821 822 if (lancer_chip(adapter)) 823 return 0; 824 825 if (mutex_lock_interruptible(&adapter->mbox_lock)) 826 return -1; 827 828 wrb = (u8 *)wrb_from_mbox(adapter); 829 *wrb++ = 0xFF; 830 *wrb++ = 0xAA; 831 *wrb++ = 0xBB; 832 *wrb++ = 0xFF; 833 *wrb++ = 0xFF; 834 *wrb++ = 0xCC; 835 *wrb++ = 0xDD; 836 *wrb = 0xFF; 837 838 status = be_mbox_notify_wait(adapter); 839 840 mutex_unlock(&adapter->mbox_lock); 841 return status; 842 } 843 844 int be_cmd_eq_create(struct be_adapter *adapter, struct be_eq_obj *eqo) 845 { 846 struct be_mcc_wrb *wrb; 847 struct be_cmd_req_eq_create *req; 848 struct be_dma_mem *q_mem = &eqo->q.dma_mem; 849 int status, ver = 0; 850 851 if (mutex_lock_interruptible(&adapter->mbox_lock)) 852 return -1; 853 854 wrb = wrb_from_mbox(adapter); 855 req = embedded_payload(wrb); 856 857 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 858 OPCODE_COMMON_EQ_CREATE, sizeof(*req), wrb, NULL); 859 860 /* Support for EQ_CREATEv2 available only SH-R onwards */ 861 if (!(BEx_chip(adapter) || lancer_chip(adapter))) 862 ver = 2; 863 864 req->hdr.version = ver; 865 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size)); 866 867 AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1); 868 /* 4byte eqe*/ 869 AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0); 870 AMAP_SET_BITS(struct amap_eq_context, count, req->context, 871 __ilog2_u32(eqo->q.len / 256)); 872 be_dws_cpu_to_le(req->context, sizeof(req->context)); 873 874 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); 875 876 status = be_mbox_notify_wait(adapter); 877 if (!status) { 878 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb); 879 eqo->q.id = le16_to_cpu(resp->eq_id); 880 eqo->msix_idx = 881 (ver == 2) ? le16_to_cpu(resp->msix_idx) : eqo->idx; 882 eqo->q.created = true; 883 } 884 885 mutex_unlock(&adapter->mbox_lock); 886 return status; 887 } 888 889 /* Use MCC */ 890 int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr, 891 bool permanent, u32 if_handle, u32 pmac_id) 892 { 893 struct be_mcc_wrb *wrb; 894 struct be_cmd_req_mac_query *req; 895 int status; 896 897 spin_lock_bh(&adapter->mcc_lock); 898 899 wrb = wrb_from_mccq(adapter); 900 if (!wrb) { 901 status = -EBUSY; 902 goto err; 903 } 904 req = embedded_payload(wrb); 905 906 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 907 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req), wrb, NULL); 908 req->type = MAC_ADDRESS_TYPE_NETWORK; 909 if (permanent) { 910 req->permanent = 1; 911 } else { 912 req->if_id = cpu_to_le16((u16) if_handle); 913 req->pmac_id = cpu_to_le32(pmac_id); 914 req->permanent = 0; 915 } 916 917 status = be_mcc_notify_wait(adapter); 918 if (!status) { 919 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb); 920 memcpy(mac_addr, resp->mac.addr, ETH_ALEN); 921 } 922 923 err: 924 spin_unlock_bh(&adapter->mcc_lock); 925 return status; 926 } 927 928 /* Uses synchronous MCCQ */ 929 int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr, 930 u32 if_id, u32 *pmac_id, u32 domain) 931 { 932 struct be_mcc_wrb *wrb; 933 struct be_cmd_req_pmac_add *req; 934 int status; 935 936 spin_lock_bh(&adapter->mcc_lock); 937 938 wrb = wrb_from_mccq(adapter); 939 if (!wrb) { 940 status = -EBUSY; 941 goto err; 942 } 943 req = embedded_payload(wrb); 944 945 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 946 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req), wrb, NULL); 947 948 req->hdr.domain = domain; 949 req->if_id = cpu_to_le32(if_id); 950 memcpy(req->mac_address, mac_addr, ETH_ALEN); 951 952 status = be_mcc_notify_wait(adapter); 953 if (!status) { 954 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb); 955 *pmac_id = le32_to_cpu(resp->pmac_id); 956 } 957 958 err: 959 spin_unlock_bh(&adapter->mcc_lock); 960 961 if (status == MCC_STATUS_UNAUTHORIZED_REQUEST) 962 status = -EPERM; 963 964 return status; 965 } 966 967 /* Uses synchronous MCCQ */ 968 int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, int pmac_id, u32 dom) 969 { 970 struct be_mcc_wrb *wrb; 971 struct be_cmd_req_pmac_del *req; 972 int status; 973 974 if (pmac_id == -1) 975 return 0; 976 977 spin_lock_bh(&adapter->mcc_lock); 978 979 wrb = wrb_from_mccq(adapter); 980 if (!wrb) { 981 status = -EBUSY; 982 goto err; 983 } 984 req = embedded_payload(wrb); 985 986 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 987 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req), wrb, NULL); 988 989 req->hdr.domain = dom; 990 req->if_id = cpu_to_le32(if_id); 991 req->pmac_id = cpu_to_le32(pmac_id); 992 993 status = be_mcc_notify_wait(adapter); 994 995 err: 996 spin_unlock_bh(&adapter->mcc_lock); 997 return status; 998 } 999 1000 /* Uses Mbox */ 1001 int be_cmd_cq_create(struct be_adapter *adapter, struct be_queue_info *cq, 1002 struct be_queue_info *eq, bool no_delay, int coalesce_wm) 1003 { 1004 struct be_mcc_wrb *wrb; 1005 struct be_cmd_req_cq_create *req; 1006 struct be_dma_mem *q_mem = &cq->dma_mem; 1007 void *ctxt; 1008 int status; 1009 1010 if (mutex_lock_interruptible(&adapter->mbox_lock)) 1011 return -1; 1012 1013 wrb = wrb_from_mbox(adapter); 1014 req = embedded_payload(wrb); 1015 ctxt = &req->context; 1016 1017 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1018 OPCODE_COMMON_CQ_CREATE, sizeof(*req), wrb, NULL); 1019 1020 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size)); 1021 1022 if (BEx_chip(adapter)) { 1023 AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt, 1024 coalesce_wm); 1025 AMAP_SET_BITS(struct amap_cq_context_be, nodelay, 1026 ctxt, no_delay); 1027 AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt, 1028 __ilog2_u32(cq->len/256)); 1029 AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1); 1030 AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1); 1031 AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id); 1032 } else { 1033 req->hdr.version = 2; 1034 req->page_size = 1; /* 1 for 4K */ 1035 1036 /* coalesce-wm field in this cmd is not relevant to Lancer. 1037 * Lancer uses COMMON_MODIFY_CQ to set this field 1038 */ 1039 if (!lancer_chip(adapter)) 1040 AMAP_SET_BITS(struct amap_cq_context_v2, coalescwm, 1041 ctxt, coalesce_wm); 1042 AMAP_SET_BITS(struct amap_cq_context_v2, nodelay, ctxt, 1043 no_delay); 1044 AMAP_SET_BITS(struct amap_cq_context_v2, count, ctxt, 1045 __ilog2_u32(cq->len/256)); 1046 AMAP_SET_BITS(struct amap_cq_context_v2, valid, ctxt, 1); 1047 AMAP_SET_BITS(struct amap_cq_context_v2, eventable, 1048 ctxt, 1); 1049 AMAP_SET_BITS(struct amap_cq_context_v2, eqid, 1050 ctxt, eq->id); 1051 } 1052 1053 be_dws_cpu_to_le(ctxt, sizeof(req->context)); 1054 1055 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); 1056 1057 status = be_mbox_notify_wait(adapter); 1058 if (!status) { 1059 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb); 1060 cq->id = le16_to_cpu(resp->cq_id); 1061 cq->created = true; 1062 } 1063 1064 mutex_unlock(&adapter->mbox_lock); 1065 1066 return status; 1067 } 1068 1069 static u32 be_encoded_q_len(int q_len) 1070 { 1071 u32 len_encoded = fls(q_len); /* log2(len) + 1 */ 1072 if (len_encoded == 16) 1073 len_encoded = 0; 1074 return len_encoded; 1075 } 1076 1077 static int be_cmd_mccq_ext_create(struct be_adapter *adapter, 1078 struct be_queue_info *mccq, 1079 struct be_queue_info *cq) 1080 { 1081 struct be_mcc_wrb *wrb; 1082 struct be_cmd_req_mcc_ext_create *req; 1083 struct be_dma_mem *q_mem = &mccq->dma_mem; 1084 void *ctxt; 1085 int status; 1086 1087 if (mutex_lock_interruptible(&adapter->mbox_lock)) 1088 return -1; 1089 1090 wrb = wrb_from_mbox(adapter); 1091 req = embedded_payload(wrb); 1092 ctxt = &req->context; 1093 1094 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1095 OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req), wrb, NULL); 1096 1097 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size)); 1098 if (lancer_chip(adapter)) { 1099 req->hdr.version = 1; 1100 req->cq_id = cpu_to_le16(cq->id); 1101 1102 AMAP_SET_BITS(struct amap_mcc_context_lancer, ring_size, ctxt, 1103 be_encoded_q_len(mccq->len)); 1104 AMAP_SET_BITS(struct amap_mcc_context_lancer, valid, ctxt, 1); 1105 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_id, 1106 ctxt, cq->id); 1107 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_valid, 1108 ctxt, 1); 1109 1110 } else { 1111 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1); 1112 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt, 1113 be_encoded_q_len(mccq->len)); 1114 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id); 1115 } 1116 1117 /* Subscribe to Link State and Group 5 Events(bits 1 and 5 set) */ 1118 req->async_event_bitmap[0] = cpu_to_le32(0x00000022); 1119 req->async_event_bitmap[0] |= cpu_to_le32(1 << ASYNC_EVENT_CODE_QNQ); 1120 be_dws_cpu_to_le(ctxt, sizeof(req->context)); 1121 1122 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); 1123 1124 status = be_mbox_notify_wait(adapter); 1125 if (!status) { 1126 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb); 1127 mccq->id = le16_to_cpu(resp->id); 1128 mccq->created = true; 1129 } 1130 mutex_unlock(&adapter->mbox_lock); 1131 1132 return status; 1133 } 1134 1135 static int be_cmd_mccq_org_create(struct be_adapter *adapter, 1136 struct be_queue_info *mccq, 1137 struct be_queue_info *cq) 1138 { 1139 struct be_mcc_wrb *wrb; 1140 struct be_cmd_req_mcc_create *req; 1141 struct be_dma_mem *q_mem = &mccq->dma_mem; 1142 void *ctxt; 1143 int status; 1144 1145 if (mutex_lock_interruptible(&adapter->mbox_lock)) 1146 return -1; 1147 1148 wrb = wrb_from_mbox(adapter); 1149 req = embedded_payload(wrb); 1150 ctxt = &req->context; 1151 1152 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1153 OPCODE_COMMON_MCC_CREATE, sizeof(*req), wrb, NULL); 1154 1155 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size)); 1156 1157 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1); 1158 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt, 1159 be_encoded_q_len(mccq->len)); 1160 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id); 1161 1162 be_dws_cpu_to_le(ctxt, sizeof(req->context)); 1163 1164 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); 1165 1166 status = be_mbox_notify_wait(adapter); 1167 if (!status) { 1168 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb); 1169 mccq->id = le16_to_cpu(resp->id); 1170 mccq->created = true; 1171 } 1172 1173 mutex_unlock(&adapter->mbox_lock); 1174 return status; 1175 } 1176 1177 int be_cmd_mccq_create(struct be_adapter *adapter, 1178 struct be_queue_info *mccq, 1179 struct be_queue_info *cq) 1180 { 1181 int status; 1182 1183 status = be_cmd_mccq_ext_create(adapter, mccq, cq); 1184 if (status && !lancer_chip(adapter)) { 1185 dev_warn(&adapter->pdev->dev, "Upgrade to F/W ver 2.102.235.0 " 1186 "or newer to avoid conflicting priorities between NIC " 1187 "and FCoE traffic"); 1188 status = be_cmd_mccq_org_create(adapter, mccq, cq); 1189 } 1190 return status; 1191 } 1192 1193 int be_cmd_txq_create(struct be_adapter *adapter, struct be_tx_obj *txo) 1194 { 1195 struct be_mcc_wrb wrb = {0}; 1196 struct be_cmd_req_eth_tx_create *req; 1197 struct be_queue_info *txq = &txo->q; 1198 struct be_queue_info *cq = &txo->cq; 1199 struct be_dma_mem *q_mem = &txq->dma_mem; 1200 int status, ver = 0; 1201 1202 req = embedded_payload(&wrb); 1203 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, 1204 OPCODE_ETH_TX_CREATE, sizeof(*req), &wrb, NULL); 1205 1206 if (lancer_chip(adapter)) { 1207 req->hdr.version = 1; 1208 } else if (BEx_chip(adapter)) { 1209 if (adapter->function_caps & BE_FUNCTION_CAPS_SUPER_NIC) 1210 req->hdr.version = 2; 1211 } else { /* For SH */ 1212 req->hdr.version = 2; 1213 } 1214 1215 if (req->hdr.version > 0) 1216 req->if_id = cpu_to_le16(adapter->if_handle); 1217 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size); 1218 req->ulp_num = BE_ULP1_NUM; 1219 req->type = BE_ETH_TX_RING_TYPE_STANDARD; 1220 req->cq_id = cpu_to_le16(cq->id); 1221 req->queue_size = be_encoded_q_len(txq->len); 1222 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); 1223 ver = req->hdr.version; 1224 1225 status = be_cmd_notify_wait(adapter, &wrb); 1226 if (!status) { 1227 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(&wrb); 1228 txq->id = le16_to_cpu(resp->cid); 1229 if (ver == 2) 1230 txo->db_offset = le32_to_cpu(resp->db_offset); 1231 else 1232 txo->db_offset = DB_TXULP1_OFFSET; 1233 txq->created = true; 1234 } 1235 1236 return status; 1237 } 1238 1239 /* Uses MCC */ 1240 int be_cmd_rxq_create(struct be_adapter *adapter, 1241 struct be_queue_info *rxq, u16 cq_id, u16 frag_size, 1242 u32 if_id, u32 rss, u8 *rss_id) 1243 { 1244 struct be_mcc_wrb *wrb; 1245 struct be_cmd_req_eth_rx_create *req; 1246 struct be_dma_mem *q_mem = &rxq->dma_mem; 1247 int status; 1248 1249 spin_lock_bh(&adapter->mcc_lock); 1250 1251 wrb = wrb_from_mccq(adapter); 1252 if (!wrb) { 1253 status = -EBUSY; 1254 goto err; 1255 } 1256 req = embedded_payload(wrb); 1257 1258 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, 1259 OPCODE_ETH_RX_CREATE, sizeof(*req), wrb, NULL); 1260 1261 req->cq_id = cpu_to_le16(cq_id); 1262 req->frag_size = fls(frag_size) - 1; 1263 req->num_pages = 2; 1264 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); 1265 req->interface_id = cpu_to_le32(if_id); 1266 req->max_frame_size = cpu_to_le16(BE_MAX_JUMBO_FRAME_SIZE); 1267 req->rss_queue = cpu_to_le32(rss); 1268 1269 status = be_mcc_notify_wait(adapter); 1270 if (!status) { 1271 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb); 1272 rxq->id = le16_to_cpu(resp->id); 1273 rxq->created = true; 1274 *rss_id = resp->rss_id; 1275 } 1276 1277 err: 1278 spin_unlock_bh(&adapter->mcc_lock); 1279 return status; 1280 } 1281 1282 /* Generic destroyer function for all types of queues 1283 * Uses Mbox 1284 */ 1285 int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q, 1286 int queue_type) 1287 { 1288 struct be_mcc_wrb *wrb; 1289 struct be_cmd_req_q_destroy *req; 1290 u8 subsys = 0, opcode = 0; 1291 int status; 1292 1293 if (mutex_lock_interruptible(&adapter->mbox_lock)) 1294 return -1; 1295 1296 wrb = wrb_from_mbox(adapter); 1297 req = embedded_payload(wrb); 1298 1299 switch (queue_type) { 1300 case QTYPE_EQ: 1301 subsys = CMD_SUBSYSTEM_COMMON; 1302 opcode = OPCODE_COMMON_EQ_DESTROY; 1303 break; 1304 case QTYPE_CQ: 1305 subsys = CMD_SUBSYSTEM_COMMON; 1306 opcode = OPCODE_COMMON_CQ_DESTROY; 1307 break; 1308 case QTYPE_TXQ: 1309 subsys = CMD_SUBSYSTEM_ETH; 1310 opcode = OPCODE_ETH_TX_DESTROY; 1311 break; 1312 case QTYPE_RXQ: 1313 subsys = CMD_SUBSYSTEM_ETH; 1314 opcode = OPCODE_ETH_RX_DESTROY; 1315 break; 1316 case QTYPE_MCCQ: 1317 subsys = CMD_SUBSYSTEM_COMMON; 1318 opcode = OPCODE_COMMON_MCC_DESTROY; 1319 break; 1320 default: 1321 BUG(); 1322 } 1323 1324 be_wrb_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req), wrb, 1325 NULL); 1326 req->id = cpu_to_le16(q->id); 1327 1328 status = be_mbox_notify_wait(adapter); 1329 q->created = false; 1330 1331 mutex_unlock(&adapter->mbox_lock); 1332 return status; 1333 } 1334 1335 /* Uses MCC */ 1336 int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q) 1337 { 1338 struct be_mcc_wrb *wrb; 1339 struct be_cmd_req_q_destroy *req; 1340 int status; 1341 1342 spin_lock_bh(&adapter->mcc_lock); 1343 1344 wrb = wrb_from_mccq(adapter); 1345 if (!wrb) { 1346 status = -EBUSY; 1347 goto err; 1348 } 1349 req = embedded_payload(wrb); 1350 1351 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, 1352 OPCODE_ETH_RX_DESTROY, sizeof(*req), wrb, NULL); 1353 req->id = cpu_to_le16(q->id); 1354 1355 status = be_mcc_notify_wait(adapter); 1356 q->created = false; 1357 1358 err: 1359 spin_unlock_bh(&adapter->mcc_lock); 1360 return status; 1361 } 1362 1363 /* Create an rx filtering policy configuration on an i/f 1364 * Will use MBOX only if MCCQ has not been created. 1365 */ 1366 int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags, 1367 u32 *if_handle, u32 domain) 1368 { 1369 struct be_mcc_wrb wrb = {0}; 1370 struct be_cmd_req_if_create *req; 1371 int status; 1372 1373 req = embedded_payload(&wrb); 1374 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1375 OPCODE_COMMON_NTWK_INTERFACE_CREATE, sizeof(*req), &wrb, NULL); 1376 req->hdr.domain = domain; 1377 req->capability_flags = cpu_to_le32(cap_flags); 1378 req->enable_flags = cpu_to_le32(en_flags); 1379 req->pmac_invalid = true; 1380 1381 status = be_cmd_notify_wait(adapter, &wrb); 1382 if (!status) { 1383 struct be_cmd_resp_if_create *resp = embedded_payload(&wrb); 1384 *if_handle = le32_to_cpu(resp->interface_id); 1385 1386 /* Hack to retrieve VF's pmac-id on BE3 */ 1387 if (BE3_chip(adapter) && !be_physfn(adapter)) 1388 adapter->pmac_id[0] = le32_to_cpu(resp->pmac_id); 1389 } 1390 return status; 1391 } 1392 1393 /* Uses MCCQ */ 1394 int be_cmd_if_destroy(struct be_adapter *adapter, int interface_id, u32 domain) 1395 { 1396 struct be_mcc_wrb *wrb; 1397 struct be_cmd_req_if_destroy *req; 1398 int status; 1399 1400 if (interface_id == -1) 1401 return 0; 1402 1403 spin_lock_bh(&adapter->mcc_lock); 1404 1405 wrb = wrb_from_mccq(adapter); 1406 if (!wrb) { 1407 status = -EBUSY; 1408 goto err; 1409 } 1410 req = embedded_payload(wrb); 1411 1412 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1413 OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req), wrb, NULL); 1414 req->hdr.domain = domain; 1415 req->interface_id = cpu_to_le32(interface_id); 1416 1417 status = be_mcc_notify_wait(adapter); 1418 err: 1419 spin_unlock_bh(&adapter->mcc_lock); 1420 return status; 1421 } 1422 1423 /* Get stats is a non embedded command: the request is not embedded inside 1424 * WRB but is a separate dma memory block 1425 * Uses asynchronous MCC 1426 */ 1427 int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd) 1428 { 1429 struct be_mcc_wrb *wrb; 1430 struct be_cmd_req_hdr *hdr; 1431 int status = 0; 1432 1433 spin_lock_bh(&adapter->mcc_lock); 1434 1435 wrb = wrb_from_mccq(adapter); 1436 if (!wrb) { 1437 status = -EBUSY; 1438 goto err; 1439 } 1440 hdr = nonemb_cmd->va; 1441 1442 be_wrb_cmd_hdr_prepare(hdr, CMD_SUBSYSTEM_ETH, 1443 OPCODE_ETH_GET_STATISTICS, nonemb_cmd->size, wrb, nonemb_cmd); 1444 1445 /* version 1 of the cmd is not supported only by BE2 */ 1446 if (BE2_chip(adapter)) 1447 hdr->version = 0; 1448 if (BE3_chip(adapter) || lancer_chip(adapter)) 1449 hdr->version = 1; 1450 else 1451 hdr->version = 2; 1452 1453 be_mcc_notify(adapter); 1454 adapter->stats_cmd_sent = true; 1455 1456 err: 1457 spin_unlock_bh(&adapter->mcc_lock); 1458 return status; 1459 } 1460 1461 /* Lancer Stats */ 1462 int lancer_cmd_get_pport_stats(struct be_adapter *adapter, 1463 struct be_dma_mem *nonemb_cmd) 1464 { 1465 1466 struct be_mcc_wrb *wrb; 1467 struct lancer_cmd_req_pport_stats *req; 1468 int status = 0; 1469 1470 if (!be_cmd_allowed(adapter, OPCODE_ETH_GET_PPORT_STATS, 1471 CMD_SUBSYSTEM_ETH)) 1472 return -EPERM; 1473 1474 spin_lock_bh(&adapter->mcc_lock); 1475 1476 wrb = wrb_from_mccq(adapter); 1477 if (!wrb) { 1478 status = -EBUSY; 1479 goto err; 1480 } 1481 req = nonemb_cmd->va; 1482 1483 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, 1484 OPCODE_ETH_GET_PPORT_STATS, nonemb_cmd->size, wrb, 1485 nonemb_cmd); 1486 1487 req->cmd_params.params.pport_num = cpu_to_le16(adapter->hba_port_num); 1488 req->cmd_params.params.reset_stats = 0; 1489 1490 be_mcc_notify(adapter); 1491 adapter->stats_cmd_sent = true; 1492 1493 err: 1494 spin_unlock_bh(&adapter->mcc_lock); 1495 return status; 1496 } 1497 1498 static int be_mac_to_link_speed(int mac_speed) 1499 { 1500 switch (mac_speed) { 1501 case PHY_LINK_SPEED_ZERO: 1502 return 0; 1503 case PHY_LINK_SPEED_10MBPS: 1504 return 10; 1505 case PHY_LINK_SPEED_100MBPS: 1506 return 100; 1507 case PHY_LINK_SPEED_1GBPS: 1508 return 1000; 1509 case PHY_LINK_SPEED_10GBPS: 1510 return 10000; 1511 case PHY_LINK_SPEED_20GBPS: 1512 return 20000; 1513 case PHY_LINK_SPEED_25GBPS: 1514 return 25000; 1515 case PHY_LINK_SPEED_40GBPS: 1516 return 40000; 1517 } 1518 return 0; 1519 } 1520 1521 /* Uses synchronous mcc 1522 * Returns link_speed in Mbps 1523 */ 1524 int be_cmd_link_status_query(struct be_adapter *adapter, u16 *link_speed, 1525 u8 *link_status, u32 dom) 1526 { 1527 struct be_mcc_wrb *wrb; 1528 struct be_cmd_req_link_status *req; 1529 int status; 1530 1531 spin_lock_bh(&adapter->mcc_lock); 1532 1533 if (link_status) 1534 *link_status = LINK_DOWN; 1535 1536 wrb = wrb_from_mccq(adapter); 1537 if (!wrb) { 1538 status = -EBUSY; 1539 goto err; 1540 } 1541 req = embedded_payload(wrb); 1542 1543 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1544 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req), wrb, NULL); 1545 1546 /* version 1 of the cmd is not supported only by BE2 */ 1547 if (!BE2_chip(adapter)) 1548 req->hdr.version = 1; 1549 1550 req->hdr.domain = dom; 1551 1552 status = be_mcc_notify_wait(adapter); 1553 if (!status) { 1554 struct be_cmd_resp_link_status *resp = embedded_payload(wrb); 1555 if (link_speed) { 1556 *link_speed = resp->link_speed ? 1557 le16_to_cpu(resp->link_speed) * 10 : 1558 be_mac_to_link_speed(resp->mac_speed); 1559 1560 if (!resp->logical_link_status) 1561 *link_speed = 0; 1562 } 1563 if (link_status) 1564 *link_status = resp->logical_link_status; 1565 } 1566 1567 err: 1568 spin_unlock_bh(&adapter->mcc_lock); 1569 return status; 1570 } 1571 1572 /* Uses synchronous mcc */ 1573 int be_cmd_get_die_temperature(struct be_adapter *adapter) 1574 { 1575 struct be_mcc_wrb *wrb; 1576 struct be_cmd_req_get_cntl_addnl_attribs *req; 1577 int status = 0; 1578 1579 spin_lock_bh(&adapter->mcc_lock); 1580 1581 wrb = wrb_from_mccq(adapter); 1582 if (!wrb) { 1583 status = -EBUSY; 1584 goto err; 1585 } 1586 req = embedded_payload(wrb); 1587 1588 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1589 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES, sizeof(*req), 1590 wrb, NULL); 1591 1592 be_mcc_notify(adapter); 1593 1594 err: 1595 spin_unlock_bh(&adapter->mcc_lock); 1596 return status; 1597 } 1598 1599 /* Uses synchronous mcc */ 1600 int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size) 1601 { 1602 struct be_mcc_wrb *wrb; 1603 struct be_cmd_req_get_fat *req; 1604 int status; 1605 1606 spin_lock_bh(&adapter->mcc_lock); 1607 1608 wrb = wrb_from_mccq(adapter); 1609 if (!wrb) { 1610 status = -EBUSY; 1611 goto err; 1612 } 1613 req = embedded_payload(wrb); 1614 1615 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1616 OPCODE_COMMON_MANAGE_FAT, sizeof(*req), wrb, NULL); 1617 req->fat_operation = cpu_to_le32(QUERY_FAT); 1618 status = be_mcc_notify_wait(adapter); 1619 if (!status) { 1620 struct be_cmd_resp_get_fat *resp = embedded_payload(wrb); 1621 if (log_size && resp->log_size) 1622 *log_size = le32_to_cpu(resp->log_size) - 1623 sizeof(u32); 1624 } 1625 err: 1626 spin_unlock_bh(&adapter->mcc_lock); 1627 return status; 1628 } 1629 1630 void be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf) 1631 { 1632 struct be_dma_mem get_fat_cmd; 1633 struct be_mcc_wrb *wrb; 1634 struct be_cmd_req_get_fat *req; 1635 u32 offset = 0, total_size, buf_size, 1636 log_offset = sizeof(u32), payload_len; 1637 int status; 1638 1639 if (buf_len == 0) 1640 return; 1641 1642 total_size = buf_len; 1643 1644 get_fat_cmd.size = sizeof(struct be_cmd_req_get_fat) + 60*1024; 1645 get_fat_cmd.va = pci_alloc_consistent(adapter->pdev, 1646 get_fat_cmd.size, 1647 &get_fat_cmd.dma); 1648 if (!get_fat_cmd.va) { 1649 status = -ENOMEM; 1650 dev_err(&adapter->pdev->dev, 1651 "Memory allocation failure while retrieving FAT data\n"); 1652 return; 1653 } 1654 1655 spin_lock_bh(&adapter->mcc_lock); 1656 1657 while (total_size) { 1658 buf_size = min(total_size, (u32)60*1024); 1659 total_size -= buf_size; 1660 1661 wrb = wrb_from_mccq(adapter); 1662 if (!wrb) { 1663 status = -EBUSY; 1664 goto err; 1665 } 1666 req = get_fat_cmd.va; 1667 1668 payload_len = sizeof(struct be_cmd_req_get_fat) + buf_size; 1669 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1670 OPCODE_COMMON_MANAGE_FAT, payload_len, wrb, 1671 &get_fat_cmd); 1672 1673 req->fat_operation = cpu_to_le32(RETRIEVE_FAT); 1674 req->read_log_offset = cpu_to_le32(log_offset); 1675 req->read_log_length = cpu_to_le32(buf_size); 1676 req->data_buffer_size = cpu_to_le32(buf_size); 1677 1678 status = be_mcc_notify_wait(adapter); 1679 if (!status) { 1680 struct be_cmd_resp_get_fat *resp = get_fat_cmd.va; 1681 memcpy(buf + offset, 1682 resp->data_buffer, 1683 le32_to_cpu(resp->read_log_length)); 1684 } else { 1685 dev_err(&adapter->pdev->dev, "FAT Table Retrieve error\n"); 1686 goto err; 1687 } 1688 offset += buf_size; 1689 log_offset += buf_size; 1690 } 1691 err: 1692 pci_free_consistent(adapter->pdev, get_fat_cmd.size, 1693 get_fat_cmd.va, 1694 get_fat_cmd.dma); 1695 spin_unlock_bh(&adapter->mcc_lock); 1696 } 1697 1698 /* Uses synchronous mcc */ 1699 int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver, 1700 char *fw_on_flash) 1701 { 1702 struct be_mcc_wrb *wrb; 1703 struct be_cmd_req_get_fw_version *req; 1704 int status; 1705 1706 spin_lock_bh(&adapter->mcc_lock); 1707 1708 wrb = wrb_from_mccq(adapter); 1709 if (!wrb) { 1710 status = -EBUSY; 1711 goto err; 1712 } 1713 1714 req = embedded_payload(wrb); 1715 1716 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1717 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req), wrb, NULL); 1718 status = be_mcc_notify_wait(adapter); 1719 if (!status) { 1720 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb); 1721 strcpy(fw_ver, resp->firmware_version_string); 1722 if (fw_on_flash) 1723 strcpy(fw_on_flash, resp->fw_on_flash_version_string); 1724 } 1725 err: 1726 spin_unlock_bh(&adapter->mcc_lock); 1727 return status; 1728 } 1729 1730 /* set the EQ delay interval of an EQ to specified value 1731 * Uses async mcc 1732 */ 1733 int be_cmd_modify_eqd(struct be_adapter *adapter, struct be_set_eqd *set_eqd, 1734 int num) 1735 { 1736 struct be_mcc_wrb *wrb; 1737 struct be_cmd_req_modify_eq_delay *req; 1738 int status = 0, i; 1739 1740 spin_lock_bh(&adapter->mcc_lock); 1741 1742 wrb = wrb_from_mccq(adapter); 1743 if (!wrb) { 1744 status = -EBUSY; 1745 goto err; 1746 } 1747 req = embedded_payload(wrb); 1748 1749 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1750 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req), wrb, NULL); 1751 1752 req->num_eq = cpu_to_le32(num); 1753 for (i = 0; i < num; i++) { 1754 req->set_eqd[i].eq_id = cpu_to_le32(set_eqd[i].eq_id); 1755 req->set_eqd[i].phase = 0; 1756 req->set_eqd[i].delay_multiplier = 1757 cpu_to_le32(set_eqd[i].delay_multiplier); 1758 } 1759 1760 be_mcc_notify(adapter); 1761 err: 1762 spin_unlock_bh(&adapter->mcc_lock); 1763 return status; 1764 } 1765 1766 /* Uses sycnhronous mcc */ 1767 int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array, 1768 u32 num, bool promiscuous) 1769 { 1770 struct be_mcc_wrb *wrb; 1771 struct be_cmd_req_vlan_config *req; 1772 int status; 1773 1774 spin_lock_bh(&adapter->mcc_lock); 1775 1776 wrb = wrb_from_mccq(adapter); 1777 if (!wrb) { 1778 status = -EBUSY; 1779 goto err; 1780 } 1781 req = embedded_payload(wrb); 1782 1783 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1784 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req), wrb, NULL); 1785 1786 req->interface_id = if_id; 1787 req->promiscuous = promiscuous; 1788 req->untagged = BE_IF_FLAGS_UNTAGGED & be_if_cap_flags(adapter) ? 1 : 0; 1789 req->num_vlan = num; 1790 if (!promiscuous) { 1791 memcpy(req->normal_vlan, vtag_array, 1792 req->num_vlan * sizeof(vtag_array[0])); 1793 } 1794 1795 status = be_mcc_notify_wait(adapter); 1796 1797 err: 1798 spin_unlock_bh(&adapter->mcc_lock); 1799 return status; 1800 } 1801 1802 int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value) 1803 { 1804 struct be_mcc_wrb *wrb; 1805 struct be_dma_mem *mem = &adapter->rx_filter; 1806 struct be_cmd_req_rx_filter *req = mem->va; 1807 int status; 1808 1809 spin_lock_bh(&adapter->mcc_lock); 1810 1811 wrb = wrb_from_mccq(adapter); 1812 if (!wrb) { 1813 status = -EBUSY; 1814 goto err; 1815 } 1816 memset(req, 0, sizeof(*req)); 1817 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1818 OPCODE_COMMON_NTWK_RX_FILTER, sizeof(*req), 1819 wrb, mem); 1820 1821 req->if_id = cpu_to_le32(adapter->if_handle); 1822 if (flags & IFF_PROMISC) { 1823 req->if_flags_mask = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS | 1824 BE_IF_FLAGS_VLAN_PROMISCUOUS | 1825 BE_IF_FLAGS_MCAST_PROMISCUOUS); 1826 if (value == ON) 1827 req->if_flags = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS | 1828 BE_IF_FLAGS_VLAN_PROMISCUOUS | 1829 BE_IF_FLAGS_MCAST_PROMISCUOUS); 1830 } else if (flags & IFF_ALLMULTI) { 1831 req->if_flags_mask = req->if_flags = 1832 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS); 1833 } else if (flags & BE_FLAGS_VLAN_PROMISC) { 1834 req->if_flags_mask = cpu_to_le32(BE_IF_FLAGS_VLAN_PROMISCUOUS); 1835 1836 if (value == ON) 1837 req->if_flags = 1838 cpu_to_le32(BE_IF_FLAGS_VLAN_PROMISCUOUS); 1839 } else { 1840 struct netdev_hw_addr *ha; 1841 int i = 0; 1842 1843 req->if_flags_mask = req->if_flags = 1844 cpu_to_le32(BE_IF_FLAGS_MULTICAST); 1845 1846 /* Reset mcast promisc mode if already set by setting mask 1847 * and not setting flags field 1848 */ 1849 req->if_flags_mask |= 1850 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS & 1851 be_if_cap_flags(adapter)); 1852 req->mcast_num = cpu_to_le32(netdev_mc_count(adapter->netdev)); 1853 netdev_for_each_mc_addr(ha, adapter->netdev) 1854 memcpy(req->mcast_mac[i++].byte, ha->addr, ETH_ALEN); 1855 } 1856 1857 if ((req->if_flags_mask & cpu_to_le32(be_if_cap_flags(adapter))) != 1858 req->if_flags_mask) { 1859 dev_warn(&adapter->pdev->dev, 1860 "Cannot set rx filter flags 0x%x\n", 1861 req->if_flags_mask); 1862 dev_warn(&adapter->pdev->dev, 1863 "Interface is capable of 0x%x flags only\n", 1864 be_if_cap_flags(adapter)); 1865 } 1866 req->if_flags_mask &= cpu_to_le32(be_if_cap_flags(adapter)); 1867 1868 status = be_mcc_notify_wait(adapter); 1869 1870 err: 1871 spin_unlock_bh(&adapter->mcc_lock); 1872 return status; 1873 } 1874 1875 /* Uses synchrounous mcc */ 1876 int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc) 1877 { 1878 struct be_mcc_wrb *wrb; 1879 struct be_cmd_req_set_flow_control *req; 1880 int status; 1881 1882 if (!be_cmd_allowed(adapter, OPCODE_COMMON_SET_FLOW_CONTROL, 1883 CMD_SUBSYSTEM_COMMON)) 1884 return -EPERM; 1885 1886 spin_lock_bh(&adapter->mcc_lock); 1887 1888 wrb = wrb_from_mccq(adapter); 1889 if (!wrb) { 1890 status = -EBUSY; 1891 goto err; 1892 } 1893 req = embedded_payload(wrb); 1894 1895 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1896 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req), wrb, NULL); 1897 1898 req->tx_flow_control = cpu_to_le16((u16)tx_fc); 1899 req->rx_flow_control = cpu_to_le16((u16)rx_fc); 1900 1901 status = be_mcc_notify_wait(adapter); 1902 1903 err: 1904 spin_unlock_bh(&adapter->mcc_lock); 1905 return status; 1906 } 1907 1908 /* Uses sycn mcc */ 1909 int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc) 1910 { 1911 struct be_mcc_wrb *wrb; 1912 struct be_cmd_req_get_flow_control *req; 1913 int status; 1914 1915 if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_FLOW_CONTROL, 1916 CMD_SUBSYSTEM_COMMON)) 1917 return -EPERM; 1918 1919 spin_lock_bh(&adapter->mcc_lock); 1920 1921 wrb = wrb_from_mccq(adapter); 1922 if (!wrb) { 1923 status = -EBUSY; 1924 goto err; 1925 } 1926 req = embedded_payload(wrb); 1927 1928 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1929 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req), wrb, NULL); 1930 1931 status = be_mcc_notify_wait(adapter); 1932 if (!status) { 1933 struct be_cmd_resp_get_flow_control *resp = 1934 embedded_payload(wrb); 1935 *tx_fc = le16_to_cpu(resp->tx_flow_control); 1936 *rx_fc = le16_to_cpu(resp->rx_flow_control); 1937 } 1938 1939 err: 1940 spin_unlock_bh(&adapter->mcc_lock); 1941 return status; 1942 } 1943 1944 /* Uses mbox */ 1945 int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num, 1946 u32 *mode, u32 *caps, u16 *asic_rev) 1947 { 1948 struct be_mcc_wrb *wrb; 1949 struct be_cmd_req_query_fw_cfg *req; 1950 int status; 1951 1952 if (mutex_lock_interruptible(&adapter->mbox_lock)) 1953 return -1; 1954 1955 wrb = wrb_from_mbox(adapter); 1956 req = embedded_payload(wrb); 1957 1958 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1959 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req), wrb, NULL); 1960 1961 status = be_mbox_notify_wait(adapter); 1962 if (!status) { 1963 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb); 1964 *port_num = le32_to_cpu(resp->phys_port); 1965 *mode = le32_to_cpu(resp->function_mode); 1966 *caps = le32_to_cpu(resp->function_caps); 1967 *asic_rev = le32_to_cpu(resp->asic_revision) & 0xFF; 1968 } 1969 1970 mutex_unlock(&adapter->mbox_lock); 1971 return status; 1972 } 1973 1974 /* Uses mbox */ 1975 int be_cmd_reset_function(struct be_adapter *adapter) 1976 { 1977 struct be_mcc_wrb *wrb; 1978 struct be_cmd_req_hdr *req; 1979 int status; 1980 1981 if (lancer_chip(adapter)) { 1982 status = lancer_wait_ready(adapter); 1983 if (!status) { 1984 iowrite32(SLI_PORT_CONTROL_IP_MASK, 1985 adapter->db + SLIPORT_CONTROL_OFFSET); 1986 status = lancer_test_and_set_rdy_state(adapter); 1987 } 1988 if (status) { 1989 dev_err(&adapter->pdev->dev, 1990 "Adapter in non recoverable error\n"); 1991 } 1992 return status; 1993 } 1994 1995 if (mutex_lock_interruptible(&adapter->mbox_lock)) 1996 return -1; 1997 1998 wrb = wrb_from_mbox(adapter); 1999 req = embedded_payload(wrb); 2000 2001 be_wrb_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON, 2002 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req), wrb, NULL); 2003 2004 status = be_mbox_notify_wait(adapter); 2005 2006 mutex_unlock(&adapter->mbox_lock); 2007 return status; 2008 } 2009 2010 int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable, 2011 u32 rss_hash_opts, u16 table_size) 2012 { 2013 struct be_mcc_wrb *wrb; 2014 struct be_cmd_req_rss_config *req; 2015 u32 myhash[10] = {0x15d43fa5, 0x2534685a, 0x5f87693a, 0x5668494e, 2016 0x33cf6a53, 0x383334c6, 0x76ac4257, 0x59b242b2, 2017 0x3ea83c02, 0x4a110304}; 2018 int status; 2019 2020 if (mutex_lock_interruptible(&adapter->mbox_lock)) 2021 return -1; 2022 2023 wrb = wrb_from_mbox(adapter); 2024 req = embedded_payload(wrb); 2025 2026 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, 2027 OPCODE_ETH_RSS_CONFIG, sizeof(*req), wrb, NULL); 2028 2029 req->if_id = cpu_to_le32(adapter->if_handle); 2030 req->enable_rss = cpu_to_le16(rss_hash_opts); 2031 req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1); 2032 2033 if (lancer_chip(adapter) || skyhawk_chip(adapter)) 2034 req->hdr.version = 1; 2035 2036 memcpy(req->cpu_table, rsstable, table_size); 2037 memcpy(req->hash, myhash, sizeof(myhash)); 2038 be_dws_cpu_to_le(req->hash, sizeof(req->hash)); 2039 2040 status = be_mbox_notify_wait(adapter); 2041 2042 mutex_unlock(&adapter->mbox_lock); 2043 return status; 2044 } 2045 2046 /* Uses sync mcc */ 2047 int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num, 2048 u8 bcn, u8 sts, u8 state) 2049 { 2050 struct be_mcc_wrb *wrb; 2051 struct be_cmd_req_enable_disable_beacon *req; 2052 int status; 2053 2054 spin_lock_bh(&adapter->mcc_lock); 2055 2056 wrb = wrb_from_mccq(adapter); 2057 if (!wrb) { 2058 status = -EBUSY; 2059 goto err; 2060 } 2061 req = embedded_payload(wrb); 2062 2063 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2064 OPCODE_COMMON_ENABLE_DISABLE_BEACON, sizeof(*req), wrb, NULL); 2065 2066 req->port_num = port_num; 2067 req->beacon_state = state; 2068 req->beacon_duration = bcn; 2069 req->status_duration = sts; 2070 2071 status = be_mcc_notify_wait(adapter); 2072 2073 err: 2074 spin_unlock_bh(&adapter->mcc_lock); 2075 return status; 2076 } 2077 2078 /* Uses sync mcc */ 2079 int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state) 2080 { 2081 struct be_mcc_wrb *wrb; 2082 struct be_cmd_req_get_beacon_state *req; 2083 int status; 2084 2085 spin_lock_bh(&adapter->mcc_lock); 2086 2087 wrb = wrb_from_mccq(adapter); 2088 if (!wrb) { 2089 status = -EBUSY; 2090 goto err; 2091 } 2092 req = embedded_payload(wrb); 2093 2094 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2095 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req), wrb, NULL); 2096 2097 req->port_num = port_num; 2098 2099 status = be_mcc_notify_wait(adapter); 2100 if (!status) { 2101 struct be_cmd_resp_get_beacon_state *resp = 2102 embedded_payload(wrb); 2103 *state = resp->beacon_state; 2104 } 2105 2106 err: 2107 spin_unlock_bh(&adapter->mcc_lock); 2108 return status; 2109 } 2110 2111 int lancer_cmd_write_object(struct be_adapter *adapter, struct be_dma_mem *cmd, 2112 u32 data_size, u32 data_offset, 2113 const char *obj_name, u32 *data_written, 2114 u8 *change_status, u8 *addn_status) 2115 { 2116 struct be_mcc_wrb *wrb; 2117 struct lancer_cmd_req_write_object *req; 2118 struct lancer_cmd_resp_write_object *resp; 2119 void *ctxt = NULL; 2120 int status; 2121 2122 spin_lock_bh(&adapter->mcc_lock); 2123 adapter->flash_status = 0; 2124 2125 wrb = wrb_from_mccq(adapter); 2126 if (!wrb) { 2127 status = -EBUSY; 2128 goto err_unlock; 2129 } 2130 2131 req = embedded_payload(wrb); 2132 2133 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2134 OPCODE_COMMON_WRITE_OBJECT, 2135 sizeof(struct lancer_cmd_req_write_object), wrb, 2136 NULL); 2137 2138 ctxt = &req->context; 2139 AMAP_SET_BITS(struct amap_lancer_write_obj_context, 2140 write_length, ctxt, data_size); 2141 2142 if (data_size == 0) 2143 AMAP_SET_BITS(struct amap_lancer_write_obj_context, 2144 eof, ctxt, 1); 2145 else 2146 AMAP_SET_BITS(struct amap_lancer_write_obj_context, 2147 eof, ctxt, 0); 2148 2149 be_dws_cpu_to_le(ctxt, sizeof(req->context)); 2150 req->write_offset = cpu_to_le32(data_offset); 2151 strcpy(req->object_name, obj_name); 2152 req->descriptor_count = cpu_to_le32(1); 2153 req->buf_len = cpu_to_le32(data_size); 2154 req->addr_low = cpu_to_le32((cmd->dma + 2155 sizeof(struct lancer_cmd_req_write_object)) 2156 & 0xFFFFFFFF); 2157 req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma + 2158 sizeof(struct lancer_cmd_req_write_object))); 2159 2160 be_mcc_notify(adapter); 2161 spin_unlock_bh(&adapter->mcc_lock); 2162 2163 if (!wait_for_completion_timeout(&adapter->flash_compl, 2164 msecs_to_jiffies(60000))) 2165 status = -1; 2166 else 2167 status = adapter->flash_status; 2168 2169 resp = embedded_payload(wrb); 2170 if (!status) { 2171 *data_written = le32_to_cpu(resp->actual_write_len); 2172 *change_status = resp->change_status; 2173 } else { 2174 *addn_status = resp->additional_status; 2175 } 2176 2177 return status; 2178 2179 err_unlock: 2180 spin_unlock_bh(&adapter->mcc_lock); 2181 return status; 2182 } 2183 2184 int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd, 2185 u32 data_size, u32 data_offset, const char *obj_name, 2186 u32 *data_read, u32 *eof, u8 *addn_status) 2187 { 2188 struct be_mcc_wrb *wrb; 2189 struct lancer_cmd_req_read_object *req; 2190 struct lancer_cmd_resp_read_object *resp; 2191 int status; 2192 2193 spin_lock_bh(&adapter->mcc_lock); 2194 2195 wrb = wrb_from_mccq(adapter); 2196 if (!wrb) { 2197 status = -EBUSY; 2198 goto err_unlock; 2199 } 2200 2201 req = embedded_payload(wrb); 2202 2203 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2204 OPCODE_COMMON_READ_OBJECT, 2205 sizeof(struct lancer_cmd_req_read_object), wrb, 2206 NULL); 2207 2208 req->desired_read_len = cpu_to_le32(data_size); 2209 req->read_offset = cpu_to_le32(data_offset); 2210 strcpy(req->object_name, obj_name); 2211 req->descriptor_count = cpu_to_le32(1); 2212 req->buf_len = cpu_to_le32(data_size); 2213 req->addr_low = cpu_to_le32((cmd->dma & 0xFFFFFFFF)); 2214 req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma)); 2215 2216 status = be_mcc_notify_wait(adapter); 2217 2218 resp = embedded_payload(wrb); 2219 if (!status) { 2220 *data_read = le32_to_cpu(resp->actual_read_len); 2221 *eof = le32_to_cpu(resp->eof); 2222 } else { 2223 *addn_status = resp->additional_status; 2224 } 2225 2226 err_unlock: 2227 spin_unlock_bh(&adapter->mcc_lock); 2228 return status; 2229 } 2230 2231 int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd, 2232 u32 flash_type, u32 flash_opcode, u32 buf_size) 2233 { 2234 struct be_mcc_wrb *wrb; 2235 struct be_cmd_write_flashrom *req; 2236 int status; 2237 2238 spin_lock_bh(&adapter->mcc_lock); 2239 adapter->flash_status = 0; 2240 2241 wrb = wrb_from_mccq(adapter); 2242 if (!wrb) { 2243 status = -EBUSY; 2244 goto err_unlock; 2245 } 2246 req = cmd->va; 2247 2248 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2249 OPCODE_COMMON_WRITE_FLASHROM, cmd->size, wrb, cmd); 2250 2251 req->params.op_type = cpu_to_le32(flash_type); 2252 req->params.op_code = cpu_to_le32(flash_opcode); 2253 req->params.data_buf_size = cpu_to_le32(buf_size); 2254 2255 be_mcc_notify(adapter); 2256 spin_unlock_bh(&adapter->mcc_lock); 2257 2258 if (!wait_for_completion_timeout(&adapter->flash_compl, 2259 msecs_to_jiffies(40000))) 2260 status = -1; 2261 else 2262 status = adapter->flash_status; 2263 2264 return status; 2265 2266 err_unlock: 2267 spin_unlock_bh(&adapter->mcc_lock); 2268 return status; 2269 } 2270 2271 int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc, 2272 int offset) 2273 { 2274 struct be_mcc_wrb *wrb; 2275 struct be_cmd_read_flash_crc *req; 2276 int status; 2277 2278 spin_lock_bh(&adapter->mcc_lock); 2279 2280 wrb = wrb_from_mccq(adapter); 2281 if (!wrb) { 2282 status = -EBUSY; 2283 goto err; 2284 } 2285 req = embedded_payload(wrb); 2286 2287 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2288 OPCODE_COMMON_READ_FLASHROM, sizeof(*req), 2289 wrb, NULL); 2290 2291 req->params.op_type = cpu_to_le32(OPTYPE_REDBOOT); 2292 req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT); 2293 req->params.offset = cpu_to_le32(offset); 2294 req->params.data_buf_size = cpu_to_le32(0x4); 2295 2296 status = be_mcc_notify_wait(adapter); 2297 if (!status) 2298 memcpy(flashed_crc, req->crc, 4); 2299 2300 err: 2301 spin_unlock_bh(&adapter->mcc_lock); 2302 return status; 2303 } 2304 2305 int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac, 2306 struct be_dma_mem *nonemb_cmd) 2307 { 2308 struct be_mcc_wrb *wrb; 2309 struct be_cmd_req_acpi_wol_magic_config *req; 2310 int status; 2311 2312 spin_lock_bh(&adapter->mcc_lock); 2313 2314 wrb = wrb_from_mccq(adapter); 2315 if (!wrb) { 2316 status = -EBUSY; 2317 goto err; 2318 } 2319 req = nonemb_cmd->va; 2320 2321 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, 2322 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req), wrb, 2323 nonemb_cmd); 2324 memcpy(req->magic_mac, mac, ETH_ALEN); 2325 2326 status = be_mcc_notify_wait(adapter); 2327 2328 err: 2329 spin_unlock_bh(&adapter->mcc_lock); 2330 return status; 2331 } 2332 2333 int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num, 2334 u8 loopback_type, u8 enable) 2335 { 2336 struct be_mcc_wrb *wrb; 2337 struct be_cmd_req_set_lmode *req; 2338 int status; 2339 2340 spin_lock_bh(&adapter->mcc_lock); 2341 2342 wrb = wrb_from_mccq(adapter); 2343 if (!wrb) { 2344 status = -EBUSY; 2345 goto err; 2346 } 2347 2348 req = embedded_payload(wrb); 2349 2350 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL, 2351 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE, sizeof(*req), wrb, 2352 NULL); 2353 2354 req->src_port = port_num; 2355 req->dest_port = port_num; 2356 req->loopback_type = loopback_type; 2357 req->loopback_state = enable; 2358 2359 status = be_mcc_notify_wait(adapter); 2360 err: 2361 spin_unlock_bh(&adapter->mcc_lock); 2362 return status; 2363 } 2364 2365 int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num, 2366 u32 loopback_type, u32 pkt_size, u32 num_pkts, u64 pattern) 2367 { 2368 struct be_mcc_wrb *wrb; 2369 struct be_cmd_req_loopback_test *req; 2370 int status; 2371 2372 spin_lock_bh(&adapter->mcc_lock); 2373 2374 wrb = wrb_from_mccq(adapter); 2375 if (!wrb) { 2376 status = -EBUSY; 2377 goto err; 2378 } 2379 2380 req = embedded_payload(wrb); 2381 2382 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL, 2383 OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req), wrb, NULL); 2384 req->hdr.timeout = cpu_to_le32(4); 2385 2386 req->pattern = cpu_to_le64(pattern); 2387 req->src_port = cpu_to_le32(port_num); 2388 req->dest_port = cpu_to_le32(port_num); 2389 req->pkt_size = cpu_to_le32(pkt_size); 2390 req->num_pkts = cpu_to_le32(num_pkts); 2391 req->loopback_type = cpu_to_le32(loopback_type); 2392 2393 status = be_mcc_notify_wait(adapter); 2394 if (!status) { 2395 struct be_cmd_resp_loopback_test *resp = embedded_payload(wrb); 2396 status = le32_to_cpu(resp->status); 2397 } 2398 2399 err: 2400 spin_unlock_bh(&adapter->mcc_lock); 2401 return status; 2402 } 2403 2404 int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern, 2405 u32 byte_cnt, struct be_dma_mem *cmd) 2406 { 2407 struct be_mcc_wrb *wrb; 2408 struct be_cmd_req_ddrdma_test *req; 2409 int status; 2410 int i, j = 0; 2411 2412 spin_lock_bh(&adapter->mcc_lock); 2413 2414 wrb = wrb_from_mccq(adapter); 2415 if (!wrb) { 2416 status = -EBUSY; 2417 goto err; 2418 } 2419 req = cmd->va; 2420 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL, 2421 OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size, wrb, cmd); 2422 2423 req->pattern = cpu_to_le64(pattern); 2424 req->byte_count = cpu_to_le32(byte_cnt); 2425 for (i = 0; i < byte_cnt; i++) { 2426 req->snd_buff[i] = (u8)(pattern >> (j*8)); 2427 j++; 2428 if (j > 7) 2429 j = 0; 2430 } 2431 2432 status = be_mcc_notify_wait(adapter); 2433 2434 if (!status) { 2435 struct be_cmd_resp_ddrdma_test *resp; 2436 resp = cmd->va; 2437 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) || 2438 resp->snd_err) { 2439 status = -1; 2440 } 2441 } 2442 2443 err: 2444 spin_unlock_bh(&adapter->mcc_lock); 2445 return status; 2446 } 2447 2448 int be_cmd_get_seeprom_data(struct be_adapter *adapter, 2449 struct be_dma_mem *nonemb_cmd) 2450 { 2451 struct be_mcc_wrb *wrb; 2452 struct be_cmd_req_seeprom_read *req; 2453 int status; 2454 2455 spin_lock_bh(&adapter->mcc_lock); 2456 2457 wrb = wrb_from_mccq(adapter); 2458 if (!wrb) { 2459 status = -EBUSY; 2460 goto err; 2461 } 2462 req = nonemb_cmd->va; 2463 2464 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2465 OPCODE_COMMON_SEEPROM_READ, sizeof(*req), wrb, 2466 nonemb_cmd); 2467 2468 status = be_mcc_notify_wait(adapter); 2469 2470 err: 2471 spin_unlock_bh(&adapter->mcc_lock); 2472 return status; 2473 } 2474 2475 int be_cmd_get_phy_info(struct be_adapter *adapter) 2476 { 2477 struct be_mcc_wrb *wrb; 2478 struct be_cmd_req_get_phy_info *req; 2479 struct be_dma_mem cmd; 2480 int status; 2481 2482 if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_PHY_DETAILS, 2483 CMD_SUBSYSTEM_COMMON)) 2484 return -EPERM; 2485 2486 spin_lock_bh(&adapter->mcc_lock); 2487 2488 wrb = wrb_from_mccq(adapter); 2489 if (!wrb) { 2490 status = -EBUSY; 2491 goto err; 2492 } 2493 cmd.size = sizeof(struct be_cmd_req_get_phy_info); 2494 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, 2495 &cmd.dma); 2496 if (!cmd.va) { 2497 dev_err(&adapter->pdev->dev, "Memory alloc failure\n"); 2498 status = -ENOMEM; 2499 goto err; 2500 } 2501 2502 req = cmd.va; 2503 2504 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2505 OPCODE_COMMON_GET_PHY_DETAILS, sizeof(*req), 2506 wrb, &cmd); 2507 2508 status = be_mcc_notify_wait(adapter); 2509 if (!status) { 2510 struct be_phy_info *resp_phy_info = 2511 cmd.va + sizeof(struct be_cmd_req_hdr); 2512 adapter->phy.phy_type = le16_to_cpu(resp_phy_info->phy_type); 2513 adapter->phy.interface_type = 2514 le16_to_cpu(resp_phy_info->interface_type); 2515 adapter->phy.auto_speeds_supported = 2516 le16_to_cpu(resp_phy_info->auto_speeds_supported); 2517 adapter->phy.fixed_speeds_supported = 2518 le16_to_cpu(resp_phy_info->fixed_speeds_supported); 2519 adapter->phy.misc_params = 2520 le32_to_cpu(resp_phy_info->misc_params); 2521 2522 if (BE2_chip(adapter)) { 2523 adapter->phy.fixed_speeds_supported = 2524 BE_SUPPORTED_SPEED_10GBPS | 2525 BE_SUPPORTED_SPEED_1GBPS; 2526 } 2527 } 2528 pci_free_consistent(adapter->pdev, cmd.size, 2529 cmd.va, cmd.dma); 2530 err: 2531 spin_unlock_bh(&adapter->mcc_lock); 2532 return status; 2533 } 2534 2535 int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain) 2536 { 2537 struct be_mcc_wrb *wrb; 2538 struct be_cmd_req_set_qos *req; 2539 int status; 2540 2541 spin_lock_bh(&adapter->mcc_lock); 2542 2543 wrb = wrb_from_mccq(adapter); 2544 if (!wrb) { 2545 status = -EBUSY; 2546 goto err; 2547 } 2548 2549 req = embedded_payload(wrb); 2550 2551 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2552 OPCODE_COMMON_SET_QOS, sizeof(*req), wrb, NULL); 2553 2554 req->hdr.domain = domain; 2555 req->valid_bits = cpu_to_le32(BE_QOS_BITS_NIC); 2556 req->max_bps_nic = cpu_to_le32(bps); 2557 2558 status = be_mcc_notify_wait(adapter); 2559 2560 err: 2561 spin_unlock_bh(&adapter->mcc_lock); 2562 return status; 2563 } 2564 2565 int be_cmd_get_cntl_attributes(struct be_adapter *adapter) 2566 { 2567 struct be_mcc_wrb *wrb; 2568 struct be_cmd_req_cntl_attribs *req; 2569 struct be_cmd_resp_cntl_attribs *resp; 2570 int status; 2571 int payload_len = max(sizeof(*req), sizeof(*resp)); 2572 struct mgmt_controller_attrib *attribs; 2573 struct be_dma_mem attribs_cmd; 2574 2575 if (mutex_lock_interruptible(&adapter->mbox_lock)) 2576 return -1; 2577 2578 memset(&attribs_cmd, 0, sizeof(struct be_dma_mem)); 2579 attribs_cmd.size = sizeof(struct be_cmd_resp_cntl_attribs); 2580 attribs_cmd.va = pci_alloc_consistent(adapter->pdev, attribs_cmd.size, 2581 &attribs_cmd.dma); 2582 if (!attribs_cmd.va) { 2583 dev_err(&adapter->pdev->dev, 2584 "Memory allocation failure\n"); 2585 status = -ENOMEM; 2586 goto err; 2587 } 2588 2589 wrb = wrb_from_mbox(adapter); 2590 if (!wrb) { 2591 status = -EBUSY; 2592 goto err; 2593 } 2594 req = attribs_cmd.va; 2595 2596 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2597 OPCODE_COMMON_GET_CNTL_ATTRIBUTES, payload_len, wrb, 2598 &attribs_cmd); 2599 2600 status = be_mbox_notify_wait(adapter); 2601 if (!status) { 2602 attribs = attribs_cmd.va + sizeof(struct be_cmd_resp_hdr); 2603 adapter->hba_port_num = attribs->hba_attribs.phy_port; 2604 } 2605 2606 err: 2607 mutex_unlock(&adapter->mbox_lock); 2608 if (attribs_cmd.va) 2609 pci_free_consistent(adapter->pdev, attribs_cmd.size, 2610 attribs_cmd.va, attribs_cmd.dma); 2611 return status; 2612 } 2613 2614 /* Uses mbox */ 2615 int be_cmd_req_native_mode(struct be_adapter *adapter) 2616 { 2617 struct be_mcc_wrb *wrb; 2618 struct be_cmd_req_set_func_cap *req; 2619 int status; 2620 2621 if (mutex_lock_interruptible(&adapter->mbox_lock)) 2622 return -1; 2623 2624 wrb = wrb_from_mbox(adapter); 2625 if (!wrb) { 2626 status = -EBUSY; 2627 goto err; 2628 } 2629 2630 req = embedded_payload(wrb); 2631 2632 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2633 OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP, sizeof(*req), wrb, NULL); 2634 2635 req->valid_cap_flags = cpu_to_le32(CAPABILITY_SW_TIMESTAMPS | 2636 CAPABILITY_BE3_NATIVE_ERX_API); 2637 req->cap_flags = cpu_to_le32(CAPABILITY_BE3_NATIVE_ERX_API); 2638 2639 status = be_mbox_notify_wait(adapter); 2640 if (!status) { 2641 struct be_cmd_resp_set_func_cap *resp = embedded_payload(wrb); 2642 adapter->be3_native = le32_to_cpu(resp->cap_flags) & 2643 CAPABILITY_BE3_NATIVE_ERX_API; 2644 if (!adapter->be3_native) 2645 dev_warn(&adapter->pdev->dev, 2646 "adapter not in advanced mode\n"); 2647 } 2648 err: 2649 mutex_unlock(&adapter->mbox_lock); 2650 return status; 2651 } 2652 2653 /* Get privilege(s) for a function */ 2654 int be_cmd_get_fn_privileges(struct be_adapter *adapter, u32 *privilege, 2655 u32 domain) 2656 { 2657 struct be_mcc_wrb *wrb; 2658 struct be_cmd_req_get_fn_privileges *req; 2659 int status; 2660 2661 spin_lock_bh(&adapter->mcc_lock); 2662 2663 wrb = wrb_from_mccq(adapter); 2664 if (!wrb) { 2665 status = -EBUSY; 2666 goto err; 2667 } 2668 2669 req = embedded_payload(wrb); 2670 2671 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2672 OPCODE_COMMON_GET_FN_PRIVILEGES, sizeof(*req), 2673 wrb, NULL); 2674 2675 req->hdr.domain = domain; 2676 2677 status = be_mcc_notify_wait(adapter); 2678 if (!status) { 2679 struct be_cmd_resp_get_fn_privileges *resp = 2680 embedded_payload(wrb); 2681 *privilege = le32_to_cpu(resp->privilege_mask); 2682 } 2683 2684 err: 2685 spin_unlock_bh(&adapter->mcc_lock); 2686 return status; 2687 } 2688 2689 /* Set privilege(s) for a function */ 2690 int be_cmd_set_fn_privileges(struct be_adapter *adapter, u32 privileges, 2691 u32 domain) 2692 { 2693 struct be_mcc_wrb *wrb; 2694 struct be_cmd_req_set_fn_privileges *req; 2695 int status; 2696 2697 spin_lock_bh(&adapter->mcc_lock); 2698 2699 wrb = wrb_from_mccq(adapter); 2700 if (!wrb) { 2701 status = -EBUSY; 2702 goto err; 2703 } 2704 2705 req = embedded_payload(wrb); 2706 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2707 OPCODE_COMMON_SET_FN_PRIVILEGES, sizeof(*req), 2708 wrb, NULL); 2709 req->hdr.domain = domain; 2710 if (lancer_chip(adapter)) 2711 req->privileges_lancer = cpu_to_le32(privileges); 2712 else 2713 req->privileges = cpu_to_le32(privileges); 2714 2715 status = be_mcc_notify_wait(adapter); 2716 err: 2717 spin_unlock_bh(&adapter->mcc_lock); 2718 return status; 2719 } 2720 2721 /* pmac_id_valid: true => pmac_id is supplied and MAC address is requested. 2722 * pmac_id_valid: false => pmac_id or MAC address is requested. 2723 * If pmac_id is returned, pmac_id_valid is returned as true 2724 */ 2725 int be_cmd_get_mac_from_list(struct be_adapter *adapter, u8 *mac, 2726 bool *pmac_id_valid, u32 *pmac_id, u8 domain) 2727 { 2728 struct be_mcc_wrb *wrb; 2729 struct be_cmd_req_get_mac_list *req; 2730 int status; 2731 int mac_count; 2732 struct be_dma_mem get_mac_list_cmd; 2733 int i; 2734 2735 memset(&get_mac_list_cmd, 0, sizeof(struct be_dma_mem)); 2736 get_mac_list_cmd.size = sizeof(struct be_cmd_resp_get_mac_list); 2737 get_mac_list_cmd.va = pci_alloc_consistent(adapter->pdev, 2738 get_mac_list_cmd.size, 2739 &get_mac_list_cmd.dma); 2740 2741 if (!get_mac_list_cmd.va) { 2742 dev_err(&adapter->pdev->dev, 2743 "Memory allocation failure during GET_MAC_LIST\n"); 2744 return -ENOMEM; 2745 } 2746 2747 spin_lock_bh(&adapter->mcc_lock); 2748 2749 wrb = wrb_from_mccq(adapter); 2750 if (!wrb) { 2751 status = -EBUSY; 2752 goto out; 2753 } 2754 2755 req = get_mac_list_cmd.va; 2756 2757 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2758 OPCODE_COMMON_GET_MAC_LIST, 2759 get_mac_list_cmd.size, wrb, &get_mac_list_cmd); 2760 req->hdr.domain = domain; 2761 req->mac_type = MAC_ADDRESS_TYPE_NETWORK; 2762 if (*pmac_id_valid) { 2763 req->mac_id = cpu_to_le32(*pmac_id); 2764 req->iface_id = cpu_to_le16(adapter->if_handle); 2765 req->perm_override = 0; 2766 } else { 2767 req->perm_override = 1; 2768 } 2769 2770 status = be_mcc_notify_wait(adapter); 2771 if (!status) { 2772 struct be_cmd_resp_get_mac_list *resp = 2773 get_mac_list_cmd.va; 2774 2775 if (*pmac_id_valid) { 2776 memcpy(mac, resp->macid_macaddr.mac_addr_id.macaddr, 2777 ETH_ALEN); 2778 goto out; 2779 } 2780 2781 mac_count = resp->true_mac_count + resp->pseudo_mac_count; 2782 /* Mac list returned could contain one or more active mac_ids 2783 * or one or more true or pseudo permanant mac addresses. 2784 * If an active mac_id is present, return first active mac_id 2785 * found. 2786 */ 2787 for (i = 0; i < mac_count; i++) { 2788 struct get_list_macaddr *mac_entry; 2789 u16 mac_addr_size; 2790 u32 mac_id; 2791 2792 mac_entry = &resp->macaddr_list[i]; 2793 mac_addr_size = le16_to_cpu(mac_entry->mac_addr_size); 2794 /* mac_id is a 32 bit value and mac_addr size 2795 * is 6 bytes 2796 */ 2797 if (mac_addr_size == sizeof(u32)) { 2798 *pmac_id_valid = true; 2799 mac_id = mac_entry->mac_addr_id.s_mac_id.mac_id; 2800 *pmac_id = le32_to_cpu(mac_id); 2801 goto out; 2802 } 2803 } 2804 /* If no active mac_id found, return first mac addr */ 2805 *pmac_id_valid = false; 2806 memcpy(mac, resp->macaddr_list[0].mac_addr_id.macaddr, 2807 ETH_ALEN); 2808 } 2809 2810 out: 2811 spin_unlock_bh(&adapter->mcc_lock); 2812 pci_free_consistent(adapter->pdev, get_mac_list_cmd.size, 2813 get_mac_list_cmd.va, get_mac_list_cmd.dma); 2814 return status; 2815 } 2816 2817 int be_cmd_get_active_mac(struct be_adapter *adapter, u32 curr_pmac_id, u8 *mac) 2818 { 2819 bool active = true; 2820 2821 if (BEx_chip(adapter)) 2822 return be_cmd_mac_addr_query(adapter, mac, false, 2823 adapter->if_handle, curr_pmac_id); 2824 else 2825 /* Fetch the MAC address using pmac_id */ 2826 return be_cmd_get_mac_from_list(adapter, mac, &active, 2827 &curr_pmac_id, 0); 2828 } 2829 2830 int be_cmd_get_perm_mac(struct be_adapter *adapter, u8 *mac) 2831 { 2832 int status; 2833 bool pmac_valid = false; 2834 2835 memset(mac, 0, ETH_ALEN); 2836 2837 if (BEx_chip(adapter)) { 2838 if (be_physfn(adapter)) 2839 status = be_cmd_mac_addr_query(adapter, mac, true, 0, 2840 0); 2841 else 2842 status = be_cmd_mac_addr_query(adapter, mac, false, 2843 adapter->if_handle, 0); 2844 } else { 2845 status = be_cmd_get_mac_from_list(adapter, mac, &pmac_valid, 2846 NULL, 0); 2847 } 2848 2849 return status; 2850 } 2851 2852 /* Uses synchronous MCCQ */ 2853 int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array, 2854 u8 mac_count, u32 domain) 2855 { 2856 struct be_mcc_wrb *wrb; 2857 struct be_cmd_req_set_mac_list *req; 2858 int status; 2859 struct be_dma_mem cmd; 2860 2861 memset(&cmd, 0, sizeof(struct be_dma_mem)); 2862 cmd.size = sizeof(struct be_cmd_req_set_mac_list); 2863 cmd.va = dma_alloc_coherent(&adapter->pdev->dev, cmd.size, 2864 &cmd.dma, GFP_KERNEL); 2865 if (!cmd.va) 2866 return -ENOMEM; 2867 2868 spin_lock_bh(&adapter->mcc_lock); 2869 2870 wrb = wrb_from_mccq(adapter); 2871 if (!wrb) { 2872 status = -EBUSY; 2873 goto err; 2874 } 2875 2876 req = cmd.va; 2877 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2878 OPCODE_COMMON_SET_MAC_LIST, sizeof(*req), 2879 wrb, &cmd); 2880 2881 req->hdr.domain = domain; 2882 req->mac_count = mac_count; 2883 if (mac_count) 2884 memcpy(req->mac, mac_array, ETH_ALEN*mac_count); 2885 2886 status = be_mcc_notify_wait(adapter); 2887 2888 err: 2889 dma_free_coherent(&adapter->pdev->dev, cmd.size, 2890 cmd.va, cmd.dma); 2891 spin_unlock_bh(&adapter->mcc_lock); 2892 return status; 2893 } 2894 2895 /* Wrapper to delete any active MACs and provision the new mac. 2896 * Changes to MAC_LIST are allowed iff none of the MAC addresses in the 2897 * current list are active. 2898 */ 2899 int be_cmd_set_mac(struct be_adapter *adapter, u8 *mac, int if_id, u32 dom) 2900 { 2901 bool active_mac = false; 2902 u8 old_mac[ETH_ALEN]; 2903 u32 pmac_id; 2904 int status; 2905 2906 status = be_cmd_get_mac_from_list(adapter, old_mac, &active_mac, 2907 &pmac_id, dom); 2908 if (!status && active_mac) 2909 be_cmd_pmac_del(adapter, if_id, pmac_id, dom); 2910 2911 return be_cmd_set_mac_list(adapter, mac, mac ? 1 : 0, dom); 2912 } 2913 2914 int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid, 2915 u32 domain, u16 intf_id, u16 hsw_mode) 2916 { 2917 struct be_mcc_wrb *wrb; 2918 struct be_cmd_req_set_hsw_config *req; 2919 void *ctxt; 2920 int status; 2921 2922 spin_lock_bh(&adapter->mcc_lock); 2923 2924 wrb = wrb_from_mccq(adapter); 2925 if (!wrb) { 2926 status = -EBUSY; 2927 goto err; 2928 } 2929 2930 req = embedded_payload(wrb); 2931 ctxt = &req->context; 2932 2933 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2934 OPCODE_COMMON_SET_HSW_CONFIG, sizeof(*req), wrb, NULL); 2935 2936 req->hdr.domain = domain; 2937 AMAP_SET_BITS(struct amap_set_hsw_context, interface_id, ctxt, intf_id); 2938 if (pvid) { 2939 AMAP_SET_BITS(struct amap_set_hsw_context, pvid_valid, ctxt, 1); 2940 AMAP_SET_BITS(struct amap_set_hsw_context, pvid, ctxt, pvid); 2941 } 2942 if (!BEx_chip(adapter) && hsw_mode) { 2943 AMAP_SET_BITS(struct amap_set_hsw_context, interface_id, 2944 ctxt, adapter->hba_port_num); 2945 AMAP_SET_BITS(struct amap_set_hsw_context, pport, ctxt, 1); 2946 AMAP_SET_BITS(struct amap_set_hsw_context, port_fwd_type, 2947 ctxt, hsw_mode); 2948 } 2949 2950 be_dws_cpu_to_le(req->context, sizeof(req->context)); 2951 status = be_mcc_notify_wait(adapter); 2952 2953 err: 2954 spin_unlock_bh(&adapter->mcc_lock); 2955 return status; 2956 } 2957 2958 /* Get Hyper switch config */ 2959 int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid, 2960 u32 domain, u16 intf_id, u8 *mode) 2961 { 2962 struct be_mcc_wrb *wrb; 2963 struct be_cmd_req_get_hsw_config *req; 2964 void *ctxt; 2965 int status; 2966 u16 vid; 2967 2968 spin_lock_bh(&adapter->mcc_lock); 2969 2970 wrb = wrb_from_mccq(adapter); 2971 if (!wrb) { 2972 status = -EBUSY; 2973 goto err; 2974 } 2975 2976 req = embedded_payload(wrb); 2977 ctxt = &req->context; 2978 2979 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2980 OPCODE_COMMON_GET_HSW_CONFIG, sizeof(*req), wrb, NULL); 2981 2982 req->hdr.domain = domain; 2983 AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id, 2984 ctxt, intf_id); 2985 AMAP_SET_BITS(struct amap_get_hsw_req_context, pvid_valid, ctxt, 1); 2986 2987 if (!BEx_chip(adapter)) { 2988 AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id, 2989 ctxt, adapter->hba_port_num); 2990 AMAP_SET_BITS(struct amap_get_hsw_req_context, pport, ctxt, 1); 2991 } 2992 be_dws_cpu_to_le(req->context, sizeof(req->context)); 2993 2994 status = be_mcc_notify_wait(adapter); 2995 if (!status) { 2996 struct be_cmd_resp_get_hsw_config *resp = 2997 embedded_payload(wrb); 2998 be_dws_le_to_cpu(&resp->context, 2999 sizeof(resp->context)); 3000 vid = AMAP_GET_BITS(struct amap_get_hsw_resp_context, 3001 pvid, &resp->context); 3002 if (pvid) 3003 *pvid = le16_to_cpu(vid); 3004 if (mode) 3005 *mode = AMAP_GET_BITS(struct amap_get_hsw_resp_context, 3006 port_fwd_type, &resp->context); 3007 } 3008 3009 err: 3010 spin_unlock_bh(&adapter->mcc_lock); 3011 return status; 3012 } 3013 3014 int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter) 3015 { 3016 struct be_mcc_wrb *wrb; 3017 struct be_cmd_req_acpi_wol_magic_config_v1 *req; 3018 int status; 3019 int payload_len = sizeof(*req); 3020 struct be_dma_mem cmd; 3021 3022 if (!be_cmd_allowed(adapter, OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, 3023 CMD_SUBSYSTEM_ETH)) 3024 return -EPERM; 3025 3026 if (mutex_lock_interruptible(&adapter->mbox_lock)) 3027 return -1; 3028 3029 memset(&cmd, 0, sizeof(struct be_dma_mem)); 3030 cmd.size = sizeof(struct be_cmd_resp_acpi_wol_magic_config_v1); 3031 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, 3032 &cmd.dma); 3033 if (!cmd.va) { 3034 dev_err(&adapter->pdev->dev, 3035 "Memory allocation failure\n"); 3036 status = -ENOMEM; 3037 goto err; 3038 } 3039 3040 wrb = wrb_from_mbox(adapter); 3041 if (!wrb) { 3042 status = -EBUSY; 3043 goto err; 3044 } 3045 3046 req = cmd.va; 3047 3048 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, 3049 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, 3050 payload_len, wrb, &cmd); 3051 3052 req->hdr.version = 1; 3053 req->query_options = BE_GET_WOL_CAP; 3054 3055 status = be_mbox_notify_wait(adapter); 3056 if (!status) { 3057 struct be_cmd_resp_acpi_wol_magic_config_v1 *resp; 3058 resp = (struct be_cmd_resp_acpi_wol_magic_config_v1 *) cmd.va; 3059 3060 /* the command could succeed misleadingly on old f/w 3061 * which is not aware of the V1 version. fake an error. */ 3062 if (resp->hdr.response_length < payload_len) { 3063 status = -1; 3064 goto err; 3065 } 3066 adapter->wol_cap = resp->wol_settings; 3067 } 3068 err: 3069 mutex_unlock(&adapter->mbox_lock); 3070 if (cmd.va) 3071 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma); 3072 return status; 3073 3074 } 3075 int be_cmd_get_ext_fat_capabilites(struct be_adapter *adapter, 3076 struct be_dma_mem *cmd) 3077 { 3078 struct be_mcc_wrb *wrb; 3079 struct be_cmd_req_get_ext_fat_caps *req; 3080 int status; 3081 3082 if (mutex_lock_interruptible(&adapter->mbox_lock)) 3083 return -1; 3084 3085 wrb = wrb_from_mbox(adapter); 3086 if (!wrb) { 3087 status = -EBUSY; 3088 goto err; 3089 } 3090 3091 req = cmd->va; 3092 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 3093 OPCODE_COMMON_GET_EXT_FAT_CAPABILITES, 3094 cmd->size, wrb, cmd); 3095 req->parameter_type = cpu_to_le32(1); 3096 3097 status = be_mbox_notify_wait(adapter); 3098 err: 3099 mutex_unlock(&adapter->mbox_lock); 3100 return status; 3101 } 3102 3103 int be_cmd_set_ext_fat_capabilites(struct be_adapter *adapter, 3104 struct be_dma_mem *cmd, 3105 struct be_fat_conf_params *configs) 3106 { 3107 struct be_mcc_wrb *wrb; 3108 struct be_cmd_req_set_ext_fat_caps *req; 3109 int status; 3110 3111 spin_lock_bh(&adapter->mcc_lock); 3112 3113 wrb = wrb_from_mccq(adapter); 3114 if (!wrb) { 3115 status = -EBUSY; 3116 goto err; 3117 } 3118 3119 req = cmd->va; 3120 memcpy(&req->set_params, configs, sizeof(struct be_fat_conf_params)); 3121 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 3122 OPCODE_COMMON_SET_EXT_FAT_CAPABILITES, 3123 cmd->size, wrb, cmd); 3124 3125 status = be_mcc_notify_wait(adapter); 3126 err: 3127 spin_unlock_bh(&adapter->mcc_lock); 3128 return status; 3129 } 3130 3131 int be_cmd_query_port_name(struct be_adapter *adapter, u8 *port_name) 3132 { 3133 struct be_mcc_wrb *wrb; 3134 struct be_cmd_req_get_port_name *req; 3135 int status; 3136 3137 if (!lancer_chip(adapter)) { 3138 *port_name = adapter->hba_port_num + '0'; 3139 return 0; 3140 } 3141 3142 spin_lock_bh(&adapter->mcc_lock); 3143 3144 wrb = wrb_from_mccq(adapter); 3145 if (!wrb) { 3146 status = -EBUSY; 3147 goto err; 3148 } 3149 3150 req = embedded_payload(wrb); 3151 3152 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 3153 OPCODE_COMMON_GET_PORT_NAME, sizeof(*req), wrb, 3154 NULL); 3155 req->hdr.version = 1; 3156 3157 status = be_mcc_notify_wait(adapter); 3158 if (!status) { 3159 struct be_cmd_resp_get_port_name *resp = embedded_payload(wrb); 3160 *port_name = resp->port_name[adapter->hba_port_num]; 3161 } else { 3162 *port_name = adapter->hba_port_num + '0'; 3163 } 3164 err: 3165 spin_unlock_bh(&adapter->mcc_lock); 3166 return status; 3167 } 3168 3169 static struct be_nic_res_desc *be_get_nic_desc(u8 *buf, u32 desc_count) 3170 { 3171 struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf; 3172 int i; 3173 3174 for (i = 0; i < desc_count; i++) { 3175 if (hdr->desc_type == NIC_RESOURCE_DESC_TYPE_V0 || 3176 hdr->desc_type == NIC_RESOURCE_DESC_TYPE_V1) 3177 return (struct be_nic_res_desc *)hdr; 3178 3179 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0; 3180 hdr = (void *)hdr + hdr->desc_len; 3181 } 3182 return NULL; 3183 } 3184 3185 static struct be_pcie_res_desc *be_get_pcie_desc(u8 devfn, u8 *buf, 3186 u32 desc_count) 3187 { 3188 struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf; 3189 struct be_pcie_res_desc *pcie; 3190 int i; 3191 3192 for (i = 0; i < desc_count; i++) { 3193 if ((hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V0 || 3194 hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V1)) { 3195 pcie = (struct be_pcie_res_desc *)hdr; 3196 if (pcie->pf_num == devfn) 3197 return pcie; 3198 } 3199 3200 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0; 3201 hdr = (void *)hdr + hdr->desc_len; 3202 } 3203 return NULL; 3204 } 3205 3206 static void be_copy_nic_desc(struct be_resources *res, 3207 struct be_nic_res_desc *desc) 3208 { 3209 res->max_uc_mac = le16_to_cpu(desc->unicast_mac_count); 3210 res->max_vlans = le16_to_cpu(desc->vlan_count); 3211 res->max_mcast_mac = le16_to_cpu(desc->mcast_mac_count); 3212 res->max_tx_qs = le16_to_cpu(desc->txq_count); 3213 res->max_rss_qs = le16_to_cpu(desc->rssq_count); 3214 res->max_rx_qs = le16_to_cpu(desc->rq_count); 3215 res->max_evt_qs = le16_to_cpu(desc->eq_count); 3216 /* Clear flags that driver is not interested in */ 3217 res->if_cap_flags = le32_to_cpu(desc->cap_flags) & 3218 BE_IF_CAP_FLAGS_WANT; 3219 /* Need 1 RXQ as the default RXQ */ 3220 if (res->max_rss_qs && res->max_rss_qs == res->max_rx_qs) 3221 res->max_rss_qs -= 1; 3222 } 3223 3224 /* Uses Mbox */ 3225 int be_cmd_get_func_config(struct be_adapter *adapter, struct be_resources *res) 3226 { 3227 struct be_mcc_wrb *wrb; 3228 struct be_cmd_req_get_func_config *req; 3229 int status; 3230 struct be_dma_mem cmd; 3231 3232 if (mutex_lock_interruptible(&adapter->mbox_lock)) 3233 return -1; 3234 3235 memset(&cmd, 0, sizeof(struct be_dma_mem)); 3236 cmd.size = sizeof(struct be_cmd_resp_get_func_config); 3237 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, 3238 &cmd.dma); 3239 if (!cmd.va) { 3240 dev_err(&adapter->pdev->dev, "Memory alloc failure\n"); 3241 status = -ENOMEM; 3242 goto err; 3243 } 3244 3245 wrb = wrb_from_mbox(adapter); 3246 if (!wrb) { 3247 status = -EBUSY; 3248 goto err; 3249 } 3250 3251 req = cmd.va; 3252 3253 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 3254 OPCODE_COMMON_GET_FUNC_CONFIG, 3255 cmd.size, wrb, &cmd); 3256 3257 if (skyhawk_chip(adapter)) 3258 req->hdr.version = 1; 3259 3260 status = be_mbox_notify_wait(adapter); 3261 if (!status) { 3262 struct be_cmd_resp_get_func_config *resp = cmd.va; 3263 u32 desc_count = le32_to_cpu(resp->desc_count); 3264 struct be_nic_res_desc *desc; 3265 3266 desc = be_get_nic_desc(resp->func_param, desc_count); 3267 if (!desc) { 3268 status = -EINVAL; 3269 goto err; 3270 } 3271 3272 adapter->pf_number = desc->pf_num; 3273 be_copy_nic_desc(res, desc); 3274 } 3275 err: 3276 mutex_unlock(&adapter->mbox_lock); 3277 if (cmd.va) 3278 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma); 3279 return status; 3280 } 3281 3282 /* Uses mbox */ 3283 static int be_cmd_get_profile_config_mbox(struct be_adapter *adapter, 3284 u8 domain, struct be_dma_mem *cmd) 3285 { 3286 struct be_mcc_wrb *wrb; 3287 struct be_cmd_req_get_profile_config *req; 3288 int status; 3289 3290 if (mutex_lock_interruptible(&adapter->mbox_lock)) 3291 return -1; 3292 wrb = wrb_from_mbox(adapter); 3293 3294 req = cmd->va; 3295 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 3296 OPCODE_COMMON_GET_PROFILE_CONFIG, 3297 cmd->size, wrb, cmd); 3298 3299 req->type = ACTIVE_PROFILE_TYPE; 3300 req->hdr.domain = domain; 3301 if (!lancer_chip(adapter)) 3302 req->hdr.version = 1; 3303 3304 status = be_mbox_notify_wait(adapter); 3305 3306 mutex_unlock(&adapter->mbox_lock); 3307 return status; 3308 } 3309 3310 /* Uses sync mcc */ 3311 static int be_cmd_get_profile_config_mccq(struct be_adapter *adapter, 3312 u8 domain, struct be_dma_mem *cmd) 3313 { 3314 struct be_mcc_wrb *wrb; 3315 struct be_cmd_req_get_profile_config *req; 3316 int status; 3317 3318 spin_lock_bh(&adapter->mcc_lock); 3319 3320 wrb = wrb_from_mccq(adapter); 3321 if (!wrb) { 3322 status = -EBUSY; 3323 goto err; 3324 } 3325 3326 req = cmd->va; 3327 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 3328 OPCODE_COMMON_GET_PROFILE_CONFIG, 3329 cmd->size, wrb, cmd); 3330 3331 req->type = ACTIVE_PROFILE_TYPE; 3332 req->hdr.domain = domain; 3333 if (!lancer_chip(adapter)) 3334 req->hdr.version = 1; 3335 3336 status = be_mcc_notify_wait(adapter); 3337 3338 err: 3339 spin_unlock_bh(&adapter->mcc_lock); 3340 return status; 3341 } 3342 3343 /* Uses sync mcc, if MCCQ is already created otherwise mbox */ 3344 int be_cmd_get_profile_config(struct be_adapter *adapter, 3345 struct be_resources *res, u8 domain) 3346 { 3347 struct be_cmd_resp_get_profile_config *resp; 3348 struct be_pcie_res_desc *pcie; 3349 struct be_nic_res_desc *nic; 3350 struct be_queue_info *mccq = &adapter->mcc_obj.q; 3351 struct be_dma_mem cmd; 3352 u32 desc_count; 3353 int status; 3354 3355 memset(&cmd, 0, sizeof(struct be_dma_mem)); 3356 cmd.size = sizeof(struct be_cmd_resp_get_profile_config); 3357 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma); 3358 if (!cmd.va) 3359 return -ENOMEM; 3360 3361 if (!mccq->created) 3362 status = be_cmd_get_profile_config_mbox(adapter, domain, &cmd); 3363 else 3364 status = be_cmd_get_profile_config_mccq(adapter, domain, &cmd); 3365 if (status) 3366 goto err; 3367 3368 resp = cmd.va; 3369 desc_count = le32_to_cpu(resp->desc_count); 3370 3371 pcie = be_get_pcie_desc(adapter->pdev->devfn, resp->func_param, 3372 desc_count); 3373 if (pcie) 3374 res->max_vfs = le16_to_cpu(pcie->num_vfs); 3375 3376 nic = be_get_nic_desc(resp->func_param, desc_count); 3377 if (nic) 3378 be_copy_nic_desc(res, nic); 3379 3380 err: 3381 if (cmd.va) 3382 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma); 3383 return status; 3384 } 3385 3386 /* Currently only Lancer uses this command and it supports version 0 only 3387 * Uses sync mcc 3388 */ 3389 int be_cmd_set_profile_config(struct be_adapter *adapter, u32 bps, 3390 u8 domain) 3391 { 3392 struct be_mcc_wrb *wrb; 3393 struct be_cmd_req_set_profile_config *req; 3394 int status; 3395 3396 spin_lock_bh(&adapter->mcc_lock); 3397 3398 wrb = wrb_from_mccq(adapter); 3399 if (!wrb) { 3400 status = -EBUSY; 3401 goto err; 3402 } 3403 3404 req = embedded_payload(wrb); 3405 3406 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 3407 OPCODE_COMMON_SET_PROFILE_CONFIG, sizeof(*req), 3408 wrb, NULL); 3409 req->hdr.domain = domain; 3410 req->desc_count = cpu_to_le32(1); 3411 req->nic_desc.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V0; 3412 req->nic_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V0; 3413 req->nic_desc.flags = (1 << QUN) | (1 << IMM) | (1 << NOSV); 3414 req->nic_desc.pf_num = adapter->pf_number; 3415 req->nic_desc.vf_num = domain; 3416 3417 /* Mark fields invalid */ 3418 req->nic_desc.unicast_mac_count = 0xFFFF; 3419 req->nic_desc.mcc_count = 0xFFFF; 3420 req->nic_desc.vlan_count = 0xFFFF; 3421 req->nic_desc.mcast_mac_count = 0xFFFF; 3422 req->nic_desc.txq_count = 0xFFFF; 3423 req->nic_desc.rq_count = 0xFFFF; 3424 req->nic_desc.rssq_count = 0xFFFF; 3425 req->nic_desc.lro_count = 0xFFFF; 3426 req->nic_desc.cq_count = 0xFFFF; 3427 req->nic_desc.toe_conn_count = 0xFFFF; 3428 req->nic_desc.eq_count = 0xFFFF; 3429 req->nic_desc.link_param = 0xFF; 3430 req->nic_desc.bw_min = 0xFFFFFFFF; 3431 req->nic_desc.acpi_params = 0xFF; 3432 req->nic_desc.wol_param = 0x0F; 3433 3434 /* Change BW */ 3435 req->nic_desc.bw_min = cpu_to_le32(bps); 3436 req->nic_desc.bw_max = cpu_to_le32(bps); 3437 status = be_mcc_notify_wait(adapter); 3438 err: 3439 spin_unlock_bh(&adapter->mcc_lock); 3440 return status; 3441 } 3442 3443 int be_cmd_get_if_id(struct be_adapter *adapter, struct be_vf_cfg *vf_cfg, 3444 int vf_num) 3445 { 3446 struct be_mcc_wrb *wrb; 3447 struct be_cmd_req_get_iface_list *req; 3448 struct be_cmd_resp_get_iface_list *resp; 3449 int status; 3450 3451 spin_lock_bh(&adapter->mcc_lock); 3452 3453 wrb = wrb_from_mccq(adapter); 3454 if (!wrb) { 3455 status = -EBUSY; 3456 goto err; 3457 } 3458 req = embedded_payload(wrb); 3459 3460 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 3461 OPCODE_COMMON_GET_IFACE_LIST, sizeof(*resp), 3462 wrb, NULL); 3463 req->hdr.domain = vf_num + 1; 3464 3465 status = be_mcc_notify_wait(adapter); 3466 if (!status) { 3467 resp = (struct be_cmd_resp_get_iface_list *)req; 3468 vf_cfg->if_handle = le32_to_cpu(resp->if_desc.if_id); 3469 } 3470 3471 err: 3472 spin_unlock_bh(&adapter->mcc_lock); 3473 return status; 3474 } 3475 3476 static int lancer_wait_idle(struct be_adapter *adapter) 3477 { 3478 #define SLIPORT_IDLE_TIMEOUT 30 3479 u32 reg_val; 3480 int status = 0, i; 3481 3482 for (i = 0; i < SLIPORT_IDLE_TIMEOUT; i++) { 3483 reg_val = ioread32(adapter->db + PHYSDEV_CONTROL_OFFSET); 3484 if ((reg_val & PHYSDEV_CONTROL_INP_MASK) == 0) 3485 break; 3486 3487 ssleep(1); 3488 } 3489 3490 if (i == SLIPORT_IDLE_TIMEOUT) 3491 status = -1; 3492 3493 return status; 3494 } 3495 3496 int lancer_physdev_ctrl(struct be_adapter *adapter, u32 mask) 3497 { 3498 int status = 0; 3499 3500 status = lancer_wait_idle(adapter); 3501 if (status) 3502 return status; 3503 3504 iowrite32(mask, adapter->db + PHYSDEV_CONTROL_OFFSET); 3505 3506 return status; 3507 } 3508 3509 /* Routine to check whether dump image is present or not */ 3510 bool dump_present(struct be_adapter *adapter) 3511 { 3512 u32 sliport_status = 0; 3513 3514 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET); 3515 return !!(sliport_status & SLIPORT_STATUS_DIP_MASK); 3516 } 3517 3518 int lancer_initiate_dump(struct be_adapter *adapter) 3519 { 3520 int status; 3521 3522 /* give firmware reset and diagnostic dump */ 3523 status = lancer_physdev_ctrl(adapter, PHYSDEV_CONTROL_FW_RESET_MASK | 3524 PHYSDEV_CONTROL_DD_MASK); 3525 if (status < 0) { 3526 dev_err(&adapter->pdev->dev, "Firmware reset failed\n"); 3527 return status; 3528 } 3529 3530 status = lancer_wait_idle(adapter); 3531 if (status) 3532 return status; 3533 3534 if (!dump_present(adapter)) { 3535 dev_err(&adapter->pdev->dev, "Dump image not present\n"); 3536 return -1; 3537 } 3538 3539 return 0; 3540 } 3541 3542 /* Uses sync mcc */ 3543 int be_cmd_enable_vf(struct be_adapter *adapter, u8 domain) 3544 { 3545 struct be_mcc_wrb *wrb; 3546 struct be_cmd_enable_disable_vf *req; 3547 int status; 3548 3549 if (BEx_chip(adapter)) 3550 return 0; 3551 3552 spin_lock_bh(&adapter->mcc_lock); 3553 3554 wrb = wrb_from_mccq(adapter); 3555 if (!wrb) { 3556 status = -EBUSY; 3557 goto err; 3558 } 3559 3560 req = embedded_payload(wrb); 3561 3562 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 3563 OPCODE_COMMON_ENABLE_DISABLE_VF, sizeof(*req), 3564 wrb, NULL); 3565 3566 req->hdr.domain = domain; 3567 req->enable = 1; 3568 status = be_mcc_notify_wait(adapter); 3569 err: 3570 spin_unlock_bh(&adapter->mcc_lock); 3571 return status; 3572 } 3573 3574 int be_cmd_intr_set(struct be_adapter *adapter, bool intr_enable) 3575 { 3576 struct be_mcc_wrb *wrb; 3577 struct be_cmd_req_intr_set *req; 3578 int status; 3579 3580 if (mutex_lock_interruptible(&adapter->mbox_lock)) 3581 return -1; 3582 3583 wrb = wrb_from_mbox(adapter); 3584 3585 req = embedded_payload(wrb); 3586 3587 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 3588 OPCODE_COMMON_SET_INTERRUPT_ENABLE, sizeof(*req), 3589 wrb, NULL); 3590 3591 req->intr_enabled = intr_enable; 3592 3593 status = be_mbox_notify_wait(adapter); 3594 3595 mutex_unlock(&adapter->mbox_lock); 3596 return status; 3597 } 3598 3599 int be_roce_mcc_cmd(void *netdev_handle, void *wrb_payload, 3600 int wrb_payload_size, u16 *cmd_status, u16 *ext_status) 3601 { 3602 struct be_adapter *adapter = netdev_priv(netdev_handle); 3603 struct be_mcc_wrb *wrb; 3604 struct be_cmd_req_hdr *hdr = (struct be_cmd_req_hdr *) wrb_payload; 3605 struct be_cmd_req_hdr *req; 3606 struct be_cmd_resp_hdr *resp; 3607 int status; 3608 3609 spin_lock_bh(&adapter->mcc_lock); 3610 3611 wrb = wrb_from_mccq(adapter); 3612 if (!wrb) { 3613 status = -EBUSY; 3614 goto err; 3615 } 3616 req = embedded_payload(wrb); 3617 resp = embedded_payload(wrb); 3618 3619 be_wrb_cmd_hdr_prepare(req, hdr->subsystem, 3620 hdr->opcode, wrb_payload_size, wrb, NULL); 3621 memcpy(req, wrb_payload, wrb_payload_size); 3622 be_dws_cpu_to_le(req, wrb_payload_size); 3623 3624 status = be_mcc_notify_wait(adapter); 3625 if (cmd_status) 3626 *cmd_status = (status & 0xffff); 3627 if (ext_status) 3628 *ext_status = 0; 3629 memcpy(wrb_payload, resp, sizeof(*resp) + resp->response_length); 3630 be_dws_le_to_cpu(wrb_payload, sizeof(*resp) + resp->response_length); 3631 err: 3632 spin_unlock_bh(&adapter->mcc_lock); 3633 return status; 3634 } 3635 EXPORT_SYMBOL(be_roce_mcc_cmd); 3636