1 /* 2 * Copyright (C) 2005 - 2013 Emulex 3 * All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License version 2 7 * as published by the Free Software Foundation. The full GNU General 8 * Public License is included in this distribution in the file called COPYING. 9 * 10 * Contact Information: 11 * linux-drivers@emulex.com 12 * 13 * Emulex 14 * 3333 Susan Street 15 * Costa Mesa, CA 92626 16 */ 17 18 #ifndef BE_H 19 #define BE_H 20 21 #include <linux/pci.h> 22 #include <linux/etherdevice.h> 23 #include <linux/delay.h> 24 #include <net/tcp.h> 25 #include <net/ip.h> 26 #include <net/ipv6.h> 27 #include <linux/if_vlan.h> 28 #include <linux/workqueue.h> 29 #include <linux/interrupt.h> 30 #include <linux/firmware.h> 31 #include <linux/slab.h> 32 #include <linux/u64_stats_sync.h> 33 34 #include "be_hw.h" 35 #include "be_roce.h" 36 37 #define DRV_VER "4.9.224.0u" 38 #define DRV_NAME "be2net" 39 #define BE_NAME "Emulex BladeEngine2" 40 #define BE3_NAME "Emulex BladeEngine3" 41 #define OC_NAME "Emulex OneConnect" 42 #define OC_NAME_BE OC_NAME "(be3)" 43 #define OC_NAME_LANCER OC_NAME "(Lancer)" 44 #define OC_NAME_SH OC_NAME "(Skyhawk)" 45 #define DRV_DESC "Emulex OneConnect 10Gbps NIC Driver" 46 47 #define BE_VENDOR_ID 0x19a2 48 #define EMULEX_VENDOR_ID 0x10df 49 #define BE_DEVICE_ID1 0x211 50 #define BE_DEVICE_ID2 0x221 51 #define OC_DEVICE_ID1 0x700 /* Device Id for BE2 cards */ 52 #define OC_DEVICE_ID2 0x710 /* Device Id for BE3 cards */ 53 #define OC_DEVICE_ID3 0xe220 /* Device id for Lancer cards */ 54 #define OC_DEVICE_ID4 0xe228 /* Device id for VF in Lancer */ 55 #define OC_DEVICE_ID5 0x720 /* Device Id for Skyhawk cards */ 56 #define OC_DEVICE_ID6 0x728 /* Device id for VF in SkyHawk */ 57 #define OC_SUBSYS_DEVICE_ID1 0xE602 58 #define OC_SUBSYS_DEVICE_ID2 0xE642 59 #define OC_SUBSYS_DEVICE_ID3 0xE612 60 #define OC_SUBSYS_DEVICE_ID4 0xE652 61 62 static inline char *nic_name(struct pci_dev *pdev) 63 { 64 switch (pdev->device) { 65 case OC_DEVICE_ID1: 66 return OC_NAME; 67 case OC_DEVICE_ID2: 68 return OC_NAME_BE; 69 case OC_DEVICE_ID3: 70 case OC_DEVICE_ID4: 71 return OC_NAME_LANCER; 72 case BE_DEVICE_ID2: 73 return BE3_NAME; 74 case OC_DEVICE_ID5: 75 case OC_DEVICE_ID6: 76 return OC_NAME_SH; 77 default: 78 return BE_NAME; 79 } 80 } 81 82 /* Number of bytes of an RX frame that are copied to skb->data */ 83 #define BE_HDR_LEN ((u16) 64) 84 /* allocate extra space to allow tunneling decapsulation without head reallocation */ 85 #define BE_RX_SKB_ALLOC_SIZE (BE_HDR_LEN + 64) 86 87 #define BE_MAX_JUMBO_FRAME_SIZE 9018 88 #define BE_MIN_MTU 256 89 90 #define BE_NUM_VLANS_SUPPORTED 64 91 #define BE_UMC_NUM_VLANS_SUPPORTED 15 92 #define BE_MAX_EQD 128u 93 #define BE_MAX_TX_FRAG_COUNT 30 94 95 #define EVNT_Q_LEN 1024 96 #define TX_Q_LEN 2048 97 #define TX_CQ_LEN 1024 98 #define RX_Q_LEN 1024 /* Does not support any other value */ 99 #define RX_CQ_LEN 1024 100 #define MCC_Q_LEN 128 /* total size not to exceed 8 pages */ 101 #define MCC_CQ_LEN 256 102 103 #define BE2_MAX_RSS_QS 4 104 #define BE3_MAX_RSS_QS 16 105 #define BE3_MAX_TX_QS 16 106 #define BE3_MAX_EVT_QS 16 107 108 #define MAX_RX_QS 32 109 #define MAX_EVT_QS 32 110 #define MAX_TX_QS 32 111 112 #define MAX_ROCE_EQS 5 113 #define MAX_MSIX_VECTORS 32 114 #define MIN_MSIX_VECTORS 1 115 #define BE_TX_BUDGET 256 116 #define BE_NAPI_WEIGHT 64 117 #define MAX_RX_POST BE_NAPI_WEIGHT /* Frags posted at a time */ 118 #define RX_FRAGS_REFILL_WM (RX_Q_LEN - MAX_RX_POST) 119 120 #define MAX_VFS 30 /* Max VFs supported by BE3 FW */ 121 #define FW_VER_LEN 32 122 123 struct be_dma_mem { 124 void *va; 125 dma_addr_t dma; 126 u32 size; 127 }; 128 129 struct be_queue_info { 130 struct be_dma_mem dma_mem; 131 u16 len; 132 u16 entry_size; /* Size of an element in the queue */ 133 u16 id; 134 u16 tail, head; 135 bool created; 136 atomic_t used; /* Number of valid elements in the queue */ 137 }; 138 139 static inline u32 MODULO(u16 val, u16 limit) 140 { 141 BUG_ON(limit & (limit - 1)); 142 return val & (limit - 1); 143 } 144 145 static inline void index_adv(u16 *index, u16 val, u16 limit) 146 { 147 *index = MODULO((*index + val), limit); 148 } 149 150 static inline void index_inc(u16 *index, u16 limit) 151 { 152 *index = MODULO((*index + 1), limit); 153 } 154 155 static inline void *queue_head_node(struct be_queue_info *q) 156 { 157 return q->dma_mem.va + q->head * q->entry_size; 158 } 159 160 static inline void *queue_tail_node(struct be_queue_info *q) 161 { 162 return q->dma_mem.va + q->tail * q->entry_size; 163 } 164 165 static inline void *queue_index_node(struct be_queue_info *q, u16 index) 166 { 167 return q->dma_mem.va + index * q->entry_size; 168 } 169 170 static inline void queue_head_inc(struct be_queue_info *q) 171 { 172 index_inc(&q->head, q->len); 173 } 174 175 static inline void index_dec(u16 *index, u16 limit) 176 { 177 *index = MODULO((*index - 1), limit); 178 } 179 180 static inline void queue_tail_inc(struct be_queue_info *q) 181 { 182 index_inc(&q->tail, q->len); 183 } 184 185 struct be_eq_obj { 186 struct be_queue_info q; 187 char desc[32]; 188 189 /* Adaptive interrupt coalescing (AIC) info */ 190 bool enable_aic; 191 u32 min_eqd; /* in usecs */ 192 u32 max_eqd; /* in usecs */ 193 u32 eqd; /* configured val when aic is off */ 194 u32 cur_eqd; /* in usecs */ 195 196 u8 idx; /* array index */ 197 u8 msix_idx; 198 u16 tx_budget; 199 u16 spurious_intr; 200 struct napi_struct napi; 201 struct be_adapter *adapter; 202 203 #ifdef CONFIG_NET_RX_BUSY_POLL 204 #define BE_EQ_IDLE 0 205 #define BE_EQ_NAPI 1 /* napi owns this EQ */ 206 #define BE_EQ_POLL 2 /* poll owns this EQ */ 207 #define BE_EQ_LOCKED (BE_EQ_NAPI | BE_EQ_POLL) 208 #define BE_EQ_NAPI_YIELD 4 /* napi yielded this EQ */ 209 #define BE_EQ_POLL_YIELD 8 /* poll yielded this EQ */ 210 #define BE_EQ_YIELD (BE_EQ_NAPI_YIELD | BE_EQ_POLL_YIELD) 211 #define BE_EQ_USER_PEND (BE_EQ_POLL | BE_EQ_POLL_YIELD) 212 unsigned int state; 213 spinlock_t lock; /* lock to serialize napi and busy-poll */ 214 #endif /* CONFIG_NET_RX_BUSY_POLL */ 215 } ____cacheline_aligned_in_smp; 216 217 struct be_aic_obj { /* Adaptive interrupt coalescing (AIC) info */ 218 bool enable; 219 u32 min_eqd; /* in usecs */ 220 u32 max_eqd; /* in usecs */ 221 u32 prev_eqd; /* in usecs */ 222 u32 et_eqd; /* configured val when aic is off */ 223 ulong jiffies; 224 u64 rx_pkts_prev; /* Used to calculate RX pps */ 225 u64 tx_reqs_prev; /* Used to calculate TX pps */ 226 }; 227 228 enum { 229 NAPI_POLLING, 230 BUSY_POLLING 231 }; 232 233 struct be_mcc_obj { 234 struct be_queue_info q; 235 struct be_queue_info cq; 236 bool rearm_cq; 237 }; 238 239 struct be_tx_stats { 240 u64 tx_bytes; 241 u64 tx_pkts; 242 u64 tx_reqs; 243 u64 tx_wrbs; 244 u64 tx_compl; 245 ulong tx_jiffies; 246 u32 tx_stops; 247 u32 tx_drv_drops; /* pkts dropped by driver */ 248 struct u64_stats_sync sync; 249 struct u64_stats_sync sync_compl; 250 }; 251 252 struct be_tx_obj { 253 u32 db_offset; 254 struct be_queue_info q; 255 struct be_queue_info cq; 256 /* Remember the skbs that were transmitted */ 257 struct sk_buff *sent_skb_list[TX_Q_LEN]; 258 struct be_tx_stats stats; 259 } ____cacheline_aligned_in_smp; 260 261 /* Struct to remember the pages posted for rx frags */ 262 struct be_rx_page_info { 263 struct page *page; 264 DEFINE_DMA_UNMAP_ADDR(bus); 265 u16 page_offset; 266 bool last_page_user; 267 }; 268 269 struct be_rx_stats { 270 u64 rx_bytes; 271 u64 rx_pkts; 272 u32 rx_drops_no_skbs; /* skb allocation errors */ 273 u32 rx_drops_no_frags; /* HW has no fetched frags */ 274 u32 rx_post_fail; /* page post alloc failures */ 275 u32 rx_compl; 276 u32 rx_mcast_pkts; 277 u32 rx_compl_err; /* completions with err set */ 278 struct u64_stats_sync sync; 279 }; 280 281 struct be_rx_compl_info { 282 u32 rss_hash; 283 u16 vlan_tag; 284 u16 pkt_size; 285 u16 rxq_idx; 286 u16 port; 287 u8 vlanf; 288 u8 num_rcvd; 289 u8 err; 290 u8 ipf; 291 u8 tcpf; 292 u8 udpf; 293 u8 ip_csum; 294 u8 l4_csum; 295 u8 ipv6; 296 u8 vtm; 297 u8 pkt_type; 298 u8 ip_frag; 299 }; 300 301 struct be_rx_obj { 302 struct be_adapter *adapter; 303 struct be_queue_info q; 304 struct be_queue_info cq; 305 struct be_rx_compl_info rxcp; 306 struct be_rx_page_info page_info_tbl[RX_Q_LEN]; 307 struct be_rx_stats stats; 308 u8 rss_id; 309 bool rx_post_starved; /* Zero rx frags have been posted to BE */ 310 } ____cacheline_aligned_in_smp; 311 312 struct be_drv_stats { 313 u32 be_on_die_temperature; 314 u32 eth_red_drops; 315 u32 rx_drops_no_pbuf; 316 u32 rx_drops_no_txpb; 317 u32 rx_drops_no_erx_descr; 318 u32 rx_drops_no_tpre_descr; 319 u32 rx_drops_too_many_frags; 320 u32 forwarded_packets; 321 u32 rx_drops_mtu; 322 u32 rx_crc_errors; 323 u32 rx_alignment_symbol_errors; 324 u32 rx_pause_frames; 325 u32 rx_priority_pause_frames; 326 u32 rx_control_frames; 327 u32 rx_in_range_errors; 328 u32 rx_out_range_errors; 329 u32 rx_frame_too_long; 330 u32 rx_address_filtered; 331 u32 rx_dropped_too_small; 332 u32 rx_dropped_too_short; 333 u32 rx_dropped_header_too_small; 334 u32 rx_dropped_tcp_length; 335 u32 rx_dropped_runt; 336 u32 rx_ip_checksum_errs; 337 u32 rx_tcp_checksum_errs; 338 u32 rx_udp_checksum_errs; 339 u32 tx_pauseframes; 340 u32 tx_priority_pauseframes; 341 u32 tx_controlframes; 342 u32 rxpp_fifo_overflow_drop; 343 u32 rx_input_fifo_overflow_drop; 344 u32 pmem_fifo_overflow_drop; 345 u32 jabber_events; 346 u32 rx_roce_bytes_lsd; 347 u32 rx_roce_bytes_msd; 348 u32 rx_roce_frames; 349 u32 roce_drops_payload_len; 350 u32 roce_drops_crc; 351 }; 352 353 struct be_vf_cfg { 354 unsigned char mac_addr[ETH_ALEN]; 355 int if_handle; 356 int pmac_id; 357 u16 def_vid; 358 u16 vlan_tag; 359 u32 tx_rate; 360 }; 361 362 enum vf_state { 363 ENABLED = 0, 364 ASSIGNED = 1 365 }; 366 367 #define BE_FLAGS_LINK_STATUS_INIT 1 368 #define BE_FLAGS_WORKER_SCHEDULED (1 << 3) 369 #define BE_FLAGS_VLAN_PROMISC (1 << 4) 370 #define BE_FLAGS_NAPI_ENABLED (1 << 9) 371 #define BE_UC_PMAC_COUNT 30 372 #define BE_VF_UC_PMAC_COUNT 2 373 #define BE_FLAGS_QNQ_ASYNC_EVT_RCVD (1 << 11) 374 375 /* Ethtool set_dump flags */ 376 #define LANCER_INITIATE_FW_DUMP 0x1 377 378 struct phy_info { 379 u8 transceiver; 380 u8 autoneg; 381 u8 fc_autoneg; 382 u8 port_type; 383 u16 phy_type; 384 u16 interface_type; 385 u32 misc_params; 386 u16 auto_speeds_supported; 387 u16 fixed_speeds_supported; 388 int link_speed; 389 u32 dac_cable_len; 390 u32 advertising; 391 u32 supported; 392 }; 393 394 struct be_resources { 395 u16 max_vfs; /* Total VFs "really" supported by FW/HW */ 396 u16 max_mcast_mac; 397 u16 max_tx_qs; 398 u16 max_rss_qs; 399 u16 max_rx_qs; 400 u16 max_uc_mac; /* Max UC MACs programmable */ 401 u16 max_vlans; /* Number of vlans supported */ 402 u16 max_evt_qs; 403 u32 if_cap_flags; 404 }; 405 406 struct be_adapter { 407 struct pci_dev *pdev; 408 struct net_device *netdev; 409 410 u8 __iomem *csr; /* CSR BAR used only for BE2/3 */ 411 u8 __iomem *db; /* Door Bell */ 412 413 struct mutex mbox_lock; /* For serializing mbox cmds to BE card */ 414 struct be_dma_mem mbox_mem; 415 /* Mbox mem is adjusted to align to 16 bytes. The allocated addr 416 * is stored for freeing purpose */ 417 struct be_dma_mem mbox_mem_alloced; 418 419 struct be_mcc_obj mcc_obj; 420 spinlock_t mcc_lock; /* For serializing mcc cmds to BE card */ 421 spinlock_t mcc_cq_lock; 422 423 u16 cfg_num_qs; /* configured via set-channels */ 424 u16 num_evt_qs; 425 u16 num_msix_vec; 426 struct be_eq_obj eq_obj[MAX_EVT_QS]; 427 struct msix_entry msix_entries[MAX_MSIX_VECTORS]; 428 bool isr_registered; 429 430 /* TX Rings */ 431 u16 num_tx_qs; 432 struct be_tx_obj tx_obj[MAX_TX_QS]; 433 434 /* Rx rings */ 435 u16 num_rx_qs; 436 struct be_rx_obj rx_obj[MAX_RX_QS]; 437 u32 big_page_size; /* Compounded page size shared by rx wrbs */ 438 439 struct be_drv_stats drv_stats; 440 struct be_aic_obj aic_obj[MAX_EVT_QS]; 441 u16 vlans_added; 442 u8 vlan_tag[VLAN_N_VID]; 443 u8 vlan_prio_bmap; /* Available Priority BitMap */ 444 u16 recommended_prio; /* Recommended Priority */ 445 struct be_dma_mem rx_filter; /* Cmd DMA mem for rx-filter */ 446 447 struct be_dma_mem stats_cmd; 448 /* Work queue used to perform periodic tasks like getting statistics */ 449 struct delayed_work work; 450 u16 work_counter; 451 452 struct delayed_work func_recovery_work; 453 u32 flags; 454 u32 cmd_privileges; 455 /* Ethtool knobs and info */ 456 char fw_ver[FW_VER_LEN]; 457 char fw_on_flash[FW_VER_LEN]; 458 int if_handle; /* Used to configure filtering */ 459 u32 *pmac_id; /* MAC addr handle used by BE card */ 460 u32 beacon_state; /* for set_phys_id */ 461 462 bool eeh_error; 463 bool fw_timeout; 464 bool hw_error; 465 466 u32 port_num; 467 bool promiscuous; 468 u32 function_mode; 469 u32 function_caps; 470 u32 rx_fc; /* Rx flow control */ 471 u32 tx_fc; /* Tx flow control */ 472 bool stats_cmd_sent; 473 struct { 474 u32 size; 475 u32 total_size; 476 u64 io_addr; 477 } roce_db; 478 u32 num_msix_roce_vec; 479 struct ocrdma_dev *ocrdma_dev; 480 struct list_head entry; 481 482 u32 flash_status; 483 struct completion flash_compl; 484 485 struct be_resources res; /* resources available for the func */ 486 u16 num_vfs; /* Number of VFs provisioned by PF */ 487 u8 virtfn; 488 struct be_vf_cfg *vf_cfg; 489 bool be3_native; 490 u32 sli_family; 491 u8 hba_port_num; 492 u16 pvid; 493 struct phy_info phy; 494 u8 wol_cap; 495 bool wol; 496 u32 uc_macs; /* Count of secondary UC MAC programmed */ 497 u16 asic_rev; 498 u16 qnq_vid; 499 u32 msg_enable; 500 int be_get_temp_freq; 501 u8 pf_number; 502 u64 rss_flags; 503 }; 504 505 #define be_physfn(adapter) (!adapter->virtfn) 506 #define be_virtfn(adapter) (adapter->virtfn) 507 #define sriov_enabled(adapter) (adapter->num_vfs > 0) 508 #define sriov_want(adapter) (be_physfn(adapter) && \ 509 (num_vfs || pci_num_vf(adapter->pdev))) 510 #define for_all_vfs(adapter, vf_cfg, i) \ 511 for (i = 0, vf_cfg = &adapter->vf_cfg[i]; i < adapter->num_vfs; \ 512 i++, vf_cfg++) 513 514 #define ON 1 515 #define OFF 0 516 517 #define be_max_vlans(adapter) (adapter->res.max_vlans) 518 #define be_max_uc(adapter) (adapter->res.max_uc_mac) 519 #define be_max_mc(adapter) (adapter->res.max_mcast_mac) 520 #define be_max_vfs(adapter) (adapter->res.max_vfs) 521 #define be_max_rss(adapter) (adapter->res.max_rss_qs) 522 #define be_max_txqs(adapter) (adapter->res.max_tx_qs) 523 #define be_max_prio_txqs(adapter) (adapter->res.max_prio_tx_qs) 524 #define be_max_rxqs(adapter) (adapter->res.max_rx_qs) 525 #define be_max_eqs(adapter) (adapter->res.max_evt_qs) 526 #define be_if_cap_flags(adapter) (adapter->res.if_cap_flags) 527 528 static inline u16 be_max_qs(struct be_adapter *adapter) 529 { 530 /* If no RSS, need atleast the one def RXQ */ 531 u16 num = max_t(u16, be_max_rss(adapter), 1); 532 533 num = min(num, be_max_eqs(adapter)); 534 return min_t(u16, num, num_online_cpus()); 535 } 536 537 #define lancer_chip(adapter) (adapter->pdev->device == OC_DEVICE_ID3 || \ 538 adapter->pdev->device == OC_DEVICE_ID4) 539 540 #define skyhawk_chip(adapter) (adapter->pdev->device == OC_DEVICE_ID5 || \ 541 adapter->pdev->device == OC_DEVICE_ID6) 542 543 #define BE3_chip(adapter) (adapter->pdev->device == BE_DEVICE_ID2 || \ 544 adapter->pdev->device == OC_DEVICE_ID2) 545 546 #define BE2_chip(adapter) (adapter->pdev->device == BE_DEVICE_ID1 || \ 547 adapter->pdev->device == OC_DEVICE_ID1) 548 549 #define BEx_chip(adapter) (BE3_chip(adapter) || BE2_chip(adapter)) 550 551 #define be_roce_supported(adapter) (skyhawk_chip(adapter) && \ 552 (adapter->function_mode & RDMA_ENABLED)) 553 554 extern const struct ethtool_ops be_ethtool_ops; 555 556 #define msix_enabled(adapter) (adapter->num_msix_vec > 0) 557 #define num_irqs(adapter) (msix_enabled(adapter) ? \ 558 adapter->num_msix_vec : 1) 559 #define tx_stats(txo) (&(txo)->stats) 560 #define rx_stats(rxo) (&(rxo)->stats) 561 562 /* The default RXQ is the last RXQ */ 563 #define default_rxo(adpt) (&adpt->rx_obj[adpt->num_rx_qs - 1]) 564 565 #define for_all_rx_queues(adapter, rxo, i) \ 566 for (i = 0, rxo = &adapter->rx_obj[i]; i < adapter->num_rx_qs; \ 567 i++, rxo++) 568 569 /* Skip the default non-rss queue (last one)*/ 570 #define for_all_rss_queues(adapter, rxo, i) \ 571 for (i = 0, rxo = &adapter->rx_obj[i]; i < (adapter->num_rx_qs - 1);\ 572 i++, rxo++) 573 574 #define for_all_tx_queues(adapter, txo, i) \ 575 for (i = 0, txo = &adapter->tx_obj[i]; i < adapter->num_tx_qs; \ 576 i++, txo++) 577 578 #define for_all_evt_queues(adapter, eqo, i) \ 579 for (i = 0, eqo = &adapter->eq_obj[i]; i < adapter->num_evt_qs; \ 580 i++, eqo++) 581 582 #define for_all_rx_queues_on_eq(adapter, eqo, rxo, i) \ 583 for (i = eqo->idx, rxo = &adapter->rx_obj[i]; i < adapter->num_rx_qs;\ 584 i += adapter->num_evt_qs, rxo += adapter->num_evt_qs) 585 586 #define is_mcc_eqo(eqo) (eqo->idx == 0) 587 #define mcc_eqo(adapter) (&adapter->eq_obj[0]) 588 589 #define PAGE_SHIFT_4K 12 590 #define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K) 591 592 /* Returns number of pages spanned by the data starting at the given addr */ 593 #define PAGES_4K_SPANNED(_address, size) \ 594 ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + \ 595 (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K)) 596 597 /* Returns bit offset within a DWORD of a bitfield */ 598 #define AMAP_BIT_OFFSET(_struct, field) \ 599 (((size_t)&(((_struct *)0)->field))%32) 600 601 /* Returns the bit mask of the field that is NOT shifted into location. */ 602 static inline u32 amap_mask(u32 bitsize) 603 { 604 return (bitsize == 32 ? 0xFFFFFFFF : (1 << bitsize) - 1); 605 } 606 607 static inline void 608 amap_set(void *ptr, u32 dw_offset, u32 mask, u32 offset, u32 value) 609 { 610 u32 *dw = (u32 *) ptr + dw_offset; 611 *dw &= ~(mask << offset); 612 *dw |= (mask & value) << offset; 613 } 614 615 #define AMAP_SET_BITS(_struct, field, ptr, val) \ 616 amap_set(ptr, \ 617 offsetof(_struct, field)/32, \ 618 amap_mask(sizeof(((_struct *)0)->field)), \ 619 AMAP_BIT_OFFSET(_struct, field), \ 620 val) 621 622 static inline u32 amap_get(void *ptr, u32 dw_offset, u32 mask, u32 offset) 623 { 624 u32 *dw = (u32 *) ptr; 625 return mask & (*(dw + dw_offset) >> offset); 626 } 627 628 #define AMAP_GET_BITS(_struct, field, ptr) \ 629 amap_get(ptr, \ 630 offsetof(_struct, field)/32, \ 631 amap_mask(sizeof(((_struct *)0)->field)), \ 632 AMAP_BIT_OFFSET(_struct, field)) 633 634 #define be_dws_cpu_to_le(wrb, len) swap_dws(wrb, len) 635 #define be_dws_le_to_cpu(wrb, len) swap_dws(wrb, len) 636 static inline void swap_dws(void *wrb, int len) 637 { 638 #ifdef __BIG_ENDIAN 639 u32 *dw = wrb; 640 BUG_ON(len % 4); 641 do { 642 *dw = cpu_to_le32(*dw); 643 dw++; 644 len -= 4; 645 } while (len); 646 #endif /* __BIG_ENDIAN */ 647 } 648 649 static inline u8 is_tcp_pkt(struct sk_buff *skb) 650 { 651 u8 val = 0; 652 653 if (ip_hdr(skb)->version == 4) 654 val = (ip_hdr(skb)->protocol == IPPROTO_TCP); 655 else if (ip_hdr(skb)->version == 6) 656 val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_TCP); 657 658 return val; 659 } 660 661 static inline u8 is_udp_pkt(struct sk_buff *skb) 662 { 663 u8 val = 0; 664 665 if (ip_hdr(skb)->version == 4) 666 val = (ip_hdr(skb)->protocol == IPPROTO_UDP); 667 else if (ip_hdr(skb)->version == 6) 668 val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_UDP); 669 670 return val; 671 } 672 673 static inline bool is_ipv4_pkt(struct sk_buff *skb) 674 { 675 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4; 676 } 677 678 static inline void be_vf_eth_addr_generate(struct be_adapter *adapter, u8 *mac) 679 { 680 u32 addr; 681 682 addr = jhash(adapter->netdev->dev_addr, ETH_ALEN, 0); 683 684 mac[5] = (u8)(addr & 0xFF); 685 mac[4] = (u8)((addr >> 8) & 0xFF); 686 mac[3] = (u8)((addr >> 16) & 0xFF); 687 /* Use the OUI from the current MAC address */ 688 memcpy(mac, adapter->netdev->dev_addr, 3); 689 } 690 691 static inline bool be_multi_rxq(const struct be_adapter *adapter) 692 { 693 return adapter->num_rx_qs > 1; 694 } 695 696 static inline bool be_error(struct be_adapter *adapter) 697 { 698 return adapter->eeh_error || adapter->hw_error || adapter->fw_timeout; 699 } 700 701 static inline bool be_hw_error(struct be_adapter *adapter) 702 { 703 return adapter->eeh_error || adapter->hw_error; 704 } 705 706 static inline void be_clear_all_error(struct be_adapter *adapter) 707 { 708 adapter->eeh_error = false; 709 adapter->hw_error = false; 710 adapter->fw_timeout = false; 711 } 712 713 static inline bool be_is_wol_excluded(struct be_adapter *adapter) 714 { 715 struct pci_dev *pdev = adapter->pdev; 716 717 if (!be_physfn(adapter)) 718 return true; 719 720 switch (pdev->subsystem_device) { 721 case OC_SUBSYS_DEVICE_ID1: 722 case OC_SUBSYS_DEVICE_ID2: 723 case OC_SUBSYS_DEVICE_ID3: 724 case OC_SUBSYS_DEVICE_ID4: 725 return true; 726 default: 727 return false; 728 } 729 } 730 731 static inline int qnq_async_evt_rcvd(struct be_adapter *adapter) 732 { 733 return adapter->flags & BE_FLAGS_QNQ_ASYNC_EVT_RCVD; 734 } 735 736 #ifdef CONFIG_NET_RX_BUSY_POLL 737 static inline bool be_lock_napi(struct be_eq_obj *eqo) 738 { 739 bool status = true; 740 741 spin_lock(&eqo->lock); /* BH is already disabled */ 742 if (eqo->state & BE_EQ_LOCKED) { 743 WARN_ON(eqo->state & BE_EQ_NAPI); 744 eqo->state |= BE_EQ_NAPI_YIELD; 745 status = false; 746 } else { 747 eqo->state = BE_EQ_NAPI; 748 } 749 spin_unlock(&eqo->lock); 750 return status; 751 } 752 753 static inline void be_unlock_napi(struct be_eq_obj *eqo) 754 { 755 spin_lock(&eqo->lock); /* BH is already disabled */ 756 757 WARN_ON(eqo->state & (BE_EQ_POLL | BE_EQ_NAPI_YIELD)); 758 eqo->state = BE_EQ_IDLE; 759 760 spin_unlock(&eqo->lock); 761 } 762 763 static inline bool be_lock_busy_poll(struct be_eq_obj *eqo) 764 { 765 bool status = true; 766 767 spin_lock_bh(&eqo->lock); 768 if (eqo->state & BE_EQ_LOCKED) { 769 eqo->state |= BE_EQ_POLL_YIELD; 770 status = false; 771 } else { 772 eqo->state |= BE_EQ_POLL; 773 } 774 spin_unlock_bh(&eqo->lock); 775 return status; 776 } 777 778 static inline void be_unlock_busy_poll(struct be_eq_obj *eqo) 779 { 780 spin_lock_bh(&eqo->lock); 781 782 WARN_ON(eqo->state & (BE_EQ_NAPI)); 783 eqo->state = BE_EQ_IDLE; 784 785 spin_unlock_bh(&eqo->lock); 786 } 787 788 static inline void be_enable_busy_poll(struct be_eq_obj *eqo) 789 { 790 spin_lock_init(&eqo->lock); 791 eqo->state = BE_EQ_IDLE; 792 } 793 794 static inline void be_disable_busy_poll(struct be_eq_obj *eqo) 795 { 796 local_bh_disable(); 797 798 /* It's enough to just acquire napi lock on the eqo to stop 799 * be_busy_poll() from processing any queueus. 800 */ 801 while (!be_lock_napi(eqo)) 802 mdelay(1); 803 804 local_bh_enable(); 805 } 806 807 #else /* CONFIG_NET_RX_BUSY_POLL */ 808 809 static inline bool be_lock_napi(struct be_eq_obj *eqo) 810 { 811 return true; 812 } 813 814 static inline void be_unlock_napi(struct be_eq_obj *eqo) 815 { 816 } 817 818 static inline bool be_lock_busy_poll(struct be_eq_obj *eqo) 819 { 820 return false; 821 } 822 823 static inline void be_unlock_busy_poll(struct be_eq_obj *eqo) 824 { 825 } 826 827 static inline void be_enable_busy_poll(struct be_eq_obj *eqo) 828 { 829 } 830 831 static inline void be_disable_busy_poll(struct be_eq_obj *eqo) 832 { 833 } 834 #endif /* CONFIG_NET_RX_BUSY_POLL */ 835 836 void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm, 837 u16 num_popped); 838 void be_link_status_update(struct be_adapter *adapter, u8 link_status); 839 void be_parse_stats(struct be_adapter *adapter); 840 int be_load_fw(struct be_adapter *adapter, u8 *func); 841 bool be_is_wol_supported(struct be_adapter *adapter); 842 bool be_pause_supported(struct be_adapter *adapter); 843 u32 be_get_fw_log_level(struct be_adapter *adapter); 844 845 static inline int fw_major_num(const char *fw_ver) 846 { 847 int fw_major = 0; 848 849 sscanf(fw_ver, "%d.", &fw_major); 850 851 return fw_major; 852 } 853 854 int be_update_queues(struct be_adapter *adapter); 855 int be_poll(struct napi_struct *napi, int budget); 856 857 /* 858 * internal function to initialize-cleanup roce device. 859 */ 860 void be_roce_dev_add(struct be_adapter *); 861 void be_roce_dev_remove(struct be_adapter *); 862 863 /* 864 * internal function to open-close roce device during ifup-ifdown. 865 */ 866 void be_roce_dev_open(struct be_adapter *); 867 void be_roce_dev_close(struct be_adapter *); 868 869 #endif /* BE_H */ 870