1 /* 2 * Dave DNET Ethernet Controller driver 3 * 4 * Copyright (C) 2008 Dave S.r.l. <www.dave.eu> 5 * Copyright (C) 2009 Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 #include <linux/io.h> 12 #include <linux/module.h> 13 #include <linux/moduleparam.h> 14 #include <linux/kernel.h> 15 #include <linux/types.h> 16 #include <linux/slab.h> 17 #include <linux/delay.h> 18 #include <linux/interrupt.h> 19 #include <linux/netdevice.h> 20 #include <linux/etherdevice.h> 21 #include <linux/dma-mapping.h> 22 #include <linux/platform_device.h> 23 #include <linux/phy.h> 24 25 #include "dnet.h" 26 27 #undef DEBUG 28 29 /* function for reading internal MAC register */ 30 static u16 dnet_readw_mac(struct dnet *bp, u16 reg) 31 { 32 u16 data_read; 33 34 /* issue a read */ 35 dnet_writel(bp, reg, MACREG_ADDR); 36 37 /* since a read/write op to the MAC is very slow, 38 * we must wait before reading the data */ 39 ndelay(500); 40 41 /* read data read from the MAC register */ 42 data_read = dnet_readl(bp, MACREG_DATA); 43 44 /* all done */ 45 return data_read; 46 } 47 48 /* function for writing internal MAC register */ 49 static void dnet_writew_mac(struct dnet *bp, u16 reg, u16 val) 50 { 51 /* load data to write */ 52 dnet_writel(bp, val, MACREG_DATA); 53 54 /* issue a write */ 55 dnet_writel(bp, reg | DNET_INTERNAL_WRITE, MACREG_ADDR); 56 57 /* since a read/write op to the MAC is very slow, 58 * we must wait before exiting */ 59 ndelay(500); 60 } 61 62 static void __dnet_set_hwaddr(struct dnet *bp) 63 { 64 u16 tmp; 65 66 tmp = be16_to_cpup((__be16 *)bp->dev->dev_addr); 67 dnet_writew_mac(bp, DNET_INTERNAL_MAC_ADDR_0_REG, tmp); 68 tmp = be16_to_cpup((__be16 *)(bp->dev->dev_addr + 2)); 69 dnet_writew_mac(bp, DNET_INTERNAL_MAC_ADDR_1_REG, tmp); 70 tmp = be16_to_cpup((__be16 *)(bp->dev->dev_addr + 4)); 71 dnet_writew_mac(bp, DNET_INTERNAL_MAC_ADDR_2_REG, tmp); 72 } 73 74 static void dnet_get_hwaddr(struct dnet *bp) 75 { 76 u16 tmp; 77 u8 addr[6]; 78 79 /* 80 * from MAC docs: 81 * "Note that the MAC address is stored in the registers in Hexadecimal 82 * form. For example, to set the MAC Address to: AC-DE-48-00-00-80 83 * would require writing 0xAC (octet 0) to address 0x0B (high byte of 84 * Mac_addr[15:0]), 0xDE (octet 1) to address 0x0A (Low byte of 85 * Mac_addr[15:0]), 0x48 (octet 2) to address 0x0D (high byte of 86 * Mac_addr[15:0]), 0x00 (octet 3) to address 0x0C (Low byte of 87 * Mac_addr[15:0]), 0x00 (octet 4) to address 0x0F (high byte of 88 * Mac_addr[15:0]), and 0x80 (octet 5) to address * 0x0E (Low byte of 89 * Mac_addr[15:0]). 90 */ 91 tmp = dnet_readw_mac(bp, DNET_INTERNAL_MAC_ADDR_0_REG); 92 *((__be16 *)addr) = cpu_to_be16(tmp); 93 tmp = dnet_readw_mac(bp, DNET_INTERNAL_MAC_ADDR_1_REG); 94 *((__be16 *)(addr + 2)) = cpu_to_be16(tmp); 95 tmp = dnet_readw_mac(bp, DNET_INTERNAL_MAC_ADDR_2_REG); 96 *((__be16 *)(addr + 4)) = cpu_to_be16(tmp); 97 98 if (is_valid_ether_addr(addr)) 99 memcpy(bp->dev->dev_addr, addr, sizeof(addr)); 100 } 101 102 static int dnet_mdio_read(struct mii_bus *bus, int mii_id, int regnum) 103 { 104 struct dnet *bp = bus->priv; 105 u16 value; 106 107 while (!(dnet_readw_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG) 108 & DNET_INTERNAL_GMII_MNG_CMD_FIN)) 109 cpu_relax(); 110 111 /* only 5 bits allowed for phy-addr and reg_offset */ 112 mii_id &= 0x1f; 113 regnum &= 0x1f; 114 115 /* prepare reg_value for a read */ 116 value = (mii_id << 8); 117 value |= regnum; 118 119 /* write control word */ 120 dnet_writew_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG, value); 121 122 /* wait for end of transfer */ 123 while (!(dnet_readw_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG) 124 & DNET_INTERNAL_GMII_MNG_CMD_FIN)) 125 cpu_relax(); 126 127 value = dnet_readw_mac(bp, DNET_INTERNAL_GMII_MNG_DAT_REG); 128 129 pr_debug("mdio_read %02x:%02x <- %04x\n", mii_id, regnum, value); 130 131 return value; 132 } 133 134 static int dnet_mdio_write(struct mii_bus *bus, int mii_id, int regnum, 135 u16 value) 136 { 137 struct dnet *bp = bus->priv; 138 u16 tmp; 139 140 pr_debug("mdio_write %02x:%02x <- %04x\n", mii_id, regnum, value); 141 142 while (!(dnet_readw_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG) 143 & DNET_INTERNAL_GMII_MNG_CMD_FIN)) 144 cpu_relax(); 145 146 /* prepare for a write operation */ 147 tmp = (1 << 13); 148 149 /* only 5 bits allowed for phy-addr and reg_offset */ 150 mii_id &= 0x1f; 151 regnum &= 0x1f; 152 153 /* only 16 bits on data */ 154 value &= 0xffff; 155 156 /* prepare reg_value for a write */ 157 tmp |= (mii_id << 8); 158 tmp |= regnum; 159 160 /* write data to write first */ 161 dnet_writew_mac(bp, DNET_INTERNAL_GMII_MNG_DAT_REG, value); 162 163 /* write control word */ 164 dnet_writew_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG, tmp); 165 166 while (!(dnet_readw_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG) 167 & DNET_INTERNAL_GMII_MNG_CMD_FIN)) 168 cpu_relax(); 169 170 return 0; 171 } 172 173 static void dnet_handle_link_change(struct net_device *dev) 174 { 175 struct dnet *bp = netdev_priv(dev); 176 struct phy_device *phydev = bp->phy_dev; 177 unsigned long flags; 178 u32 mode_reg, ctl_reg; 179 180 int status_change = 0; 181 182 spin_lock_irqsave(&bp->lock, flags); 183 184 mode_reg = dnet_readw_mac(bp, DNET_INTERNAL_MODE_REG); 185 ctl_reg = dnet_readw_mac(bp, DNET_INTERNAL_RXTX_CONTROL_REG); 186 187 if (phydev->link) { 188 if (bp->duplex != phydev->duplex) { 189 if (phydev->duplex) 190 ctl_reg &= 191 ~(DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP); 192 else 193 ctl_reg |= 194 DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP; 195 196 bp->duplex = phydev->duplex; 197 status_change = 1; 198 } 199 200 if (bp->speed != phydev->speed) { 201 status_change = 1; 202 switch (phydev->speed) { 203 case 1000: 204 mode_reg |= DNET_INTERNAL_MODE_GBITEN; 205 break; 206 case 100: 207 case 10: 208 mode_reg &= ~DNET_INTERNAL_MODE_GBITEN; 209 break; 210 default: 211 printk(KERN_WARNING 212 "%s: Ack! Speed (%d) is not " 213 "10/100/1000!\n", dev->name, 214 phydev->speed); 215 break; 216 } 217 bp->speed = phydev->speed; 218 } 219 } 220 221 if (phydev->link != bp->link) { 222 if (phydev->link) { 223 mode_reg |= 224 (DNET_INTERNAL_MODE_RXEN | DNET_INTERNAL_MODE_TXEN); 225 } else { 226 mode_reg &= 227 ~(DNET_INTERNAL_MODE_RXEN | 228 DNET_INTERNAL_MODE_TXEN); 229 bp->speed = 0; 230 bp->duplex = -1; 231 } 232 bp->link = phydev->link; 233 234 status_change = 1; 235 } 236 237 if (status_change) { 238 dnet_writew_mac(bp, DNET_INTERNAL_RXTX_CONTROL_REG, ctl_reg); 239 dnet_writew_mac(bp, DNET_INTERNAL_MODE_REG, mode_reg); 240 } 241 242 spin_unlock_irqrestore(&bp->lock, flags); 243 244 if (status_change) { 245 if (phydev->link) 246 printk(KERN_INFO "%s: link up (%d/%s)\n", 247 dev->name, phydev->speed, 248 DUPLEX_FULL == phydev->duplex ? "Full" : "Half"); 249 else 250 printk(KERN_INFO "%s: link down\n", dev->name); 251 } 252 } 253 254 static int dnet_mii_probe(struct net_device *dev) 255 { 256 struct dnet *bp = netdev_priv(dev); 257 struct phy_device *phydev = NULL; 258 int phy_addr; 259 260 /* find the first phy */ 261 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) { 262 if (bp->mii_bus->phy_map[phy_addr]) { 263 phydev = bp->mii_bus->phy_map[phy_addr]; 264 break; 265 } 266 } 267 268 if (!phydev) { 269 printk(KERN_ERR "%s: no PHY found\n", dev->name); 270 return -ENODEV; 271 } 272 273 /* TODO : add pin_irq */ 274 275 /* attach the mac to the phy */ 276 if (bp->capabilities & DNET_HAS_RMII) { 277 phydev = phy_connect(dev, dev_name(&phydev->dev), 278 &dnet_handle_link_change, 279 PHY_INTERFACE_MODE_RMII); 280 } else { 281 phydev = phy_connect(dev, dev_name(&phydev->dev), 282 &dnet_handle_link_change, 283 PHY_INTERFACE_MODE_MII); 284 } 285 286 if (IS_ERR(phydev)) { 287 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name); 288 return PTR_ERR(phydev); 289 } 290 291 /* mask with MAC supported features */ 292 if (bp->capabilities & DNET_HAS_GIGABIT) 293 phydev->supported &= PHY_GBIT_FEATURES; 294 else 295 phydev->supported &= PHY_BASIC_FEATURES; 296 297 phydev->supported |= SUPPORTED_Asym_Pause | SUPPORTED_Pause; 298 299 phydev->advertising = phydev->supported; 300 301 bp->link = 0; 302 bp->speed = 0; 303 bp->duplex = -1; 304 bp->phy_dev = phydev; 305 306 return 0; 307 } 308 309 static int dnet_mii_init(struct dnet *bp) 310 { 311 int err, i; 312 313 bp->mii_bus = mdiobus_alloc(); 314 if (bp->mii_bus == NULL) 315 return -ENOMEM; 316 317 bp->mii_bus->name = "dnet_mii_bus"; 318 bp->mii_bus->read = &dnet_mdio_read; 319 bp->mii_bus->write = &dnet_mdio_write; 320 321 snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 322 bp->pdev->name, bp->pdev->id); 323 324 bp->mii_bus->priv = bp; 325 326 bp->mii_bus->irq = devm_kmalloc(&bp->pdev->dev, 327 sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL); 328 if (!bp->mii_bus->irq) { 329 err = -ENOMEM; 330 goto err_out; 331 } 332 333 for (i = 0; i < PHY_MAX_ADDR; i++) 334 bp->mii_bus->irq[i] = PHY_POLL; 335 336 if (mdiobus_register(bp->mii_bus)) { 337 err = -ENXIO; 338 goto err_out; 339 } 340 341 if (dnet_mii_probe(bp->dev) != 0) { 342 err = -ENXIO; 343 goto err_out_unregister_bus; 344 } 345 346 return 0; 347 348 err_out_unregister_bus: 349 mdiobus_unregister(bp->mii_bus); 350 err_out: 351 mdiobus_free(bp->mii_bus); 352 return err; 353 } 354 355 /* For Neptune board: LINK1000 as Link LED and TX as activity LED */ 356 static int dnet_phy_marvell_fixup(struct phy_device *phydev) 357 { 358 return phy_write(phydev, 0x18, 0x4148); 359 } 360 361 static void dnet_update_stats(struct dnet *bp) 362 { 363 u32 __iomem *reg = bp->regs + DNET_RX_PKT_IGNR_CNT; 364 u32 *p = &bp->hw_stats.rx_pkt_ignr; 365 u32 *end = &bp->hw_stats.rx_byte + 1; 366 367 WARN_ON((unsigned long)(end - p - 1) != 368 (DNET_RX_BYTE_CNT - DNET_RX_PKT_IGNR_CNT) / 4); 369 370 for (; p < end; p++, reg++) 371 *p += readl(reg); 372 373 reg = bp->regs + DNET_TX_UNICAST_CNT; 374 p = &bp->hw_stats.tx_unicast; 375 end = &bp->hw_stats.tx_byte + 1; 376 377 WARN_ON((unsigned long)(end - p - 1) != 378 (DNET_TX_BYTE_CNT - DNET_TX_UNICAST_CNT) / 4); 379 380 for (; p < end; p++, reg++) 381 *p += readl(reg); 382 } 383 384 static int dnet_poll(struct napi_struct *napi, int budget) 385 { 386 struct dnet *bp = container_of(napi, struct dnet, napi); 387 struct net_device *dev = bp->dev; 388 int npackets = 0; 389 unsigned int pkt_len; 390 struct sk_buff *skb; 391 unsigned int *data_ptr; 392 u32 int_enable; 393 u32 cmd_word; 394 int i; 395 396 while (npackets < budget) { 397 /* 398 * break out of while loop if there are no more 399 * packets waiting 400 */ 401 if (!(dnet_readl(bp, RX_FIFO_WCNT) >> 16)) 402 break; 403 404 cmd_word = dnet_readl(bp, RX_LEN_FIFO); 405 pkt_len = cmd_word & 0xFFFF; 406 407 if (cmd_word & 0xDF180000) 408 printk(KERN_ERR "%s packet receive error %x\n", 409 __func__, cmd_word); 410 411 skb = netdev_alloc_skb(dev, pkt_len + 5); 412 if (skb != NULL) { 413 /* Align IP on 16 byte boundaries */ 414 skb_reserve(skb, 2); 415 /* 416 * 'skb_put()' points to the start of sk_buff 417 * data area. 418 */ 419 data_ptr = (unsigned int *)skb_put(skb, pkt_len); 420 for (i = 0; i < (pkt_len + 3) >> 2; i++) 421 *data_ptr++ = dnet_readl(bp, RX_DATA_FIFO); 422 skb->protocol = eth_type_trans(skb, dev); 423 netif_receive_skb(skb); 424 npackets++; 425 } else 426 printk(KERN_NOTICE 427 "%s: No memory to allocate a sk_buff of " 428 "size %u.\n", dev->name, pkt_len); 429 } 430 431 if (npackets < budget) { 432 /* We processed all packets available. Tell NAPI it can 433 * stop polling then re-enable rx interrupts. 434 */ 435 napi_complete(napi); 436 int_enable = dnet_readl(bp, INTR_ENB); 437 int_enable |= DNET_INTR_SRC_RX_CMDFIFOAF; 438 dnet_writel(bp, int_enable, INTR_ENB); 439 } 440 441 return npackets; 442 } 443 444 static irqreturn_t dnet_interrupt(int irq, void *dev_id) 445 { 446 struct net_device *dev = dev_id; 447 struct dnet *bp = netdev_priv(dev); 448 u32 int_src, int_enable, int_current; 449 unsigned long flags; 450 unsigned int handled = 0; 451 452 spin_lock_irqsave(&bp->lock, flags); 453 454 /* read and clear the DNET irq (clear on read) */ 455 int_src = dnet_readl(bp, INTR_SRC); 456 int_enable = dnet_readl(bp, INTR_ENB); 457 int_current = int_src & int_enable; 458 459 /* restart the queue if we had stopped it for TX fifo almost full */ 460 if (int_current & DNET_INTR_SRC_TX_FIFOAE) { 461 int_enable = dnet_readl(bp, INTR_ENB); 462 int_enable &= ~DNET_INTR_ENB_TX_FIFOAE; 463 dnet_writel(bp, int_enable, INTR_ENB); 464 netif_wake_queue(dev); 465 handled = 1; 466 } 467 468 /* RX FIFO error checking */ 469 if (int_current & 470 (DNET_INTR_SRC_RX_CMDFIFOFF | DNET_INTR_SRC_RX_DATAFIFOFF)) { 471 printk(KERN_ERR "%s: RX fifo error %x, irq %x\n", __func__, 472 dnet_readl(bp, RX_STATUS), int_current); 473 /* we can only flush the RX FIFOs */ 474 dnet_writel(bp, DNET_SYS_CTL_RXFIFOFLUSH, SYS_CTL); 475 ndelay(500); 476 dnet_writel(bp, 0, SYS_CTL); 477 handled = 1; 478 } 479 480 /* TX FIFO error checking */ 481 if (int_current & 482 (DNET_INTR_SRC_TX_FIFOFULL | DNET_INTR_SRC_TX_DISCFRM)) { 483 printk(KERN_ERR "%s: TX fifo error %x, irq %x\n", __func__, 484 dnet_readl(bp, TX_STATUS), int_current); 485 /* we can only flush the TX FIFOs */ 486 dnet_writel(bp, DNET_SYS_CTL_TXFIFOFLUSH, SYS_CTL); 487 ndelay(500); 488 dnet_writel(bp, 0, SYS_CTL); 489 handled = 1; 490 } 491 492 if (int_current & DNET_INTR_SRC_RX_CMDFIFOAF) { 493 if (napi_schedule_prep(&bp->napi)) { 494 /* 495 * There's no point taking any more interrupts 496 * until we have processed the buffers 497 */ 498 /* Disable Rx interrupts and schedule NAPI poll */ 499 int_enable = dnet_readl(bp, INTR_ENB); 500 int_enable &= ~DNET_INTR_SRC_RX_CMDFIFOAF; 501 dnet_writel(bp, int_enable, INTR_ENB); 502 __napi_schedule(&bp->napi); 503 } 504 handled = 1; 505 } 506 507 if (!handled) 508 pr_debug("%s: irq %x remains\n", __func__, int_current); 509 510 spin_unlock_irqrestore(&bp->lock, flags); 511 512 return IRQ_RETVAL(handled); 513 } 514 515 #ifdef DEBUG 516 static inline void dnet_print_skb(struct sk_buff *skb) 517 { 518 int k; 519 printk(KERN_DEBUG PFX "data:"); 520 for (k = 0; k < skb->len; k++) 521 printk(" %02x", (unsigned int)skb->data[k]); 522 printk("\n"); 523 } 524 #else 525 #define dnet_print_skb(skb) do {} while (0) 526 #endif 527 528 static netdev_tx_t dnet_start_xmit(struct sk_buff *skb, struct net_device *dev) 529 { 530 531 struct dnet *bp = netdev_priv(dev); 532 u32 tx_status, irq_enable; 533 unsigned int len, i, tx_cmd, wrsz; 534 unsigned long flags; 535 unsigned int *bufp; 536 537 tx_status = dnet_readl(bp, TX_STATUS); 538 539 pr_debug("start_xmit: len %u head %p data %p\n", 540 skb->len, skb->head, skb->data); 541 dnet_print_skb(skb); 542 543 /* frame size (words) */ 544 len = (skb->len + 3) >> 2; 545 546 spin_lock_irqsave(&bp->lock, flags); 547 548 tx_status = dnet_readl(bp, TX_STATUS); 549 550 bufp = (unsigned int *)(((unsigned long) skb->data) & ~0x3UL); 551 wrsz = (u32) skb->len + 3; 552 wrsz += ((unsigned long) skb->data) & 0x3; 553 wrsz >>= 2; 554 tx_cmd = ((((unsigned long)(skb->data)) & 0x03) << 16) | (u32) skb->len; 555 556 /* check if there is enough room for the current frame */ 557 if (wrsz < (DNET_FIFO_SIZE - dnet_readl(bp, TX_FIFO_WCNT))) { 558 for (i = 0; i < wrsz; i++) 559 dnet_writel(bp, *bufp++, TX_DATA_FIFO); 560 561 /* 562 * inform MAC that a packet's written and ready to be 563 * shipped out 564 */ 565 dnet_writel(bp, tx_cmd, TX_LEN_FIFO); 566 } 567 568 if (dnet_readl(bp, TX_FIFO_WCNT) > DNET_FIFO_TX_DATA_AF_TH) { 569 netif_stop_queue(dev); 570 tx_status = dnet_readl(bp, INTR_SRC); 571 irq_enable = dnet_readl(bp, INTR_ENB); 572 irq_enable |= DNET_INTR_ENB_TX_FIFOAE; 573 dnet_writel(bp, irq_enable, INTR_ENB); 574 } 575 576 skb_tx_timestamp(skb); 577 578 /* free the buffer */ 579 dev_kfree_skb(skb); 580 581 spin_unlock_irqrestore(&bp->lock, flags); 582 583 return NETDEV_TX_OK; 584 } 585 586 static void dnet_reset_hw(struct dnet *bp) 587 { 588 /* put ts_mac in IDLE state i.e. disable rx/tx */ 589 dnet_writew_mac(bp, DNET_INTERNAL_MODE_REG, DNET_INTERNAL_MODE_FCEN); 590 591 /* 592 * RX FIFO almost full threshold: only cmd FIFO almost full is 593 * implemented for RX side 594 */ 595 dnet_writel(bp, DNET_FIFO_RX_CMD_AF_TH, RX_FIFO_TH); 596 /* 597 * TX FIFO almost empty threshold: only data FIFO almost empty 598 * is implemented for TX side 599 */ 600 dnet_writel(bp, DNET_FIFO_TX_DATA_AE_TH, TX_FIFO_TH); 601 602 /* flush rx/tx fifos */ 603 dnet_writel(bp, DNET_SYS_CTL_RXFIFOFLUSH | DNET_SYS_CTL_TXFIFOFLUSH, 604 SYS_CTL); 605 msleep(1); 606 dnet_writel(bp, 0, SYS_CTL); 607 } 608 609 static void dnet_init_hw(struct dnet *bp) 610 { 611 u32 config; 612 613 dnet_reset_hw(bp); 614 __dnet_set_hwaddr(bp); 615 616 config = dnet_readw_mac(bp, DNET_INTERNAL_RXTX_CONTROL_REG); 617 618 if (bp->dev->flags & IFF_PROMISC) 619 /* Copy All Frames */ 620 config |= DNET_INTERNAL_RXTX_CONTROL_ENPROMISC; 621 if (!(bp->dev->flags & IFF_BROADCAST)) 622 /* No BroadCast */ 623 config |= DNET_INTERNAL_RXTX_CONTROL_RXMULTICAST; 624 625 config |= DNET_INTERNAL_RXTX_CONTROL_RXPAUSE | 626 DNET_INTERNAL_RXTX_CONTROL_RXBROADCAST | 627 DNET_INTERNAL_RXTX_CONTROL_DROPCONTROL | 628 DNET_INTERNAL_RXTX_CONTROL_DISCFXFCS; 629 630 dnet_writew_mac(bp, DNET_INTERNAL_RXTX_CONTROL_REG, config); 631 632 /* clear irq before enabling them */ 633 config = dnet_readl(bp, INTR_SRC); 634 635 /* enable RX/TX interrupt, recv packet ready interrupt */ 636 dnet_writel(bp, DNET_INTR_ENB_GLOBAL_ENABLE | DNET_INTR_ENB_RX_SUMMARY | 637 DNET_INTR_ENB_TX_SUMMARY | DNET_INTR_ENB_RX_FIFOERR | 638 DNET_INTR_ENB_RX_ERROR | DNET_INTR_ENB_RX_FIFOFULL | 639 DNET_INTR_ENB_TX_FIFOFULL | DNET_INTR_ENB_TX_DISCFRM | 640 DNET_INTR_ENB_RX_PKTRDY, INTR_ENB); 641 } 642 643 static int dnet_open(struct net_device *dev) 644 { 645 struct dnet *bp = netdev_priv(dev); 646 647 /* if the phy is not yet register, retry later */ 648 if (!bp->phy_dev) 649 return -EAGAIN; 650 651 napi_enable(&bp->napi); 652 dnet_init_hw(bp); 653 654 phy_start_aneg(bp->phy_dev); 655 656 /* schedule a link state check */ 657 phy_start(bp->phy_dev); 658 659 netif_start_queue(dev); 660 661 return 0; 662 } 663 664 static int dnet_close(struct net_device *dev) 665 { 666 struct dnet *bp = netdev_priv(dev); 667 668 netif_stop_queue(dev); 669 napi_disable(&bp->napi); 670 671 if (bp->phy_dev) 672 phy_stop(bp->phy_dev); 673 674 dnet_reset_hw(bp); 675 netif_carrier_off(dev); 676 677 return 0; 678 } 679 680 static inline void dnet_print_pretty_hwstats(struct dnet_stats *hwstat) 681 { 682 pr_debug("%s\n", __func__); 683 pr_debug("----------------------------- RX statistics " 684 "-------------------------------\n"); 685 pr_debug("RX_PKT_IGNR_CNT %-8x\n", hwstat->rx_pkt_ignr); 686 pr_debug("RX_LEN_CHK_ERR_CNT %-8x\n", hwstat->rx_len_chk_err); 687 pr_debug("RX_LNG_FRM_CNT %-8x\n", hwstat->rx_lng_frm); 688 pr_debug("RX_SHRT_FRM_CNT %-8x\n", hwstat->rx_shrt_frm); 689 pr_debug("RX_IPG_VIOL_CNT %-8x\n", hwstat->rx_ipg_viol); 690 pr_debug("RX_CRC_ERR_CNT %-8x\n", hwstat->rx_crc_err); 691 pr_debug("RX_OK_PKT_CNT %-8x\n", hwstat->rx_ok_pkt); 692 pr_debug("RX_CTL_FRM_CNT %-8x\n", hwstat->rx_ctl_frm); 693 pr_debug("RX_PAUSE_FRM_CNT %-8x\n", hwstat->rx_pause_frm); 694 pr_debug("RX_MULTICAST_CNT %-8x\n", hwstat->rx_multicast); 695 pr_debug("RX_BROADCAST_CNT %-8x\n", hwstat->rx_broadcast); 696 pr_debug("RX_VLAN_TAG_CNT %-8x\n", hwstat->rx_vlan_tag); 697 pr_debug("RX_PRE_SHRINK_CNT %-8x\n", hwstat->rx_pre_shrink); 698 pr_debug("RX_DRIB_NIB_CNT %-8x\n", hwstat->rx_drib_nib); 699 pr_debug("RX_UNSUP_OPCD_CNT %-8x\n", hwstat->rx_unsup_opcd); 700 pr_debug("RX_BYTE_CNT %-8x\n", hwstat->rx_byte); 701 pr_debug("----------------------------- TX statistics " 702 "-------------------------------\n"); 703 pr_debug("TX_UNICAST_CNT %-8x\n", hwstat->tx_unicast); 704 pr_debug("TX_PAUSE_FRM_CNT %-8x\n", hwstat->tx_pause_frm); 705 pr_debug("TX_MULTICAST_CNT %-8x\n", hwstat->tx_multicast); 706 pr_debug("TX_BRDCAST_CNT %-8x\n", hwstat->tx_brdcast); 707 pr_debug("TX_VLAN_TAG_CNT %-8x\n", hwstat->tx_vlan_tag); 708 pr_debug("TX_BAD_FCS_CNT %-8x\n", hwstat->tx_bad_fcs); 709 pr_debug("TX_JUMBO_CNT %-8x\n", hwstat->tx_jumbo); 710 pr_debug("TX_BYTE_CNT %-8x\n", hwstat->tx_byte); 711 } 712 713 static struct net_device_stats *dnet_get_stats(struct net_device *dev) 714 { 715 716 struct dnet *bp = netdev_priv(dev); 717 struct net_device_stats *nstat = &dev->stats; 718 struct dnet_stats *hwstat = &bp->hw_stats; 719 720 /* read stats from hardware */ 721 dnet_update_stats(bp); 722 723 /* Convert HW stats into netdevice stats */ 724 nstat->rx_errors = (hwstat->rx_len_chk_err + 725 hwstat->rx_lng_frm + hwstat->rx_shrt_frm + 726 /* ignore IGP violation error 727 hwstat->rx_ipg_viol + */ 728 hwstat->rx_crc_err + 729 hwstat->rx_pre_shrink + 730 hwstat->rx_drib_nib + hwstat->rx_unsup_opcd); 731 nstat->tx_errors = hwstat->tx_bad_fcs; 732 nstat->rx_length_errors = (hwstat->rx_len_chk_err + 733 hwstat->rx_lng_frm + 734 hwstat->rx_shrt_frm + hwstat->rx_pre_shrink); 735 nstat->rx_crc_errors = hwstat->rx_crc_err; 736 nstat->rx_frame_errors = hwstat->rx_pre_shrink + hwstat->rx_drib_nib; 737 nstat->rx_packets = hwstat->rx_ok_pkt; 738 nstat->tx_packets = (hwstat->tx_unicast + 739 hwstat->tx_multicast + hwstat->tx_brdcast); 740 nstat->rx_bytes = hwstat->rx_byte; 741 nstat->tx_bytes = hwstat->tx_byte; 742 nstat->multicast = hwstat->rx_multicast; 743 nstat->rx_missed_errors = hwstat->rx_pkt_ignr; 744 745 dnet_print_pretty_hwstats(hwstat); 746 747 return nstat; 748 } 749 750 static int dnet_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 751 { 752 struct dnet *bp = netdev_priv(dev); 753 struct phy_device *phydev = bp->phy_dev; 754 755 if (!phydev) 756 return -ENODEV; 757 758 return phy_ethtool_gset(phydev, cmd); 759 } 760 761 static int dnet_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 762 { 763 struct dnet *bp = netdev_priv(dev); 764 struct phy_device *phydev = bp->phy_dev; 765 766 if (!phydev) 767 return -ENODEV; 768 769 return phy_ethtool_sset(phydev, cmd); 770 } 771 772 static int dnet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 773 { 774 struct dnet *bp = netdev_priv(dev); 775 struct phy_device *phydev = bp->phy_dev; 776 777 if (!netif_running(dev)) 778 return -EINVAL; 779 780 if (!phydev) 781 return -ENODEV; 782 783 return phy_mii_ioctl(phydev, rq, cmd); 784 } 785 786 static void dnet_get_drvinfo(struct net_device *dev, 787 struct ethtool_drvinfo *info) 788 { 789 strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); 790 strlcpy(info->version, DRV_VERSION, sizeof(info->version)); 791 strlcpy(info->bus_info, "0", sizeof(info->bus_info)); 792 } 793 794 static const struct ethtool_ops dnet_ethtool_ops = { 795 .get_settings = dnet_get_settings, 796 .set_settings = dnet_set_settings, 797 .get_drvinfo = dnet_get_drvinfo, 798 .get_link = ethtool_op_get_link, 799 .get_ts_info = ethtool_op_get_ts_info, 800 }; 801 802 static const struct net_device_ops dnet_netdev_ops = { 803 .ndo_open = dnet_open, 804 .ndo_stop = dnet_close, 805 .ndo_get_stats = dnet_get_stats, 806 .ndo_start_xmit = dnet_start_xmit, 807 .ndo_do_ioctl = dnet_ioctl, 808 .ndo_set_mac_address = eth_mac_addr, 809 .ndo_validate_addr = eth_validate_addr, 810 .ndo_change_mtu = eth_change_mtu, 811 }; 812 813 static int dnet_probe(struct platform_device *pdev) 814 { 815 struct resource *res; 816 struct net_device *dev; 817 struct dnet *bp; 818 struct phy_device *phydev; 819 int err; 820 unsigned int irq; 821 822 irq = platform_get_irq(pdev, 0); 823 824 dev = alloc_etherdev(sizeof(*bp)); 825 if (!dev) 826 return -ENOMEM; 827 828 /* TODO: Actually, we have some interesting features... */ 829 dev->features |= 0; 830 831 bp = netdev_priv(dev); 832 bp->dev = dev; 833 834 platform_set_drvdata(pdev, dev); 835 SET_NETDEV_DEV(dev, &pdev->dev); 836 837 spin_lock_init(&bp->lock); 838 839 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 840 bp->regs = devm_ioremap_resource(&pdev->dev, res); 841 if (IS_ERR(bp->regs)) { 842 err = PTR_ERR(bp->regs); 843 goto err_out_free_dev; 844 } 845 846 dev->irq = irq; 847 err = request_irq(dev->irq, dnet_interrupt, 0, DRV_NAME, dev); 848 if (err) { 849 dev_err(&pdev->dev, "Unable to request IRQ %d (error %d)\n", 850 irq, err); 851 goto err_out_free_dev; 852 } 853 854 dev->netdev_ops = &dnet_netdev_ops; 855 netif_napi_add(dev, &bp->napi, dnet_poll, 64); 856 dev->ethtool_ops = &dnet_ethtool_ops; 857 858 dev->base_addr = (unsigned long)bp->regs; 859 860 bp->capabilities = dnet_readl(bp, VERCAPS) & DNET_CAPS_MASK; 861 862 dnet_get_hwaddr(bp); 863 864 if (!is_valid_ether_addr(dev->dev_addr)) { 865 /* choose a random ethernet address */ 866 eth_hw_addr_random(dev); 867 __dnet_set_hwaddr(bp); 868 } 869 870 err = register_netdev(dev); 871 if (err) { 872 dev_err(&pdev->dev, "Cannot register net device, aborting.\n"); 873 goto err_out_free_irq; 874 } 875 876 /* register the PHY board fixup (for Marvell 88E1111) */ 877 err = phy_register_fixup_for_uid(0x01410cc0, 0xfffffff0, 878 dnet_phy_marvell_fixup); 879 /* we can live without it, so just issue a warning */ 880 if (err) 881 dev_warn(&pdev->dev, "Cannot register PHY board fixup.\n"); 882 883 err = dnet_mii_init(bp); 884 if (err) 885 goto err_out_unregister_netdev; 886 887 dev_info(&pdev->dev, "Dave DNET at 0x%p (0x%08x) irq %d %pM\n", 888 bp->regs, (unsigned int)res->start, dev->irq, dev->dev_addr); 889 dev_info(&pdev->dev, "has %smdio, %sirq, %sgigabit, %sdma\n", 890 (bp->capabilities & DNET_HAS_MDIO) ? "" : "no ", 891 (bp->capabilities & DNET_HAS_IRQ) ? "" : "no ", 892 (bp->capabilities & DNET_HAS_GIGABIT) ? "" : "no ", 893 (bp->capabilities & DNET_HAS_DMA) ? "" : "no "); 894 phydev = bp->phy_dev; 895 dev_info(&pdev->dev, "attached PHY driver [%s] " 896 "(mii_bus:phy_addr=%s, irq=%d)\n", 897 phydev->drv->name, dev_name(&phydev->dev), phydev->irq); 898 899 return 0; 900 901 err_out_unregister_netdev: 902 unregister_netdev(dev); 903 err_out_free_irq: 904 free_irq(dev->irq, dev); 905 err_out_free_dev: 906 free_netdev(dev); 907 return err; 908 } 909 910 static int dnet_remove(struct platform_device *pdev) 911 { 912 913 struct net_device *dev; 914 struct dnet *bp; 915 916 dev = platform_get_drvdata(pdev); 917 918 if (dev) { 919 bp = netdev_priv(dev); 920 if (bp->phy_dev) 921 phy_disconnect(bp->phy_dev); 922 mdiobus_unregister(bp->mii_bus); 923 mdiobus_free(bp->mii_bus); 924 unregister_netdev(dev); 925 free_irq(dev->irq, dev); 926 free_netdev(dev); 927 } 928 929 return 0; 930 } 931 932 static struct platform_driver dnet_driver = { 933 .probe = dnet_probe, 934 .remove = dnet_remove, 935 .driver = { 936 .name = "dnet", 937 }, 938 }; 939 940 module_platform_driver(dnet_driver); 941 942 MODULE_LICENSE("GPL"); 943 MODULE_DESCRIPTION("Dave DNET Ethernet driver"); 944 MODULE_AUTHOR("Ilya Yanok <yanok@emcraft.com>, " 945 "Matteo Vit <matteo.vit@dave.eu>"); 946