1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022 Davicom Semiconductor,Inc. 4 * Davicom DM9051 SPI Fast Ethernet Linux driver 5 */ 6 7 #ifndef _DM9051_H_ 8 #define _DM9051_H_ 9 10 #include <linux/bits.h> 11 #include <linux/netdevice.h> 12 #include <linux/types.h> 13 14 #define DM9051_ID 0x9051 15 16 #define DM9051_NCR 0x00 17 #define DM9051_NSR 0x01 18 #define DM9051_TCR 0x02 19 #define DM9051_RCR 0x05 20 #define DM9051_BPTR 0x08 21 #define DM9051_FCR 0x0A 22 #define DM9051_EPCR 0x0B 23 #define DM9051_EPAR 0x0C 24 #define DM9051_EPDRL 0x0D 25 #define DM9051_EPDRH 0x0E 26 #define DM9051_PAR 0x10 27 #define DM9051_MAR 0x16 28 #define DM9051_GPCR 0x1E 29 #define DM9051_GPR 0x1F 30 31 #define DM9051_VIDL 0x28 32 #define DM9051_VIDH 0x29 33 #define DM9051_PIDL 0x2A 34 #define DM9051_PIDH 0x2B 35 #define DM9051_SMCR 0x2F 36 #define DM9051_ATCR 0x30 37 #define DM9051_SPIBCR 0x38 38 #define DM9051_INTCR 0x39 39 #define DM9051_PPCR 0x3D 40 41 #define DM9051_MPCR 0x55 42 #define DM9051_LMCR 0x57 43 #define DM9051_MBNDRY 0x5E 44 45 #define DM9051_MRRL 0x74 46 #define DM9051_MRRH 0x75 47 #define DM9051_MWRL 0x7A 48 #define DM9051_MWRH 0x7B 49 #define DM9051_TXPLL 0x7C 50 #define DM9051_TXPLH 0x7D 51 #define DM9051_ISR 0x7E 52 #define DM9051_IMR 0x7F 53 54 #define DM_SPI_MRCMDX 0x70 55 #define DM_SPI_MRCMD 0x72 56 #define DM_SPI_MWCMD 0x78 57 58 #define DM_SPI_WR 0x80 59 60 /* dm9051 Ethernet controller registers bits 61 */ 62 /* 0x00 */ 63 #define NCR_WAKEEN BIT(6) 64 #define NCR_FDX BIT(3) 65 #define NCR_RST BIT(0) 66 /* 0x01 */ 67 #define NSR_SPEED BIT(7) 68 #define NSR_LINKST BIT(6) 69 #define NSR_WAKEST BIT(5) 70 #define NSR_TX2END BIT(3) 71 #define NSR_TX1END BIT(2) 72 /* 0x02 */ 73 #define TCR_DIS_JABBER_TIMER BIT(6) /* for Jabber Packet support */ 74 #define TCR_TXREQ BIT(0) 75 /* 0x05 */ 76 #define RCR_DIS_WATCHDOG_TIMER BIT(6) /* for Jabber Packet support */ 77 #define RCR_DIS_LONG BIT(5) 78 #define RCR_DIS_CRC BIT(4) 79 #define RCR_ALL BIT(3) 80 #define RCR_PRMSC BIT(1) 81 #define RCR_RXEN BIT(0) 82 #define RCR_RX_DISABLE (RCR_DIS_LONG | RCR_DIS_CRC) 83 /* 0x06 */ 84 #define RSR_RF BIT(7) 85 #define RSR_MF BIT(6) 86 #define RSR_LCS BIT(5) 87 #define RSR_RWTO BIT(4) 88 #define RSR_PLE BIT(3) 89 #define RSR_AE BIT(2) 90 #define RSR_CE BIT(1) 91 #define RSR_FOE BIT(0) 92 #define RSR_ERR_BITS (RSR_RF | RSR_LCS | RSR_RWTO | RSR_PLE | \ 93 RSR_AE | RSR_CE | RSR_FOE) 94 /* 0x0A */ 95 #define FCR_TXPEN BIT(5) 96 #define FCR_BKPM BIT(3) 97 #define FCR_FLCE BIT(0) 98 #define FCR_RXTX_BITS (FCR_TXPEN | FCR_BKPM | FCR_FLCE) 99 /* 0x0B */ 100 #define EPCR_WEP BIT(4) 101 #define EPCR_EPOS BIT(3) 102 #define EPCR_ERPRR BIT(2) 103 #define EPCR_ERPRW BIT(1) 104 #define EPCR_ERRE BIT(0) 105 /* 0x1E */ 106 #define GPCR_GEP_CNTL BIT(0) 107 /* 0x1F */ 108 #define GPR_PHY_OFF BIT(0) 109 /* 0x30 */ 110 #define ATCR_AUTO_TX BIT(7) 111 /* 0x39 */ 112 #define INTCR_POL_LOW (1 << 0) 113 #define INTCR_POL_HIGH (0 << 0) 114 /* 0x3D */ 115 /* Pause Packet Control Register - default = 1 */ 116 #define PPCR_PAUSE_COUNT 0x08 117 /* 0x55 */ 118 #define MPCR_RSTTX BIT(1) 119 #define MPCR_RSTRX BIT(0) 120 /* 0x57 */ 121 /* LEDMode Control Register - LEDMode1 */ 122 /* Value 0x81 : bit[7] = 1, bit[2] = 0, bit[1:0] = 01b */ 123 #define LMCR_NEWMOD BIT(7) 124 #define LMCR_TYPED1 BIT(1) 125 #define LMCR_TYPED0 BIT(0) 126 #define LMCR_MODE1 (LMCR_NEWMOD | LMCR_TYPED0) 127 /* 0x5E */ 128 #define MBNDRY_BYTE BIT(7) 129 /* 0xFE */ 130 #define ISR_MBS BIT(7) 131 #define ISR_LNKCHG BIT(5) 132 #define ISR_ROOS BIT(3) 133 #define ISR_ROS BIT(2) 134 #define ISR_PTS BIT(1) 135 #define ISR_PRS BIT(0) 136 #define ISR_CLR_INT (ISR_LNKCHG | ISR_ROOS | ISR_ROS | \ 137 ISR_PTS | ISR_PRS) 138 #define ISR_STOP_MRCMD (ISR_MBS) 139 /* 0xFF */ 140 #define IMR_PAR BIT(7) 141 #define IMR_LNKCHGI BIT(5) 142 #define IMR_PTM BIT(1) 143 #define IMR_PRM BIT(0) 144 145 /* Const 146 */ 147 #define DM9051_PHY_ADDR 1 /* PHY id */ 148 #define DM9051_PHY 0x40 /* PHY address 0x01 */ 149 #define DM9051_PKT_RDY 0x01 /* Packet ready to receive */ 150 #define DM9051_PKT_MAX 1536 /* Received packet max size */ 151 #define DM9051_TX_QUE_HI_WATER 50 152 #define DM9051_TX_QUE_LO_WATER 25 153 #define DM_EEPROM_MAGIC 0x9051 154 155 #define DM_RXHDR_SIZE sizeof(struct dm9051_rxhdr) 156 157 static inline struct board_info *to_dm9051_board(struct net_device *ndev) 158 { 159 return netdev_priv(ndev); 160 } 161 162 #endif /* _DM9051_H_ */ 163