xref: /linux/drivers/net/ethernet/davicom/dm9051.h (revision 4f2c0a4acffbec01079c28f839422e64ddeff004)
1*2dc95a4dSJoseph CHAMG /* SPDX-License-Identifier: GPL-2.0-only */
2*2dc95a4dSJoseph CHAMG /*
3*2dc95a4dSJoseph CHAMG  * Copyright (c) 2022 Davicom Semiconductor,Inc.
4*2dc95a4dSJoseph CHAMG  * Davicom DM9051 SPI Fast Ethernet Linux driver
5*2dc95a4dSJoseph CHAMG  */
6*2dc95a4dSJoseph CHAMG 
7*2dc95a4dSJoseph CHAMG #ifndef _DM9051_H_
8*2dc95a4dSJoseph CHAMG #define _DM9051_H_
9*2dc95a4dSJoseph CHAMG 
10*2dc95a4dSJoseph CHAMG #include <linux/bits.h>
11*2dc95a4dSJoseph CHAMG #include <linux/netdevice.h>
12*2dc95a4dSJoseph CHAMG #include <linux/types.h>
13*2dc95a4dSJoseph CHAMG 
14*2dc95a4dSJoseph CHAMG #define DM9051_ID		0x9051
15*2dc95a4dSJoseph CHAMG 
16*2dc95a4dSJoseph CHAMG #define DM9051_NCR		0x00
17*2dc95a4dSJoseph CHAMG #define DM9051_NSR		0x01
18*2dc95a4dSJoseph CHAMG #define DM9051_TCR		0x02
19*2dc95a4dSJoseph CHAMG #define DM9051_RCR		0x05
20*2dc95a4dSJoseph CHAMG #define DM9051_BPTR		0x08
21*2dc95a4dSJoseph CHAMG #define DM9051_FCR		0x0A
22*2dc95a4dSJoseph CHAMG #define DM9051_EPCR		0x0B
23*2dc95a4dSJoseph CHAMG #define DM9051_EPAR		0x0C
24*2dc95a4dSJoseph CHAMG #define DM9051_EPDRL		0x0D
25*2dc95a4dSJoseph CHAMG #define DM9051_EPDRH		0x0E
26*2dc95a4dSJoseph CHAMG #define DM9051_PAR		0x10
27*2dc95a4dSJoseph CHAMG #define DM9051_MAR		0x16
28*2dc95a4dSJoseph CHAMG #define DM9051_GPCR		0x1E
29*2dc95a4dSJoseph CHAMG #define DM9051_GPR		0x1F
30*2dc95a4dSJoseph CHAMG 
31*2dc95a4dSJoseph CHAMG #define DM9051_VIDL		0x28
32*2dc95a4dSJoseph CHAMG #define DM9051_VIDH		0x29
33*2dc95a4dSJoseph CHAMG #define DM9051_PIDL		0x2A
34*2dc95a4dSJoseph CHAMG #define DM9051_PIDH		0x2B
35*2dc95a4dSJoseph CHAMG #define DM9051_SMCR		0x2F
36*2dc95a4dSJoseph CHAMG #define	DM9051_ATCR		0x30
37*2dc95a4dSJoseph CHAMG #define	DM9051_SPIBCR		0x38
38*2dc95a4dSJoseph CHAMG #define DM9051_INTCR		0x39
39*2dc95a4dSJoseph CHAMG #define DM9051_PPCR		0x3D
40*2dc95a4dSJoseph CHAMG 
41*2dc95a4dSJoseph CHAMG #define DM9051_MPCR		0x55
42*2dc95a4dSJoseph CHAMG #define DM9051_LMCR		0x57
43*2dc95a4dSJoseph CHAMG #define DM9051_MBNDRY		0x5E
44*2dc95a4dSJoseph CHAMG 
45*2dc95a4dSJoseph CHAMG #define DM9051_MRRL		0x74
46*2dc95a4dSJoseph CHAMG #define DM9051_MRRH		0x75
47*2dc95a4dSJoseph CHAMG #define DM9051_MWRL		0x7A
48*2dc95a4dSJoseph CHAMG #define DM9051_MWRH		0x7B
49*2dc95a4dSJoseph CHAMG #define DM9051_TXPLL		0x7C
50*2dc95a4dSJoseph CHAMG #define DM9051_TXPLH		0x7D
51*2dc95a4dSJoseph CHAMG #define DM9051_ISR		0x7E
52*2dc95a4dSJoseph CHAMG #define DM9051_IMR		0x7F
53*2dc95a4dSJoseph CHAMG 
54*2dc95a4dSJoseph CHAMG #define DM_SPI_MRCMDX		0x70
55*2dc95a4dSJoseph CHAMG #define DM_SPI_MRCMD		0x72
56*2dc95a4dSJoseph CHAMG #define DM_SPI_MWCMD		0x78
57*2dc95a4dSJoseph CHAMG 
58*2dc95a4dSJoseph CHAMG #define DM_SPI_WR		0x80
59*2dc95a4dSJoseph CHAMG 
60*2dc95a4dSJoseph CHAMG /* dm9051 Ethernet controller registers bits
61*2dc95a4dSJoseph CHAMG  */
62*2dc95a4dSJoseph CHAMG /* 0x00 */
63*2dc95a4dSJoseph CHAMG #define NCR_WAKEEN		BIT(6)
64*2dc95a4dSJoseph CHAMG #define NCR_FDX			BIT(3)
65*2dc95a4dSJoseph CHAMG #define NCR_RST			BIT(0)
66*2dc95a4dSJoseph CHAMG /* 0x01 */
67*2dc95a4dSJoseph CHAMG #define NSR_SPEED		BIT(7)
68*2dc95a4dSJoseph CHAMG #define NSR_LINKST		BIT(6)
69*2dc95a4dSJoseph CHAMG #define NSR_WAKEST		BIT(5)
70*2dc95a4dSJoseph CHAMG #define NSR_TX2END		BIT(3)
71*2dc95a4dSJoseph CHAMG #define NSR_TX1END		BIT(2)
72*2dc95a4dSJoseph CHAMG /* 0x02 */
73*2dc95a4dSJoseph CHAMG #define TCR_DIS_JABBER_TIMER	BIT(6) /* for Jabber Packet support */
74*2dc95a4dSJoseph CHAMG #define TCR_TXREQ		BIT(0)
75*2dc95a4dSJoseph CHAMG /* 0x05 */
76*2dc95a4dSJoseph CHAMG #define RCR_DIS_WATCHDOG_TIMER	BIT(6)  /* for Jabber Packet support */
77*2dc95a4dSJoseph CHAMG #define RCR_DIS_LONG		BIT(5)
78*2dc95a4dSJoseph CHAMG #define RCR_DIS_CRC		BIT(4)
79*2dc95a4dSJoseph CHAMG #define RCR_ALL			BIT(3)
80*2dc95a4dSJoseph CHAMG #define RCR_PRMSC		BIT(1)
81*2dc95a4dSJoseph CHAMG #define RCR_RXEN		BIT(0)
82*2dc95a4dSJoseph CHAMG #define RCR_RX_DISABLE		(RCR_DIS_LONG | RCR_DIS_CRC)
83*2dc95a4dSJoseph CHAMG /* 0x06 */
84*2dc95a4dSJoseph CHAMG #define RSR_RF			BIT(7)
85*2dc95a4dSJoseph CHAMG #define RSR_MF			BIT(6)
86*2dc95a4dSJoseph CHAMG #define RSR_LCS			BIT(5)
87*2dc95a4dSJoseph CHAMG #define RSR_RWTO		BIT(4)
88*2dc95a4dSJoseph CHAMG #define RSR_PLE			BIT(3)
89*2dc95a4dSJoseph CHAMG #define RSR_AE			BIT(2)
90*2dc95a4dSJoseph CHAMG #define RSR_CE			BIT(1)
91*2dc95a4dSJoseph CHAMG #define RSR_FOE			BIT(0)
92*2dc95a4dSJoseph CHAMG #define	RSR_ERR_BITS		(RSR_RF | RSR_LCS | RSR_RWTO | RSR_PLE | \
93*2dc95a4dSJoseph CHAMG 				 RSR_AE | RSR_CE | RSR_FOE)
94*2dc95a4dSJoseph CHAMG /* 0x0A */
95*2dc95a4dSJoseph CHAMG #define FCR_TXPEN		BIT(5)
96*2dc95a4dSJoseph CHAMG #define FCR_BKPM		BIT(3)
97*2dc95a4dSJoseph CHAMG #define FCR_FLCE		BIT(0)
98*2dc95a4dSJoseph CHAMG #define FCR_RXTX_BITS		(FCR_TXPEN | FCR_BKPM | FCR_FLCE)
99*2dc95a4dSJoseph CHAMG /* 0x0B */
100*2dc95a4dSJoseph CHAMG #define EPCR_WEP		BIT(4)
101*2dc95a4dSJoseph CHAMG #define EPCR_EPOS		BIT(3)
102*2dc95a4dSJoseph CHAMG #define EPCR_ERPRR		BIT(2)
103*2dc95a4dSJoseph CHAMG #define EPCR_ERPRW		BIT(1)
104*2dc95a4dSJoseph CHAMG #define EPCR_ERRE		BIT(0)
105*2dc95a4dSJoseph CHAMG /* 0x1E */
106*2dc95a4dSJoseph CHAMG #define GPCR_GEP_CNTL		BIT(0)
107*2dc95a4dSJoseph CHAMG /* 0x1F */
108*2dc95a4dSJoseph CHAMG #define GPR_PHY_OFF		BIT(0)
109*2dc95a4dSJoseph CHAMG /* 0x30 */
110*2dc95a4dSJoseph CHAMG #define	ATCR_AUTO_TX		BIT(7)
111*2dc95a4dSJoseph CHAMG /* 0x39 */
112*2dc95a4dSJoseph CHAMG #define INTCR_POL_LOW		(1 << 0)
113*2dc95a4dSJoseph CHAMG #define INTCR_POL_HIGH		(0 << 0)
114*2dc95a4dSJoseph CHAMG /* 0x3D */
115*2dc95a4dSJoseph CHAMG /* Pause Packet Control Register - default = 1 */
116*2dc95a4dSJoseph CHAMG #define PPCR_PAUSE_COUNT	0x08
117*2dc95a4dSJoseph CHAMG /* 0x55 */
118*2dc95a4dSJoseph CHAMG #define MPCR_RSTTX		BIT(1)
119*2dc95a4dSJoseph CHAMG #define MPCR_RSTRX		BIT(0)
120*2dc95a4dSJoseph CHAMG /* 0x57 */
121*2dc95a4dSJoseph CHAMG /* LEDMode Control Register - LEDMode1 */
122*2dc95a4dSJoseph CHAMG /* Value 0x81 : bit[7] = 1, bit[2] = 0, bit[1:0] = 01b */
123*2dc95a4dSJoseph CHAMG #define LMCR_NEWMOD		BIT(7)
124*2dc95a4dSJoseph CHAMG #define LMCR_TYPED1		BIT(1)
125*2dc95a4dSJoseph CHAMG #define LMCR_TYPED0		BIT(0)
126*2dc95a4dSJoseph CHAMG #define LMCR_MODE1		(LMCR_NEWMOD | LMCR_TYPED0)
127*2dc95a4dSJoseph CHAMG /* 0x5E */
128*2dc95a4dSJoseph CHAMG #define MBNDRY_BYTE		BIT(7)
129*2dc95a4dSJoseph CHAMG /* 0xFE */
130*2dc95a4dSJoseph CHAMG #define ISR_MBS			BIT(7)
131*2dc95a4dSJoseph CHAMG #define ISR_LNKCHG		BIT(5)
132*2dc95a4dSJoseph CHAMG #define ISR_ROOS		BIT(3)
133*2dc95a4dSJoseph CHAMG #define ISR_ROS			BIT(2)
134*2dc95a4dSJoseph CHAMG #define ISR_PTS			BIT(1)
135*2dc95a4dSJoseph CHAMG #define ISR_PRS			BIT(0)
136*2dc95a4dSJoseph CHAMG #define ISR_CLR_INT		(ISR_LNKCHG | ISR_ROOS | ISR_ROS | \
137*2dc95a4dSJoseph CHAMG 				 ISR_PTS | ISR_PRS)
138*2dc95a4dSJoseph CHAMG #define ISR_STOP_MRCMD		(ISR_MBS)
139*2dc95a4dSJoseph CHAMG /* 0xFF */
140*2dc95a4dSJoseph CHAMG #define IMR_PAR			BIT(7)
141*2dc95a4dSJoseph CHAMG #define IMR_LNKCHGI		BIT(5)
142*2dc95a4dSJoseph CHAMG #define IMR_PTM			BIT(1)
143*2dc95a4dSJoseph CHAMG #define IMR_PRM			BIT(0)
144*2dc95a4dSJoseph CHAMG 
145*2dc95a4dSJoseph CHAMG /* Const
146*2dc95a4dSJoseph CHAMG  */
147*2dc95a4dSJoseph CHAMG #define DM9051_PHY_ADDR			1	/* PHY id */
148*2dc95a4dSJoseph CHAMG #define DM9051_PHY			0x40	/* PHY address 0x01 */
149*2dc95a4dSJoseph CHAMG #define DM9051_PKT_RDY			0x01	/* Packet ready to receive */
150*2dc95a4dSJoseph CHAMG #define DM9051_PKT_MAX			1536	/* Received packet max size */
151*2dc95a4dSJoseph CHAMG #define DM9051_TX_QUE_HI_WATER		50
152*2dc95a4dSJoseph CHAMG #define DM9051_TX_QUE_LO_WATER		25
153*2dc95a4dSJoseph CHAMG #define DM_EEPROM_MAGIC			0x9051
154*2dc95a4dSJoseph CHAMG 
155*2dc95a4dSJoseph CHAMG #define	DM_RXHDR_SIZE			sizeof(struct dm9051_rxhdr)
156*2dc95a4dSJoseph CHAMG 
to_dm9051_board(struct net_device * ndev)157*2dc95a4dSJoseph CHAMG static inline struct board_info *to_dm9051_board(struct net_device *ndev)
158*2dc95a4dSJoseph CHAMG {
159*2dc95a4dSJoseph CHAMG 	return netdev_priv(ndev);
160*2dc95a4dSJoseph CHAMG }
161*2dc95a4dSJoseph CHAMG 
162*2dc95a4dSJoseph CHAMG #endif /* _DM9051_H_ */
163