1 // SPDX-License-Identifier: GPL-2.0 2 /* Ethernet device driver for Cortina Systems Gemini SoC 3 * Also known as the StorLink SL3512 and SL3516 (SL351x) or Lepus 4 * Net Engine and Gigabit Ethernet MAC (GMAC) 5 * This hardware contains a TCP Offload Engine (TOE) but currently the 6 * driver does not make use of it. 7 * 8 * Authors: 9 * Linus Walleij <linus.walleij@linaro.org> 10 * Tobias Waldvogel <tobias.waldvogel@gmail.com> (OpenWRT) 11 * Michał Mirosław <mirq-linux@rere.qmqm.pl> 12 * Paulius Zaleckas <paulius.zaleckas@gmail.com> 13 * Giuseppe De Robertis <Giuseppe.DeRobertis@ba.infn.it> 14 * Gary Chen & Ch Hsu Storlink Semiconductor 15 */ 16 #include <linux/kernel.h> 17 #include <linux/init.h> 18 #include <linux/module.h> 19 #include <linux/platform_device.h> 20 #include <linux/spinlock.h> 21 #include <linux/slab.h> 22 #include <linux/dma-mapping.h> 23 #include <linux/cache.h> 24 #include <linux/interrupt.h> 25 #include <linux/reset.h> 26 #include <linux/clk.h> 27 #include <linux/of.h> 28 #include <linux/of_mdio.h> 29 #include <linux/of_net.h> 30 #include <linux/of_platform.h> 31 #include <linux/etherdevice.h> 32 #include <linux/if_vlan.h> 33 #include <linux/skbuff.h> 34 #include <linux/phy.h> 35 #include <linux/crc32.h> 36 #include <linux/ethtool.h> 37 #include <linux/tcp.h> 38 #include <linux/u64_stats_sync.h> 39 40 #include <linux/in.h> 41 #include <linux/ip.h> 42 #include <linux/ipv6.h> 43 #include <net/gro.h> 44 45 #include "gemini.h" 46 47 #define DRV_NAME "gmac-gemini" 48 49 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK) 50 static int debug = -1; 51 module_param(debug, int, 0); 52 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 53 54 #define HSIZE_8 0x00 55 #define HSIZE_16 0x01 56 #define HSIZE_32 0x02 57 58 #define HBURST_SINGLE 0x00 59 #define HBURST_INCR 0x01 60 #define HBURST_INCR4 0x02 61 #define HBURST_INCR8 0x03 62 63 #define HPROT_DATA_CACHE BIT(0) 64 #define HPROT_PRIVILIGED BIT(1) 65 #define HPROT_BUFFERABLE BIT(2) 66 #define HPROT_CACHABLE BIT(3) 67 68 #define DEFAULT_RX_COALESCE_NSECS 0 69 #define DEFAULT_GMAC_RXQ_ORDER 9 70 #define DEFAULT_GMAC_TXQ_ORDER 8 71 #define DEFAULT_RX_BUF_ORDER 11 72 #define TX_MAX_FRAGS 16 73 #define TX_QUEUE_NUM 1 /* max: 6 */ 74 #define RX_MAX_ALLOC_ORDER 2 75 76 #define GMAC0_IRQ0_2 (GMAC0_TXDERR_INT_BIT | GMAC0_TXPERR_INT_BIT | \ 77 GMAC0_RXDERR_INT_BIT | GMAC0_RXPERR_INT_BIT) 78 #define GMAC0_IRQ0_TXQ0_INTS (GMAC0_SWTQ00_EOF_INT_BIT | \ 79 GMAC0_SWTQ00_FIN_INT_BIT) 80 #define GMAC0_IRQ4_8 (GMAC0_MIB_INT_BIT | GMAC0_RX_OVERRUN_INT_BIT) 81 82 #define GMAC_OFFLOAD_FEATURES (NETIF_F_SG | NETIF_F_IP_CSUM | \ 83 NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM | \ 84 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6) 85 86 /** 87 * struct gmac_queue_page - page buffer per-page info 88 * @page: the page struct 89 * @mapping: the dma address handle 90 */ 91 struct gmac_queue_page { 92 struct page *page; 93 dma_addr_t mapping; 94 }; 95 96 struct gmac_txq { 97 struct gmac_txdesc *ring; 98 struct sk_buff **skb; 99 unsigned int cptr; 100 unsigned int noirq_packets; 101 }; 102 103 struct gemini_ethernet; 104 105 struct gemini_ethernet_port { 106 u8 id; /* 0 or 1 */ 107 108 struct gemini_ethernet *geth; 109 struct net_device *netdev; 110 struct device *dev; 111 void __iomem *dma_base; 112 void __iomem *gmac_base; 113 struct clk *pclk; 114 struct reset_control *reset; 115 int irq; 116 __le32 mac_addr[3]; 117 118 void __iomem *rxq_rwptr; 119 struct gmac_rxdesc *rxq_ring; 120 unsigned int rxq_order; 121 122 struct napi_struct napi; 123 struct hrtimer rx_coalesce_timer; 124 unsigned int rx_coalesce_nsecs; 125 struct sk_buff *rx_skb; 126 unsigned int rx_frag_nr; 127 128 unsigned int freeq_refill; 129 struct gmac_txq txq[TX_QUEUE_NUM]; 130 unsigned int txq_order; 131 unsigned int irq_every_tx_packets; 132 133 dma_addr_t rxq_dma_base; 134 dma_addr_t txq_dma_base; 135 136 unsigned int msg_enable; 137 spinlock_t config_lock; /* Locks config register */ 138 139 struct u64_stats_sync tx_stats_syncp; 140 struct u64_stats_sync rx_stats_syncp; 141 struct u64_stats_sync ir_stats_syncp; 142 143 struct rtnl_link_stats64 stats; 144 u64 hw_stats[RX_STATS_NUM]; 145 u64 rx_stats[RX_STATUS_NUM]; 146 u64 rx_csum_stats[RX_CHKSUM_NUM]; 147 u64 rx_napi_exits; 148 u64 tx_frag_stats[TX_MAX_FRAGS]; 149 u64 tx_frags_linearized; 150 u64 tx_hw_csummed; 151 }; 152 153 struct gemini_ethernet { 154 struct device *dev; 155 void __iomem *base; 156 struct gemini_ethernet_port *port0; 157 struct gemini_ethernet_port *port1; 158 bool initialized; 159 160 spinlock_t irq_lock; /* Locks IRQ-related registers */ 161 unsigned int freeq_order; 162 unsigned int freeq_frag_order; 163 struct gmac_rxdesc *freeq_ring; 164 dma_addr_t freeq_dma_base; 165 struct gmac_queue_page *freeq_pages; 166 unsigned int num_freeq_pages; 167 spinlock_t freeq_lock; /* Locks queue from reentrance */ 168 }; 169 170 #define GMAC_STATS_NUM ( \ 171 RX_STATS_NUM + RX_STATUS_NUM + RX_CHKSUM_NUM + 1 + \ 172 TX_MAX_FRAGS + 2) 173 174 static const char gmac_stats_strings[GMAC_STATS_NUM][ETH_GSTRING_LEN] = { 175 "GMAC_IN_DISCARDS", 176 "GMAC_IN_ERRORS", 177 "GMAC_IN_MCAST", 178 "GMAC_IN_BCAST", 179 "GMAC_IN_MAC1", 180 "GMAC_IN_MAC2", 181 "RX_STATUS_GOOD_FRAME", 182 "RX_STATUS_TOO_LONG_GOOD_CRC", 183 "RX_STATUS_RUNT_FRAME", 184 "RX_STATUS_SFD_NOT_FOUND", 185 "RX_STATUS_CRC_ERROR", 186 "RX_STATUS_TOO_LONG_BAD_CRC", 187 "RX_STATUS_ALIGNMENT_ERROR", 188 "RX_STATUS_TOO_LONG_BAD_ALIGN", 189 "RX_STATUS_RX_ERR", 190 "RX_STATUS_DA_FILTERED", 191 "RX_STATUS_BUFFER_FULL", 192 "RX_STATUS_11", 193 "RX_STATUS_12", 194 "RX_STATUS_13", 195 "RX_STATUS_14", 196 "RX_STATUS_15", 197 "RX_CHKSUM_IP_UDP_TCP_OK", 198 "RX_CHKSUM_IP_OK_ONLY", 199 "RX_CHKSUM_NONE", 200 "RX_CHKSUM_3", 201 "RX_CHKSUM_IP_ERR_UNKNOWN", 202 "RX_CHKSUM_IP_ERR", 203 "RX_CHKSUM_TCP_UDP_ERR", 204 "RX_CHKSUM_7", 205 "RX_NAPI_EXITS", 206 "TX_FRAGS[1]", 207 "TX_FRAGS[2]", 208 "TX_FRAGS[3]", 209 "TX_FRAGS[4]", 210 "TX_FRAGS[5]", 211 "TX_FRAGS[6]", 212 "TX_FRAGS[7]", 213 "TX_FRAGS[8]", 214 "TX_FRAGS[9]", 215 "TX_FRAGS[10]", 216 "TX_FRAGS[11]", 217 "TX_FRAGS[12]", 218 "TX_FRAGS[13]", 219 "TX_FRAGS[14]", 220 "TX_FRAGS[15]", 221 "TX_FRAGS[16+]", 222 "TX_FRAGS_LINEARIZED", 223 "TX_HW_CSUMMED", 224 }; 225 226 static void gmac_dump_dma_state(struct net_device *netdev); 227 228 static void gmac_update_config0_reg(struct net_device *netdev, 229 u32 val, u32 vmask) 230 { 231 struct gemini_ethernet_port *port = netdev_priv(netdev); 232 unsigned long flags; 233 u32 reg; 234 235 spin_lock_irqsave(&port->config_lock, flags); 236 237 reg = readl(port->gmac_base + GMAC_CONFIG0); 238 reg = (reg & ~vmask) | val; 239 writel(reg, port->gmac_base + GMAC_CONFIG0); 240 241 spin_unlock_irqrestore(&port->config_lock, flags); 242 } 243 244 static void gmac_enable_tx_rx(struct net_device *netdev) 245 { 246 struct gemini_ethernet_port *port = netdev_priv(netdev); 247 unsigned long flags; 248 u32 reg; 249 250 spin_lock_irqsave(&port->config_lock, flags); 251 252 reg = readl(port->gmac_base + GMAC_CONFIG0); 253 reg &= ~CONFIG0_TX_RX_DISABLE; 254 writel(reg, port->gmac_base + GMAC_CONFIG0); 255 256 spin_unlock_irqrestore(&port->config_lock, flags); 257 } 258 259 static void gmac_disable_tx_rx(struct net_device *netdev) 260 { 261 struct gemini_ethernet_port *port = netdev_priv(netdev); 262 unsigned long flags; 263 u32 val; 264 265 spin_lock_irqsave(&port->config_lock, flags); 266 267 val = readl(port->gmac_base + GMAC_CONFIG0); 268 val |= CONFIG0_TX_RX_DISABLE; 269 writel(val, port->gmac_base + GMAC_CONFIG0); 270 271 spin_unlock_irqrestore(&port->config_lock, flags); 272 273 mdelay(10); /* let GMAC consume packet */ 274 } 275 276 static void gmac_set_flow_control(struct net_device *netdev, bool tx, bool rx) 277 { 278 struct gemini_ethernet_port *port = netdev_priv(netdev); 279 unsigned long flags; 280 u32 val; 281 282 spin_lock_irqsave(&port->config_lock, flags); 283 284 val = readl(port->gmac_base + GMAC_CONFIG0); 285 val &= ~CONFIG0_FLOW_CTL; 286 if (tx) 287 val |= CONFIG0_FLOW_TX; 288 if (rx) 289 val |= CONFIG0_FLOW_RX; 290 writel(val, port->gmac_base + GMAC_CONFIG0); 291 292 spin_unlock_irqrestore(&port->config_lock, flags); 293 } 294 295 static void gmac_adjust_link(struct net_device *netdev) 296 { 297 struct gemini_ethernet_port *port = netdev_priv(netdev); 298 struct phy_device *phydev = netdev->phydev; 299 union gmac_status status, old_status; 300 bool pause_tx = false; 301 bool pause_rx = false; 302 303 status.bits32 = readl(port->gmac_base + GMAC_STATUS); 304 old_status.bits32 = status.bits32; 305 status.bits.link = phydev->link; 306 status.bits.duplex = phydev->duplex; 307 308 switch (phydev->speed) { 309 case 1000: 310 status.bits.speed = GMAC_SPEED_1000; 311 if (phy_interface_mode_is_rgmii(phydev->interface)) 312 status.bits.mii_rmii = GMAC_PHY_RGMII_1000; 313 netdev_dbg(netdev, "connect %s to RGMII @ 1Gbit\n", 314 phydev_name(phydev)); 315 break; 316 case 100: 317 status.bits.speed = GMAC_SPEED_100; 318 if (phy_interface_mode_is_rgmii(phydev->interface)) 319 status.bits.mii_rmii = GMAC_PHY_RGMII_100_10; 320 netdev_dbg(netdev, "connect %s to RGMII @ 100 Mbit\n", 321 phydev_name(phydev)); 322 break; 323 case 10: 324 status.bits.speed = GMAC_SPEED_10; 325 if (phy_interface_mode_is_rgmii(phydev->interface)) 326 status.bits.mii_rmii = GMAC_PHY_RGMII_100_10; 327 netdev_dbg(netdev, "connect %s to RGMII @ 10 Mbit\n", 328 phydev_name(phydev)); 329 break; 330 default: 331 netdev_warn(netdev, "Unsupported PHY speed (%d) on %s\n", 332 phydev->speed, phydev_name(phydev)); 333 } 334 335 if (phydev->duplex == DUPLEX_FULL) { 336 phy_get_pause(phydev, &pause_tx, &pause_rx); 337 netdev_dbg(netdev, "set negotiated pause params pause TX = %s, pause RX = %s\n", 338 pause_tx ? "ON" : "OFF", pause_rx ? "ON" : "OFF"); 339 } 340 341 gmac_set_flow_control(netdev, pause_tx, pause_rx); 342 343 if (old_status.bits32 == status.bits32) 344 return; 345 346 if (netif_msg_link(port)) { 347 phy_print_status(phydev); 348 netdev_info(netdev, "link flow control: %s\n", 349 phydev->pause 350 ? (phydev->asym_pause ? "tx" : "both") 351 : (phydev->asym_pause ? "rx" : "none") 352 ); 353 } 354 355 gmac_disable_tx_rx(netdev); 356 writel(status.bits32, port->gmac_base + GMAC_STATUS); 357 gmac_enable_tx_rx(netdev); 358 } 359 360 static int gmac_setup_phy(struct net_device *netdev) 361 { 362 struct gemini_ethernet_port *port = netdev_priv(netdev); 363 union gmac_status status = { .bits32 = 0 }; 364 struct device *dev = port->dev; 365 struct phy_device *phy; 366 367 phy = of_phy_get_and_connect(netdev, 368 dev->of_node, 369 gmac_adjust_link); 370 if (!phy) 371 return -ENODEV; 372 netdev->phydev = phy; 373 374 phy_set_max_speed(phy, SPEED_1000); 375 phy_support_asym_pause(phy); 376 377 /* set PHY interface type */ 378 switch (phy->interface) { 379 case PHY_INTERFACE_MODE_MII: 380 netdev_dbg(netdev, 381 "MII: set GMAC0 to GMII mode, GMAC1 disabled\n"); 382 status.bits.mii_rmii = GMAC_PHY_MII; 383 break; 384 case PHY_INTERFACE_MODE_GMII: 385 netdev_dbg(netdev, 386 "GMII: set GMAC0 to GMII mode, GMAC1 disabled\n"); 387 status.bits.mii_rmii = GMAC_PHY_GMII; 388 break; 389 case PHY_INTERFACE_MODE_RGMII: 390 case PHY_INTERFACE_MODE_RGMII_ID: 391 case PHY_INTERFACE_MODE_RGMII_TXID: 392 case PHY_INTERFACE_MODE_RGMII_RXID: 393 netdev_dbg(netdev, 394 "RGMII: set GMAC0 and GMAC1 to MII/RGMII mode\n"); 395 status.bits.mii_rmii = GMAC_PHY_RGMII_100_10; 396 break; 397 default: 398 netdev_err(netdev, "Unsupported MII interface\n"); 399 phy_disconnect(phy); 400 netdev->phydev = NULL; 401 return -EINVAL; 402 } 403 writel(status.bits32, port->gmac_base + GMAC_STATUS); 404 405 if (netif_msg_link(port)) 406 phy_attached_info(phy); 407 408 return 0; 409 } 410 411 /* The maximum frame length is not logically enumerated in the 412 * hardware, so we do a table lookup to find the applicable max 413 * frame length. 414 */ 415 struct gmac_max_framelen { 416 unsigned int max_l3_len; 417 u8 val; 418 }; 419 420 static const struct gmac_max_framelen gmac_maxlens[] = { 421 { 422 .max_l3_len = 1518, 423 .val = CONFIG0_MAXLEN_1518, 424 }, 425 { 426 .max_l3_len = 1522, 427 .val = CONFIG0_MAXLEN_1522, 428 }, 429 { 430 .max_l3_len = 1536, 431 .val = CONFIG0_MAXLEN_1536, 432 }, 433 { 434 .max_l3_len = 1548, 435 .val = CONFIG0_MAXLEN_1548, 436 }, 437 { 438 .max_l3_len = 9212, 439 .val = CONFIG0_MAXLEN_9k, 440 }, 441 { 442 .max_l3_len = 10236, 443 .val = CONFIG0_MAXLEN_10k, 444 }, 445 }; 446 447 static int gmac_pick_rx_max_len(unsigned int max_l3_len) 448 { 449 const struct gmac_max_framelen *maxlen; 450 int maxtot; 451 int i; 452 453 maxtot = max_l3_len + ETH_HLEN + VLAN_HLEN; 454 455 for (i = 0; i < ARRAY_SIZE(gmac_maxlens); i++) { 456 maxlen = &gmac_maxlens[i]; 457 if (maxtot <= maxlen->max_l3_len) 458 return maxlen->val; 459 } 460 461 return -1; 462 } 463 464 static int gmac_init(struct net_device *netdev) 465 { 466 struct gemini_ethernet_port *port = netdev_priv(netdev); 467 union gmac_config0 config0 = { .bits = { 468 .dis_tx = 1, 469 .dis_rx = 1, 470 .ipv4_rx_chksum = 1, 471 .ipv6_rx_chksum = 1, 472 .rx_err_detect = 1, 473 .rgmm_edge = 1, 474 .port0_chk_hwq = 1, 475 .port1_chk_hwq = 1, 476 .port0_chk_toeq = 1, 477 .port1_chk_toeq = 1, 478 .port0_chk_classq = 1, 479 .port1_chk_classq = 1, 480 } }; 481 union gmac_ahb_weight ahb_weight = { .bits = { 482 .rx_weight = 1, 483 .tx_weight = 1, 484 .hash_weight = 1, 485 .pre_req = 0x1f, 486 .tq_dv_threshold = 0, 487 } }; 488 union gmac_tx_wcr0 hw_weigh = { .bits = { 489 .hw_tq3 = 1, 490 .hw_tq2 = 1, 491 .hw_tq1 = 1, 492 .hw_tq0 = 1, 493 } }; 494 union gmac_tx_wcr1 sw_weigh = { .bits = { 495 .sw_tq5 = 1, 496 .sw_tq4 = 1, 497 .sw_tq3 = 1, 498 .sw_tq2 = 1, 499 .sw_tq1 = 1, 500 .sw_tq0 = 1, 501 } }; 502 union gmac_config1 config1 = { .bits = { 503 .set_threshold = 16, 504 .rel_threshold = 24, 505 } }; 506 union gmac_config2 config2 = { .bits = { 507 .set_threshold = 16, 508 .rel_threshold = 32, 509 } }; 510 union gmac_config3 config3 = { .bits = { 511 .set_threshold = 0, 512 .rel_threshold = 0, 513 } }; 514 union gmac_config0 tmp; 515 516 config0.bits.max_len = gmac_pick_rx_max_len(netdev->mtu); 517 tmp.bits32 = readl(port->gmac_base + GMAC_CONFIG0); 518 config0.bits.reserved = tmp.bits.reserved; 519 writel(config0.bits32, port->gmac_base + GMAC_CONFIG0); 520 writel(config1.bits32, port->gmac_base + GMAC_CONFIG1); 521 writel(config2.bits32, port->gmac_base + GMAC_CONFIG2); 522 writel(config3.bits32, port->gmac_base + GMAC_CONFIG3); 523 524 readl(port->dma_base + GMAC_AHB_WEIGHT_REG); 525 writel(ahb_weight.bits32, port->dma_base + GMAC_AHB_WEIGHT_REG); 526 527 writel(hw_weigh.bits32, 528 port->dma_base + GMAC_TX_WEIGHTING_CTRL_0_REG); 529 writel(sw_weigh.bits32, 530 port->dma_base + GMAC_TX_WEIGHTING_CTRL_1_REG); 531 532 port->rxq_order = DEFAULT_GMAC_RXQ_ORDER; 533 port->txq_order = DEFAULT_GMAC_TXQ_ORDER; 534 port->rx_coalesce_nsecs = DEFAULT_RX_COALESCE_NSECS; 535 536 /* Mark every quarter of the queue a packet for interrupt 537 * in order to be able to wake up the queue if it was stopped 538 */ 539 port->irq_every_tx_packets = 1 << (port->txq_order - 2); 540 541 return 0; 542 } 543 544 static int gmac_setup_txqs(struct net_device *netdev) 545 { 546 struct gemini_ethernet_port *port = netdev_priv(netdev); 547 unsigned int n_txq = netdev->num_tx_queues; 548 struct gemini_ethernet *geth = port->geth; 549 size_t entries = 1 << port->txq_order; 550 struct gmac_txq *txq = port->txq; 551 struct gmac_txdesc *desc_ring; 552 size_t len = n_txq * entries; 553 struct sk_buff **skb_tab; 554 void __iomem *rwptr_reg; 555 unsigned int r; 556 int i; 557 558 rwptr_reg = port->dma_base + GMAC_SW_TX_QUEUE0_PTR_REG; 559 560 skb_tab = kzalloc_objs(*skb_tab, len); 561 if (!skb_tab) 562 return -ENOMEM; 563 564 desc_ring = dma_alloc_coherent(geth->dev, len * sizeof(*desc_ring), 565 &port->txq_dma_base, GFP_KERNEL); 566 567 if (!desc_ring) { 568 kfree(skb_tab); 569 return -ENOMEM; 570 } 571 572 if (port->txq_dma_base & ~DMA_Q_BASE_MASK) { 573 dev_warn(geth->dev, "TX queue base is not aligned\n"); 574 dma_free_coherent(geth->dev, len * sizeof(*desc_ring), 575 desc_ring, port->txq_dma_base); 576 kfree(skb_tab); 577 return -ENOMEM; 578 } 579 580 writel(port->txq_dma_base | port->txq_order, 581 port->dma_base + GMAC_SW_TX_QUEUE_BASE_REG); 582 583 for (i = 0; i < n_txq; i++) { 584 txq->ring = desc_ring; 585 txq->skb = skb_tab; 586 txq->noirq_packets = 0; 587 588 r = readw(rwptr_reg); 589 rwptr_reg += 2; 590 writew(r, rwptr_reg); 591 rwptr_reg += 2; 592 txq->cptr = r; 593 594 txq++; 595 desc_ring += entries; 596 skb_tab += entries; 597 } 598 599 return 0; 600 } 601 602 static void gmac_clean_txq(struct net_device *netdev, struct gmac_txq *txq, 603 unsigned int r) 604 { 605 struct gemini_ethernet_port *port = netdev_priv(netdev); 606 unsigned int m = (1 << port->txq_order) - 1; 607 struct gemini_ethernet *geth = port->geth; 608 unsigned int c = txq->cptr; 609 union gmac_txdesc_0 word0; 610 union gmac_txdesc_1 word1; 611 unsigned int hwchksum = 0; 612 unsigned long bytes = 0; 613 struct gmac_txdesc *txd; 614 unsigned short nfrags; 615 unsigned int errs = 0; 616 unsigned int pkts = 0; 617 unsigned int word3; 618 dma_addr_t mapping; 619 620 if (c == r) 621 return; 622 623 while (c != r) { 624 txd = txq->ring + c; 625 word0 = txd->word0; 626 word1 = txd->word1; 627 mapping = txd->word2.buf_adr; 628 word3 = txd->word3.bits32; 629 630 dma_unmap_single(geth->dev, mapping, 631 word0.bits.buffer_size, DMA_TO_DEVICE); 632 633 if (word3 & EOF_BIT) 634 dev_kfree_skb(txq->skb[c]); 635 636 c++; 637 c &= m; 638 639 if (!(word3 & SOF_BIT)) 640 continue; 641 642 if (!word0.bits.status_tx_ok) { 643 errs++; 644 continue; 645 } 646 647 pkts++; 648 bytes += txd->word1.bits.byte_count; 649 650 if (word1.bits32 & TSS_CHECKUM_ENABLE) 651 hwchksum++; 652 653 nfrags = word0.bits.desc_count - 1; 654 if (nfrags) { 655 if (nfrags >= TX_MAX_FRAGS) 656 nfrags = TX_MAX_FRAGS - 1; 657 658 u64_stats_update_begin(&port->tx_stats_syncp); 659 port->tx_frag_stats[nfrags]++; 660 u64_stats_update_end(&port->tx_stats_syncp); 661 } 662 } 663 664 u64_stats_update_begin(&port->ir_stats_syncp); 665 port->stats.tx_errors += errs; 666 port->stats.tx_packets += pkts; 667 port->stats.tx_bytes += bytes; 668 port->tx_hw_csummed += hwchksum; 669 u64_stats_update_end(&port->ir_stats_syncp); 670 671 txq->cptr = c; 672 } 673 674 static void gmac_cleanup_txqs(struct net_device *netdev) 675 { 676 struct gemini_ethernet_port *port = netdev_priv(netdev); 677 unsigned int n_txq = netdev->num_tx_queues; 678 struct gemini_ethernet *geth = port->geth; 679 void __iomem *rwptr_reg; 680 unsigned int r, i; 681 682 rwptr_reg = port->dma_base + GMAC_SW_TX_QUEUE0_PTR_REG; 683 684 for (i = 0; i < n_txq; i++) { 685 r = readw(rwptr_reg); 686 rwptr_reg += 2; 687 writew(r, rwptr_reg); 688 rwptr_reg += 2; 689 690 gmac_clean_txq(netdev, port->txq + i, r); 691 } 692 writel(0, port->dma_base + GMAC_SW_TX_QUEUE_BASE_REG); 693 694 kfree(port->txq->skb); 695 dma_free_coherent(geth->dev, 696 n_txq * sizeof(*port->txq->ring) << port->txq_order, 697 port->txq->ring, port->txq_dma_base); 698 } 699 700 static int gmac_setup_rxq(struct net_device *netdev) 701 { 702 struct gemini_ethernet_port *port = netdev_priv(netdev); 703 struct gemini_ethernet *geth = port->geth; 704 struct nontoe_qhdr __iomem *qhdr; 705 706 qhdr = geth->base + TOE_DEFAULT_Q_HDR_BASE(netdev->dev_id); 707 port->rxq_rwptr = &qhdr->word1; 708 709 /* Remap a slew of memory to use for the RX queue */ 710 port->rxq_ring = dma_alloc_coherent(geth->dev, 711 sizeof(*port->rxq_ring) << port->rxq_order, 712 &port->rxq_dma_base, GFP_KERNEL); 713 if (!port->rxq_ring) 714 return -ENOMEM; 715 if (port->rxq_dma_base & ~NONTOE_QHDR0_BASE_MASK) { 716 dev_warn(geth->dev, "RX queue base is not aligned\n"); 717 return -ENOMEM; 718 } 719 720 writel(port->rxq_dma_base | port->rxq_order, &qhdr->word0); 721 writel(0, port->rxq_rwptr); 722 return 0; 723 } 724 725 static struct gmac_queue_page * 726 gmac_get_queue_page(struct gemini_ethernet *geth, 727 struct gemini_ethernet_port *port, 728 dma_addr_t addr) 729 { 730 struct gmac_queue_page *gpage; 731 dma_addr_t mapping; 732 int i; 733 734 /* Only look for even pages */ 735 mapping = addr & PAGE_MASK; 736 737 if (!geth->freeq_pages) { 738 dev_err(geth->dev, "try to get page with no page list\n"); 739 return NULL; 740 } 741 742 /* Look up a ring buffer page from virtual mapping */ 743 for (i = 0; i < geth->num_freeq_pages; i++) { 744 gpage = &geth->freeq_pages[i]; 745 if (gpage->mapping == mapping) 746 return gpage; 747 } 748 749 return NULL; 750 } 751 752 static void gmac_cleanup_rxq(struct net_device *netdev) 753 { 754 struct gemini_ethernet_port *port = netdev_priv(netdev); 755 struct gemini_ethernet *geth = port->geth; 756 struct gmac_rxdesc *rxd = port->rxq_ring; 757 static struct gmac_queue_page *gpage; 758 struct nontoe_qhdr __iomem *qhdr; 759 void __iomem *dma_reg; 760 void __iomem *ptr_reg; 761 dma_addr_t mapping; 762 union dma_rwptr rw; 763 unsigned int r, w; 764 765 qhdr = geth->base + 766 TOE_DEFAULT_Q_HDR_BASE(netdev->dev_id); 767 dma_reg = &qhdr->word0; 768 ptr_reg = &qhdr->word1; 769 770 rw.bits32 = readl(ptr_reg); 771 r = rw.bits.rptr; 772 w = rw.bits.wptr; 773 writew(r, ptr_reg + 2); 774 775 writel(0, dma_reg); 776 777 /* Loop from read pointer to write pointer of the RX queue 778 * and free up all pages by the queue. 779 */ 780 while (r != w) { 781 mapping = rxd[r].word2.buf_adr; 782 r++; 783 r &= ((1 << port->rxq_order) - 1); 784 785 if (!mapping) 786 continue; 787 788 /* Freeq pointers are one page off */ 789 gpage = gmac_get_queue_page(geth, port, mapping + PAGE_SIZE); 790 if (!gpage) { 791 dev_err(geth->dev, "could not find page\n"); 792 continue; 793 } 794 /* Release the RX queue reference to the page */ 795 put_page(gpage->page); 796 } 797 798 dma_free_coherent(geth->dev, sizeof(*port->rxq_ring) << port->rxq_order, 799 port->rxq_ring, port->rxq_dma_base); 800 } 801 802 static struct page *geth_freeq_alloc_map_page(struct gemini_ethernet *geth, 803 int pn) 804 { 805 struct gmac_rxdesc *freeq_entry; 806 struct gmac_queue_page *gpage; 807 unsigned int fpp_order; 808 unsigned int frag_len; 809 dma_addr_t mapping; 810 struct page *page; 811 int i; 812 813 /* First allocate and DMA map a single page */ 814 page = alloc_page(GFP_ATOMIC); 815 if (!page) 816 return NULL; 817 818 mapping = dma_map_single(geth->dev, page_address(page), 819 PAGE_SIZE, DMA_FROM_DEVICE); 820 if (dma_mapping_error(geth->dev, mapping)) { 821 put_page(page); 822 return NULL; 823 } 824 825 /* The assign the page mapping (physical address) to the buffer address 826 * in the hardware queue. PAGE_SHIFT on ARM is 12 (1 page is 4096 bytes, 827 * 4k), and the default RX frag order is 11 (fragments are up 20 2048 828 * bytes, 2k) so fpp_order (fragments per page order) is default 1. Thus 829 * each page normally needs two entries in the queue. 830 */ 831 frag_len = 1 << geth->freeq_frag_order; /* Usually 2048 */ 832 fpp_order = PAGE_SHIFT - geth->freeq_frag_order; 833 freeq_entry = geth->freeq_ring + (pn << fpp_order); 834 dev_dbg(geth->dev, "allocate page %d fragment length %d fragments per page %d, freeq entry %p\n", 835 pn, frag_len, (1 << fpp_order), freeq_entry); 836 for (i = (1 << fpp_order); i > 0; i--) { 837 freeq_entry->word2.buf_adr = mapping; 838 freeq_entry++; 839 mapping += frag_len; 840 } 841 842 /* If the freeq entry already has a page mapped, then unmap it. */ 843 gpage = &geth->freeq_pages[pn]; 844 if (gpage->page) { 845 mapping = geth->freeq_ring[pn << fpp_order].word2.buf_adr; 846 dma_unmap_single(geth->dev, mapping, frag_len, DMA_FROM_DEVICE); 847 /* This should be the last reference to the page so it gets 848 * released 849 */ 850 put_page(gpage->page); 851 } 852 853 /* Then put our new mapping into the page table */ 854 dev_dbg(geth->dev, "page %d, DMA addr: %08x, page %p\n", 855 pn, (unsigned int)mapping, page); 856 gpage->mapping = mapping; 857 gpage->page = page; 858 859 return page; 860 } 861 862 /** 863 * geth_fill_freeq() - Fill the freeq with empty fragments to use 864 * @geth: the ethernet adapter 865 * @refill: whether to reset the queue by filling in all freeq entries or 866 * just refill it, usually the interrupt to refill the queue happens when 867 * the queue is half empty. 868 */ 869 static unsigned int geth_fill_freeq(struct gemini_ethernet *geth, bool refill) 870 { 871 unsigned int fpp_order = PAGE_SHIFT - geth->freeq_frag_order; 872 unsigned int count = 0; 873 unsigned int pn, epn; 874 unsigned long flags; 875 union dma_rwptr rw; 876 unsigned int m_pn; 877 878 /* Mask for page */ 879 m_pn = (1 << (geth->freeq_order - fpp_order)) - 1; 880 881 spin_lock_irqsave(&geth->freeq_lock, flags); 882 883 rw.bits32 = readl(geth->base + GLOBAL_SWFQ_RWPTR_REG); 884 pn = (refill ? rw.bits.wptr : rw.bits.rptr) >> fpp_order; 885 epn = (rw.bits.rptr >> fpp_order) - 1; 886 epn &= m_pn; 887 888 /* Loop over the freeq ring buffer entries */ 889 while (pn != epn) { 890 struct gmac_queue_page *gpage; 891 struct page *page; 892 893 gpage = &geth->freeq_pages[pn]; 894 page = gpage->page; 895 896 dev_dbg(geth->dev, "fill entry %d page ref count %d add %d refs\n", 897 pn, page_ref_count(page), 1 << fpp_order); 898 899 if (page_ref_count(page) > 1) { 900 unsigned int fl = (pn - epn) & m_pn; 901 902 if (fl > 64 >> fpp_order) 903 break; 904 905 page = geth_freeq_alloc_map_page(geth, pn); 906 if (!page) 907 break; 908 } 909 910 /* Add one reference per fragment in the page */ 911 page_ref_add(page, 1 << fpp_order); 912 count += 1 << fpp_order; 913 pn++; 914 pn &= m_pn; 915 } 916 917 writew(pn << fpp_order, geth->base + GLOBAL_SWFQ_RWPTR_REG + 2); 918 919 spin_unlock_irqrestore(&geth->freeq_lock, flags); 920 921 return count; 922 } 923 924 static int geth_setup_freeq(struct gemini_ethernet *geth) 925 { 926 unsigned int fpp_order = PAGE_SHIFT - geth->freeq_frag_order; 927 unsigned int frag_len = 1 << geth->freeq_frag_order; 928 unsigned int len = 1 << geth->freeq_order; 929 unsigned int pages = len >> fpp_order; 930 union queue_threshold qt; 931 union dma_skb_size skbsz; 932 unsigned int filled; 933 unsigned int pn; 934 935 geth->freeq_ring = dma_alloc_coherent(geth->dev, 936 sizeof(*geth->freeq_ring) << geth->freeq_order, 937 &geth->freeq_dma_base, GFP_KERNEL); 938 if (!geth->freeq_ring) 939 return -ENOMEM; 940 if (geth->freeq_dma_base & ~DMA_Q_BASE_MASK) { 941 dev_warn(geth->dev, "queue ring base is not aligned\n"); 942 goto err_freeq; 943 } 944 945 /* Allocate a mapping to page look-up index */ 946 geth->freeq_pages = kzalloc_objs(*geth->freeq_pages, pages); 947 if (!geth->freeq_pages) 948 goto err_freeq; 949 geth->num_freeq_pages = pages; 950 951 dev_info(geth->dev, "allocate %d pages for queue\n", pages); 952 for (pn = 0; pn < pages; pn++) 953 if (!geth_freeq_alloc_map_page(geth, pn)) 954 goto err_freeq_alloc; 955 956 filled = geth_fill_freeq(geth, false); 957 if (!filled) 958 goto err_freeq_alloc; 959 960 qt.bits32 = readl(geth->base + GLOBAL_QUEUE_THRESHOLD_REG); 961 qt.bits.swfq_empty = 32; 962 writel(qt.bits32, geth->base + GLOBAL_QUEUE_THRESHOLD_REG); 963 964 skbsz.bits.sw_skb_size = 1 << geth->freeq_frag_order; 965 writel(skbsz.bits32, geth->base + GLOBAL_DMA_SKB_SIZE_REG); 966 writel(geth->freeq_dma_base | geth->freeq_order, 967 geth->base + GLOBAL_SW_FREEQ_BASE_SIZE_REG); 968 969 return 0; 970 971 err_freeq_alloc: 972 while (pn > 0) { 973 struct gmac_queue_page *gpage; 974 dma_addr_t mapping; 975 976 --pn; 977 mapping = geth->freeq_ring[pn << fpp_order].word2.buf_adr; 978 dma_unmap_single(geth->dev, mapping, frag_len, DMA_FROM_DEVICE); 979 gpage = &geth->freeq_pages[pn]; 980 put_page(gpage->page); 981 } 982 983 kfree(geth->freeq_pages); 984 err_freeq: 985 dma_free_coherent(geth->dev, 986 sizeof(*geth->freeq_ring) << geth->freeq_order, 987 geth->freeq_ring, geth->freeq_dma_base); 988 geth->freeq_ring = NULL; 989 return -ENOMEM; 990 } 991 992 /** 993 * geth_cleanup_freeq() - cleanup the DMA mappings and free the queue 994 * @geth: the Gemini global ethernet state 995 */ 996 static void geth_cleanup_freeq(struct gemini_ethernet *geth) 997 { 998 unsigned int fpp_order = PAGE_SHIFT - geth->freeq_frag_order; 999 unsigned int frag_len = 1 << geth->freeq_frag_order; 1000 unsigned int len = 1 << geth->freeq_order; 1001 unsigned int pages = len >> fpp_order; 1002 unsigned int pn; 1003 1004 writew(readw(geth->base + GLOBAL_SWFQ_RWPTR_REG), 1005 geth->base + GLOBAL_SWFQ_RWPTR_REG + 2); 1006 writel(0, geth->base + GLOBAL_SW_FREEQ_BASE_SIZE_REG); 1007 1008 for (pn = 0; pn < pages; pn++) { 1009 struct gmac_queue_page *gpage; 1010 dma_addr_t mapping; 1011 1012 mapping = geth->freeq_ring[pn << fpp_order].word2.buf_adr; 1013 dma_unmap_single(geth->dev, mapping, frag_len, DMA_FROM_DEVICE); 1014 1015 gpage = &geth->freeq_pages[pn]; 1016 while (page_ref_count(gpage->page) > 0) 1017 put_page(gpage->page); 1018 } 1019 1020 kfree(geth->freeq_pages); 1021 1022 dma_free_coherent(geth->dev, 1023 sizeof(*geth->freeq_ring) << geth->freeq_order, 1024 geth->freeq_ring, geth->freeq_dma_base); 1025 } 1026 1027 /** 1028 * geth_resize_freeq() - resize the software queue depth 1029 * @port: the port requesting the change 1030 * 1031 * This gets called at least once during probe() so the device queue gets 1032 * "resized" from the hardware defaults. Since both ports/net devices share 1033 * the same hardware queue, some synchronization between the ports is 1034 * needed. 1035 */ 1036 static int geth_resize_freeq(struct gemini_ethernet_port *port) 1037 { 1038 struct gemini_ethernet *geth = port->geth; 1039 struct net_device *netdev = port->netdev; 1040 struct gemini_ethernet_port *other_port; 1041 struct net_device *other_netdev; 1042 unsigned int new_size = 0; 1043 unsigned int new_order; 1044 unsigned long flags; 1045 u32 en; 1046 int ret; 1047 1048 if (netdev->dev_id == 0) 1049 other_netdev = geth->port1->netdev; 1050 else 1051 other_netdev = geth->port0->netdev; 1052 1053 if (other_netdev && netif_running(other_netdev)) 1054 return -EBUSY; 1055 1056 new_size = 1 << (port->rxq_order + 1); 1057 netdev_dbg(netdev, "port %d size: %d order %d\n", 1058 netdev->dev_id, 1059 new_size, 1060 port->rxq_order); 1061 if (other_netdev) { 1062 other_port = netdev_priv(other_netdev); 1063 new_size += 1 << (other_port->rxq_order + 1); 1064 netdev_dbg(other_netdev, "port %d size: %d order %d\n", 1065 other_netdev->dev_id, 1066 (1 << (other_port->rxq_order + 1)), 1067 other_port->rxq_order); 1068 } 1069 1070 new_order = min(15, ilog2(new_size - 1) + 1); 1071 dev_dbg(geth->dev, "set shared queue to size %d order %d\n", 1072 new_size, new_order); 1073 if (geth->freeq_order == new_order) 1074 return 0; 1075 1076 spin_lock_irqsave(&geth->irq_lock, flags); 1077 1078 /* Disable the software queue IRQs */ 1079 en = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG); 1080 en &= ~SWFQ_EMPTY_INT_BIT; 1081 writel(en, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG); 1082 spin_unlock_irqrestore(&geth->irq_lock, flags); 1083 1084 /* Drop the old queue */ 1085 if (geth->freeq_ring) 1086 geth_cleanup_freeq(geth); 1087 1088 /* Allocate a new queue with the desired order */ 1089 geth->freeq_order = new_order; 1090 ret = geth_setup_freeq(geth); 1091 1092 /* Restart the interrupts - NOTE if this is the first resize 1093 * after probe(), this is where the interrupts get turned on 1094 * in the first place. 1095 */ 1096 spin_lock_irqsave(&geth->irq_lock, flags); 1097 en |= SWFQ_EMPTY_INT_BIT; 1098 writel(en, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG); 1099 spin_unlock_irqrestore(&geth->irq_lock, flags); 1100 1101 return ret; 1102 } 1103 1104 static void gmac_tx_irq_enable(struct net_device *netdev, 1105 unsigned int txq, int en) 1106 { 1107 struct gemini_ethernet_port *port = netdev_priv(netdev); 1108 struct gemini_ethernet *geth = port->geth; 1109 unsigned long flags; 1110 u32 val, mask; 1111 1112 netdev_dbg(netdev, "%s device %d\n", __func__, netdev->dev_id); 1113 1114 spin_lock_irqsave(&geth->irq_lock, flags); 1115 1116 mask = GMAC0_IRQ0_TXQ0_INTS << (6 * netdev->dev_id + txq); 1117 1118 if (en) 1119 writel(mask, geth->base + GLOBAL_INTERRUPT_STATUS_0_REG); 1120 1121 val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG); 1122 val = en ? val | mask : val & ~mask; 1123 writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG); 1124 1125 spin_unlock_irqrestore(&geth->irq_lock, flags); 1126 } 1127 1128 static void gmac_tx_irq(struct net_device *netdev, unsigned int txq_num) 1129 { 1130 struct netdev_queue *ntxq = netdev_get_tx_queue(netdev, txq_num); 1131 1132 gmac_tx_irq_enable(netdev, txq_num, 0); 1133 netif_tx_wake_queue(ntxq); 1134 } 1135 1136 static int gmac_map_tx_bufs(struct net_device *netdev, struct sk_buff *skb, 1137 struct gmac_txq *txq, unsigned short *desc) 1138 { 1139 struct gemini_ethernet_port *port = netdev_priv(netdev); 1140 struct skb_shared_info *skb_si = skb_shinfo(skb); 1141 unsigned short m = (1 << port->txq_order) - 1; 1142 short frag, last_frag = skb_si->nr_frags - 1; 1143 struct gemini_ethernet *geth = port->geth; 1144 unsigned int word1, word3, buflen; 1145 unsigned short w = *desc; 1146 struct gmac_txdesc *txd; 1147 skb_frag_t *skb_frag; 1148 dma_addr_t mapping; 1149 bool tcp = false; 1150 void *buffer; 1151 u16 mss; 1152 int ret; 1153 1154 word1 = skb->len; 1155 word3 = SOF_BIT; 1156 1157 /* Determine if we are doing TCP */ 1158 if (skb->protocol == htons(ETH_P_IP)) 1159 tcp = (ip_hdr(skb)->protocol == IPPROTO_TCP); 1160 else 1161 /* IPv6 */ 1162 tcp = (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP); 1163 1164 mss = skb_shinfo(skb)->gso_size; 1165 if (mss) { 1166 /* This means we are dealing with TCP and skb->len is the 1167 * sum total of all the segments. The TSO will deal with 1168 * chopping this up for us. 1169 */ 1170 /* The accelerator needs the full frame size here */ 1171 mss += skb_tcp_all_headers(skb); 1172 netdev_dbg(netdev, "segment offloading mss = %04x len=%04x\n", 1173 mss, skb->len); 1174 word1 |= TSS_MTU_ENABLE_BIT; 1175 word3 |= mss; 1176 } else if (tcp) { 1177 /* Even if we are not using TSO, use the hardware offloader 1178 * for transferring the TCP frame: this hardware has partial 1179 * TCP awareness (called TOE - TCP Offload Engine) and will 1180 * according to the datasheet put packets belonging to the 1181 * same TCP connection in the same queue for the TOE/TSO 1182 * engine to process. The engine will deal with chopping 1183 * up frames that exceed ETH_DATA_LEN which the 1184 * checksumming engine cannot handle (see below) into 1185 * manageable chunks. It flawlessly deals with quite big 1186 * frames and frames containing custom DSA EtherTypes. 1187 */ 1188 mss = netdev->mtu + skb_tcp_all_headers(skb); 1189 mss = min(mss, skb->len); 1190 netdev_dbg(netdev, "TOE/TSO len %04x mtu %04x mss %04x\n", 1191 skb->len, netdev->mtu, mss); 1192 word1 |= TSS_MTU_ENABLE_BIT; 1193 word3 |= mss; 1194 } else if (skb->len >= ETH_FRAME_LEN) { 1195 /* Hardware offloaded checksumming isn't working on non-TCP frames 1196 * bigger than 1514 bytes. A hypothesis about this is that the 1197 * checksum buffer is only 1518 bytes, so when the frames get 1198 * bigger they get truncated, or the last few bytes get 1199 * overwritten by the FCS. 1200 * 1201 * Just use software checksumming and bypass on bigger frames. 1202 */ 1203 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1204 ret = skb_checksum_help(skb); 1205 if (ret) 1206 return ret; 1207 } 1208 word1 |= TSS_BYPASS_BIT; 1209 } 1210 1211 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1212 /* We do not switch off the checksumming on non TCP/UDP 1213 * frames: as is shown from tests, the checksumming engine 1214 * is smart enough to see that a frame is not actually TCP 1215 * or UDP and then just pass it through without any changes 1216 * to the frame. 1217 */ 1218 if (skb->protocol == htons(ETH_P_IP)) 1219 word1 |= TSS_IP_CHKSUM_BIT; 1220 else 1221 word1 |= TSS_IPV6_ENABLE_BIT; 1222 1223 word1 |= tcp ? TSS_TCP_CHKSUM_BIT : TSS_UDP_CHKSUM_BIT; 1224 } 1225 1226 frag = -1; 1227 while (frag <= last_frag) { 1228 if (frag == -1) { 1229 buffer = skb->data; 1230 buflen = skb_headlen(skb); 1231 } else { 1232 skb_frag = skb_si->frags + frag; 1233 buffer = skb_frag_address(skb_frag); 1234 buflen = skb_frag_size(skb_frag); 1235 } 1236 1237 if (frag == last_frag) { 1238 word3 |= EOF_BIT; 1239 txq->skb[w] = skb; 1240 } 1241 1242 mapping = dma_map_single(geth->dev, buffer, buflen, 1243 DMA_TO_DEVICE); 1244 if (dma_mapping_error(geth->dev, mapping)) 1245 goto map_error; 1246 1247 txd = txq->ring + w; 1248 txd->word0.bits32 = buflen; 1249 txd->word1.bits32 = word1; 1250 txd->word2.buf_adr = mapping; 1251 txd->word3.bits32 = word3; 1252 1253 word3 &= MTU_SIZE_BIT_MASK; 1254 w++; 1255 w &= m; 1256 frag++; 1257 } 1258 1259 *desc = w; 1260 return 0; 1261 1262 map_error: 1263 while (w != *desc) { 1264 w--; 1265 w &= m; 1266 1267 dma_unmap_page(geth->dev, txq->ring[w].word2.buf_adr, 1268 txq->ring[w].word0.bits.buffer_size, 1269 DMA_TO_DEVICE); 1270 } 1271 return -ENOMEM; 1272 } 1273 1274 static netdev_tx_t gmac_start_xmit(struct sk_buff *skb, 1275 struct net_device *netdev) 1276 { 1277 struct gemini_ethernet_port *port = netdev_priv(netdev); 1278 unsigned short m = (1 << port->txq_order) - 1; 1279 struct netdev_queue *ntxq; 1280 unsigned short r, w, d; 1281 void __iomem *ptr_reg; 1282 struct gmac_txq *txq; 1283 int txq_num, nfrags; 1284 union dma_rwptr rw; 1285 1286 if (skb->len >= 0x10000) 1287 goto out_drop_free; 1288 1289 txq_num = skb_get_queue_mapping(skb); 1290 ptr_reg = port->dma_base + GMAC_SW_TX_QUEUE_PTR_REG(txq_num); 1291 txq = &port->txq[txq_num]; 1292 ntxq = netdev_get_tx_queue(netdev, txq_num); 1293 nfrags = skb_shinfo(skb)->nr_frags; 1294 1295 rw.bits32 = readl(ptr_reg); 1296 r = rw.bits.rptr; 1297 w = rw.bits.wptr; 1298 1299 d = txq->cptr - w - 1; 1300 d &= m; 1301 1302 if (d < nfrags + 2) { 1303 gmac_clean_txq(netdev, txq, r); 1304 d = txq->cptr - w - 1; 1305 d &= m; 1306 1307 if (d < nfrags + 2) { 1308 netif_tx_stop_queue(ntxq); 1309 1310 d = txq->cptr + nfrags + 16; 1311 d &= m; 1312 txq->ring[d].word3.bits.eofie = 1; 1313 gmac_tx_irq_enable(netdev, txq_num, 1); 1314 1315 u64_stats_update_begin(&port->tx_stats_syncp); 1316 netdev->stats.tx_fifo_errors++; 1317 u64_stats_update_end(&port->tx_stats_syncp); 1318 return NETDEV_TX_BUSY; 1319 } 1320 } 1321 1322 if (gmac_map_tx_bufs(netdev, skb, txq, &w)) { 1323 if (skb_linearize(skb)) 1324 goto out_drop; 1325 1326 u64_stats_update_begin(&port->tx_stats_syncp); 1327 port->tx_frags_linearized++; 1328 u64_stats_update_end(&port->tx_stats_syncp); 1329 1330 if (gmac_map_tx_bufs(netdev, skb, txq, &w)) 1331 goto out_drop_free; 1332 } 1333 1334 writew(w, ptr_reg + 2); 1335 1336 gmac_clean_txq(netdev, txq, r); 1337 return NETDEV_TX_OK; 1338 1339 out_drop_free: 1340 dev_kfree_skb(skb); 1341 out_drop: 1342 u64_stats_update_begin(&port->tx_stats_syncp); 1343 port->stats.tx_dropped++; 1344 u64_stats_update_end(&port->tx_stats_syncp); 1345 return NETDEV_TX_OK; 1346 } 1347 1348 static void gmac_tx_timeout(struct net_device *netdev, unsigned int txqueue) 1349 { 1350 netdev_err(netdev, "Tx timeout\n"); 1351 gmac_dump_dma_state(netdev); 1352 } 1353 1354 static void gmac_enable_irq(struct net_device *netdev, int enable) 1355 { 1356 struct gemini_ethernet_port *port = netdev_priv(netdev); 1357 struct gemini_ethernet *geth = port->geth; 1358 unsigned long flags; 1359 u32 val, mask; 1360 1361 netdev_dbg(netdev, "%s device %d %s\n", __func__, 1362 netdev->dev_id, enable ? "enable" : "disable"); 1363 spin_lock_irqsave(&geth->irq_lock, flags); 1364 1365 mask = GMAC0_IRQ0_2 << (netdev->dev_id * 2); 1366 val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG); 1367 val = enable ? (val | mask) : (val & ~mask); 1368 writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG); 1369 1370 mask = DEFAULT_Q0_INT_BIT << netdev->dev_id; 1371 val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG); 1372 val = enable ? (val | mask) : (val & ~mask); 1373 writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG); 1374 1375 mask = GMAC0_IRQ4_8 << (netdev->dev_id * 8); 1376 val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG); 1377 val = enable ? (val | mask) : (val & ~mask); 1378 writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG); 1379 1380 spin_unlock_irqrestore(&geth->irq_lock, flags); 1381 } 1382 1383 static void gmac_enable_rx_irq(struct net_device *netdev, int enable) 1384 { 1385 struct gemini_ethernet_port *port = netdev_priv(netdev); 1386 struct gemini_ethernet *geth = port->geth; 1387 unsigned long flags; 1388 u32 val, mask; 1389 1390 netdev_dbg(netdev, "%s device %d %s\n", __func__, netdev->dev_id, 1391 enable ? "enable" : "disable"); 1392 spin_lock_irqsave(&geth->irq_lock, flags); 1393 mask = DEFAULT_Q0_INT_BIT << netdev->dev_id; 1394 1395 val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG); 1396 val = enable ? (val | mask) : (val & ~mask); 1397 writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG); 1398 1399 spin_unlock_irqrestore(&geth->irq_lock, flags); 1400 } 1401 1402 static struct sk_buff *gmac_skb_if_good_frame(struct gemini_ethernet_port *port, 1403 union gmac_rxdesc_0 word0, 1404 unsigned int frame_len) 1405 { 1406 unsigned int rx_csum = word0.bits.chksum_status; 1407 unsigned int rx_status = word0.bits.status; 1408 struct sk_buff *skb = NULL; 1409 1410 port->rx_stats[rx_status]++; 1411 port->rx_csum_stats[rx_csum]++; 1412 1413 if (word0.bits.derr || word0.bits.perr || 1414 rx_status || frame_len < ETH_ZLEN || 1415 rx_csum >= RX_CHKSUM_IP_ERR_UNKNOWN) { 1416 port->stats.rx_errors++; 1417 1418 if (frame_len < ETH_ZLEN || RX_ERROR_LENGTH(rx_status)) 1419 port->stats.rx_length_errors++; 1420 if (RX_ERROR_OVER(rx_status)) 1421 port->stats.rx_over_errors++; 1422 if (RX_ERROR_CRC(rx_status)) 1423 port->stats.rx_crc_errors++; 1424 if (RX_ERROR_FRAME(rx_status)) 1425 port->stats.rx_frame_errors++; 1426 return NULL; 1427 } 1428 1429 skb = napi_get_frags(&port->napi); 1430 if (!skb) 1431 goto update_exit; 1432 1433 if (rx_csum == RX_CHKSUM_IP_UDP_TCP_OK) 1434 skb->ip_summed = CHECKSUM_UNNECESSARY; 1435 1436 update_exit: 1437 port->stats.rx_bytes += frame_len; 1438 port->stats.rx_packets++; 1439 return skb; 1440 } 1441 1442 static unsigned int gmac_rx(struct net_device *netdev, unsigned int budget) 1443 { 1444 struct gemini_ethernet_port *port = netdev_priv(netdev); 1445 unsigned short m = (1 << port->rxq_order) - 1; 1446 struct gemini_ethernet *geth = port->geth; 1447 void __iomem *ptr_reg = port->rxq_rwptr; 1448 unsigned int frag_nr = port->rx_frag_nr; 1449 struct sk_buff *skb = port->rx_skb; 1450 unsigned int frame_len, frag_len; 1451 struct gmac_rxdesc *rx = NULL; 1452 struct gmac_queue_page *gpage; 1453 union gmac_rxdesc_0 word0; 1454 union gmac_rxdesc_1 word1; 1455 union gmac_rxdesc_3 word3; 1456 struct page *page = NULL; 1457 unsigned int page_offs; 1458 unsigned long flags; 1459 unsigned short r, w; 1460 union dma_rwptr rw; 1461 dma_addr_t mapping; 1462 1463 spin_lock_irqsave(&geth->irq_lock, flags); 1464 rw.bits32 = readl(ptr_reg); 1465 /* Reset interrupt as all packages until here are taken into account */ 1466 writel(DEFAULT_Q0_INT_BIT << netdev->dev_id, 1467 geth->base + GLOBAL_INTERRUPT_STATUS_1_REG); 1468 spin_unlock_irqrestore(&geth->irq_lock, flags); 1469 1470 r = rw.bits.rptr; 1471 w = rw.bits.wptr; 1472 1473 while (budget && w != r) { 1474 rx = port->rxq_ring + r; 1475 word0 = rx->word0; 1476 word1 = rx->word1; 1477 mapping = rx->word2.buf_adr; 1478 word3 = rx->word3; 1479 1480 r++; 1481 r &= m; 1482 1483 frag_len = word0.bits.buffer_size; 1484 frame_len = word1.bits.byte_count; 1485 page_offs = mapping & ~PAGE_MASK; 1486 1487 if (!mapping) { 1488 netdev_err(netdev, 1489 "rxq[%u]: HW BUG: zero DMA desc\n", r); 1490 goto err_drop; 1491 } 1492 1493 /* Freeq pointers are one page off */ 1494 gpage = gmac_get_queue_page(geth, port, mapping + PAGE_SIZE); 1495 if (!gpage) { 1496 dev_err(geth->dev, "could not find mapping\n"); 1497 port->stats.rx_dropped++; 1498 if (skb) { 1499 napi_free_frags(&port->napi); 1500 skb = NULL; 1501 frag_nr = 0; 1502 } 1503 continue; 1504 } 1505 page = gpage->page; 1506 1507 if (word3.bits32 & SOF_BIT) { 1508 if (skb) { 1509 napi_free_frags(&port->napi); 1510 port->stats.rx_dropped++; 1511 skb = NULL; 1512 frag_nr = 0; 1513 } 1514 1515 skb = gmac_skb_if_good_frame(port, word0, frame_len); 1516 if (!skb) 1517 goto err_drop; 1518 1519 page_offs += NET_IP_ALIGN; 1520 frag_len -= NET_IP_ALIGN; 1521 frag_nr = 0; 1522 1523 } else if (!skb) { 1524 put_page(page); 1525 continue; 1526 } 1527 1528 if (word3.bits32 & EOF_BIT) 1529 frag_len = frame_len - skb->len; 1530 1531 /* append page frag to skb */ 1532 if (frag_nr == MAX_SKB_FRAGS) 1533 goto err_drop; 1534 1535 if (frag_len == 0) 1536 netdev_err(netdev, "Received fragment with len = 0\n"); 1537 1538 skb_fill_page_desc(skb, frag_nr, page, page_offs, frag_len); 1539 skb->len += frag_len; 1540 skb->data_len += frag_len; 1541 skb->truesize += frag_len; 1542 frag_nr++; 1543 1544 if (word3.bits32 & EOF_BIT) { 1545 napi_gro_frags(&port->napi); 1546 skb = NULL; 1547 frag_nr = 0; 1548 --budget; 1549 } 1550 continue; 1551 1552 err_drop: 1553 if (skb) { 1554 napi_free_frags(&port->napi); 1555 skb = NULL; 1556 frag_nr = 0; 1557 } 1558 1559 if (mapping) 1560 put_page(page); 1561 1562 port->stats.rx_dropped++; 1563 } 1564 1565 port->rx_skb = skb; 1566 port->rx_frag_nr = frag_nr; 1567 writew(r, ptr_reg); 1568 return budget; 1569 } 1570 1571 static int gmac_napi_poll(struct napi_struct *napi, int budget) 1572 { 1573 struct gemini_ethernet_port *port = netdev_priv(napi->dev); 1574 struct gemini_ethernet *geth = port->geth; 1575 unsigned int freeq_threshold; 1576 unsigned int received; 1577 1578 freeq_threshold = 1 << (geth->freeq_order - 1); 1579 u64_stats_update_begin(&port->rx_stats_syncp); 1580 1581 received = gmac_rx(napi->dev, budget); 1582 if (received < budget) { 1583 napi_gro_flush(napi, false); 1584 napi_complete_done(napi, received); 1585 gmac_enable_rx_irq(napi->dev, 1); 1586 ++port->rx_napi_exits; 1587 } 1588 1589 port->freeq_refill += (budget - received); 1590 if (port->freeq_refill > freeq_threshold) { 1591 port->freeq_refill -= freeq_threshold; 1592 geth_fill_freeq(geth, true); 1593 } 1594 1595 u64_stats_update_end(&port->rx_stats_syncp); 1596 return received; 1597 } 1598 1599 static void gmac_dump_dma_state(struct net_device *netdev) 1600 { 1601 struct gemini_ethernet_port *port = netdev_priv(netdev); 1602 struct gemini_ethernet *geth = port->geth; 1603 void __iomem *ptr_reg; 1604 u32 reg[5]; 1605 1606 /* Interrupt status */ 1607 reg[0] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_0_REG); 1608 reg[1] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_1_REG); 1609 reg[2] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_2_REG); 1610 reg[3] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_3_REG); 1611 reg[4] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_4_REG); 1612 netdev_err(netdev, "IRQ status: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", 1613 reg[0], reg[1], reg[2], reg[3], reg[4]); 1614 1615 /* Interrupt enable */ 1616 reg[0] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG); 1617 reg[1] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG); 1618 reg[2] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_2_REG); 1619 reg[3] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_3_REG); 1620 reg[4] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG); 1621 netdev_err(netdev, "IRQ enable: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", 1622 reg[0], reg[1], reg[2], reg[3], reg[4]); 1623 1624 /* RX DMA status */ 1625 reg[0] = readl(port->dma_base + GMAC_DMA_RX_FIRST_DESC_REG); 1626 reg[1] = readl(port->dma_base + GMAC_DMA_RX_CURR_DESC_REG); 1627 reg[2] = GET_RPTR(port->rxq_rwptr); 1628 reg[3] = GET_WPTR(port->rxq_rwptr); 1629 netdev_err(netdev, "RX DMA regs: 0x%08x 0x%08x, ptr: %u %u\n", 1630 reg[0], reg[1], reg[2], reg[3]); 1631 1632 reg[0] = readl(port->dma_base + GMAC_DMA_RX_DESC_WORD0_REG); 1633 reg[1] = readl(port->dma_base + GMAC_DMA_RX_DESC_WORD1_REG); 1634 reg[2] = readl(port->dma_base + GMAC_DMA_RX_DESC_WORD2_REG); 1635 reg[3] = readl(port->dma_base + GMAC_DMA_RX_DESC_WORD3_REG); 1636 netdev_err(netdev, "RX DMA descriptor: 0x%08x 0x%08x 0x%08x 0x%08x\n", 1637 reg[0], reg[1], reg[2], reg[3]); 1638 1639 /* TX DMA status */ 1640 ptr_reg = port->dma_base + GMAC_SW_TX_QUEUE0_PTR_REG; 1641 1642 reg[0] = readl(port->dma_base + GMAC_DMA_TX_FIRST_DESC_REG); 1643 reg[1] = readl(port->dma_base + GMAC_DMA_TX_CURR_DESC_REG); 1644 reg[2] = GET_RPTR(ptr_reg); 1645 reg[3] = GET_WPTR(ptr_reg); 1646 netdev_err(netdev, "TX DMA regs: 0x%08x 0x%08x, ptr: %u %u\n", 1647 reg[0], reg[1], reg[2], reg[3]); 1648 1649 reg[0] = readl(port->dma_base + GMAC_DMA_TX_DESC_WORD0_REG); 1650 reg[1] = readl(port->dma_base + GMAC_DMA_TX_DESC_WORD1_REG); 1651 reg[2] = readl(port->dma_base + GMAC_DMA_TX_DESC_WORD2_REG); 1652 reg[3] = readl(port->dma_base + GMAC_DMA_TX_DESC_WORD3_REG); 1653 netdev_err(netdev, "TX DMA descriptor: 0x%08x 0x%08x 0x%08x 0x%08x\n", 1654 reg[0], reg[1], reg[2], reg[3]); 1655 1656 /* FREE queues status */ 1657 ptr_reg = geth->base + GLOBAL_SWFQ_RWPTR_REG; 1658 1659 reg[0] = GET_RPTR(ptr_reg); 1660 reg[1] = GET_WPTR(ptr_reg); 1661 1662 ptr_reg = geth->base + GLOBAL_HWFQ_RWPTR_REG; 1663 1664 reg[2] = GET_RPTR(ptr_reg); 1665 reg[3] = GET_WPTR(ptr_reg); 1666 netdev_err(netdev, "FQ SW ptr: %u %u, HW ptr: %u %u\n", 1667 reg[0], reg[1], reg[2], reg[3]); 1668 } 1669 1670 static void gmac_update_hw_stats(struct net_device *netdev) 1671 { 1672 struct gemini_ethernet_port *port = netdev_priv(netdev); 1673 unsigned int rx_discards, rx_mcast, rx_bcast; 1674 struct gemini_ethernet *geth = port->geth; 1675 unsigned long flags; 1676 1677 spin_lock_irqsave(&geth->irq_lock, flags); 1678 u64_stats_update_begin(&port->ir_stats_syncp); 1679 1680 rx_discards = readl(port->gmac_base + GMAC_IN_DISCARDS); 1681 port->hw_stats[0] += rx_discards; 1682 port->hw_stats[1] += readl(port->gmac_base + GMAC_IN_ERRORS); 1683 rx_mcast = readl(port->gmac_base + GMAC_IN_MCAST); 1684 port->hw_stats[2] += rx_mcast; 1685 rx_bcast = readl(port->gmac_base + GMAC_IN_BCAST); 1686 port->hw_stats[3] += rx_bcast; 1687 port->hw_stats[4] += readl(port->gmac_base + GMAC_IN_MAC1); 1688 port->hw_stats[5] += readl(port->gmac_base + GMAC_IN_MAC2); 1689 1690 port->stats.rx_missed_errors += rx_discards; 1691 port->stats.multicast += rx_mcast; 1692 port->stats.multicast += rx_bcast; 1693 1694 writel(GMAC0_MIB_INT_BIT << (netdev->dev_id * 8), 1695 geth->base + GLOBAL_INTERRUPT_STATUS_4_REG); 1696 1697 u64_stats_update_end(&port->ir_stats_syncp); 1698 spin_unlock_irqrestore(&geth->irq_lock, flags); 1699 } 1700 1701 /** 1702 * gmac_get_intr_flags() - get interrupt status flags for a port from 1703 * @netdev: the net device for the port to get flags from 1704 * @i: the interrupt status register 0..4 1705 */ 1706 static u32 gmac_get_intr_flags(struct net_device *netdev, int i) 1707 { 1708 struct gemini_ethernet_port *port = netdev_priv(netdev); 1709 struct gemini_ethernet *geth = port->geth; 1710 void __iomem *irqif_reg, *irqen_reg; 1711 unsigned int offs, val; 1712 1713 /* Calculate the offset using the stride of the status registers */ 1714 offs = i * (GLOBAL_INTERRUPT_STATUS_1_REG - 1715 GLOBAL_INTERRUPT_STATUS_0_REG); 1716 1717 irqif_reg = geth->base + GLOBAL_INTERRUPT_STATUS_0_REG + offs; 1718 irqen_reg = geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG + offs; 1719 1720 val = readl(irqif_reg) & readl(irqen_reg); 1721 return val; 1722 } 1723 1724 static enum hrtimer_restart gmac_coalesce_delay_expired(struct hrtimer *timer) 1725 { 1726 struct gemini_ethernet_port *port = 1727 container_of(timer, struct gemini_ethernet_port, 1728 rx_coalesce_timer); 1729 1730 napi_schedule(&port->napi); 1731 return HRTIMER_NORESTART; 1732 } 1733 1734 static irqreturn_t gmac_irq(int irq, void *data) 1735 { 1736 struct gemini_ethernet_port *port; 1737 struct net_device *netdev = data; 1738 struct gemini_ethernet *geth; 1739 u32 val, orr = 0; 1740 1741 port = netdev_priv(netdev); 1742 geth = port->geth; 1743 1744 val = gmac_get_intr_flags(netdev, 0); 1745 orr |= val; 1746 1747 if (val & (GMAC0_IRQ0_2 << (netdev->dev_id * 2))) { 1748 /* Oh, crap */ 1749 netdev_err(netdev, "hw failure/sw bug\n"); 1750 gmac_dump_dma_state(netdev); 1751 1752 /* don't know how to recover, just reduce losses */ 1753 gmac_enable_irq(netdev, 0); 1754 return IRQ_HANDLED; 1755 } 1756 1757 if (val & (GMAC0_IRQ0_TXQ0_INTS << (netdev->dev_id * 6))) 1758 gmac_tx_irq(netdev, 0); 1759 1760 val = gmac_get_intr_flags(netdev, 1); 1761 orr |= val; 1762 1763 if (val & (DEFAULT_Q0_INT_BIT << netdev->dev_id)) { 1764 gmac_enable_rx_irq(netdev, 0); 1765 1766 if (!port->rx_coalesce_nsecs) { 1767 napi_schedule(&port->napi); 1768 } else { 1769 ktime_t ktime; 1770 1771 ktime = ktime_set(0, port->rx_coalesce_nsecs); 1772 hrtimer_start(&port->rx_coalesce_timer, ktime, 1773 HRTIMER_MODE_REL); 1774 } 1775 } 1776 1777 val = gmac_get_intr_flags(netdev, 4); 1778 orr |= val; 1779 1780 if (val & (GMAC0_MIB_INT_BIT << (netdev->dev_id * 8))) 1781 gmac_update_hw_stats(netdev); 1782 1783 if (val & (GMAC0_RX_OVERRUN_INT_BIT << (netdev->dev_id * 8))) { 1784 spin_lock(&geth->irq_lock); 1785 writel(GMAC0_RXDERR_INT_BIT << (netdev->dev_id * 8), 1786 geth->base + GLOBAL_INTERRUPT_STATUS_4_REG); 1787 u64_stats_update_begin(&port->ir_stats_syncp); 1788 ++port->stats.rx_fifo_errors; 1789 u64_stats_update_end(&port->ir_stats_syncp); 1790 spin_unlock(&geth->irq_lock); 1791 } 1792 1793 return orr ? IRQ_HANDLED : IRQ_NONE; 1794 } 1795 1796 static void gmac_start_dma(struct gemini_ethernet_port *port) 1797 { 1798 void __iomem *dma_ctrl_reg = port->dma_base + GMAC_DMA_CTRL_REG; 1799 union gmac_dma_ctrl dma_ctrl; 1800 1801 dma_ctrl.bits32 = readl(dma_ctrl_reg); 1802 dma_ctrl.bits.rd_enable = 1; 1803 dma_ctrl.bits.td_enable = 1; 1804 dma_ctrl.bits.loopback = 0; 1805 dma_ctrl.bits.drop_small_ack = 0; 1806 dma_ctrl.bits.rd_insert_bytes = NET_IP_ALIGN; 1807 dma_ctrl.bits.rd_prot = HPROT_DATA_CACHE | HPROT_PRIVILIGED; 1808 dma_ctrl.bits.rd_burst_size = HBURST_INCR8; 1809 dma_ctrl.bits.rd_bus = HSIZE_8; 1810 dma_ctrl.bits.td_prot = HPROT_DATA_CACHE; 1811 dma_ctrl.bits.td_burst_size = HBURST_INCR8; 1812 dma_ctrl.bits.td_bus = HSIZE_8; 1813 1814 writel(dma_ctrl.bits32, dma_ctrl_reg); 1815 } 1816 1817 static void gmac_stop_dma(struct gemini_ethernet_port *port) 1818 { 1819 void __iomem *dma_ctrl_reg = port->dma_base + GMAC_DMA_CTRL_REG; 1820 union gmac_dma_ctrl dma_ctrl; 1821 1822 dma_ctrl.bits32 = readl(dma_ctrl_reg); 1823 dma_ctrl.bits.rd_enable = 0; 1824 dma_ctrl.bits.td_enable = 0; 1825 writel(dma_ctrl.bits32, dma_ctrl_reg); 1826 } 1827 1828 static int gmac_open(struct net_device *netdev) 1829 { 1830 struct gemini_ethernet_port *port = netdev_priv(netdev); 1831 int err; 1832 1833 err = request_irq(netdev->irq, gmac_irq, 1834 IRQF_SHARED, netdev->name, netdev); 1835 if (err) { 1836 netdev_err(netdev, "no IRQ\n"); 1837 return err; 1838 } 1839 1840 netif_carrier_off(netdev); 1841 phy_start(netdev->phydev); 1842 1843 err = geth_resize_freeq(port); 1844 /* It's fine if it's just busy, the other port has set up 1845 * the freeq in that case. 1846 */ 1847 if (err && (err != -EBUSY)) { 1848 netdev_err(netdev, "could not resize freeq\n"); 1849 goto err_stop_phy; 1850 } 1851 1852 err = gmac_setup_rxq(netdev); 1853 if (err) { 1854 netdev_err(netdev, "could not setup RXQ\n"); 1855 goto err_stop_phy; 1856 } 1857 1858 err = gmac_setup_txqs(netdev); 1859 if (err) { 1860 netdev_err(netdev, "could not setup TXQs\n"); 1861 gmac_cleanup_rxq(netdev); 1862 goto err_stop_phy; 1863 } 1864 1865 napi_enable(&port->napi); 1866 1867 gmac_start_dma(port); 1868 gmac_enable_irq(netdev, 1); 1869 gmac_enable_tx_rx(netdev); 1870 netif_tx_start_all_queues(netdev); 1871 1872 hrtimer_setup(&port->rx_coalesce_timer, &gmac_coalesce_delay_expired, CLOCK_MONOTONIC, 1873 HRTIMER_MODE_REL); 1874 1875 netdev_dbg(netdev, "opened\n"); 1876 1877 return 0; 1878 1879 err_stop_phy: 1880 phy_stop(netdev->phydev); 1881 free_irq(netdev->irq, netdev); 1882 return err; 1883 } 1884 1885 static int gmac_stop(struct net_device *netdev) 1886 { 1887 struct gemini_ethernet_port *port = netdev_priv(netdev); 1888 1889 hrtimer_cancel(&port->rx_coalesce_timer); 1890 netif_tx_stop_all_queues(netdev); 1891 gmac_disable_tx_rx(netdev); 1892 gmac_stop_dma(port); 1893 napi_disable(&port->napi); 1894 port->rx_skb = NULL; 1895 port->rx_frag_nr = 0; 1896 1897 gmac_enable_irq(netdev, 0); 1898 gmac_cleanup_rxq(netdev); 1899 gmac_cleanup_txqs(netdev); 1900 1901 phy_stop(netdev->phydev); 1902 free_irq(netdev->irq, netdev); 1903 1904 gmac_update_hw_stats(netdev); 1905 return 0; 1906 } 1907 1908 static void gmac_set_rx_mode(struct net_device *netdev) 1909 { 1910 struct gemini_ethernet_port *port = netdev_priv(netdev); 1911 union gmac_rx_fltr filter = { .bits = { 1912 .broadcast = 1, 1913 .multicast = 1, 1914 .unicast = 1, 1915 } }; 1916 struct netdev_hw_addr *ha; 1917 unsigned int bit_nr; 1918 u32 mc_filter[2]; 1919 1920 mc_filter[1] = 0; 1921 mc_filter[0] = 0; 1922 1923 if (netdev->flags & IFF_PROMISC) { 1924 filter.bits.error = 1; 1925 filter.bits.promiscuous = 1; 1926 mc_filter[1] = ~0; 1927 mc_filter[0] = ~0; 1928 } else if (netdev->flags & IFF_ALLMULTI) { 1929 mc_filter[1] = ~0; 1930 mc_filter[0] = ~0; 1931 } else { 1932 netdev_for_each_mc_addr(ha, netdev) { 1933 bit_nr = ~crc32_le(~0, ha->addr, ETH_ALEN) & 0x3f; 1934 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 0x1f); 1935 } 1936 } 1937 1938 writel(mc_filter[0], port->gmac_base + GMAC_MCAST_FIL0); 1939 writel(mc_filter[1], port->gmac_base + GMAC_MCAST_FIL1); 1940 writel(filter.bits32, port->gmac_base + GMAC_RX_FLTR); 1941 } 1942 1943 static void gmac_write_mac_address(struct net_device *netdev) 1944 { 1945 struct gemini_ethernet_port *port = netdev_priv(netdev); 1946 __le32 addr[3]; 1947 1948 memset(addr, 0, sizeof(addr)); 1949 memcpy(addr, netdev->dev_addr, ETH_ALEN); 1950 1951 writel(le32_to_cpu(addr[0]), port->gmac_base + GMAC_STA_ADD0); 1952 writel(le32_to_cpu(addr[1]), port->gmac_base + GMAC_STA_ADD1); 1953 writel(le32_to_cpu(addr[2]), port->gmac_base + GMAC_STA_ADD2); 1954 } 1955 1956 static int gmac_set_mac_address(struct net_device *netdev, void *addr) 1957 { 1958 struct sockaddr *sa = addr; 1959 1960 eth_hw_addr_set(netdev, sa->sa_data); 1961 gmac_write_mac_address(netdev); 1962 1963 return 0; 1964 } 1965 1966 static void gmac_clear_hw_stats(struct net_device *netdev) 1967 { 1968 struct gemini_ethernet_port *port = netdev_priv(netdev); 1969 1970 readl(port->gmac_base + GMAC_IN_DISCARDS); 1971 readl(port->gmac_base + GMAC_IN_ERRORS); 1972 readl(port->gmac_base + GMAC_IN_MCAST); 1973 readl(port->gmac_base + GMAC_IN_BCAST); 1974 readl(port->gmac_base + GMAC_IN_MAC1); 1975 readl(port->gmac_base + GMAC_IN_MAC2); 1976 } 1977 1978 static void gmac_get_stats64(struct net_device *netdev, 1979 struct rtnl_link_stats64 *stats) 1980 { 1981 struct gemini_ethernet_port *port = netdev_priv(netdev); 1982 unsigned int start; 1983 1984 gmac_update_hw_stats(netdev); 1985 1986 /* Racing with RX NAPI */ 1987 do { 1988 start = u64_stats_fetch_begin(&port->rx_stats_syncp); 1989 1990 stats->rx_packets = port->stats.rx_packets; 1991 stats->rx_bytes = port->stats.rx_bytes; 1992 stats->rx_errors = port->stats.rx_errors; 1993 stats->rx_dropped = port->stats.rx_dropped; 1994 1995 stats->rx_length_errors = port->stats.rx_length_errors; 1996 stats->rx_over_errors = port->stats.rx_over_errors; 1997 stats->rx_crc_errors = port->stats.rx_crc_errors; 1998 stats->rx_frame_errors = port->stats.rx_frame_errors; 1999 2000 } while (u64_stats_fetch_retry(&port->rx_stats_syncp, start)); 2001 2002 /* Racing with MIB and TX completion interrupts */ 2003 do { 2004 start = u64_stats_fetch_begin(&port->ir_stats_syncp); 2005 2006 stats->tx_errors = port->stats.tx_errors; 2007 stats->tx_packets = port->stats.tx_packets; 2008 stats->tx_bytes = port->stats.tx_bytes; 2009 2010 stats->multicast = port->stats.multicast; 2011 stats->rx_missed_errors = port->stats.rx_missed_errors; 2012 stats->rx_fifo_errors = port->stats.rx_fifo_errors; 2013 2014 } while (u64_stats_fetch_retry(&port->ir_stats_syncp, start)); 2015 2016 /* Racing with hard_start_xmit */ 2017 do { 2018 start = u64_stats_fetch_begin(&port->tx_stats_syncp); 2019 2020 stats->tx_dropped = port->stats.tx_dropped; 2021 2022 } while (u64_stats_fetch_retry(&port->tx_stats_syncp, start)); 2023 2024 stats->rx_dropped += stats->rx_missed_errors; 2025 } 2026 2027 static int gmac_change_mtu(struct net_device *netdev, int new_mtu) 2028 { 2029 int max_len = gmac_pick_rx_max_len(new_mtu); 2030 2031 if (max_len < 0) 2032 return -EINVAL; 2033 2034 gmac_disable_tx_rx(netdev); 2035 2036 WRITE_ONCE(netdev->mtu, new_mtu); 2037 gmac_update_config0_reg(netdev, max_len << CONFIG0_MAXLEN_SHIFT, 2038 CONFIG0_MAXLEN_MASK); 2039 2040 netdev_update_features(netdev); 2041 2042 gmac_enable_tx_rx(netdev); 2043 2044 return 0; 2045 } 2046 2047 static int gmac_set_features(struct net_device *netdev, 2048 netdev_features_t features) 2049 { 2050 struct gemini_ethernet_port *port = netdev_priv(netdev); 2051 int enable = features & NETIF_F_RXCSUM; 2052 unsigned long flags; 2053 u32 reg; 2054 2055 spin_lock_irqsave(&port->config_lock, flags); 2056 2057 reg = readl(port->gmac_base + GMAC_CONFIG0); 2058 reg = enable ? reg | CONFIG0_RX_CHKSUM : reg & ~CONFIG0_RX_CHKSUM; 2059 writel(reg, port->gmac_base + GMAC_CONFIG0); 2060 2061 spin_unlock_irqrestore(&port->config_lock, flags); 2062 return 0; 2063 } 2064 2065 static int gmac_get_sset_count(struct net_device *netdev, int sset) 2066 { 2067 return sset == ETH_SS_STATS ? GMAC_STATS_NUM : 0; 2068 } 2069 2070 static void gmac_get_strings(struct net_device *netdev, u32 stringset, u8 *data) 2071 { 2072 if (stringset != ETH_SS_STATS) 2073 return; 2074 2075 memcpy(data, gmac_stats_strings, sizeof(gmac_stats_strings)); 2076 } 2077 2078 static void gmac_get_ethtool_stats(struct net_device *netdev, 2079 struct ethtool_stats *estats, u64 *values) 2080 { 2081 struct gemini_ethernet_port *port = netdev_priv(netdev); 2082 unsigned int start; 2083 u64 *p; 2084 int i; 2085 2086 gmac_update_hw_stats(netdev); 2087 2088 /* Racing with MIB interrupt */ 2089 do { 2090 p = values; 2091 start = u64_stats_fetch_begin(&port->ir_stats_syncp); 2092 2093 for (i = 0; i < RX_STATS_NUM; i++) 2094 *p++ = port->hw_stats[i]; 2095 2096 } while (u64_stats_fetch_retry(&port->ir_stats_syncp, start)); 2097 values = p; 2098 2099 /* Racing with RX NAPI */ 2100 do { 2101 p = values; 2102 start = u64_stats_fetch_begin(&port->rx_stats_syncp); 2103 2104 for (i = 0; i < RX_STATUS_NUM; i++) 2105 *p++ = port->rx_stats[i]; 2106 for (i = 0; i < RX_CHKSUM_NUM; i++) 2107 *p++ = port->rx_csum_stats[i]; 2108 *p++ = port->rx_napi_exits; 2109 2110 } while (u64_stats_fetch_retry(&port->rx_stats_syncp, start)); 2111 values = p; 2112 2113 /* Racing with TX start_xmit */ 2114 do { 2115 p = values; 2116 start = u64_stats_fetch_begin(&port->tx_stats_syncp); 2117 2118 for (i = 0; i < TX_MAX_FRAGS; i++) { 2119 *values++ = port->tx_frag_stats[i]; 2120 port->tx_frag_stats[i] = 0; 2121 } 2122 *values++ = port->tx_frags_linearized; 2123 *values++ = port->tx_hw_csummed; 2124 2125 } while (u64_stats_fetch_retry(&port->tx_stats_syncp, start)); 2126 } 2127 2128 static int gmac_get_ksettings(struct net_device *netdev, 2129 struct ethtool_link_ksettings *cmd) 2130 { 2131 if (!netdev->phydev) 2132 return -ENXIO; 2133 phy_ethtool_ksettings_get(netdev->phydev, cmd); 2134 2135 return 0; 2136 } 2137 2138 static int gmac_set_ksettings(struct net_device *netdev, 2139 const struct ethtool_link_ksettings *cmd) 2140 { 2141 if (!netdev->phydev) 2142 return -ENXIO; 2143 return phy_ethtool_ksettings_set(netdev->phydev, cmd); 2144 } 2145 2146 static int gmac_nway_reset(struct net_device *netdev) 2147 { 2148 if (!netdev->phydev) 2149 return -ENXIO; 2150 return phy_start_aneg(netdev->phydev); 2151 } 2152 2153 static void gmac_get_pauseparam(struct net_device *netdev, 2154 struct ethtool_pauseparam *pparam) 2155 { 2156 struct gemini_ethernet_port *port = netdev_priv(netdev); 2157 union gmac_config0 config0; 2158 2159 config0.bits32 = readl(port->gmac_base + GMAC_CONFIG0); 2160 2161 pparam->rx_pause = config0.bits.rx_fc_en; 2162 pparam->tx_pause = config0.bits.tx_fc_en; 2163 pparam->autoneg = true; 2164 } 2165 2166 static int gmac_set_pauseparam(struct net_device *netdev, 2167 struct ethtool_pauseparam *pparam) 2168 { 2169 struct phy_device *phydev = netdev->phydev; 2170 2171 if (!pparam->autoneg) 2172 return -EOPNOTSUPP; 2173 2174 phy_set_asym_pause(phydev, pparam->rx_pause, pparam->tx_pause); 2175 2176 return 0; 2177 } 2178 2179 static void gmac_get_ringparam(struct net_device *netdev, 2180 struct ethtool_ringparam *rp, 2181 struct kernel_ethtool_ringparam *kernel_rp, 2182 struct netlink_ext_ack *extack) 2183 { 2184 struct gemini_ethernet_port *port = netdev_priv(netdev); 2185 2186 readl(port->gmac_base + GMAC_CONFIG0); 2187 2188 rp->rx_max_pending = 1 << 15; 2189 rp->rx_mini_max_pending = 0; 2190 rp->rx_jumbo_max_pending = 0; 2191 rp->tx_max_pending = 1 << 15; 2192 2193 rp->rx_pending = 1 << port->rxq_order; 2194 rp->rx_mini_pending = 0; 2195 rp->rx_jumbo_pending = 0; 2196 rp->tx_pending = 1 << port->txq_order; 2197 } 2198 2199 static int gmac_set_ringparam(struct net_device *netdev, 2200 struct ethtool_ringparam *rp, 2201 struct kernel_ethtool_ringparam *kernel_rp, 2202 struct netlink_ext_ack *extack) 2203 { 2204 struct gemini_ethernet_port *port = netdev_priv(netdev); 2205 int err = 0; 2206 2207 if (netif_running(netdev)) 2208 return -EBUSY; 2209 2210 if (rp->rx_pending) { 2211 port->rxq_order = min(15, ilog2(rp->rx_pending - 1) + 1); 2212 err = geth_resize_freeq(port); 2213 } 2214 if (rp->tx_pending) { 2215 port->txq_order = min(15, ilog2(rp->tx_pending - 1) + 1); 2216 port->irq_every_tx_packets = 1 << (port->txq_order - 2); 2217 } 2218 2219 return err; 2220 } 2221 2222 static int gmac_get_coalesce(struct net_device *netdev, 2223 struct ethtool_coalesce *ecmd, 2224 struct kernel_ethtool_coalesce *kernel_coal, 2225 struct netlink_ext_ack *extack) 2226 { 2227 struct gemini_ethernet_port *port = netdev_priv(netdev); 2228 2229 ecmd->rx_max_coalesced_frames = 1; 2230 ecmd->tx_max_coalesced_frames = port->irq_every_tx_packets; 2231 ecmd->rx_coalesce_usecs = port->rx_coalesce_nsecs / 1000; 2232 2233 return 0; 2234 } 2235 2236 static int gmac_set_coalesce(struct net_device *netdev, 2237 struct ethtool_coalesce *ecmd, 2238 struct kernel_ethtool_coalesce *kernel_coal, 2239 struct netlink_ext_ack *extack) 2240 { 2241 struct gemini_ethernet_port *port = netdev_priv(netdev); 2242 2243 if (ecmd->tx_max_coalesced_frames < 1) 2244 return -EINVAL; 2245 if (ecmd->tx_max_coalesced_frames >= 1 << port->txq_order) 2246 return -EINVAL; 2247 2248 port->irq_every_tx_packets = ecmd->tx_max_coalesced_frames; 2249 port->rx_coalesce_nsecs = ecmd->rx_coalesce_usecs * 1000; 2250 2251 return 0; 2252 } 2253 2254 static u32 gmac_get_msglevel(struct net_device *netdev) 2255 { 2256 struct gemini_ethernet_port *port = netdev_priv(netdev); 2257 2258 return port->msg_enable; 2259 } 2260 2261 static void gmac_set_msglevel(struct net_device *netdev, u32 level) 2262 { 2263 struct gemini_ethernet_port *port = netdev_priv(netdev); 2264 2265 port->msg_enable = level; 2266 } 2267 2268 static void gmac_get_drvinfo(struct net_device *netdev, 2269 struct ethtool_drvinfo *info) 2270 { 2271 strcpy(info->driver, DRV_NAME); 2272 strcpy(info->bus_info, netdev->dev_id ? "1" : "0"); 2273 } 2274 2275 static const struct net_device_ops gmac_351x_ops = { 2276 .ndo_init = gmac_init, 2277 .ndo_open = gmac_open, 2278 .ndo_stop = gmac_stop, 2279 .ndo_start_xmit = gmac_start_xmit, 2280 .ndo_tx_timeout = gmac_tx_timeout, 2281 .ndo_set_rx_mode = gmac_set_rx_mode, 2282 .ndo_set_mac_address = gmac_set_mac_address, 2283 .ndo_get_stats64 = gmac_get_stats64, 2284 .ndo_change_mtu = gmac_change_mtu, 2285 .ndo_set_features = gmac_set_features, 2286 }; 2287 2288 static const struct ethtool_ops gmac_351x_ethtool_ops = { 2289 .supported_coalesce_params = ETHTOOL_COALESCE_RX_USECS | 2290 ETHTOOL_COALESCE_MAX_FRAMES, 2291 .get_sset_count = gmac_get_sset_count, 2292 .get_strings = gmac_get_strings, 2293 .get_ethtool_stats = gmac_get_ethtool_stats, 2294 .get_link = ethtool_op_get_link, 2295 .get_link_ksettings = gmac_get_ksettings, 2296 .set_link_ksettings = gmac_set_ksettings, 2297 .nway_reset = gmac_nway_reset, 2298 .get_pauseparam = gmac_get_pauseparam, 2299 .set_pauseparam = gmac_set_pauseparam, 2300 .get_ringparam = gmac_get_ringparam, 2301 .set_ringparam = gmac_set_ringparam, 2302 .get_coalesce = gmac_get_coalesce, 2303 .set_coalesce = gmac_set_coalesce, 2304 .get_msglevel = gmac_get_msglevel, 2305 .set_msglevel = gmac_set_msglevel, 2306 .get_drvinfo = gmac_get_drvinfo, 2307 }; 2308 2309 static irqreturn_t gemini_port_irq_thread(int irq, void *data) 2310 { 2311 unsigned long irqmask = SWFQ_EMPTY_INT_BIT; 2312 struct gemini_ethernet_port *port = data; 2313 struct gemini_ethernet *geth; 2314 unsigned long flags; 2315 2316 geth = port->geth; 2317 /* The queue is half empty so refill it */ 2318 geth_fill_freeq(geth, true); 2319 2320 spin_lock_irqsave(&geth->irq_lock, flags); 2321 /* ACK queue interrupt */ 2322 writel(irqmask, geth->base + GLOBAL_INTERRUPT_STATUS_4_REG); 2323 /* Enable queue interrupt again */ 2324 irqmask |= readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG); 2325 writel(irqmask, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG); 2326 spin_unlock_irqrestore(&geth->irq_lock, flags); 2327 2328 return IRQ_HANDLED; 2329 } 2330 2331 static irqreturn_t gemini_port_irq(int irq, void *data) 2332 { 2333 struct gemini_ethernet_port *port = data; 2334 struct gemini_ethernet *geth; 2335 irqreturn_t ret = IRQ_NONE; 2336 u32 val, en; 2337 2338 geth = port->geth; 2339 spin_lock(&geth->irq_lock); 2340 2341 val = readl(geth->base + GLOBAL_INTERRUPT_STATUS_4_REG); 2342 en = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG); 2343 2344 if (val & en & SWFQ_EMPTY_INT_BIT) { 2345 /* Disable the queue empty interrupt while we work on 2346 * processing the queue. Also disable overrun interrupts 2347 * as there is not much we can do about it here. 2348 */ 2349 en &= ~(SWFQ_EMPTY_INT_BIT | GMAC0_RX_OVERRUN_INT_BIT 2350 | GMAC1_RX_OVERRUN_INT_BIT); 2351 writel(en, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG); 2352 ret = IRQ_WAKE_THREAD; 2353 } 2354 2355 spin_unlock(&geth->irq_lock); 2356 2357 return ret; 2358 } 2359 2360 static void gemini_port_remove(struct gemini_ethernet_port *port) 2361 { 2362 if (port->netdev) { 2363 phy_disconnect(port->netdev->phydev); 2364 unregister_netdev(port->netdev); 2365 } 2366 clk_disable_unprepare(port->pclk); 2367 geth_cleanup_freeq(port->geth); 2368 } 2369 2370 static void gemini_ethernet_init(struct gemini_ethernet *geth) 2371 { 2372 /* Only do this once both ports are online */ 2373 if (geth->initialized) 2374 return; 2375 if (geth->port0 && geth->port1) 2376 geth->initialized = true; 2377 else 2378 return; 2379 2380 writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG); 2381 writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG); 2382 writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_2_REG); 2383 writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_3_REG); 2384 writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG); 2385 2386 /* Interrupt config: 2387 * 2388 * GMAC0 intr bits ------> int0 ----> eth0 2389 * GMAC1 intr bits ------> int1 ----> eth1 2390 * TOE intr -------------> int1 ----> eth1 2391 * Classification Intr --> int0 ----> eth0 2392 * Default Q0 -----------> int0 ----> eth0 2393 * Default Q1 -----------> int1 ----> eth1 2394 * FreeQ intr -----------> int1 ----> eth1 2395 */ 2396 writel(0xCCFC0FC0, geth->base + GLOBAL_INTERRUPT_SELECT_0_REG); 2397 writel(0x00F00002, geth->base + GLOBAL_INTERRUPT_SELECT_1_REG); 2398 writel(0xFFFFFFFF, geth->base + GLOBAL_INTERRUPT_SELECT_2_REG); 2399 writel(0xFFFFFFFF, geth->base + GLOBAL_INTERRUPT_SELECT_3_REG); 2400 writel(0xFF000003, geth->base + GLOBAL_INTERRUPT_SELECT_4_REG); 2401 2402 /* edge-triggered interrupts packed to level-triggered one... */ 2403 writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_0_REG); 2404 writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_1_REG); 2405 writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_2_REG); 2406 writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_3_REG); 2407 writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_4_REG); 2408 2409 /* Set up queue */ 2410 writel(0, geth->base + GLOBAL_SW_FREEQ_BASE_SIZE_REG); 2411 writel(0, geth->base + GLOBAL_HW_FREEQ_BASE_SIZE_REG); 2412 writel(0, geth->base + GLOBAL_SWFQ_RWPTR_REG); 2413 writel(0, geth->base + GLOBAL_HWFQ_RWPTR_REG); 2414 2415 geth->freeq_frag_order = DEFAULT_RX_BUF_ORDER; 2416 /* This makes the queue resize on probe() so that we 2417 * set up and enable the queue IRQ. FIXME: fragile. 2418 */ 2419 geth->freeq_order = 1; 2420 } 2421 2422 static void gemini_port_save_mac_addr(struct gemini_ethernet_port *port) 2423 { 2424 port->mac_addr[0] = 2425 cpu_to_le32(readl(port->gmac_base + GMAC_STA_ADD0)); 2426 port->mac_addr[1] = 2427 cpu_to_le32(readl(port->gmac_base + GMAC_STA_ADD1)); 2428 port->mac_addr[2] = 2429 cpu_to_le32(readl(port->gmac_base + GMAC_STA_ADD2)); 2430 } 2431 2432 static int gemini_ethernet_port_probe(struct platform_device *pdev) 2433 { 2434 char *port_names[2] = { "ethernet0", "ethernet1" }; 2435 struct device_node *np = pdev->dev.of_node; 2436 struct gemini_ethernet_port *port; 2437 struct device *dev = &pdev->dev; 2438 struct gemini_ethernet *geth; 2439 struct net_device *netdev; 2440 struct device *parent; 2441 u8 mac[ETH_ALEN]; 2442 unsigned int id; 2443 int irq; 2444 int ret; 2445 2446 parent = dev->parent; 2447 geth = dev_get_drvdata(parent); 2448 2449 if (!strcmp(dev_name(dev), "60008000.ethernet-port")) 2450 id = 0; 2451 else if (!strcmp(dev_name(dev), "6000c000.ethernet-port")) 2452 id = 1; 2453 else 2454 return -ENODEV; 2455 2456 dev_info(dev, "probe %s ID %d\n", dev_name(dev), id); 2457 2458 netdev = devm_alloc_etherdev_mqs(dev, sizeof(*port), TX_QUEUE_NUM, TX_QUEUE_NUM); 2459 if (!netdev) { 2460 dev_err(dev, "Can't allocate ethernet device #%d\n", id); 2461 return -ENOMEM; 2462 } 2463 2464 port = netdev_priv(netdev); 2465 SET_NETDEV_DEV(netdev, dev); 2466 port->netdev = netdev; 2467 port->id = id; 2468 port->geth = geth; 2469 port->dev = dev; 2470 port->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 2471 2472 /* DMA memory */ 2473 port->dma_base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); 2474 if (IS_ERR(port->dma_base)) { 2475 dev_err(dev, "get DMA address failed\n"); 2476 return PTR_ERR(port->dma_base); 2477 } 2478 2479 /* GMAC config memory */ 2480 port->gmac_base = devm_platform_get_and_ioremap_resource(pdev, 1, NULL); 2481 if (IS_ERR(port->gmac_base)) { 2482 dev_err(dev, "get GMAC address failed\n"); 2483 return PTR_ERR(port->gmac_base); 2484 } 2485 2486 /* Interrupt */ 2487 irq = platform_get_irq(pdev, 0); 2488 if (irq < 0) 2489 return irq; 2490 port->irq = irq; 2491 2492 /* Clock the port */ 2493 port->pclk = devm_clk_get(dev, "PCLK"); 2494 if (IS_ERR(port->pclk)) { 2495 dev_err(dev, "no PCLK\n"); 2496 return PTR_ERR(port->pclk); 2497 } 2498 ret = clk_prepare_enable(port->pclk); 2499 if (ret) 2500 return ret; 2501 2502 /* Maybe there is a nice ethernet address we should use */ 2503 gemini_port_save_mac_addr(port); 2504 2505 /* Reset the port */ 2506 port->reset = devm_reset_control_get_exclusive(dev, NULL); 2507 if (IS_ERR(port->reset)) { 2508 dev_err(dev, "no reset\n"); 2509 ret = PTR_ERR(port->reset); 2510 goto unprepare; 2511 } 2512 reset_control_reset(port->reset); 2513 usleep_range(100, 500); 2514 2515 /* Assign pointer in the main state container */ 2516 if (!id) 2517 geth->port0 = port; 2518 else 2519 geth->port1 = port; 2520 2521 /* This will just be done once both ports are up and reset */ 2522 gemini_ethernet_init(geth); 2523 2524 platform_set_drvdata(pdev, port); 2525 2526 /* Set up and register the netdev */ 2527 netdev->dev_id = port->id; 2528 netdev->irq = irq; 2529 netdev->netdev_ops = &gmac_351x_ops; 2530 netdev->ethtool_ops = &gmac_351x_ethtool_ops; 2531 2532 spin_lock_init(&port->config_lock); 2533 gmac_clear_hw_stats(netdev); 2534 2535 netdev->hw_features = GMAC_OFFLOAD_FEATURES; 2536 netdev->features |= GMAC_OFFLOAD_FEATURES | NETIF_F_GRO; 2537 /* We can receive jumbo frames up to 10236 bytes but only 2538 * transmit 2047 bytes so, let's accept payloads of 2047 2539 * bytes minus VLAN and ethernet header 2540 */ 2541 netdev->min_mtu = ETH_MIN_MTU; 2542 netdev->max_mtu = MTU_SIZE_BIT_MASK - VLAN_ETH_HLEN; 2543 2544 port->freeq_refill = 0; 2545 netif_napi_add(netdev, &port->napi, gmac_napi_poll); 2546 2547 ret = of_get_mac_address(np, mac); 2548 if (!ret) { 2549 dev_info(dev, "Setting macaddr from DT %pM\n", mac); 2550 memcpy(port->mac_addr, mac, ETH_ALEN); 2551 } 2552 2553 if (is_valid_ether_addr((void *)port->mac_addr)) { 2554 eth_hw_addr_set(netdev, (u8 *)port->mac_addr); 2555 } else { 2556 dev_dbg(dev, "ethernet address 0x%08x%08x%08x invalid\n", 2557 port->mac_addr[0], port->mac_addr[1], 2558 port->mac_addr[2]); 2559 dev_info(dev, "using a random ethernet address\n"); 2560 eth_hw_addr_random(netdev); 2561 } 2562 gmac_write_mac_address(netdev); 2563 2564 ret = devm_request_threaded_irq(port->dev, 2565 port->irq, 2566 gemini_port_irq, 2567 gemini_port_irq_thread, 2568 IRQF_SHARED, 2569 port_names[port->id], 2570 port); 2571 if (ret) 2572 goto unprepare; 2573 2574 ret = gmac_setup_phy(netdev); 2575 if (ret) { 2576 netdev_err(netdev, 2577 "PHY init failed\n"); 2578 goto unprepare; 2579 } 2580 2581 ret = register_netdev(netdev); 2582 if (ret) 2583 goto unprepare; 2584 2585 return 0; 2586 2587 unprepare: 2588 clk_disable_unprepare(port->pclk); 2589 return ret; 2590 } 2591 2592 static void gemini_ethernet_port_remove(struct platform_device *pdev) 2593 { 2594 struct gemini_ethernet_port *port = platform_get_drvdata(pdev); 2595 2596 gemini_port_remove(port); 2597 } 2598 2599 static const struct of_device_id gemini_ethernet_port_of_match[] = { 2600 { 2601 .compatible = "cortina,gemini-ethernet-port", 2602 }, 2603 {}, 2604 }; 2605 MODULE_DEVICE_TABLE(of, gemini_ethernet_port_of_match); 2606 2607 static struct platform_driver gemini_ethernet_port_driver = { 2608 .driver = { 2609 .name = "gemini-ethernet-port", 2610 .of_match_table = gemini_ethernet_port_of_match, 2611 }, 2612 .probe = gemini_ethernet_port_probe, 2613 .remove = gemini_ethernet_port_remove, 2614 }; 2615 2616 static int gemini_ethernet_probe(struct platform_device *pdev) 2617 { 2618 struct device *dev = &pdev->dev; 2619 struct gemini_ethernet *geth; 2620 unsigned int retry = 5; 2621 u32 val; 2622 2623 /* Global registers */ 2624 geth = devm_kzalloc(dev, sizeof(*geth), GFP_KERNEL); 2625 if (!geth) 2626 return -ENOMEM; 2627 geth->base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); 2628 if (IS_ERR(geth->base)) 2629 return PTR_ERR(geth->base); 2630 geth->dev = dev; 2631 2632 /* Wait for ports to stabilize */ 2633 do { 2634 udelay(2); 2635 val = readl(geth->base + GLOBAL_TOE_VERSION_REG); 2636 barrier(); 2637 } while (!val && --retry); 2638 if (!retry) { 2639 dev_err(dev, "failed to reset ethernet\n"); 2640 return -EIO; 2641 } 2642 dev_info(dev, "Ethernet device ID: 0x%03x, revision 0x%01x\n", 2643 (val >> 4) & 0xFFFU, val & 0xFU); 2644 2645 spin_lock_init(&geth->irq_lock); 2646 spin_lock_init(&geth->freeq_lock); 2647 2648 /* The children will use this */ 2649 platform_set_drvdata(pdev, geth); 2650 2651 /* Spawn child devices for the two ports */ 2652 return devm_of_platform_populate(dev); 2653 } 2654 2655 static void gemini_ethernet_remove(struct platform_device *pdev) 2656 { 2657 struct gemini_ethernet *geth = platform_get_drvdata(pdev); 2658 2659 geth_cleanup_freeq(geth); 2660 geth->initialized = false; 2661 } 2662 2663 static const struct of_device_id gemini_ethernet_of_match[] = { 2664 { 2665 .compatible = "cortina,gemini-ethernet", 2666 }, 2667 {}, 2668 }; 2669 MODULE_DEVICE_TABLE(of, gemini_ethernet_of_match); 2670 2671 static struct platform_driver gemini_ethernet_driver = { 2672 .driver = { 2673 .name = DRV_NAME, 2674 .of_match_table = gemini_ethernet_of_match, 2675 }, 2676 .probe = gemini_ethernet_probe, 2677 .remove = gemini_ethernet_remove, 2678 }; 2679 2680 static int __init gemini_ethernet_module_init(void) 2681 { 2682 int ret; 2683 2684 ret = platform_driver_register(&gemini_ethernet_port_driver); 2685 if (ret) 2686 return ret; 2687 2688 ret = platform_driver_register(&gemini_ethernet_driver); 2689 if (ret) { 2690 platform_driver_unregister(&gemini_ethernet_port_driver); 2691 return ret; 2692 } 2693 2694 return 0; 2695 } 2696 module_init(gemini_ethernet_module_init); 2697 2698 static void __exit gemini_ethernet_module_exit(void) 2699 { 2700 platform_driver_unregister(&gemini_ethernet_driver); 2701 platform_driver_unregister(&gemini_ethernet_port_driver); 2702 } 2703 module_exit(gemini_ethernet_module_exit); 2704 2705 MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>"); 2706 MODULE_DESCRIPTION("StorLink SL351x (Gemini) ethernet driver"); 2707 MODULE_LICENSE("GPL"); 2708 MODULE_ALIAS("platform:" DRV_NAME); 2709