1 /* 2 * Copyright 2008-2010 Cisco Systems, Inc. All rights reserved. 3 * Copyright 2007 Nuova Systems, Inc. All rights reserved. 4 * 5 * This program is free software; you may redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; version 2 of the License. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 10 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 11 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 12 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 13 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 14 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 15 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 16 * SOFTWARE. 17 * 18 */ 19 20 #ifndef _ENIC_H_ 21 #define _ENIC_H_ 22 23 #include "vnic_enet.h" 24 #include "vnic_dev.h" 25 #include "vnic_wq.h" 26 #include "vnic_rq.h" 27 #include "vnic_cq.h" 28 #include "vnic_intr.h" 29 #include "vnic_stats.h" 30 #include "vnic_nic.h" 31 #include "vnic_rss.h" 32 #include <linux/irq.h> 33 34 #define DRV_NAME "enic" 35 #define DRV_DESCRIPTION "Cisco VIC Ethernet NIC Driver" 36 #define DRV_VERSION "2.3.0.53" 37 #define DRV_COPYRIGHT "Copyright 2008-2013 Cisco Systems, Inc" 38 39 #define ENIC_BARS_MAX 6 40 41 #define ENIC_WQ_MAX 8 42 #define ENIC_RQ_MAX 8 43 #define ENIC_CQ_MAX (ENIC_WQ_MAX + ENIC_RQ_MAX) 44 #define ENIC_INTR_MAX (ENIC_CQ_MAX + 2) 45 46 #define ENIC_WQ_NAPI_BUDGET 256 47 48 #define ENIC_AIC_LARGE_PKT_DIFF 3 49 50 struct enic_msix_entry { 51 int requested; 52 char devname[IFNAMSIZ + 8]; 53 irqreturn_t (*isr)(int, void *); 54 void *devid; 55 cpumask_var_t affinity_mask; 56 }; 57 58 /* Store only the lower range. Higher range is given by fw. */ 59 struct enic_intr_mod_range { 60 u32 small_pkt_range_start; 61 u32 large_pkt_range_start; 62 }; 63 64 struct enic_intr_mod_table { 65 u32 rx_rate; 66 u32 range_percent; 67 }; 68 69 #define ENIC_MAX_LINK_SPEEDS 3 70 #define ENIC_LINK_SPEED_10G 10000 71 #define ENIC_LINK_SPEED_4G 4000 72 #define ENIC_LINK_40G_INDEX 2 73 #define ENIC_LINK_10G_INDEX 1 74 #define ENIC_LINK_4G_INDEX 0 75 #define ENIC_RX_COALESCE_RANGE_END 125 76 #define ENIC_AIC_TS_BREAK 100 77 78 struct enic_rx_coal { 79 u32 small_pkt_range_start; 80 u32 large_pkt_range_start; 81 u32 range_end; 82 u32 use_adaptive_rx_coalesce; 83 }; 84 85 /* priv_flags */ 86 #define ENIC_SRIOV_ENABLED (1 << 0) 87 88 /* enic port profile set flags */ 89 #define ENIC_PORT_REQUEST_APPLIED (1 << 0) 90 #define ENIC_SET_REQUEST (1 << 1) 91 #define ENIC_SET_NAME (1 << 2) 92 #define ENIC_SET_INSTANCE (1 << 3) 93 #define ENIC_SET_HOST (1 << 4) 94 95 struct enic_port_profile { 96 u32 set; 97 u8 request; 98 char name[PORT_PROFILE_MAX]; 99 u8 instance_uuid[PORT_UUID_MAX]; 100 u8 host_uuid[PORT_UUID_MAX]; 101 u8 vf_mac[ETH_ALEN]; 102 u8 mac_addr[ETH_ALEN]; 103 }; 104 105 /* enic_rfs_fltr_node - rfs filter node in hash table 106 * @@keys: IPv4 5 tuple 107 * @flow_id: flow_id of clsf filter provided by kernel 108 * @fltr_id: filter id of clsf filter returned by adaptor 109 * @rq_id: desired rq index 110 * @node: hlist_node 111 */ 112 struct enic_rfs_fltr_node { 113 struct flow_keys keys; 114 u32 flow_id; 115 u16 fltr_id; 116 u16 rq_id; 117 struct hlist_node node; 118 }; 119 120 /* enic_rfs_flw_tbl - rfs flow table 121 * @max: Maximum number of filters vNIC supports 122 * @free: Number of free filters available 123 * @toclean: hash table index to clean next 124 * @ht_head: hash table list head 125 * @lock: spin lock 126 * @rfs_may_expire: timer function for enic_rps_may_expire_flow 127 */ 128 struct enic_rfs_flw_tbl { 129 u16 max; 130 int free; 131 132 #define ENIC_RFS_FLW_BITSHIFT (10) 133 #define ENIC_RFS_FLW_MASK ((1 << ENIC_RFS_FLW_BITSHIFT) - 1) 134 u16 toclean:ENIC_RFS_FLW_BITSHIFT; 135 struct hlist_head ht_head[1 << ENIC_RFS_FLW_BITSHIFT]; 136 spinlock_t lock; 137 struct timer_list rfs_may_expire; 138 }; 139 140 struct vxlan_offload { 141 u16 vxlan_udp_port_number; 142 u8 patch_level; 143 u8 flags; 144 }; 145 146 /* Per-instance private data structure */ 147 struct enic { 148 struct net_device *netdev; 149 struct pci_dev *pdev; 150 struct vnic_enet_config config; 151 struct vnic_dev_bar bar[ENIC_BARS_MAX]; 152 struct vnic_dev *vdev; 153 struct timer_list notify_timer; 154 struct work_struct reset; 155 struct work_struct tx_hang_reset; 156 struct work_struct change_mtu_work; 157 struct msix_entry msix_entry[ENIC_INTR_MAX]; 158 struct enic_msix_entry msix[ENIC_INTR_MAX]; 159 u32 msg_enable; 160 spinlock_t devcmd_lock; 161 u8 mac_addr[ETH_ALEN]; 162 unsigned int flags; 163 unsigned int priv_flags; 164 unsigned int mc_count; 165 unsigned int uc_count; 166 u32 port_mtu; 167 struct enic_rx_coal rx_coalesce_setting; 168 u32 rx_coalesce_usecs; 169 u32 tx_coalesce_usecs; 170 #ifdef CONFIG_PCI_IOV 171 u16 num_vfs; 172 #endif 173 spinlock_t enic_api_lock; 174 struct enic_port_profile *pp; 175 176 /* work queue cache line section */ 177 ____cacheline_aligned struct vnic_wq wq[ENIC_WQ_MAX]; 178 spinlock_t wq_lock[ENIC_WQ_MAX]; 179 unsigned int wq_count; 180 u16 loop_enable; 181 u16 loop_tag; 182 183 /* receive queue cache line section */ 184 ____cacheline_aligned struct vnic_rq rq[ENIC_RQ_MAX]; 185 unsigned int rq_count; 186 struct vxlan_offload vxlan; 187 u64 rq_truncated_pkts; 188 u64 rq_bad_fcs; 189 struct napi_struct napi[ENIC_RQ_MAX + ENIC_WQ_MAX]; 190 191 /* interrupt resource cache line section */ 192 ____cacheline_aligned struct vnic_intr intr[ENIC_INTR_MAX]; 193 unsigned int intr_count; 194 u32 __iomem *legacy_pba; /* memory-mapped */ 195 196 /* completion queue cache line section */ 197 ____cacheline_aligned struct vnic_cq cq[ENIC_CQ_MAX]; 198 unsigned int cq_count; 199 struct enic_rfs_flw_tbl rfs_h; 200 u32 rx_copybreak; 201 u8 rss_key[ENIC_RSS_LEN]; 202 struct vnic_gen_stats gen_stats; 203 }; 204 205 static inline struct net_device *vnic_get_netdev(struct vnic_dev *vdev) 206 { 207 struct enic *enic = vdev->priv; 208 209 return enic->netdev; 210 } 211 212 /* wrappers function for kernel log 213 */ 214 #define vdev_err(vdev, fmt, ...) \ 215 dev_err(&(vdev)->pdev->dev, fmt, ##__VA_ARGS__) 216 #define vdev_warn(vdev, fmt, ...) \ 217 dev_warn(&(vdev)->pdev->dev, fmt, ##__VA_ARGS__) 218 #define vdev_info(vdev, fmt, ...) \ 219 dev_info(&(vdev)->pdev->dev, fmt, ##__VA_ARGS__) 220 221 #define vdev_neterr(vdev, fmt, ...) \ 222 netdev_err(vnic_get_netdev(vdev), fmt, ##__VA_ARGS__) 223 #define vdev_netwarn(vdev, fmt, ...) \ 224 netdev_warn(vnic_get_netdev(vdev), fmt, ##__VA_ARGS__) 225 #define vdev_netinfo(vdev, fmt, ...) \ 226 netdev_info(vnic_get_netdev(vdev), fmt, ##__VA_ARGS__) 227 228 static inline struct device *enic_get_dev(struct enic *enic) 229 { 230 return &(enic->pdev->dev); 231 } 232 233 static inline unsigned int enic_cq_rq(struct enic *enic, unsigned int rq) 234 { 235 return rq; 236 } 237 238 static inline unsigned int enic_cq_wq(struct enic *enic, unsigned int wq) 239 { 240 return enic->rq_count + wq; 241 } 242 243 static inline unsigned int enic_legacy_io_intr(void) 244 { 245 return 0; 246 } 247 248 static inline unsigned int enic_legacy_err_intr(void) 249 { 250 return 1; 251 } 252 253 static inline unsigned int enic_legacy_notify_intr(void) 254 { 255 return 2; 256 } 257 258 static inline unsigned int enic_msix_rq_intr(struct enic *enic, 259 unsigned int rq) 260 { 261 return enic->cq[enic_cq_rq(enic, rq)].interrupt_offset; 262 } 263 264 static inline unsigned int enic_msix_wq_intr(struct enic *enic, 265 unsigned int wq) 266 { 267 return enic->cq[enic_cq_wq(enic, wq)].interrupt_offset; 268 } 269 270 static inline unsigned int enic_msix_err_intr(struct enic *enic) 271 { 272 return enic->rq_count + enic->wq_count; 273 } 274 275 static inline unsigned int enic_msix_notify_intr(struct enic *enic) 276 { 277 return enic->rq_count + enic->wq_count + 1; 278 } 279 280 static inline bool enic_is_err_intr(struct enic *enic, int intr) 281 { 282 switch (vnic_dev_get_intr_mode(enic->vdev)) { 283 case VNIC_DEV_INTR_MODE_INTX: 284 return intr == enic_legacy_err_intr(); 285 case VNIC_DEV_INTR_MODE_MSIX: 286 return intr == enic_msix_err_intr(enic); 287 case VNIC_DEV_INTR_MODE_MSI: 288 default: 289 return false; 290 } 291 } 292 293 static inline bool enic_is_notify_intr(struct enic *enic, int intr) 294 { 295 switch (vnic_dev_get_intr_mode(enic->vdev)) { 296 case VNIC_DEV_INTR_MODE_INTX: 297 return intr == enic_legacy_notify_intr(); 298 case VNIC_DEV_INTR_MODE_MSIX: 299 return intr == enic_msix_notify_intr(enic); 300 case VNIC_DEV_INTR_MODE_MSI: 301 default: 302 return false; 303 } 304 } 305 306 static inline int enic_dma_map_check(struct enic *enic, dma_addr_t dma_addr) 307 { 308 if (unlikely(pci_dma_mapping_error(enic->pdev, dma_addr))) { 309 net_warn_ratelimited("%s: PCI dma mapping failed!\n", 310 enic->netdev->name); 311 enic->gen_stats.dma_map_error++; 312 313 return -ENOMEM; 314 } 315 316 return 0; 317 } 318 319 void enic_reset_addr_lists(struct enic *enic); 320 int enic_sriov_enabled(struct enic *enic); 321 int enic_is_valid_vf(struct enic *enic, int vf); 322 int enic_is_dynamic(struct enic *enic); 323 void enic_set_ethtool_ops(struct net_device *netdev); 324 int __enic_set_rsskey(struct enic *enic); 325 326 #endif /* _ENIC_H_ */ 327