1 /* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2009-2016 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #ifndef _T4FW_INTERFACE_H_ 36 #define _T4FW_INTERFACE_H_ 37 38 enum fw_retval { 39 FW_SUCCESS = 0, /* completed successfully */ 40 FW_EPERM = 1, /* operation not permitted */ 41 FW_ENOENT = 2, /* no such file or directory */ 42 FW_EIO = 5, /* input/output error; hw bad */ 43 FW_ENOEXEC = 8, /* exec format error; inv microcode */ 44 FW_EAGAIN = 11, /* try again */ 45 FW_ENOMEM = 12, /* out of memory */ 46 FW_EFAULT = 14, /* bad address; fw bad */ 47 FW_EBUSY = 16, /* resource busy */ 48 FW_EEXIST = 17, /* file exists */ 49 FW_ENODEV = 19, /* no such device */ 50 FW_EINVAL = 22, /* invalid argument */ 51 FW_ENOSPC = 28, /* no space left on device */ 52 FW_ENOSYS = 38, /* functionality not implemented */ 53 FW_ENODATA = 61, /* no data available */ 54 FW_EPROTO = 71, /* protocol error */ 55 FW_EADDRINUSE = 98, /* address already in use */ 56 FW_EADDRNOTAVAIL = 99, /* cannot assigned requested address */ 57 FW_ENETDOWN = 100, /* network is down */ 58 FW_ENETUNREACH = 101, /* network is unreachable */ 59 FW_ENOBUFS = 105, /* no buffer space available */ 60 FW_ETIMEDOUT = 110, /* timeout */ 61 FW_EINPROGRESS = 115, /* fw internal */ 62 FW_SCSI_ABORT_REQUESTED = 128, /* */ 63 FW_SCSI_ABORT_TIMEDOUT = 129, /* */ 64 FW_SCSI_ABORTED = 130, /* */ 65 FW_SCSI_CLOSE_REQUESTED = 131, /* */ 66 FW_ERR_LINK_DOWN = 132, /* */ 67 FW_RDEV_NOT_READY = 133, /* */ 68 FW_ERR_RDEV_LOST = 134, /* */ 69 FW_ERR_RDEV_LOGO = 135, /* */ 70 FW_FCOE_NO_XCHG = 136, /* */ 71 FW_SCSI_RSP_ERR = 137, /* */ 72 FW_ERR_RDEV_IMPL_LOGO = 138, /* */ 73 FW_SCSI_UNDER_FLOW_ERR = 139, /* */ 74 FW_SCSI_OVER_FLOW_ERR = 140, /* */ 75 FW_SCSI_DDP_ERR = 141, /* DDP error*/ 76 FW_SCSI_TASK_ERR = 142, /* No SCSI tasks available */ 77 }; 78 79 #define FW_T4VF_SGE_BASE_ADDR 0x0000 80 #define FW_T4VF_MPS_BASE_ADDR 0x0100 81 #define FW_T4VF_PL_BASE_ADDR 0x0200 82 #define FW_T4VF_MBDATA_BASE_ADDR 0x0240 83 #define FW_T4VF_CIM_BASE_ADDR 0x0300 84 85 enum fw_wr_opcodes { 86 FW_FILTER_WR = 0x02, 87 FW_ULPTX_WR = 0x04, 88 FW_TP_WR = 0x05, 89 FW_ETH_TX_PKT_WR = 0x08, 90 FW_OFLD_CONNECTION_WR = 0x2f, 91 FW_FLOWC_WR = 0x0a, 92 FW_OFLD_TX_DATA_WR = 0x0b, 93 FW_CMD_WR = 0x10, 94 FW_ETH_TX_PKT_VM_WR = 0x11, 95 FW_RI_RES_WR = 0x0c, 96 FW_RI_INIT_WR = 0x0d, 97 FW_RI_RDMA_WRITE_WR = 0x14, 98 FW_RI_SEND_WR = 0x15, 99 FW_RI_RDMA_READ_WR = 0x16, 100 FW_RI_RECV_WR = 0x17, 101 FW_RI_BIND_MW_WR = 0x18, 102 FW_RI_FR_NSMR_WR = 0x19, 103 FW_RI_FR_NSMR_TPTE_WR = 0x20, 104 FW_RI_INV_LSTAG_WR = 0x1a, 105 FW_ISCSI_TX_DATA_WR = 0x45, 106 FW_PTP_TX_PKT_WR = 0x46, 107 FW_CRYPTO_LOOKASIDE_WR = 0X6d, 108 FW_LASTC2E_WR = 0x70, 109 FW_FILTER2_WR = 0x77 110 }; 111 112 struct fw_wr_hdr { 113 __be32 hi; 114 __be32 lo; 115 }; 116 117 /* work request opcode (hi) */ 118 #define FW_WR_OP_S 24 119 #define FW_WR_OP_M 0xff 120 #define FW_WR_OP_V(x) ((x) << FW_WR_OP_S) 121 #define FW_WR_OP_G(x) (((x) >> FW_WR_OP_S) & FW_WR_OP_M) 122 123 /* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER */ 124 #define FW_WR_ATOMIC_S 23 125 #define FW_WR_ATOMIC_V(x) ((x) << FW_WR_ATOMIC_S) 126 127 /* flush flag (hi) - firmware flushes flushable work request buffered 128 * in the flow context. 129 */ 130 #define FW_WR_FLUSH_S 22 131 #define FW_WR_FLUSH_V(x) ((x) << FW_WR_FLUSH_S) 132 133 /* completion flag (hi) - firmware generates a cpl_fw6_ack */ 134 #define FW_WR_COMPL_S 21 135 #define FW_WR_COMPL_V(x) ((x) << FW_WR_COMPL_S) 136 #define FW_WR_COMPL_F FW_WR_COMPL_V(1U) 137 138 /* work request immediate data length (hi) */ 139 #define FW_WR_IMMDLEN_S 0 140 #define FW_WR_IMMDLEN_M 0xff 141 #define FW_WR_IMMDLEN_V(x) ((x) << FW_WR_IMMDLEN_S) 142 143 /* egress queue status update to associated ingress queue entry (lo) */ 144 #define FW_WR_EQUIQ_S 31 145 #define FW_WR_EQUIQ_V(x) ((x) << FW_WR_EQUIQ_S) 146 #define FW_WR_EQUIQ_F FW_WR_EQUIQ_V(1U) 147 148 /* egress queue status update to egress queue status entry (lo) */ 149 #define FW_WR_EQUEQ_S 30 150 #define FW_WR_EQUEQ_V(x) ((x) << FW_WR_EQUEQ_S) 151 #define FW_WR_EQUEQ_F FW_WR_EQUEQ_V(1U) 152 153 /* flow context identifier (lo) */ 154 #define FW_WR_FLOWID_S 8 155 #define FW_WR_FLOWID_V(x) ((x) << FW_WR_FLOWID_S) 156 157 /* length in units of 16-bytes (lo) */ 158 #define FW_WR_LEN16_S 0 159 #define FW_WR_LEN16_V(x) ((x) << FW_WR_LEN16_S) 160 161 #define HW_TPL_FR_MT_PR_IV_P_FC 0X32B 162 #define HW_TPL_FR_MT_PR_OV_P_FC 0X327 163 164 /* filter wr reply code in cookie in CPL_SET_TCB_RPL */ 165 enum fw_filter_wr_cookie { 166 FW_FILTER_WR_SUCCESS, 167 FW_FILTER_WR_FLT_ADDED, 168 FW_FILTER_WR_FLT_DELETED, 169 FW_FILTER_WR_SMT_TBL_FULL, 170 FW_FILTER_WR_EINVAL, 171 }; 172 173 struct fw_filter_wr { 174 __be32 op_pkd; 175 __be32 len16_pkd; 176 __be64 r3; 177 __be32 tid_to_iq; 178 __be32 del_filter_to_l2tix; 179 __be16 ethtype; 180 __be16 ethtypem; 181 __u8 frag_to_ovlan_vldm; 182 __u8 smac_sel; 183 __be16 rx_chan_rx_rpl_iq; 184 __be32 maci_to_matchtypem; 185 __u8 ptcl; 186 __u8 ptclm; 187 __u8 ttyp; 188 __u8 ttypm; 189 __be16 ivlan; 190 __be16 ivlanm; 191 __be16 ovlan; 192 __be16 ovlanm; 193 __u8 lip[16]; 194 __u8 lipm[16]; 195 __u8 fip[16]; 196 __u8 fipm[16]; 197 __be16 lp; 198 __be16 lpm; 199 __be16 fp; 200 __be16 fpm; 201 __be16 r7; 202 __u8 sma[6]; 203 }; 204 205 struct fw_filter2_wr { 206 __be32 op_pkd; 207 __be32 len16_pkd; 208 __be64 r3; 209 __be32 tid_to_iq; 210 __be32 del_filter_to_l2tix; 211 __be16 ethtype; 212 __be16 ethtypem; 213 __u8 frag_to_ovlan_vldm; 214 __u8 smac_sel; 215 __be16 rx_chan_rx_rpl_iq; 216 __be32 maci_to_matchtypem; 217 __u8 ptcl; 218 __u8 ptclm; 219 __u8 ttyp; 220 __u8 ttypm; 221 __be16 ivlan; 222 __be16 ivlanm; 223 __be16 ovlan; 224 __be16 ovlanm; 225 __u8 lip[16]; 226 __u8 lipm[16]; 227 __u8 fip[16]; 228 __u8 fipm[16]; 229 __be16 lp; 230 __be16 lpm; 231 __be16 fp; 232 __be16 fpm; 233 __be16 r7; 234 __u8 sma[6]; 235 __be16 r8; 236 __u8 filter_type_swapmac; 237 __u8 natmode_to_ulp_type; 238 __be16 newlport; 239 __be16 newfport; 240 __u8 newlip[16]; 241 __u8 newfip[16]; 242 __be32 natseqcheck; 243 __be32 r9; 244 __be64 r10; 245 __be64 r11; 246 __be64 r12; 247 __be64 r13; 248 }; 249 250 #define FW_FILTER_WR_TID_S 12 251 #define FW_FILTER_WR_TID_M 0xfffff 252 #define FW_FILTER_WR_TID_V(x) ((x) << FW_FILTER_WR_TID_S) 253 #define FW_FILTER_WR_TID_G(x) \ 254 (((x) >> FW_FILTER_WR_TID_S) & FW_FILTER_WR_TID_M) 255 256 #define FW_FILTER_WR_RQTYPE_S 11 257 #define FW_FILTER_WR_RQTYPE_M 0x1 258 #define FW_FILTER_WR_RQTYPE_V(x) ((x) << FW_FILTER_WR_RQTYPE_S) 259 #define FW_FILTER_WR_RQTYPE_G(x) \ 260 (((x) >> FW_FILTER_WR_RQTYPE_S) & FW_FILTER_WR_RQTYPE_M) 261 #define FW_FILTER_WR_RQTYPE_F FW_FILTER_WR_RQTYPE_V(1U) 262 263 #define FW_FILTER_WR_NOREPLY_S 10 264 #define FW_FILTER_WR_NOREPLY_M 0x1 265 #define FW_FILTER_WR_NOREPLY_V(x) ((x) << FW_FILTER_WR_NOREPLY_S) 266 #define FW_FILTER_WR_NOREPLY_G(x) \ 267 (((x) >> FW_FILTER_WR_NOREPLY_S) & FW_FILTER_WR_NOREPLY_M) 268 #define FW_FILTER_WR_NOREPLY_F FW_FILTER_WR_NOREPLY_V(1U) 269 270 #define FW_FILTER_WR_IQ_S 0 271 #define FW_FILTER_WR_IQ_M 0x3ff 272 #define FW_FILTER_WR_IQ_V(x) ((x) << FW_FILTER_WR_IQ_S) 273 #define FW_FILTER_WR_IQ_G(x) \ 274 (((x) >> FW_FILTER_WR_IQ_S) & FW_FILTER_WR_IQ_M) 275 276 #define FW_FILTER_WR_DEL_FILTER_S 31 277 #define FW_FILTER_WR_DEL_FILTER_M 0x1 278 #define FW_FILTER_WR_DEL_FILTER_V(x) ((x) << FW_FILTER_WR_DEL_FILTER_S) 279 #define FW_FILTER_WR_DEL_FILTER_G(x) \ 280 (((x) >> FW_FILTER_WR_DEL_FILTER_S) & FW_FILTER_WR_DEL_FILTER_M) 281 #define FW_FILTER_WR_DEL_FILTER_F FW_FILTER_WR_DEL_FILTER_V(1U) 282 283 #define FW_FILTER_WR_RPTTID_S 25 284 #define FW_FILTER_WR_RPTTID_M 0x1 285 #define FW_FILTER_WR_RPTTID_V(x) ((x) << FW_FILTER_WR_RPTTID_S) 286 #define FW_FILTER_WR_RPTTID_G(x) \ 287 (((x) >> FW_FILTER_WR_RPTTID_S) & FW_FILTER_WR_RPTTID_M) 288 #define FW_FILTER_WR_RPTTID_F FW_FILTER_WR_RPTTID_V(1U) 289 290 #define FW_FILTER_WR_DROP_S 24 291 #define FW_FILTER_WR_DROP_M 0x1 292 #define FW_FILTER_WR_DROP_V(x) ((x) << FW_FILTER_WR_DROP_S) 293 #define FW_FILTER_WR_DROP_G(x) \ 294 (((x) >> FW_FILTER_WR_DROP_S) & FW_FILTER_WR_DROP_M) 295 #define FW_FILTER_WR_DROP_F FW_FILTER_WR_DROP_V(1U) 296 297 #define FW_FILTER_WR_DIRSTEER_S 23 298 #define FW_FILTER_WR_DIRSTEER_M 0x1 299 #define FW_FILTER_WR_DIRSTEER_V(x) ((x) << FW_FILTER_WR_DIRSTEER_S) 300 #define FW_FILTER_WR_DIRSTEER_G(x) \ 301 (((x) >> FW_FILTER_WR_DIRSTEER_S) & FW_FILTER_WR_DIRSTEER_M) 302 #define FW_FILTER_WR_DIRSTEER_F FW_FILTER_WR_DIRSTEER_V(1U) 303 304 #define FW_FILTER_WR_MASKHASH_S 22 305 #define FW_FILTER_WR_MASKHASH_M 0x1 306 #define FW_FILTER_WR_MASKHASH_V(x) ((x) << FW_FILTER_WR_MASKHASH_S) 307 #define FW_FILTER_WR_MASKHASH_G(x) \ 308 (((x) >> FW_FILTER_WR_MASKHASH_S) & FW_FILTER_WR_MASKHASH_M) 309 #define FW_FILTER_WR_MASKHASH_F FW_FILTER_WR_MASKHASH_V(1U) 310 311 #define FW_FILTER_WR_DIRSTEERHASH_S 21 312 #define FW_FILTER_WR_DIRSTEERHASH_M 0x1 313 #define FW_FILTER_WR_DIRSTEERHASH_V(x) ((x) << FW_FILTER_WR_DIRSTEERHASH_S) 314 #define FW_FILTER_WR_DIRSTEERHASH_G(x) \ 315 (((x) >> FW_FILTER_WR_DIRSTEERHASH_S) & FW_FILTER_WR_DIRSTEERHASH_M) 316 #define FW_FILTER_WR_DIRSTEERHASH_F FW_FILTER_WR_DIRSTEERHASH_V(1U) 317 318 #define FW_FILTER_WR_LPBK_S 20 319 #define FW_FILTER_WR_LPBK_M 0x1 320 #define FW_FILTER_WR_LPBK_V(x) ((x) << FW_FILTER_WR_LPBK_S) 321 #define FW_FILTER_WR_LPBK_G(x) \ 322 (((x) >> FW_FILTER_WR_LPBK_S) & FW_FILTER_WR_LPBK_M) 323 #define FW_FILTER_WR_LPBK_F FW_FILTER_WR_LPBK_V(1U) 324 325 #define FW_FILTER_WR_DMAC_S 19 326 #define FW_FILTER_WR_DMAC_M 0x1 327 #define FW_FILTER_WR_DMAC_V(x) ((x) << FW_FILTER_WR_DMAC_S) 328 #define FW_FILTER_WR_DMAC_G(x) \ 329 (((x) >> FW_FILTER_WR_DMAC_S) & FW_FILTER_WR_DMAC_M) 330 #define FW_FILTER_WR_DMAC_F FW_FILTER_WR_DMAC_V(1U) 331 332 #define FW_FILTER_WR_SMAC_S 18 333 #define FW_FILTER_WR_SMAC_M 0x1 334 #define FW_FILTER_WR_SMAC_V(x) ((x) << FW_FILTER_WR_SMAC_S) 335 #define FW_FILTER_WR_SMAC_G(x) \ 336 (((x) >> FW_FILTER_WR_SMAC_S) & FW_FILTER_WR_SMAC_M) 337 #define FW_FILTER_WR_SMAC_F FW_FILTER_WR_SMAC_V(1U) 338 339 #define FW_FILTER_WR_INSVLAN_S 17 340 #define FW_FILTER_WR_INSVLAN_M 0x1 341 #define FW_FILTER_WR_INSVLAN_V(x) ((x) << FW_FILTER_WR_INSVLAN_S) 342 #define FW_FILTER_WR_INSVLAN_G(x) \ 343 (((x) >> FW_FILTER_WR_INSVLAN_S) & FW_FILTER_WR_INSVLAN_M) 344 #define FW_FILTER_WR_INSVLAN_F FW_FILTER_WR_INSVLAN_V(1U) 345 346 #define FW_FILTER_WR_RMVLAN_S 16 347 #define FW_FILTER_WR_RMVLAN_M 0x1 348 #define FW_FILTER_WR_RMVLAN_V(x) ((x) << FW_FILTER_WR_RMVLAN_S) 349 #define FW_FILTER_WR_RMVLAN_G(x) \ 350 (((x) >> FW_FILTER_WR_RMVLAN_S) & FW_FILTER_WR_RMVLAN_M) 351 #define FW_FILTER_WR_RMVLAN_F FW_FILTER_WR_RMVLAN_V(1U) 352 353 #define FW_FILTER_WR_HITCNTS_S 15 354 #define FW_FILTER_WR_HITCNTS_M 0x1 355 #define FW_FILTER_WR_HITCNTS_V(x) ((x) << FW_FILTER_WR_HITCNTS_S) 356 #define FW_FILTER_WR_HITCNTS_G(x) \ 357 (((x) >> FW_FILTER_WR_HITCNTS_S) & FW_FILTER_WR_HITCNTS_M) 358 #define FW_FILTER_WR_HITCNTS_F FW_FILTER_WR_HITCNTS_V(1U) 359 360 #define FW_FILTER_WR_TXCHAN_S 13 361 #define FW_FILTER_WR_TXCHAN_M 0x3 362 #define FW_FILTER_WR_TXCHAN_V(x) ((x) << FW_FILTER_WR_TXCHAN_S) 363 #define FW_FILTER_WR_TXCHAN_G(x) \ 364 (((x) >> FW_FILTER_WR_TXCHAN_S) & FW_FILTER_WR_TXCHAN_M) 365 366 #define FW_FILTER_WR_PRIO_S 12 367 #define FW_FILTER_WR_PRIO_M 0x1 368 #define FW_FILTER_WR_PRIO_V(x) ((x) << FW_FILTER_WR_PRIO_S) 369 #define FW_FILTER_WR_PRIO_G(x) \ 370 (((x) >> FW_FILTER_WR_PRIO_S) & FW_FILTER_WR_PRIO_M) 371 #define FW_FILTER_WR_PRIO_F FW_FILTER_WR_PRIO_V(1U) 372 373 #define FW_FILTER_WR_L2TIX_S 0 374 #define FW_FILTER_WR_L2TIX_M 0xfff 375 #define FW_FILTER_WR_L2TIX_V(x) ((x) << FW_FILTER_WR_L2TIX_S) 376 #define FW_FILTER_WR_L2TIX_G(x) \ 377 (((x) >> FW_FILTER_WR_L2TIX_S) & FW_FILTER_WR_L2TIX_M) 378 379 #define FW_FILTER_WR_FRAG_S 7 380 #define FW_FILTER_WR_FRAG_M 0x1 381 #define FW_FILTER_WR_FRAG_V(x) ((x) << FW_FILTER_WR_FRAG_S) 382 #define FW_FILTER_WR_FRAG_G(x) \ 383 (((x) >> FW_FILTER_WR_FRAG_S) & FW_FILTER_WR_FRAG_M) 384 #define FW_FILTER_WR_FRAG_F FW_FILTER_WR_FRAG_V(1U) 385 386 #define FW_FILTER_WR_FRAGM_S 6 387 #define FW_FILTER_WR_FRAGM_M 0x1 388 #define FW_FILTER_WR_FRAGM_V(x) ((x) << FW_FILTER_WR_FRAGM_S) 389 #define FW_FILTER_WR_FRAGM_G(x) \ 390 (((x) >> FW_FILTER_WR_FRAGM_S) & FW_FILTER_WR_FRAGM_M) 391 #define FW_FILTER_WR_FRAGM_F FW_FILTER_WR_FRAGM_V(1U) 392 393 #define FW_FILTER_WR_IVLAN_VLD_S 5 394 #define FW_FILTER_WR_IVLAN_VLD_M 0x1 395 #define FW_FILTER_WR_IVLAN_VLD_V(x) ((x) << FW_FILTER_WR_IVLAN_VLD_S) 396 #define FW_FILTER_WR_IVLAN_VLD_G(x) \ 397 (((x) >> FW_FILTER_WR_IVLAN_VLD_S) & FW_FILTER_WR_IVLAN_VLD_M) 398 #define FW_FILTER_WR_IVLAN_VLD_F FW_FILTER_WR_IVLAN_VLD_V(1U) 399 400 #define FW_FILTER_WR_OVLAN_VLD_S 4 401 #define FW_FILTER_WR_OVLAN_VLD_M 0x1 402 #define FW_FILTER_WR_OVLAN_VLD_V(x) ((x) << FW_FILTER_WR_OVLAN_VLD_S) 403 #define FW_FILTER_WR_OVLAN_VLD_G(x) \ 404 (((x) >> FW_FILTER_WR_OVLAN_VLD_S) & FW_FILTER_WR_OVLAN_VLD_M) 405 #define FW_FILTER_WR_OVLAN_VLD_F FW_FILTER_WR_OVLAN_VLD_V(1U) 406 407 #define FW_FILTER_WR_IVLAN_VLDM_S 3 408 #define FW_FILTER_WR_IVLAN_VLDM_M 0x1 409 #define FW_FILTER_WR_IVLAN_VLDM_V(x) ((x) << FW_FILTER_WR_IVLAN_VLDM_S) 410 #define FW_FILTER_WR_IVLAN_VLDM_G(x) \ 411 (((x) >> FW_FILTER_WR_IVLAN_VLDM_S) & FW_FILTER_WR_IVLAN_VLDM_M) 412 #define FW_FILTER_WR_IVLAN_VLDM_F FW_FILTER_WR_IVLAN_VLDM_V(1U) 413 414 #define FW_FILTER_WR_OVLAN_VLDM_S 2 415 #define FW_FILTER_WR_OVLAN_VLDM_M 0x1 416 #define FW_FILTER_WR_OVLAN_VLDM_V(x) ((x) << FW_FILTER_WR_OVLAN_VLDM_S) 417 #define FW_FILTER_WR_OVLAN_VLDM_G(x) \ 418 (((x) >> FW_FILTER_WR_OVLAN_VLDM_S) & FW_FILTER_WR_OVLAN_VLDM_M) 419 #define FW_FILTER_WR_OVLAN_VLDM_F FW_FILTER_WR_OVLAN_VLDM_V(1U) 420 421 #define FW_FILTER_WR_RX_CHAN_S 15 422 #define FW_FILTER_WR_RX_CHAN_M 0x1 423 #define FW_FILTER_WR_RX_CHAN_V(x) ((x) << FW_FILTER_WR_RX_CHAN_S) 424 #define FW_FILTER_WR_RX_CHAN_G(x) \ 425 (((x) >> FW_FILTER_WR_RX_CHAN_S) & FW_FILTER_WR_RX_CHAN_M) 426 #define FW_FILTER_WR_RX_CHAN_F FW_FILTER_WR_RX_CHAN_V(1U) 427 428 #define FW_FILTER_WR_RX_RPL_IQ_S 0 429 #define FW_FILTER_WR_RX_RPL_IQ_M 0x3ff 430 #define FW_FILTER_WR_RX_RPL_IQ_V(x) ((x) << FW_FILTER_WR_RX_RPL_IQ_S) 431 #define FW_FILTER_WR_RX_RPL_IQ_G(x) \ 432 (((x) >> FW_FILTER_WR_RX_RPL_IQ_S) & FW_FILTER_WR_RX_RPL_IQ_M) 433 434 #define FW_FILTER2_WR_FILTER_TYPE_S 1 435 #define FW_FILTER2_WR_FILTER_TYPE_M 0x1 436 #define FW_FILTER2_WR_FILTER_TYPE_V(x) ((x) << FW_FILTER2_WR_FILTER_TYPE_S) 437 #define FW_FILTER2_WR_FILTER_TYPE_G(x) \ 438 (((x) >> FW_FILTER2_WR_FILTER_TYPE_S) & FW_FILTER2_WR_FILTER_TYPE_M) 439 #define FW_FILTER2_WR_FILTER_TYPE_F FW_FILTER2_WR_FILTER_TYPE_V(1U) 440 441 #define FW_FILTER2_WR_NATMODE_S 5 442 #define FW_FILTER2_WR_NATMODE_M 0x7 443 #define FW_FILTER2_WR_NATMODE_V(x) ((x) << FW_FILTER2_WR_NATMODE_S) 444 #define FW_FILTER2_WR_NATMODE_G(x) \ 445 (((x) >> FW_FILTER2_WR_NATMODE_S) & FW_FILTER2_WR_NATMODE_M) 446 447 #define FW_FILTER2_WR_NATFLAGCHECK_S 4 448 #define FW_FILTER2_WR_NATFLAGCHECK_M 0x1 449 #define FW_FILTER2_WR_NATFLAGCHECK_V(x) ((x) << FW_FILTER2_WR_NATFLAGCHECK_S) 450 #define FW_FILTER2_WR_NATFLAGCHECK_G(x) \ 451 (((x) >> FW_FILTER2_WR_NATFLAGCHECK_S) & FW_FILTER2_WR_NATFLAGCHECK_M) 452 #define FW_FILTER2_WR_NATFLAGCHECK_F FW_FILTER2_WR_NATFLAGCHECK_V(1U) 453 454 #define FW_FILTER2_WR_ULP_TYPE_S 0 455 #define FW_FILTER2_WR_ULP_TYPE_M 0xf 456 #define FW_FILTER2_WR_ULP_TYPE_V(x) ((x) << FW_FILTER2_WR_ULP_TYPE_S) 457 #define FW_FILTER2_WR_ULP_TYPE_G(x) \ 458 (((x) >> FW_FILTER2_WR_ULP_TYPE_S) & FW_FILTER2_WR_ULP_TYPE_M) 459 460 #define FW_FILTER_WR_MACI_S 23 461 #define FW_FILTER_WR_MACI_M 0x1ff 462 #define FW_FILTER_WR_MACI_V(x) ((x) << FW_FILTER_WR_MACI_S) 463 #define FW_FILTER_WR_MACI_G(x) \ 464 (((x) >> FW_FILTER_WR_MACI_S) & FW_FILTER_WR_MACI_M) 465 466 #define FW_FILTER_WR_MACIM_S 14 467 #define FW_FILTER_WR_MACIM_M 0x1ff 468 #define FW_FILTER_WR_MACIM_V(x) ((x) << FW_FILTER_WR_MACIM_S) 469 #define FW_FILTER_WR_MACIM_G(x) \ 470 (((x) >> FW_FILTER_WR_MACIM_S) & FW_FILTER_WR_MACIM_M) 471 472 #define FW_FILTER_WR_FCOE_S 13 473 #define FW_FILTER_WR_FCOE_M 0x1 474 #define FW_FILTER_WR_FCOE_V(x) ((x) << FW_FILTER_WR_FCOE_S) 475 #define FW_FILTER_WR_FCOE_G(x) \ 476 (((x) >> FW_FILTER_WR_FCOE_S) & FW_FILTER_WR_FCOE_M) 477 #define FW_FILTER_WR_FCOE_F FW_FILTER_WR_FCOE_V(1U) 478 479 #define FW_FILTER_WR_FCOEM_S 12 480 #define FW_FILTER_WR_FCOEM_M 0x1 481 #define FW_FILTER_WR_FCOEM_V(x) ((x) << FW_FILTER_WR_FCOEM_S) 482 #define FW_FILTER_WR_FCOEM_G(x) \ 483 (((x) >> FW_FILTER_WR_FCOEM_S) & FW_FILTER_WR_FCOEM_M) 484 #define FW_FILTER_WR_FCOEM_F FW_FILTER_WR_FCOEM_V(1U) 485 486 #define FW_FILTER_WR_PORT_S 9 487 #define FW_FILTER_WR_PORT_M 0x7 488 #define FW_FILTER_WR_PORT_V(x) ((x) << FW_FILTER_WR_PORT_S) 489 #define FW_FILTER_WR_PORT_G(x) \ 490 (((x) >> FW_FILTER_WR_PORT_S) & FW_FILTER_WR_PORT_M) 491 492 #define FW_FILTER_WR_PORTM_S 6 493 #define FW_FILTER_WR_PORTM_M 0x7 494 #define FW_FILTER_WR_PORTM_V(x) ((x) << FW_FILTER_WR_PORTM_S) 495 #define FW_FILTER_WR_PORTM_G(x) \ 496 (((x) >> FW_FILTER_WR_PORTM_S) & FW_FILTER_WR_PORTM_M) 497 498 #define FW_FILTER_WR_MATCHTYPE_S 3 499 #define FW_FILTER_WR_MATCHTYPE_M 0x7 500 #define FW_FILTER_WR_MATCHTYPE_V(x) ((x) << FW_FILTER_WR_MATCHTYPE_S) 501 #define FW_FILTER_WR_MATCHTYPE_G(x) \ 502 (((x) >> FW_FILTER_WR_MATCHTYPE_S) & FW_FILTER_WR_MATCHTYPE_M) 503 504 #define FW_FILTER_WR_MATCHTYPEM_S 0 505 #define FW_FILTER_WR_MATCHTYPEM_M 0x7 506 #define FW_FILTER_WR_MATCHTYPEM_V(x) ((x) << FW_FILTER_WR_MATCHTYPEM_S) 507 #define FW_FILTER_WR_MATCHTYPEM_G(x) \ 508 (((x) >> FW_FILTER_WR_MATCHTYPEM_S) & FW_FILTER_WR_MATCHTYPEM_M) 509 510 struct fw_ulptx_wr { 511 __be32 op_to_compl; 512 __be32 flowid_len16; 513 u64 cookie; 514 }; 515 516 #define FW_ULPTX_WR_DATA_S 28 517 #define FW_ULPTX_WR_DATA_M 0x1 518 #define FW_ULPTX_WR_DATA_V(x) ((x) << FW_ULPTX_WR_DATA_S) 519 #define FW_ULPTX_WR_DATA_G(x) \ 520 (((x) >> FW_ULPTX_WR_DATA_S) & FW_ULPTX_WR_DATA_M) 521 #define FW_ULPTX_WR_DATA_F FW_ULPTX_WR_DATA_V(1U) 522 523 struct fw_tp_wr { 524 __be32 op_to_immdlen; 525 __be32 flowid_len16; 526 u64 cookie; 527 }; 528 529 struct fw_eth_tx_pkt_wr { 530 __be32 op_immdlen; 531 __be32 equiq_to_len16; 532 __be64 r3; 533 }; 534 535 struct fw_ofld_connection_wr { 536 __be32 op_compl; 537 __be32 len16_pkd; 538 __u64 cookie; 539 __be64 r2; 540 __be64 r3; 541 struct fw_ofld_connection_le { 542 __be32 version_cpl; 543 __be32 filter; 544 __be32 r1; 545 __be16 lport; 546 __be16 pport; 547 union fw_ofld_connection_leip { 548 struct fw_ofld_connection_le_ipv4 { 549 __be32 pip; 550 __be32 lip; 551 __be64 r0; 552 __be64 r1; 553 __be64 r2; 554 } ipv4; 555 struct fw_ofld_connection_le_ipv6 { 556 __be64 pip_hi; 557 __be64 pip_lo; 558 __be64 lip_hi; 559 __be64 lip_lo; 560 } ipv6; 561 } u; 562 } le; 563 struct fw_ofld_connection_tcb { 564 __be32 t_state_to_astid; 565 __be16 cplrxdataack_cplpassacceptrpl; 566 __be16 rcv_adv; 567 __be32 rcv_nxt; 568 __be32 tx_max; 569 __be64 opt0; 570 __be32 opt2; 571 __be32 r1; 572 __be64 r2; 573 __be64 r3; 574 } tcb; 575 }; 576 577 #define FW_OFLD_CONNECTION_WR_VERSION_S 31 578 #define FW_OFLD_CONNECTION_WR_VERSION_M 0x1 579 #define FW_OFLD_CONNECTION_WR_VERSION_V(x) \ 580 ((x) << FW_OFLD_CONNECTION_WR_VERSION_S) 581 #define FW_OFLD_CONNECTION_WR_VERSION_G(x) \ 582 (((x) >> FW_OFLD_CONNECTION_WR_VERSION_S) & \ 583 FW_OFLD_CONNECTION_WR_VERSION_M) 584 #define FW_OFLD_CONNECTION_WR_VERSION_F \ 585 FW_OFLD_CONNECTION_WR_VERSION_V(1U) 586 587 #define FW_OFLD_CONNECTION_WR_CPL_S 30 588 #define FW_OFLD_CONNECTION_WR_CPL_M 0x1 589 #define FW_OFLD_CONNECTION_WR_CPL_V(x) ((x) << FW_OFLD_CONNECTION_WR_CPL_S) 590 #define FW_OFLD_CONNECTION_WR_CPL_G(x) \ 591 (((x) >> FW_OFLD_CONNECTION_WR_CPL_S) & FW_OFLD_CONNECTION_WR_CPL_M) 592 #define FW_OFLD_CONNECTION_WR_CPL_F FW_OFLD_CONNECTION_WR_CPL_V(1U) 593 594 #define FW_OFLD_CONNECTION_WR_T_STATE_S 28 595 #define FW_OFLD_CONNECTION_WR_T_STATE_M 0xf 596 #define FW_OFLD_CONNECTION_WR_T_STATE_V(x) \ 597 ((x) << FW_OFLD_CONNECTION_WR_T_STATE_S) 598 #define FW_OFLD_CONNECTION_WR_T_STATE_G(x) \ 599 (((x) >> FW_OFLD_CONNECTION_WR_T_STATE_S) & \ 600 FW_OFLD_CONNECTION_WR_T_STATE_M) 601 602 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_S 24 603 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_M 0xf 604 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_V(x) \ 605 ((x) << FW_OFLD_CONNECTION_WR_RCV_SCALE_S) 606 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_G(x) \ 607 (((x) >> FW_OFLD_CONNECTION_WR_RCV_SCALE_S) & \ 608 FW_OFLD_CONNECTION_WR_RCV_SCALE_M) 609 610 #define FW_OFLD_CONNECTION_WR_ASTID_S 0 611 #define FW_OFLD_CONNECTION_WR_ASTID_M 0xffffff 612 #define FW_OFLD_CONNECTION_WR_ASTID_V(x) \ 613 ((x) << FW_OFLD_CONNECTION_WR_ASTID_S) 614 #define FW_OFLD_CONNECTION_WR_ASTID_G(x) \ 615 (((x) >> FW_OFLD_CONNECTION_WR_ASTID_S) & FW_OFLD_CONNECTION_WR_ASTID_M) 616 617 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S 15 618 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_M 0x1 619 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_V(x) \ 620 ((x) << FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S) 621 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_G(x) \ 622 (((x) >> FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S) & \ 623 FW_OFLD_CONNECTION_WR_CPLRXDATAACK_M) 624 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_F \ 625 FW_OFLD_CONNECTION_WR_CPLRXDATAACK_V(1U) 626 627 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S 14 628 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_M 0x1 629 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_V(x) \ 630 ((x) << FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S) 631 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_G(x) \ 632 (((x) >> FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S) & \ 633 FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_M) 634 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_F \ 635 FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_V(1U) 636 637 enum fw_flowc_mnem { 638 FW_FLOWC_MNEM_PFNVFN, /* PFN [15:8] VFN [7:0] */ 639 FW_FLOWC_MNEM_CH, 640 FW_FLOWC_MNEM_PORT, 641 FW_FLOWC_MNEM_IQID, 642 FW_FLOWC_MNEM_SNDNXT, 643 FW_FLOWC_MNEM_RCVNXT, 644 FW_FLOWC_MNEM_SNDBUF, 645 FW_FLOWC_MNEM_MSS, 646 FW_FLOWC_MNEM_TXDATAPLEN_MAX, 647 FW_FLOWC_MNEM_TCPSTATE, 648 FW_FLOWC_MNEM_EOSTATE, 649 FW_FLOWC_MNEM_SCHEDCLASS, 650 FW_FLOWC_MNEM_DCBPRIO, 651 FW_FLOWC_MNEM_SND_SCALE, 652 FW_FLOWC_MNEM_RCV_SCALE, 653 }; 654 655 struct fw_flowc_mnemval { 656 u8 mnemonic; 657 u8 r4[3]; 658 __be32 val; 659 }; 660 661 struct fw_flowc_wr { 662 __be32 op_to_nparams; 663 __be32 flowid_len16; 664 struct fw_flowc_mnemval mnemval[0]; 665 }; 666 667 #define FW_FLOWC_WR_NPARAMS_S 0 668 #define FW_FLOWC_WR_NPARAMS_V(x) ((x) << FW_FLOWC_WR_NPARAMS_S) 669 670 struct fw_ofld_tx_data_wr { 671 __be32 op_to_immdlen; 672 __be32 flowid_len16; 673 __be32 plen; 674 __be32 tunnel_to_proxy; 675 }; 676 677 #define FW_OFLD_TX_DATA_WR_TUNNEL_S 19 678 #define FW_OFLD_TX_DATA_WR_TUNNEL_V(x) ((x) << FW_OFLD_TX_DATA_WR_TUNNEL_S) 679 680 #define FW_OFLD_TX_DATA_WR_SAVE_S 18 681 #define FW_OFLD_TX_DATA_WR_SAVE_V(x) ((x) << FW_OFLD_TX_DATA_WR_SAVE_S) 682 683 #define FW_OFLD_TX_DATA_WR_FLUSH_S 17 684 #define FW_OFLD_TX_DATA_WR_FLUSH_V(x) ((x) << FW_OFLD_TX_DATA_WR_FLUSH_S) 685 #define FW_OFLD_TX_DATA_WR_FLUSH_F FW_OFLD_TX_DATA_WR_FLUSH_V(1U) 686 687 #define FW_OFLD_TX_DATA_WR_URGENT_S 16 688 #define FW_OFLD_TX_DATA_WR_URGENT_V(x) ((x) << FW_OFLD_TX_DATA_WR_URGENT_S) 689 690 #define FW_OFLD_TX_DATA_WR_MORE_S 15 691 #define FW_OFLD_TX_DATA_WR_MORE_V(x) ((x) << FW_OFLD_TX_DATA_WR_MORE_S) 692 693 #define FW_OFLD_TX_DATA_WR_SHOVE_S 14 694 #define FW_OFLD_TX_DATA_WR_SHOVE_V(x) ((x) << FW_OFLD_TX_DATA_WR_SHOVE_S) 695 #define FW_OFLD_TX_DATA_WR_SHOVE_F FW_OFLD_TX_DATA_WR_SHOVE_V(1U) 696 697 #define FW_OFLD_TX_DATA_WR_ULPMODE_S 10 698 #define FW_OFLD_TX_DATA_WR_ULPMODE_V(x) ((x) << FW_OFLD_TX_DATA_WR_ULPMODE_S) 699 700 #define FW_OFLD_TX_DATA_WR_ULPSUBMODE_S 6 701 #define FW_OFLD_TX_DATA_WR_ULPSUBMODE_V(x) \ 702 ((x) << FW_OFLD_TX_DATA_WR_ULPSUBMODE_S) 703 704 struct fw_cmd_wr { 705 __be32 op_dma; 706 __be32 len16_pkd; 707 __be64 cookie_daddr; 708 }; 709 710 #define FW_CMD_WR_DMA_S 17 711 #define FW_CMD_WR_DMA_V(x) ((x) << FW_CMD_WR_DMA_S) 712 713 struct fw_eth_tx_pkt_vm_wr { 714 __be32 op_immdlen; 715 __be32 equiq_to_len16; 716 __be32 r3[2]; 717 u8 ethmacdst[6]; 718 u8 ethmacsrc[6]; 719 __be16 ethtype; 720 __be16 vlantci; 721 }; 722 723 #define FW_CMD_MAX_TIMEOUT 10000 724 725 /* 726 * If a host driver does a HELLO and discovers that there's already a MASTER 727 * selected, we may have to wait for that MASTER to finish issuing RESET, 728 * configuration and INITIALIZE commands. Also, there's a possibility that 729 * our own HELLO may get lost if it happens right as the MASTER is issuign a 730 * RESET command, so we need to be willing to make a few retries of our HELLO. 731 */ 732 #define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT) 733 #define FW_CMD_HELLO_RETRIES 3 734 735 736 enum fw_cmd_opcodes { 737 FW_LDST_CMD = 0x01, 738 FW_RESET_CMD = 0x03, 739 FW_HELLO_CMD = 0x04, 740 FW_BYE_CMD = 0x05, 741 FW_INITIALIZE_CMD = 0x06, 742 FW_CAPS_CONFIG_CMD = 0x07, 743 FW_PARAMS_CMD = 0x08, 744 FW_PFVF_CMD = 0x09, 745 FW_IQ_CMD = 0x10, 746 FW_EQ_MNGT_CMD = 0x11, 747 FW_EQ_ETH_CMD = 0x12, 748 FW_EQ_CTRL_CMD = 0x13, 749 FW_EQ_OFLD_CMD = 0x21, 750 FW_VI_CMD = 0x14, 751 FW_VI_MAC_CMD = 0x15, 752 FW_VI_RXMODE_CMD = 0x16, 753 FW_VI_ENABLE_CMD = 0x17, 754 FW_ACL_MAC_CMD = 0x18, 755 FW_ACL_VLAN_CMD = 0x19, 756 FW_VI_STATS_CMD = 0x1a, 757 FW_PORT_CMD = 0x1b, 758 FW_PORT_STATS_CMD = 0x1c, 759 FW_PORT_LB_STATS_CMD = 0x1d, 760 FW_PORT_TRACE_CMD = 0x1e, 761 FW_PORT_TRACE_MMAP_CMD = 0x1f, 762 FW_RSS_IND_TBL_CMD = 0x20, 763 FW_RSS_GLB_CONFIG_CMD = 0x22, 764 FW_RSS_VI_CONFIG_CMD = 0x23, 765 FW_SCHED_CMD = 0x24, 766 FW_DEVLOG_CMD = 0x25, 767 FW_CLIP_CMD = 0x28, 768 FW_PTP_CMD = 0x3e, 769 FW_LASTC2E_CMD = 0x40, 770 FW_ERROR_CMD = 0x80, 771 FW_DEBUG_CMD = 0x81, 772 }; 773 774 enum fw_cmd_cap { 775 FW_CMD_CAP_PF = 0x01, 776 FW_CMD_CAP_DMAQ = 0x02, 777 FW_CMD_CAP_PORT = 0x04, 778 FW_CMD_CAP_PORTPROMISC = 0x08, 779 FW_CMD_CAP_PORTSTATS = 0x10, 780 FW_CMD_CAP_VF = 0x80, 781 }; 782 783 /* 784 * Generic command header flit0 785 */ 786 struct fw_cmd_hdr { 787 __be32 hi; 788 __be32 lo; 789 }; 790 791 #define FW_CMD_OP_S 24 792 #define FW_CMD_OP_M 0xff 793 #define FW_CMD_OP_V(x) ((x) << FW_CMD_OP_S) 794 #define FW_CMD_OP_G(x) (((x) >> FW_CMD_OP_S) & FW_CMD_OP_M) 795 796 #define FW_CMD_REQUEST_S 23 797 #define FW_CMD_REQUEST_V(x) ((x) << FW_CMD_REQUEST_S) 798 #define FW_CMD_REQUEST_F FW_CMD_REQUEST_V(1U) 799 800 #define FW_CMD_READ_S 22 801 #define FW_CMD_READ_V(x) ((x) << FW_CMD_READ_S) 802 #define FW_CMD_READ_F FW_CMD_READ_V(1U) 803 804 #define FW_CMD_WRITE_S 21 805 #define FW_CMD_WRITE_V(x) ((x) << FW_CMD_WRITE_S) 806 #define FW_CMD_WRITE_F FW_CMD_WRITE_V(1U) 807 808 #define FW_CMD_EXEC_S 20 809 #define FW_CMD_EXEC_V(x) ((x) << FW_CMD_EXEC_S) 810 #define FW_CMD_EXEC_F FW_CMD_EXEC_V(1U) 811 812 #define FW_CMD_RAMASK_S 20 813 #define FW_CMD_RAMASK_V(x) ((x) << FW_CMD_RAMASK_S) 814 815 #define FW_CMD_RETVAL_S 8 816 #define FW_CMD_RETVAL_M 0xff 817 #define FW_CMD_RETVAL_V(x) ((x) << FW_CMD_RETVAL_S) 818 #define FW_CMD_RETVAL_G(x) (((x) >> FW_CMD_RETVAL_S) & FW_CMD_RETVAL_M) 819 820 #define FW_CMD_LEN16_S 0 821 #define FW_CMD_LEN16_V(x) ((x) << FW_CMD_LEN16_S) 822 823 #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16) 824 825 enum fw_ldst_addrspc { 826 FW_LDST_ADDRSPC_FIRMWARE = 0x0001, 827 FW_LDST_ADDRSPC_SGE_EGRC = 0x0008, 828 FW_LDST_ADDRSPC_SGE_INGC = 0x0009, 829 FW_LDST_ADDRSPC_SGE_FLMC = 0x000a, 830 FW_LDST_ADDRSPC_SGE_CONMC = 0x000b, 831 FW_LDST_ADDRSPC_TP_PIO = 0x0010, 832 FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011, 833 FW_LDST_ADDRSPC_TP_MIB = 0x0012, 834 FW_LDST_ADDRSPC_MDIO = 0x0018, 835 FW_LDST_ADDRSPC_MPS = 0x0020, 836 FW_LDST_ADDRSPC_FUNC = 0x0028, 837 FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029, 838 FW_LDST_ADDRSPC_I2C = 0x0038, 839 }; 840 841 enum fw_ldst_mps_fid { 842 FW_LDST_MPS_ATRB, 843 FW_LDST_MPS_RPLC 844 }; 845 846 enum fw_ldst_func_access_ctl { 847 FW_LDST_FUNC_ACC_CTL_VIID, 848 FW_LDST_FUNC_ACC_CTL_FID 849 }; 850 851 enum fw_ldst_func_mod_index { 852 FW_LDST_FUNC_MPS 853 }; 854 855 struct fw_ldst_cmd { 856 __be32 op_to_addrspace; 857 __be32 cycles_to_len16; 858 union fw_ldst { 859 struct fw_ldst_addrval { 860 __be32 addr; 861 __be32 val; 862 } addrval; 863 struct fw_ldst_idctxt { 864 __be32 physid; 865 __be32 msg_ctxtflush; 866 __be32 ctxt_data7; 867 __be32 ctxt_data6; 868 __be32 ctxt_data5; 869 __be32 ctxt_data4; 870 __be32 ctxt_data3; 871 __be32 ctxt_data2; 872 __be32 ctxt_data1; 873 __be32 ctxt_data0; 874 } idctxt; 875 struct fw_ldst_mdio { 876 __be16 paddr_mmd; 877 __be16 raddr; 878 __be16 vctl; 879 __be16 rval; 880 } mdio; 881 struct fw_ldst_cim_rq { 882 u8 req_first64[8]; 883 u8 req_second64[8]; 884 u8 resp_first64[8]; 885 u8 resp_second64[8]; 886 __be32 r3[2]; 887 } cim_rq; 888 union fw_ldst_mps { 889 struct fw_ldst_mps_rplc { 890 __be16 fid_idx; 891 __be16 rplcpf_pkd; 892 __be32 rplc255_224; 893 __be32 rplc223_192; 894 __be32 rplc191_160; 895 __be32 rplc159_128; 896 __be32 rplc127_96; 897 __be32 rplc95_64; 898 __be32 rplc63_32; 899 __be32 rplc31_0; 900 } rplc; 901 struct fw_ldst_mps_atrb { 902 __be16 fid_mpsid; 903 __be16 r2[3]; 904 __be32 r3[2]; 905 __be32 r4; 906 __be32 atrb; 907 __be16 vlan[16]; 908 } atrb; 909 } mps; 910 struct fw_ldst_func { 911 u8 access_ctl; 912 u8 mod_index; 913 __be16 ctl_id; 914 __be32 offset; 915 __be64 data0; 916 __be64 data1; 917 } func; 918 struct fw_ldst_pcie { 919 u8 ctrl_to_fn; 920 u8 bnum; 921 u8 r; 922 u8 ext_r; 923 u8 select_naccess; 924 u8 pcie_fn; 925 __be16 nset_pkd; 926 __be32 data[12]; 927 } pcie; 928 struct fw_ldst_i2c_deprecated { 929 u8 pid_pkd; 930 u8 base; 931 u8 boffset; 932 u8 data; 933 __be32 r9; 934 } i2c_deprecated; 935 struct fw_ldst_i2c { 936 u8 pid; 937 u8 did; 938 u8 boffset; 939 u8 blen; 940 __be32 r9; 941 __u8 data[48]; 942 } i2c; 943 struct fw_ldst_le { 944 __be32 index; 945 __be32 r9; 946 u8 val[33]; 947 u8 r11[7]; 948 } le; 949 } u; 950 }; 951 952 #define FW_LDST_CMD_ADDRSPACE_S 0 953 #define FW_LDST_CMD_ADDRSPACE_V(x) ((x) << FW_LDST_CMD_ADDRSPACE_S) 954 955 #define FW_LDST_CMD_MSG_S 31 956 #define FW_LDST_CMD_MSG_V(x) ((x) << FW_LDST_CMD_MSG_S) 957 958 #define FW_LDST_CMD_CTXTFLUSH_S 30 959 #define FW_LDST_CMD_CTXTFLUSH_V(x) ((x) << FW_LDST_CMD_CTXTFLUSH_S) 960 #define FW_LDST_CMD_CTXTFLUSH_F FW_LDST_CMD_CTXTFLUSH_V(1U) 961 962 #define FW_LDST_CMD_PADDR_S 8 963 #define FW_LDST_CMD_PADDR_V(x) ((x) << FW_LDST_CMD_PADDR_S) 964 965 #define FW_LDST_CMD_MMD_S 0 966 #define FW_LDST_CMD_MMD_V(x) ((x) << FW_LDST_CMD_MMD_S) 967 968 #define FW_LDST_CMD_FID_S 15 969 #define FW_LDST_CMD_FID_V(x) ((x) << FW_LDST_CMD_FID_S) 970 971 #define FW_LDST_CMD_IDX_S 0 972 #define FW_LDST_CMD_IDX_V(x) ((x) << FW_LDST_CMD_IDX_S) 973 974 #define FW_LDST_CMD_RPLCPF_S 0 975 #define FW_LDST_CMD_RPLCPF_V(x) ((x) << FW_LDST_CMD_RPLCPF_S) 976 977 #define FW_LDST_CMD_LC_S 4 978 #define FW_LDST_CMD_LC_V(x) ((x) << FW_LDST_CMD_LC_S) 979 #define FW_LDST_CMD_LC_F FW_LDST_CMD_LC_V(1U) 980 981 #define FW_LDST_CMD_FN_S 0 982 #define FW_LDST_CMD_FN_V(x) ((x) << FW_LDST_CMD_FN_S) 983 984 #define FW_LDST_CMD_NACCESS_S 0 985 #define FW_LDST_CMD_NACCESS_V(x) ((x) << FW_LDST_CMD_NACCESS_S) 986 987 struct fw_reset_cmd { 988 __be32 op_to_write; 989 __be32 retval_len16; 990 __be32 val; 991 __be32 halt_pkd; 992 }; 993 994 #define FW_RESET_CMD_HALT_S 31 995 #define FW_RESET_CMD_HALT_M 0x1 996 #define FW_RESET_CMD_HALT_V(x) ((x) << FW_RESET_CMD_HALT_S) 997 #define FW_RESET_CMD_HALT_G(x) \ 998 (((x) >> FW_RESET_CMD_HALT_S) & FW_RESET_CMD_HALT_M) 999 #define FW_RESET_CMD_HALT_F FW_RESET_CMD_HALT_V(1U) 1000 1001 enum fw_hellow_cmd { 1002 fw_hello_cmd_stage_os = 0x0 1003 }; 1004 1005 struct fw_hello_cmd { 1006 __be32 op_to_write; 1007 __be32 retval_len16; 1008 __be32 err_to_clearinit; 1009 __be32 fwrev; 1010 }; 1011 1012 #define FW_HELLO_CMD_ERR_S 31 1013 #define FW_HELLO_CMD_ERR_V(x) ((x) << FW_HELLO_CMD_ERR_S) 1014 #define FW_HELLO_CMD_ERR_F FW_HELLO_CMD_ERR_V(1U) 1015 1016 #define FW_HELLO_CMD_INIT_S 30 1017 #define FW_HELLO_CMD_INIT_V(x) ((x) << FW_HELLO_CMD_INIT_S) 1018 #define FW_HELLO_CMD_INIT_F FW_HELLO_CMD_INIT_V(1U) 1019 1020 #define FW_HELLO_CMD_MASTERDIS_S 29 1021 #define FW_HELLO_CMD_MASTERDIS_V(x) ((x) << FW_HELLO_CMD_MASTERDIS_S) 1022 1023 #define FW_HELLO_CMD_MASTERFORCE_S 28 1024 #define FW_HELLO_CMD_MASTERFORCE_V(x) ((x) << FW_HELLO_CMD_MASTERFORCE_S) 1025 1026 #define FW_HELLO_CMD_MBMASTER_S 24 1027 #define FW_HELLO_CMD_MBMASTER_M 0xfU 1028 #define FW_HELLO_CMD_MBMASTER_V(x) ((x) << FW_HELLO_CMD_MBMASTER_S) 1029 #define FW_HELLO_CMD_MBMASTER_G(x) \ 1030 (((x) >> FW_HELLO_CMD_MBMASTER_S) & FW_HELLO_CMD_MBMASTER_M) 1031 1032 #define FW_HELLO_CMD_MBASYNCNOTINT_S 23 1033 #define FW_HELLO_CMD_MBASYNCNOTINT_V(x) ((x) << FW_HELLO_CMD_MBASYNCNOTINT_S) 1034 1035 #define FW_HELLO_CMD_MBASYNCNOT_S 20 1036 #define FW_HELLO_CMD_MBASYNCNOT_V(x) ((x) << FW_HELLO_CMD_MBASYNCNOT_S) 1037 1038 #define FW_HELLO_CMD_STAGE_S 17 1039 #define FW_HELLO_CMD_STAGE_V(x) ((x) << FW_HELLO_CMD_STAGE_S) 1040 1041 #define FW_HELLO_CMD_CLEARINIT_S 16 1042 #define FW_HELLO_CMD_CLEARINIT_V(x) ((x) << FW_HELLO_CMD_CLEARINIT_S) 1043 #define FW_HELLO_CMD_CLEARINIT_F FW_HELLO_CMD_CLEARINIT_V(1U) 1044 1045 struct fw_bye_cmd { 1046 __be32 op_to_write; 1047 __be32 retval_len16; 1048 __be64 r3; 1049 }; 1050 1051 struct fw_initialize_cmd { 1052 __be32 op_to_write; 1053 __be32 retval_len16; 1054 __be64 r3; 1055 }; 1056 1057 enum fw_caps_config_hm { 1058 FW_CAPS_CONFIG_HM_PCIE = 0x00000001, 1059 FW_CAPS_CONFIG_HM_PL = 0x00000002, 1060 FW_CAPS_CONFIG_HM_SGE = 0x00000004, 1061 FW_CAPS_CONFIG_HM_CIM = 0x00000008, 1062 FW_CAPS_CONFIG_HM_ULPTX = 0x00000010, 1063 FW_CAPS_CONFIG_HM_TP = 0x00000020, 1064 FW_CAPS_CONFIG_HM_ULPRX = 0x00000040, 1065 FW_CAPS_CONFIG_HM_PMRX = 0x00000080, 1066 FW_CAPS_CONFIG_HM_PMTX = 0x00000100, 1067 FW_CAPS_CONFIG_HM_MC = 0x00000200, 1068 FW_CAPS_CONFIG_HM_LE = 0x00000400, 1069 FW_CAPS_CONFIG_HM_MPS = 0x00000800, 1070 FW_CAPS_CONFIG_HM_XGMAC = 0x00001000, 1071 FW_CAPS_CONFIG_HM_CPLSWITCH = 0x00002000, 1072 FW_CAPS_CONFIG_HM_T4DBG = 0x00004000, 1073 FW_CAPS_CONFIG_HM_MI = 0x00008000, 1074 FW_CAPS_CONFIG_HM_I2CM = 0x00010000, 1075 FW_CAPS_CONFIG_HM_NCSI = 0x00020000, 1076 FW_CAPS_CONFIG_HM_SMB = 0x00040000, 1077 FW_CAPS_CONFIG_HM_MA = 0x00080000, 1078 FW_CAPS_CONFIG_HM_EDRAM = 0x00100000, 1079 FW_CAPS_CONFIG_HM_PMU = 0x00200000, 1080 FW_CAPS_CONFIG_HM_UART = 0x00400000, 1081 FW_CAPS_CONFIG_HM_SF = 0x00800000, 1082 }; 1083 1084 enum fw_caps_config_nbm { 1085 FW_CAPS_CONFIG_NBM_IPMI = 0x00000001, 1086 FW_CAPS_CONFIG_NBM_NCSI = 0x00000002, 1087 }; 1088 1089 enum fw_caps_config_link { 1090 FW_CAPS_CONFIG_LINK_PPP = 0x00000001, 1091 FW_CAPS_CONFIG_LINK_QFC = 0x00000002, 1092 FW_CAPS_CONFIG_LINK_DCBX = 0x00000004, 1093 }; 1094 1095 enum fw_caps_config_switch { 1096 FW_CAPS_CONFIG_SWITCH_INGRESS = 0x00000001, 1097 FW_CAPS_CONFIG_SWITCH_EGRESS = 0x00000002, 1098 }; 1099 1100 enum fw_caps_config_nic { 1101 FW_CAPS_CONFIG_NIC = 0x00000001, 1102 FW_CAPS_CONFIG_NIC_VM = 0x00000002, 1103 FW_CAPS_CONFIG_NIC_HASHFILTER = 0x00000020, 1104 }; 1105 1106 enum fw_caps_config_ofld { 1107 FW_CAPS_CONFIG_OFLD = 0x00000001, 1108 }; 1109 1110 enum fw_caps_config_rdma { 1111 FW_CAPS_CONFIG_RDMA_RDDP = 0x00000001, 1112 FW_CAPS_CONFIG_RDMA_RDMAC = 0x00000002, 1113 }; 1114 1115 enum fw_caps_config_iscsi { 1116 FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU = 0x00000001, 1117 FW_CAPS_CONFIG_ISCSI_TARGET_PDU = 0x00000002, 1118 FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD = 0x00000004, 1119 FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008, 1120 }; 1121 1122 enum fw_caps_config_fcoe { 1123 FW_CAPS_CONFIG_FCOE_INITIATOR = 0x00000001, 1124 FW_CAPS_CONFIG_FCOE_TARGET = 0x00000002, 1125 FW_CAPS_CONFIG_FCOE_CTRL_OFLD = 0x00000004, 1126 }; 1127 1128 enum fw_memtype_cf { 1129 FW_MEMTYPE_CF_EDC0 = 0x0, 1130 FW_MEMTYPE_CF_EDC1 = 0x1, 1131 FW_MEMTYPE_CF_EXTMEM = 0x2, 1132 FW_MEMTYPE_CF_FLASH = 0x4, 1133 FW_MEMTYPE_CF_INTERNAL = 0x5, 1134 FW_MEMTYPE_CF_EXTMEM1 = 0x6, 1135 }; 1136 1137 struct fw_caps_config_cmd { 1138 __be32 op_to_write; 1139 __be32 cfvalid_to_len16; 1140 __be32 r2; 1141 __be32 hwmbitmap; 1142 __be16 nbmcaps; 1143 __be16 linkcaps; 1144 __be16 switchcaps; 1145 __be16 r3; 1146 __be16 niccaps; 1147 __be16 ofldcaps; 1148 __be16 rdmacaps; 1149 __be16 cryptocaps; 1150 __be16 iscsicaps; 1151 __be16 fcoecaps; 1152 __be32 cfcsum; 1153 __be32 finiver; 1154 __be32 finicsum; 1155 }; 1156 1157 #define FW_CAPS_CONFIG_CMD_CFVALID_S 27 1158 #define FW_CAPS_CONFIG_CMD_CFVALID_V(x) ((x) << FW_CAPS_CONFIG_CMD_CFVALID_S) 1159 #define FW_CAPS_CONFIG_CMD_CFVALID_F FW_CAPS_CONFIG_CMD_CFVALID_V(1U) 1160 1161 #define FW_CAPS_CONFIG_CMD_MEMTYPE_CF_S 24 1162 #define FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(x) \ 1163 ((x) << FW_CAPS_CONFIG_CMD_MEMTYPE_CF_S) 1164 1165 #define FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_S 16 1166 #define FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(x) \ 1167 ((x) << FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_S) 1168 1169 /* 1170 * params command mnemonics 1171 */ 1172 enum fw_params_mnem { 1173 FW_PARAMS_MNEM_DEV = 1, /* device params */ 1174 FW_PARAMS_MNEM_PFVF = 2, /* function params */ 1175 FW_PARAMS_MNEM_REG = 3, /* limited register access */ 1176 FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */ 1177 FW_PARAMS_MNEM_CHNET = 5, /* chnet params */ 1178 FW_PARAMS_MNEM_LAST 1179 }; 1180 1181 /* 1182 * device parameters 1183 */ 1184 enum fw_params_param_dev { 1185 FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */ 1186 FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */ 1187 FW_PARAMS_PARAM_DEV_NTID = 0x02, /* reads the number of TIDs 1188 * allocated by the device's 1189 * Lookup Engine 1190 */ 1191 FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03, 1192 FW_PARAMS_PARAM_DEV_INTVER_NIC = 0x04, 1193 FW_PARAMS_PARAM_DEV_INTVER_VNIC = 0x05, 1194 FW_PARAMS_PARAM_DEV_INTVER_OFLD = 0x06, 1195 FW_PARAMS_PARAM_DEV_INTVER_RI = 0x07, 1196 FW_PARAMS_PARAM_DEV_INTVER_ISCSIPDU = 0x08, 1197 FW_PARAMS_PARAM_DEV_INTVER_ISCSI = 0x09, 1198 FW_PARAMS_PARAM_DEV_INTVER_FCOE = 0x0A, 1199 FW_PARAMS_PARAM_DEV_FWREV = 0x0B, 1200 FW_PARAMS_PARAM_DEV_TPREV = 0x0C, 1201 FW_PARAMS_PARAM_DEV_CF = 0x0D, 1202 FW_PARAMS_PARAM_DEV_PHYFW = 0x0F, 1203 FW_PARAMS_PARAM_DEV_DIAG = 0x11, 1204 FW_PARAMS_PARAM_DEV_MAXORDIRD_QP = 0x13, /* max supported QP IRD/ORD */ 1205 FW_PARAMS_PARAM_DEV_MAXIRD_ADAPTER = 0x14, /* max supported adap IRD */ 1206 FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17, 1207 FW_PARAMS_PARAM_DEV_FWCACHE = 0x18, 1208 FW_PARAMS_PARAM_DEV_SCFGREV = 0x1A, 1209 FW_PARAMS_PARAM_DEV_VPDREV = 0x1B, 1210 FW_PARAMS_PARAM_DEV_RI_FR_NSMR_TPTE_WR = 0x1C, 1211 FW_PARAMS_PARAM_DEV_FILTER2_WR = 0x1D, 1212 FW_PARAMS_PARAM_DEV_MPSBGMAP = 0x1E, 1213 }; 1214 1215 /* 1216 * physical and virtual function parameters 1217 */ 1218 enum fw_params_param_pfvf { 1219 FW_PARAMS_PARAM_PFVF_RWXCAPS = 0x00, 1220 FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01, 1221 FW_PARAMS_PARAM_PFVF_ROUTE_END = 0x02, 1222 FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03, 1223 FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04, 1224 FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05, 1225 FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06, 1226 FW_PARAMS_PARAM_PFVF_SERVER_START = 0x07, 1227 FW_PARAMS_PARAM_PFVF_SERVER_END = 0x08, 1228 FW_PARAMS_PARAM_PFVF_TDDP_START = 0x09, 1229 FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A, 1230 FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B, 1231 FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C, 1232 FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D, 1233 FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E, 1234 FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F, 1235 FW_PARAMS_PARAM_PFVF_RQ_END = 0x10, 1236 FW_PARAMS_PARAM_PFVF_PBL_START = 0x11, 1237 FW_PARAMS_PARAM_PFVF_PBL_END = 0x12, 1238 FW_PARAMS_PARAM_PFVF_L2T_START = 0x13, 1239 FW_PARAMS_PARAM_PFVF_L2T_END = 0x14, 1240 FW_PARAMS_PARAM_PFVF_SQRQ_START = 0x15, 1241 FW_PARAMS_PARAM_PFVF_SQRQ_END = 0x16, 1242 FW_PARAMS_PARAM_PFVF_CQ_START = 0x17, 1243 FW_PARAMS_PARAM_PFVF_CQ_END = 0x18, 1244 FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20, 1245 FW_PARAMS_PARAM_PFVF_VIID = 0x24, 1246 FW_PARAMS_PARAM_PFVF_CPMASK = 0x25, 1247 FW_PARAMS_PARAM_PFVF_OCQ_START = 0x26, 1248 FW_PARAMS_PARAM_PFVF_OCQ_END = 0x27, 1249 FW_PARAMS_PARAM_PFVF_CONM_MAP = 0x28, 1250 FW_PARAMS_PARAM_PFVF_IQFLINT_START = 0x29, 1251 FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A, 1252 FW_PARAMS_PARAM_PFVF_EQ_START = 0x2B, 1253 FW_PARAMS_PARAM_PFVF_EQ_END = 0x2C, 1254 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D, 1255 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E, 1256 FW_PARAMS_PARAM_PFVF_ETHOFLD_START = 0x2F, 1257 FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30, 1258 FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31, 1259 FW_PARAMS_PARAM_PFVF_HPFILTER_START = 0x32, 1260 FW_PARAMS_PARAM_PFVF_HPFILTER_END = 0x33, 1261 FW_PARAMS_PARAM_PFVF_NCRYPTO_LOOKASIDE = 0x39, 1262 FW_PARAMS_PARAM_PFVF_PORT_CAPS32 = 0x3A, 1263 }; 1264 1265 /* 1266 * dma queue parameters 1267 */ 1268 enum fw_params_param_dmaq { 1269 FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00, 1270 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01, 1271 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10, 1272 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11, 1273 FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12, 1274 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13, 1275 FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20, 1276 }; 1277 1278 enum fw_params_param_dev_phyfw { 1279 FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD = 0x00, 1280 FW_PARAMS_PARAM_DEV_PHYFW_VERSION = 0x01, 1281 }; 1282 1283 enum fw_params_param_dev_diag { 1284 FW_PARAM_DEV_DIAG_TMP = 0x00, 1285 FW_PARAM_DEV_DIAG_VDD = 0x01, 1286 }; 1287 1288 enum fw_params_param_dev_fwcache { 1289 FW_PARAM_DEV_FWCACHE_FLUSH = 0x00, 1290 FW_PARAM_DEV_FWCACHE_FLUSHINV = 0x01, 1291 }; 1292 1293 #define FW_PARAMS_MNEM_S 24 1294 #define FW_PARAMS_MNEM_V(x) ((x) << FW_PARAMS_MNEM_S) 1295 1296 #define FW_PARAMS_PARAM_X_S 16 1297 #define FW_PARAMS_PARAM_X_V(x) ((x) << FW_PARAMS_PARAM_X_S) 1298 1299 #define FW_PARAMS_PARAM_Y_S 8 1300 #define FW_PARAMS_PARAM_Y_M 0xffU 1301 #define FW_PARAMS_PARAM_Y_V(x) ((x) << FW_PARAMS_PARAM_Y_S) 1302 #define FW_PARAMS_PARAM_Y_G(x) (((x) >> FW_PARAMS_PARAM_Y_S) &\ 1303 FW_PARAMS_PARAM_Y_M) 1304 1305 #define FW_PARAMS_PARAM_Z_S 0 1306 #define FW_PARAMS_PARAM_Z_M 0xffu 1307 #define FW_PARAMS_PARAM_Z_V(x) ((x) << FW_PARAMS_PARAM_Z_S) 1308 #define FW_PARAMS_PARAM_Z_G(x) (((x) >> FW_PARAMS_PARAM_Z_S) &\ 1309 FW_PARAMS_PARAM_Z_M) 1310 1311 #define FW_PARAMS_PARAM_XYZ_S 0 1312 #define FW_PARAMS_PARAM_XYZ_V(x) ((x) << FW_PARAMS_PARAM_XYZ_S) 1313 1314 #define FW_PARAMS_PARAM_YZ_S 0 1315 #define FW_PARAMS_PARAM_YZ_V(x) ((x) << FW_PARAMS_PARAM_YZ_S) 1316 1317 struct fw_params_cmd { 1318 __be32 op_to_vfn; 1319 __be32 retval_len16; 1320 struct fw_params_param { 1321 __be32 mnem; 1322 __be32 val; 1323 } param[7]; 1324 }; 1325 1326 #define FW_PARAMS_CMD_PFN_S 8 1327 #define FW_PARAMS_CMD_PFN_V(x) ((x) << FW_PARAMS_CMD_PFN_S) 1328 1329 #define FW_PARAMS_CMD_VFN_S 0 1330 #define FW_PARAMS_CMD_VFN_V(x) ((x) << FW_PARAMS_CMD_VFN_S) 1331 1332 struct fw_pfvf_cmd { 1333 __be32 op_to_vfn; 1334 __be32 retval_len16; 1335 __be32 niqflint_niq; 1336 __be32 type_to_neq; 1337 __be32 tc_to_nexactf; 1338 __be32 r_caps_to_nethctrl; 1339 __be16 nricq; 1340 __be16 nriqp; 1341 __be32 r4; 1342 }; 1343 1344 #define FW_PFVF_CMD_PFN_S 8 1345 #define FW_PFVF_CMD_PFN_V(x) ((x) << FW_PFVF_CMD_PFN_S) 1346 1347 #define FW_PFVF_CMD_VFN_S 0 1348 #define FW_PFVF_CMD_VFN_V(x) ((x) << FW_PFVF_CMD_VFN_S) 1349 1350 #define FW_PFVF_CMD_NIQFLINT_S 20 1351 #define FW_PFVF_CMD_NIQFLINT_M 0xfff 1352 #define FW_PFVF_CMD_NIQFLINT_V(x) ((x) << FW_PFVF_CMD_NIQFLINT_S) 1353 #define FW_PFVF_CMD_NIQFLINT_G(x) \ 1354 (((x) >> FW_PFVF_CMD_NIQFLINT_S) & FW_PFVF_CMD_NIQFLINT_M) 1355 1356 #define FW_PFVF_CMD_NIQ_S 0 1357 #define FW_PFVF_CMD_NIQ_M 0xfffff 1358 #define FW_PFVF_CMD_NIQ_V(x) ((x) << FW_PFVF_CMD_NIQ_S) 1359 #define FW_PFVF_CMD_NIQ_G(x) \ 1360 (((x) >> FW_PFVF_CMD_NIQ_S) & FW_PFVF_CMD_NIQ_M) 1361 1362 #define FW_PFVF_CMD_TYPE_S 31 1363 #define FW_PFVF_CMD_TYPE_M 0x1 1364 #define FW_PFVF_CMD_TYPE_V(x) ((x) << FW_PFVF_CMD_TYPE_S) 1365 #define FW_PFVF_CMD_TYPE_G(x) \ 1366 (((x) >> FW_PFVF_CMD_TYPE_S) & FW_PFVF_CMD_TYPE_M) 1367 #define FW_PFVF_CMD_TYPE_F FW_PFVF_CMD_TYPE_V(1U) 1368 1369 #define FW_PFVF_CMD_CMASK_S 24 1370 #define FW_PFVF_CMD_CMASK_M 0xf 1371 #define FW_PFVF_CMD_CMASK_V(x) ((x) << FW_PFVF_CMD_CMASK_S) 1372 #define FW_PFVF_CMD_CMASK_G(x) \ 1373 (((x) >> FW_PFVF_CMD_CMASK_S) & FW_PFVF_CMD_CMASK_M) 1374 1375 #define FW_PFVF_CMD_PMASK_S 20 1376 #define FW_PFVF_CMD_PMASK_M 0xf 1377 #define FW_PFVF_CMD_PMASK_V(x) ((x) << FW_PFVF_CMD_PMASK_S) 1378 #define FW_PFVF_CMD_PMASK_G(x) \ 1379 (((x) >> FW_PFVF_CMD_PMASK_S) & FW_PFVF_CMD_PMASK_M) 1380 1381 #define FW_PFVF_CMD_NEQ_S 0 1382 #define FW_PFVF_CMD_NEQ_M 0xfffff 1383 #define FW_PFVF_CMD_NEQ_V(x) ((x) << FW_PFVF_CMD_NEQ_S) 1384 #define FW_PFVF_CMD_NEQ_G(x) \ 1385 (((x) >> FW_PFVF_CMD_NEQ_S) & FW_PFVF_CMD_NEQ_M) 1386 1387 #define FW_PFVF_CMD_TC_S 24 1388 #define FW_PFVF_CMD_TC_M 0xff 1389 #define FW_PFVF_CMD_TC_V(x) ((x) << FW_PFVF_CMD_TC_S) 1390 #define FW_PFVF_CMD_TC_G(x) (((x) >> FW_PFVF_CMD_TC_S) & FW_PFVF_CMD_TC_M) 1391 1392 #define FW_PFVF_CMD_NVI_S 16 1393 #define FW_PFVF_CMD_NVI_M 0xff 1394 #define FW_PFVF_CMD_NVI_V(x) ((x) << FW_PFVF_CMD_NVI_S) 1395 #define FW_PFVF_CMD_NVI_G(x) (((x) >> FW_PFVF_CMD_NVI_S) & FW_PFVF_CMD_NVI_M) 1396 1397 #define FW_PFVF_CMD_NEXACTF_S 0 1398 #define FW_PFVF_CMD_NEXACTF_M 0xffff 1399 #define FW_PFVF_CMD_NEXACTF_V(x) ((x) << FW_PFVF_CMD_NEXACTF_S) 1400 #define FW_PFVF_CMD_NEXACTF_G(x) \ 1401 (((x) >> FW_PFVF_CMD_NEXACTF_S) & FW_PFVF_CMD_NEXACTF_M) 1402 1403 #define FW_PFVF_CMD_R_CAPS_S 24 1404 #define FW_PFVF_CMD_R_CAPS_M 0xff 1405 #define FW_PFVF_CMD_R_CAPS_V(x) ((x) << FW_PFVF_CMD_R_CAPS_S) 1406 #define FW_PFVF_CMD_R_CAPS_G(x) \ 1407 (((x) >> FW_PFVF_CMD_R_CAPS_S) & FW_PFVF_CMD_R_CAPS_M) 1408 1409 #define FW_PFVF_CMD_WX_CAPS_S 16 1410 #define FW_PFVF_CMD_WX_CAPS_M 0xff 1411 #define FW_PFVF_CMD_WX_CAPS_V(x) ((x) << FW_PFVF_CMD_WX_CAPS_S) 1412 #define FW_PFVF_CMD_WX_CAPS_G(x) \ 1413 (((x) >> FW_PFVF_CMD_WX_CAPS_S) & FW_PFVF_CMD_WX_CAPS_M) 1414 1415 #define FW_PFVF_CMD_NETHCTRL_S 0 1416 #define FW_PFVF_CMD_NETHCTRL_M 0xffff 1417 #define FW_PFVF_CMD_NETHCTRL_V(x) ((x) << FW_PFVF_CMD_NETHCTRL_S) 1418 #define FW_PFVF_CMD_NETHCTRL_G(x) \ 1419 (((x) >> FW_PFVF_CMD_NETHCTRL_S) & FW_PFVF_CMD_NETHCTRL_M) 1420 1421 enum fw_iq_type { 1422 FW_IQ_TYPE_FL_INT_CAP, 1423 FW_IQ_TYPE_NO_FL_INT_CAP 1424 }; 1425 1426 struct fw_iq_cmd { 1427 __be32 op_to_vfn; 1428 __be32 alloc_to_len16; 1429 __be16 physiqid; 1430 __be16 iqid; 1431 __be16 fl0id; 1432 __be16 fl1id; 1433 __be32 type_to_iqandstindex; 1434 __be16 iqdroprss_to_iqesize; 1435 __be16 iqsize; 1436 __be64 iqaddr; 1437 __be32 iqns_to_fl0congen; 1438 __be16 fl0dcaen_to_fl0cidxfthresh; 1439 __be16 fl0size; 1440 __be64 fl0addr; 1441 __be32 fl1cngchmap_to_fl1congen; 1442 __be16 fl1dcaen_to_fl1cidxfthresh; 1443 __be16 fl1size; 1444 __be64 fl1addr; 1445 }; 1446 1447 #define FW_IQ_CMD_PFN_S 8 1448 #define FW_IQ_CMD_PFN_V(x) ((x) << FW_IQ_CMD_PFN_S) 1449 1450 #define FW_IQ_CMD_VFN_S 0 1451 #define FW_IQ_CMD_VFN_V(x) ((x) << FW_IQ_CMD_VFN_S) 1452 1453 #define FW_IQ_CMD_ALLOC_S 31 1454 #define FW_IQ_CMD_ALLOC_V(x) ((x) << FW_IQ_CMD_ALLOC_S) 1455 #define FW_IQ_CMD_ALLOC_F FW_IQ_CMD_ALLOC_V(1U) 1456 1457 #define FW_IQ_CMD_FREE_S 30 1458 #define FW_IQ_CMD_FREE_V(x) ((x) << FW_IQ_CMD_FREE_S) 1459 #define FW_IQ_CMD_FREE_F FW_IQ_CMD_FREE_V(1U) 1460 1461 #define FW_IQ_CMD_MODIFY_S 29 1462 #define FW_IQ_CMD_MODIFY_V(x) ((x) << FW_IQ_CMD_MODIFY_S) 1463 #define FW_IQ_CMD_MODIFY_F FW_IQ_CMD_MODIFY_V(1U) 1464 1465 #define FW_IQ_CMD_IQSTART_S 28 1466 #define FW_IQ_CMD_IQSTART_V(x) ((x) << FW_IQ_CMD_IQSTART_S) 1467 #define FW_IQ_CMD_IQSTART_F FW_IQ_CMD_IQSTART_V(1U) 1468 1469 #define FW_IQ_CMD_IQSTOP_S 27 1470 #define FW_IQ_CMD_IQSTOP_V(x) ((x) << FW_IQ_CMD_IQSTOP_S) 1471 #define FW_IQ_CMD_IQSTOP_F FW_IQ_CMD_IQSTOP_V(1U) 1472 1473 #define FW_IQ_CMD_TYPE_S 29 1474 #define FW_IQ_CMD_TYPE_V(x) ((x) << FW_IQ_CMD_TYPE_S) 1475 1476 #define FW_IQ_CMD_IQASYNCH_S 28 1477 #define FW_IQ_CMD_IQASYNCH_V(x) ((x) << FW_IQ_CMD_IQASYNCH_S) 1478 1479 #define FW_IQ_CMD_VIID_S 16 1480 #define FW_IQ_CMD_VIID_V(x) ((x) << FW_IQ_CMD_VIID_S) 1481 1482 #define FW_IQ_CMD_IQANDST_S 15 1483 #define FW_IQ_CMD_IQANDST_V(x) ((x) << FW_IQ_CMD_IQANDST_S) 1484 1485 #define FW_IQ_CMD_IQANUS_S 14 1486 #define FW_IQ_CMD_IQANUS_V(x) ((x) << FW_IQ_CMD_IQANUS_S) 1487 1488 #define FW_IQ_CMD_IQANUD_S 12 1489 #define FW_IQ_CMD_IQANUD_V(x) ((x) << FW_IQ_CMD_IQANUD_S) 1490 1491 #define FW_IQ_CMD_IQANDSTINDEX_S 0 1492 #define FW_IQ_CMD_IQANDSTINDEX_V(x) ((x) << FW_IQ_CMD_IQANDSTINDEX_S) 1493 1494 #define FW_IQ_CMD_IQDROPRSS_S 15 1495 #define FW_IQ_CMD_IQDROPRSS_V(x) ((x) << FW_IQ_CMD_IQDROPRSS_S) 1496 #define FW_IQ_CMD_IQDROPRSS_F FW_IQ_CMD_IQDROPRSS_V(1U) 1497 1498 #define FW_IQ_CMD_IQGTSMODE_S 14 1499 #define FW_IQ_CMD_IQGTSMODE_V(x) ((x) << FW_IQ_CMD_IQGTSMODE_S) 1500 #define FW_IQ_CMD_IQGTSMODE_F FW_IQ_CMD_IQGTSMODE_V(1U) 1501 1502 #define FW_IQ_CMD_IQPCIECH_S 12 1503 #define FW_IQ_CMD_IQPCIECH_V(x) ((x) << FW_IQ_CMD_IQPCIECH_S) 1504 1505 #define FW_IQ_CMD_IQDCAEN_S 11 1506 #define FW_IQ_CMD_IQDCAEN_V(x) ((x) << FW_IQ_CMD_IQDCAEN_S) 1507 1508 #define FW_IQ_CMD_IQDCACPU_S 6 1509 #define FW_IQ_CMD_IQDCACPU_V(x) ((x) << FW_IQ_CMD_IQDCACPU_S) 1510 1511 #define FW_IQ_CMD_IQINTCNTTHRESH_S 4 1512 #define FW_IQ_CMD_IQINTCNTTHRESH_V(x) ((x) << FW_IQ_CMD_IQINTCNTTHRESH_S) 1513 1514 #define FW_IQ_CMD_IQO_S 3 1515 #define FW_IQ_CMD_IQO_V(x) ((x) << FW_IQ_CMD_IQO_S) 1516 #define FW_IQ_CMD_IQO_F FW_IQ_CMD_IQO_V(1U) 1517 1518 #define FW_IQ_CMD_IQCPRIO_S 2 1519 #define FW_IQ_CMD_IQCPRIO_V(x) ((x) << FW_IQ_CMD_IQCPRIO_S) 1520 1521 #define FW_IQ_CMD_IQESIZE_S 0 1522 #define FW_IQ_CMD_IQESIZE_V(x) ((x) << FW_IQ_CMD_IQESIZE_S) 1523 1524 #define FW_IQ_CMD_IQNS_S 31 1525 #define FW_IQ_CMD_IQNS_V(x) ((x) << FW_IQ_CMD_IQNS_S) 1526 1527 #define FW_IQ_CMD_IQRO_S 30 1528 #define FW_IQ_CMD_IQRO_V(x) ((x) << FW_IQ_CMD_IQRO_S) 1529 1530 #define FW_IQ_CMD_IQFLINTIQHSEN_S 28 1531 #define FW_IQ_CMD_IQFLINTIQHSEN_V(x) ((x) << FW_IQ_CMD_IQFLINTIQHSEN_S) 1532 1533 #define FW_IQ_CMD_IQFLINTCONGEN_S 27 1534 #define FW_IQ_CMD_IQFLINTCONGEN_V(x) ((x) << FW_IQ_CMD_IQFLINTCONGEN_S) 1535 #define FW_IQ_CMD_IQFLINTCONGEN_F FW_IQ_CMD_IQFLINTCONGEN_V(1U) 1536 1537 #define FW_IQ_CMD_IQFLINTISCSIC_S 26 1538 #define FW_IQ_CMD_IQFLINTISCSIC_V(x) ((x) << FW_IQ_CMD_IQFLINTISCSIC_S) 1539 1540 #define FW_IQ_CMD_FL0CNGCHMAP_S 20 1541 #define FW_IQ_CMD_FL0CNGCHMAP_V(x) ((x) << FW_IQ_CMD_FL0CNGCHMAP_S) 1542 1543 #define FW_IQ_CMD_FL0CACHELOCK_S 15 1544 #define FW_IQ_CMD_FL0CACHELOCK_V(x) ((x) << FW_IQ_CMD_FL0CACHELOCK_S) 1545 1546 #define FW_IQ_CMD_FL0DBP_S 14 1547 #define FW_IQ_CMD_FL0DBP_V(x) ((x) << FW_IQ_CMD_FL0DBP_S) 1548 1549 #define FW_IQ_CMD_FL0DATANS_S 13 1550 #define FW_IQ_CMD_FL0DATANS_V(x) ((x) << FW_IQ_CMD_FL0DATANS_S) 1551 1552 #define FW_IQ_CMD_FL0DATARO_S 12 1553 #define FW_IQ_CMD_FL0DATARO_V(x) ((x) << FW_IQ_CMD_FL0DATARO_S) 1554 #define FW_IQ_CMD_FL0DATARO_F FW_IQ_CMD_FL0DATARO_V(1U) 1555 1556 #define FW_IQ_CMD_FL0CONGCIF_S 11 1557 #define FW_IQ_CMD_FL0CONGCIF_V(x) ((x) << FW_IQ_CMD_FL0CONGCIF_S) 1558 #define FW_IQ_CMD_FL0CONGCIF_F FW_IQ_CMD_FL0CONGCIF_V(1U) 1559 1560 #define FW_IQ_CMD_FL0ONCHIP_S 10 1561 #define FW_IQ_CMD_FL0ONCHIP_V(x) ((x) << FW_IQ_CMD_FL0ONCHIP_S) 1562 1563 #define FW_IQ_CMD_FL0STATUSPGNS_S 9 1564 #define FW_IQ_CMD_FL0STATUSPGNS_V(x) ((x) << FW_IQ_CMD_FL0STATUSPGNS_S) 1565 1566 #define FW_IQ_CMD_FL0STATUSPGRO_S 8 1567 #define FW_IQ_CMD_FL0STATUSPGRO_V(x) ((x) << FW_IQ_CMD_FL0STATUSPGRO_S) 1568 1569 #define FW_IQ_CMD_FL0FETCHNS_S 7 1570 #define FW_IQ_CMD_FL0FETCHNS_V(x) ((x) << FW_IQ_CMD_FL0FETCHNS_S) 1571 1572 #define FW_IQ_CMD_FL0FETCHRO_S 6 1573 #define FW_IQ_CMD_FL0FETCHRO_V(x) ((x) << FW_IQ_CMD_FL0FETCHRO_S) 1574 #define FW_IQ_CMD_FL0FETCHRO_F FW_IQ_CMD_FL0FETCHRO_V(1U) 1575 1576 #define FW_IQ_CMD_FL0HOSTFCMODE_S 4 1577 #define FW_IQ_CMD_FL0HOSTFCMODE_V(x) ((x) << FW_IQ_CMD_FL0HOSTFCMODE_S) 1578 1579 #define FW_IQ_CMD_FL0CPRIO_S 3 1580 #define FW_IQ_CMD_FL0CPRIO_V(x) ((x) << FW_IQ_CMD_FL0CPRIO_S) 1581 1582 #define FW_IQ_CMD_FL0PADEN_S 2 1583 #define FW_IQ_CMD_FL0PADEN_V(x) ((x) << FW_IQ_CMD_FL0PADEN_S) 1584 #define FW_IQ_CMD_FL0PADEN_F FW_IQ_CMD_FL0PADEN_V(1U) 1585 1586 #define FW_IQ_CMD_FL0PACKEN_S 1 1587 #define FW_IQ_CMD_FL0PACKEN_V(x) ((x) << FW_IQ_CMD_FL0PACKEN_S) 1588 #define FW_IQ_CMD_FL0PACKEN_F FW_IQ_CMD_FL0PACKEN_V(1U) 1589 1590 #define FW_IQ_CMD_FL0CONGEN_S 0 1591 #define FW_IQ_CMD_FL0CONGEN_V(x) ((x) << FW_IQ_CMD_FL0CONGEN_S) 1592 #define FW_IQ_CMD_FL0CONGEN_F FW_IQ_CMD_FL0CONGEN_V(1U) 1593 1594 #define FW_IQ_CMD_FL0DCAEN_S 15 1595 #define FW_IQ_CMD_FL0DCAEN_V(x) ((x) << FW_IQ_CMD_FL0DCAEN_S) 1596 1597 #define FW_IQ_CMD_FL0DCACPU_S 10 1598 #define FW_IQ_CMD_FL0DCACPU_V(x) ((x) << FW_IQ_CMD_FL0DCACPU_S) 1599 1600 #define FW_IQ_CMD_FL0FBMIN_S 7 1601 #define FW_IQ_CMD_FL0FBMIN_V(x) ((x) << FW_IQ_CMD_FL0FBMIN_S) 1602 1603 #define FW_IQ_CMD_FL0FBMAX_S 4 1604 #define FW_IQ_CMD_FL0FBMAX_V(x) ((x) << FW_IQ_CMD_FL0FBMAX_S) 1605 1606 #define FW_IQ_CMD_FL0CIDXFTHRESHO_S 3 1607 #define FW_IQ_CMD_FL0CIDXFTHRESHO_V(x) ((x) << FW_IQ_CMD_FL0CIDXFTHRESHO_S) 1608 #define FW_IQ_CMD_FL0CIDXFTHRESHO_F FW_IQ_CMD_FL0CIDXFTHRESHO_V(1U) 1609 1610 #define FW_IQ_CMD_FL0CIDXFTHRESH_S 0 1611 #define FW_IQ_CMD_FL0CIDXFTHRESH_V(x) ((x) << FW_IQ_CMD_FL0CIDXFTHRESH_S) 1612 1613 #define FW_IQ_CMD_FL1CNGCHMAP_S 20 1614 #define FW_IQ_CMD_FL1CNGCHMAP_V(x) ((x) << FW_IQ_CMD_FL1CNGCHMAP_S) 1615 1616 #define FW_IQ_CMD_FL1CACHELOCK_S 15 1617 #define FW_IQ_CMD_FL1CACHELOCK_V(x) ((x) << FW_IQ_CMD_FL1CACHELOCK_S) 1618 1619 #define FW_IQ_CMD_FL1DBP_S 14 1620 #define FW_IQ_CMD_FL1DBP_V(x) ((x) << FW_IQ_CMD_FL1DBP_S) 1621 1622 #define FW_IQ_CMD_FL1DATANS_S 13 1623 #define FW_IQ_CMD_FL1DATANS_V(x) ((x) << FW_IQ_CMD_FL1DATANS_S) 1624 1625 #define FW_IQ_CMD_FL1DATARO_S 12 1626 #define FW_IQ_CMD_FL1DATARO_V(x) ((x) << FW_IQ_CMD_FL1DATARO_S) 1627 1628 #define FW_IQ_CMD_FL1CONGCIF_S 11 1629 #define FW_IQ_CMD_FL1CONGCIF_V(x) ((x) << FW_IQ_CMD_FL1CONGCIF_S) 1630 1631 #define FW_IQ_CMD_FL1ONCHIP_S 10 1632 #define FW_IQ_CMD_FL1ONCHIP_V(x) ((x) << FW_IQ_CMD_FL1ONCHIP_S) 1633 1634 #define FW_IQ_CMD_FL1STATUSPGNS_S 9 1635 #define FW_IQ_CMD_FL1STATUSPGNS_V(x) ((x) << FW_IQ_CMD_FL1STATUSPGNS_S) 1636 1637 #define FW_IQ_CMD_FL1STATUSPGRO_S 8 1638 #define FW_IQ_CMD_FL1STATUSPGRO_V(x) ((x) << FW_IQ_CMD_FL1STATUSPGRO_S) 1639 1640 #define FW_IQ_CMD_FL1FETCHNS_S 7 1641 #define FW_IQ_CMD_FL1FETCHNS_V(x) ((x) << FW_IQ_CMD_FL1FETCHNS_S) 1642 1643 #define FW_IQ_CMD_FL1FETCHRO_S 6 1644 #define FW_IQ_CMD_FL1FETCHRO_V(x) ((x) << FW_IQ_CMD_FL1FETCHRO_S) 1645 1646 #define FW_IQ_CMD_FL1HOSTFCMODE_S 4 1647 #define FW_IQ_CMD_FL1HOSTFCMODE_V(x) ((x) << FW_IQ_CMD_FL1HOSTFCMODE_S) 1648 1649 #define FW_IQ_CMD_FL1CPRIO_S 3 1650 #define FW_IQ_CMD_FL1CPRIO_V(x) ((x) << FW_IQ_CMD_FL1CPRIO_S) 1651 1652 #define FW_IQ_CMD_FL1PADEN_S 2 1653 #define FW_IQ_CMD_FL1PADEN_V(x) ((x) << FW_IQ_CMD_FL1PADEN_S) 1654 #define FW_IQ_CMD_FL1PADEN_F FW_IQ_CMD_FL1PADEN_V(1U) 1655 1656 #define FW_IQ_CMD_FL1PACKEN_S 1 1657 #define FW_IQ_CMD_FL1PACKEN_V(x) ((x) << FW_IQ_CMD_FL1PACKEN_S) 1658 #define FW_IQ_CMD_FL1PACKEN_F FW_IQ_CMD_FL1PACKEN_V(1U) 1659 1660 #define FW_IQ_CMD_FL1CONGEN_S 0 1661 #define FW_IQ_CMD_FL1CONGEN_V(x) ((x) << FW_IQ_CMD_FL1CONGEN_S) 1662 #define FW_IQ_CMD_FL1CONGEN_F FW_IQ_CMD_FL1CONGEN_V(1U) 1663 1664 #define FW_IQ_CMD_FL1DCAEN_S 15 1665 #define FW_IQ_CMD_FL1DCAEN_V(x) ((x) << FW_IQ_CMD_FL1DCAEN_S) 1666 1667 #define FW_IQ_CMD_FL1DCACPU_S 10 1668 #define FW_IQ_CMD_FL1DCACPU_V(x) ((x) << FW_IQ_CMD_FL1DCACPU_S) 1669 1670 #define FW_IQ_CMD_FL1FBMIN_S 7 1671 #define FW_IQ_CMD_FL1FBMIN_V(x) ((x) << FW_IQ_CMD_FL1FBMIN_S) 1672 1673 #define FW_IQ_CMD_FL1FBMAX_S 4 1674 #define FW_IQ_CMD_FL1FBMAX_V(x) ((x) << FW_IQ_CMD_FL1FBMAX_S) 1675 1676 #define FW_IQ_CMD_FL1CIDXFTHRESHO_S 3 1677 #define FW_IQ_CMD_FL1CIDXFTHRESHO_V(x) ((x) << FW_IQ_CMD_FL1CIDXFTHRESHO_S) 1678 #define FW_IQ_CMD_FL1CIDXFTHRESHO_F FW_IQ_CMD_FL1CIDXFTHRESHO_V(1U) 1679 1680 #define FW_IQ_CMD_FL1CIDXFTHRESH_S 0 1681 #define FW_IQ_CMD_FL1CIDXFTHRESH_V(x) ((x) << FW_IQ_CMD_FL1CIDXFTHRESH_S) 1682 1683 struct fw_eq_eth_cmd { 1684 __be32 op_to_vfn; 1685 __be32 alloc_to_len16; 1686 __be32 eqid_pkd; 1687 __be32 physeqid_pkd; 1688 __be32 fetchszm_to_iqid; 1689 __be32 dcaen_to_eqsize; 1690 __be64 eqaddr; 1691 __be32 viid_pkd; 1692 __be32 r8_lo; 1693 __be64 r9; 1694 }; 1695 1696 #define FW_EQ_ETH_CMD_PFN_S 8 1697 #define FW_EQ_ETH_CMD_PFN_V(x) ((x) << FW_EQ_ETH_CMD_PFN_S) 1698 1699 #define FW_EQ_ETH_CMD_VFN_S 0 1700 #define FW_EQ_ETH_CMD_VFN_V(x) ((x) << FW_EQ_ETH_CMD_VFN_S) 1701 1702 #define FW_EQ_ETH_CMD_ALLOC_S 31 1703 #define FW_EQ_ETH_CMD_ALLOC_V(x) ((x) << FW_EQ_ETH_CMD_ALLOC_S) 1704 #define FW_EQ_ETH_CMD_ALLOC_F FW_EQ_ETH_CMD_ALLOC_V(1U) 1705 1706 #define FW_EQ_ETH_CMD_FREE_S 30 1707 #define FW_EQ_ETH_CMD_FREE_V(x) ((x) << FW_EQ_ETH_CMD_FREE_S) 1708 #define FW_EQ_ETH_CMD_FREE_F FW_EQ_ETH_CMD_FREE_V(1U) 1709 1710 #define FW_EQ_ETH_CMD_MODIFY_S 29 1711 #define FW_EQ_ETH_CMD_MODIFY_V(x) ((x) << FW_EQ_ETH_CMD_MODIFY_S) 1712 #define FW_EQ_ETH_CMD_MODIFY_F FW_EQ_ETH_CMD_MODIFY_V(1U) 1713 1714 #define FW_EQ_ETH_CMD_EQSTART_S 28 1715 #define FW_EQ_ETH_CMD_EQSTART_V(x) ((x) << FW_EQ_ETH_CMD_EQSTART_S) 1716 #define FW_EQ_ETH_CMD_EQSTART_F FW_EQ_ETH_CMD_EQSTART_V(1U) 1717 1718 #define FW_EQ_ETH_CMD_EQSTOP_S 27 1719 #define FW_EQ_ETH_CMD_EQSTOP_V(x) ((x) << FW_EQ_ETH_CMD_EQSTOP_S) 1720 #define FW_EQ_ETH_CMD_EQSTOP_F FW_EQ_ETH_CMD_EQSTOP_V(1U) 1721 1722 #define FW_EQ_ETH_CMD_EQID_S 0 1723 #define FW_EQ_ETH_CMD_EQID_M 0xfffff 1724 #define FW_EQ_ETH_CMD_EQID_V(x) ((x) << FW_EQ_ETH_CMD_EQID_S) 1725 #define FW_EQ_ETH_CMD_EQID_G(x) \ 1726 (((x) >> FW_EQ_ETH_CMD_EQID_S) & FW_EQ_ETH_CMD_EQID_M) 1727 1728 #define FW_EQ_ETH_CMD_PHYSEQID_S 0 1729 #define FW_EQ_ETH_CMD_PHYSEQID_M 0xfffff 1730 #define FW_EQ_ETH_CMD_PHYSEQID_V(x) ((x) << FW_EQ_ETH_CMD_PHYSEQID_S) 1731 #define FW_EQ_ETH_CMD_PHYSEQID_G(x) \ 1732 (((x) >> FW_EQ_ETH_CMD_PHYSEQID_S) & FW_EQ_ETH_CMD_PHYSEQID_M) 1733 1734 #define FW_EQ_ETH_CMD_FETCHSZM_S 26 1735 #define FW_EQ_ETH_CMD_FETCHSZM_V(x) ((x) << FW_EQ_ETH_CMD_FETCHSZM_S) 1736 #define FW_EQ_ETH_CMD_FETCHSZM_F FW_EQ_ETH_CMD_FETCHSZM_V(1U) 1737 1738 #define FW_EQ_ETH_CMD_STATUSPGNS_S 25 1739 #define FW_EQ_ETH_CMD_STATUSPGNS_V(x) ((x) << FW_EQ_ETH_CMD_STATUSPGNS_S) 1740 1741 #define FW_EQ_ETH_CMD_STATUSPGRO_S 24 1742 #define FW_EQ_ETH_CMD_STATUSPGRO_V(x) ((x) << FW_EQ_ETH_CMD_STATUSPGRO_S) 1743 1744 #define FW_EQ_ETH_CMD_FETCHNS_S 23 1745 #define FW_EQ_ETH_CMD_FETCHNS_V(x) ((x) << FW_EQ_ETH_CMD_FETCHNS_S) 1746 1747 #define FW_EQ_ETH_CMD_FETCHRO_S 22 1748 #define FW_EQ_ETH_CMD_FETCHRO_V(x) ((x) << FW_EQ_ETH_CMD_FETCHRO_S) 1749 #define FW_EQ_ETH_CMD_FETCHRO_F FW_EQ_ETH_CMD_FETCHRO_V(1U) 1750 1751 #define FW_EQ_ETH_CMD_HOSTFCMODE_S 20 1752 #define FW_EQ_ETH_CMD_HOSTFCMODE_V(x) ((x) << FW_EQ_ETH_CMD_HOSTFCMODE_S) 1753 1754 #define FW_EQ_ETH_CMD_CPRIO_S 19 1755 #define FW_EQ_ETH_CMD_CPRIO_V(x) ((x) << FW_EQ_ETH_CMD_CPRIO_S) 1756 1757 #define FW_EQ_ETH_CMD_ONCHIP_S 18 1758 #define FW_EQ_ETH_CMD_ONCHIP_V(x) ((x) << FW_EQ_ETH_CMD_ONCHIP_S) 1759 1760 #define FW_EQ_ETH_CMD_PCIECHN_S 16 1761 #define FW_EQ_ETH_CMD_PCIECHN_V(x) ((x) << FW_EQ_ETH_CMD_PCIECHN_S) 1762 1763 #define FW_EQ_ETH_CMD_IQID_S 0 1764 #define FW_EQ_ETH_CMD_IQID_V(x) ((x) << FW_EQ_ETH_CMD_IQID_S) 1765 1766 #define FW_EQ_ETH_CMD_DCAEN_S 31 1767 #define FW_EQ_ETH_CMD_DCAEN_V(x) ((x) << FW_EQ_ETH_CMD_DCAEN_S) 1768 1769 #define FW_EQ_ETH_CMD_DCACPU_S 26 1770 #define FW_EQ_ETH_CMD_DCACPU_V(x) ((x) << FW_EQ_ETH_CMD_DCACPU_S) 1771 1772 #define FW_EQ_ETH_CMD_FBMIN_S 23 1773 #define FW_EQ_ETH_CMD_FBMIN_V(x) ((x) << FW_EQ_ETH_CMD_FBMIN_S) 1774 1775 #define FW_EQ_ETH_CMD_FBMAX_S 20 1776 #define FW_EQ_ETH_CMD_FBMAX_V(x) ((x) << FW_EQ_ETH_CMD_FBMAX_S) 1777 1778 #define FW_EQ_ETH_CMD_CIDXFTHRESHO_S 19 1779 #define FW_EQ_ETH_CMD_CIDXFTHRESHO_V(x) ((x) << FW_EQ_ETH_CMD_CIDXFTHRESHO_S) 1780 1781 #define FW_EQ_ETH_CMD_CIDXFTHRESH_S 16 1782 #define FW_EQ_ETH_CMD_CIDXFTHRESH_V(x) ((x) << FW_EQ_ETH_CMD_CIDXFTHRESH_S) 1783 1784 #define FW_EQ_ETH_CMD_EQSIZE_S 0 1785 #define FW_EQ_ETH_CMD_EQSIZE_V(x) ((x) << FW_EQ_ETH_CMD_EQSIZE_S) 1786 1787 #define FW_EQ_ETH_CMD_AUTOEQUEQE_S 30 1788 #define FW_EQ_ETH_CMD_AUTOEQUEQE_V(x) ((x) << FW_EQ_ETH_CMD_AUTOEQUEQE_S) 1789 #define FW_EQ_ETH_CMD_AUTOEQUEQE_F FW_EQ_ETH_CMD_AUTOEQUEQE_V(1U) 1790 1791 #define FW_EQ_ETH_CMD_VIID_S 16 1792 #define FW_EQ_ETH_CMD_VIID_V(x) ((x) << FW_EQ_ETH_CMD_VIID_S) 1793 1794 struct fw_eq_ctrl_cmd { 1795 __be32 op_to_vfn; 1796 __be32 alloc_to_len16; 1797 __be32 cmpliqid_eqid; 1798 __be32 physeqid_pkd; 1799 __be32 fetchszm_to_iqid; 1800 __be32 dcaen_to_eqsize; 1801 __be64 eqaddr; 1802 }; 1803 1804 #define FW_EQ_CTRL_CMD_PFN_S 8 1805 #define FW_EQ_CTRL_CMD_PFN_V(x) ((x) << FW_EQ_CTRL_CMD_PFN_S) 1806 1807 #define FW_EQ_CTRL_CMD_VFN_S 0 1808 #define FW_EQ_CTRL_CMD_VFN_V(x) ((x) << FW_EQ_CTRL_CMD_VFN_S) 1809 1810 #define FW_EQ_CTRL_CMD_ALLOC_S 31 1811 #define FW_EQ_CTRL_CMD_ALLOC_V(x) ((x) << FW_EQ_CTRL_CMD_ALLOC_S) 1812 #define FW_EQ_CTRL_CMD_ALLOC_F FW_EQ_CTRL_CMD_ALLOC_V(1U) 1813 1814 #define FW_EQ_CTRL_CMD_FREE_S 30 1815 #define FW_EQ_CTRL_CMD_FREE_V(x) ((x) << FW_EQ_CTRL_CMD_FREE_S) 1816 #define FW_EQ_CTRL_CMD_FREE_F FW_EQ_CTRL_CMD_FREE_V(1U) 1817 1818 #define FW_EQ_CTRL_CMD_MODIFY_S 29 1819 #define FW_EQ_CTRL_CMD_MODIFY_V(x) ((x) << FW_EQ_CTRL_CMD_MODIFY_S) 1820 #define FW_EQ_CTRL_CMD_MODIFY_F FW_EQ_CTRL_CMD_MODIFY_V(1U) 1821 1822 #define FW_EQ_CTRL_CMD_EQSTART_S 28 1823 #define FW_EQ_CTRL_CMD_EQSTART_V(x) ((x) << FW_EQ_CTRL_CMD_EQSTART_S) 1824 #define FW_EQ_CTRL_CMD_EQSTART_F FW_EQ_CTRL_CMD_EQSTART_V(1U) 1825 1826 #define FW_EQ_CTRL_CMD_EQSTOP_S 27 1827 #define FW_EQ_CTRL_CMD_EQSTOP_V(x) ((x) << FW_EQ_CTRL_CMD_EQSTOP_S) 1828 #define FW_EQ_CTRL_CMD_EQSTOP_F FW_EQ_CTRL_CMD_EQSTOP_V(1U) 1829 1830 #define FW_EQ_CTRL_CMD_CMPLIQID_S 20 1831 #define FW_EQ_CTRL_CMD_CMPLIQID_V(x) ((x) << FW_EQ_CTRL_CMD_CMPLIQID_S) 1832 1833 #define FW_EQ_CTRL_CMD_EQID_S 0 1834 #define FW_EQ_CTRL_CMD_EQID_M 0xfffff 1835 #define FW_EQ_CTRL_CMD_EQID_V(x) ((x) << FW_EQ_CTRL_CMD_EQID_S) 1836 #define FW_EQ_CTRL_CMD_EQID_G(x) \ 1837 (((x) >> FW_EQ_CTRL_CMD_EQID_S) & FW_EQ_CTRL_CMD_EQID_M) 1838 1839 #define FW_EQ_CTRL_CMD_PHYSEQID_S 0 1840 #define FW_EQ_CTRL_CMD_PHYSEQID_M 0xfffff 1841 #define FW_EQ_CTRL_CMD_PHYSEQID_G(x) \ 1842 (((x) >> FW_EQ_CTRL_CMD_PHYSEQID_S) & FW_EQ_CTRL_CMD_PHYSEQID_M) 1843 1844 #define FW_EQ_CTRL_CMD_FETCHSZM_S 26 1845 #define FW_EQ_CTRL_CMD_FETCHSZM_V(x) ((x) << FW_EQ_CTRL_CMD_FETCHSZM_S) 1846 #define FW_EQ_CTRL_CMD_FETCHSZM_F FW_EQ_CTRL_CMD_FETCHSZM_V(1U) 1847 1848 #define FW_EQ_CTRL_CMD_STATUSPGNS_S 25 1849 #define FW_EQ_CTRL_CMD_STATUSPGNS_V(x) ((x) << FW_EQ_CTRL_CMD_STATUSPGNS_S) 1850 #define FW_EQ_CTRL_CMD_STATUSPGNS_F FW_EQ_CTRL_CMD_STATUSPGNS_V(1U) 1851 1852 #define FW_EQ_CTRL_CMD_STATUSPGRO_S 24 1853 #define FW_EQ_CTRL_CMD_STATUSPGRO_V(x) ((x) << FW_EQ_CTRL_CMD_STATUSPGRO_S) 1854 #define FW_EQ_CTRL_CMD_STATUSPGRO_F FW_EQ_CTRL_CMD_STATUSPGRO_V(1U) 1855 1856 #define FW_EQ_CTRL_CMD_FETCHNS_S 23 1857 #define FW_EQ_CTRL_CMD_FETCHNS_V(x) ((x) << FW_EQ_CTRL_CMD_FETCHNS_S) 1858 #define FW_EQ_CTRL_CMD_FETCHNS_F FW_EQ_CTRL_CMD_FETCHNS_V(1U) 1859 1860 #define FW_EQ_CTRL_CMD_FETCHRO_S 22 1861 #define FW_EQ_CTRL_CMD_FETCHRO_V(x) ((x) << FW_EQ_CTRL_CMD_FETCHRO_S) 1862 #define FW_EQ_CTRL_CMD_FETCHRO_F FW_EQ_CTRL_CMD_FETCHRO_V(1U) 1863 1864 #define FW_EQ_CTRL_CMD_HOSTFCMODE_S 20 1865 #define FW_EQ_CTRL_CMD_HOSTFCMODE_V(x) ((x) << FW_EQ_CTRL_CMD_HOSTFCMODE_S) 1866 1867 #define FW_EQ_CTRL_CMD_CPRIO_S 19 1868 #define FW_EQ_CTRL_CMD_CPRIO_V(x) ((x) << FW_EQ_CTRL_CMD_CPRIO_S) 1869 1870 #define FW_EQ_CTRL_CMD_ONCHIP_S 18 1871 #define FW_EQ_CTRL_CMD_ONCHIP_V(x) ((x) << FW_EQ_CTRL_CMD_ONCHIP_S) 1872 1873 #define FW_EQ_CTRL_CMD_PCIECHN_S 16 1874 #define FW_EQ_CTRL_CMD_PCIECHN_V(x) ((x) << FW_EQ_CTRL_CMD_PCIECHN_S) 1875 1876 #define FW_EQ_CTRL_CMD_IQID_S 0 1877 #define FW_EQ_CTRL_CMD_IQID_V(x) ((x) << FW_EQ_CTRL_CMD_IQID_S) 1878 1879 #define FW_EQ_CTRL_CMD_DCAEN_S 31 1880 #define FW_EQ_CTRL_CMD_DCAEN_V(x) ((x) << FW_EQ_CTRL_CMD_DCAEN_S) 1881 1882 #define FW_EQ_CTRL_CMD_DCACPU_S 26 1883 #define FW_EQ_CTRL_CMD_DCACPU_V(x) ((x) << FW_EQ_CTRL_CMD_DCACPU_S) 1884 1885 #define FW_EQ_CTRL_CMD_FBMIN_S 23 1886 #define FW_EQ_CTRL_CMD_FBMIN_V(x) ((x) << FW_EQ_CTRL_CMD_FBMIN_S) 1887 1888 #define FW_EQ_CTRL_CMD_FBMAX_S 20 1889 #define FW_EQ_CTRL_CMD_FBMAX_V(x) ((x) << FW_EQ_CTRL_CMD_FBMAX_S) 1890 1891 #define FW_EQ_CTRL_CMD_CIDXFTHRESHO_S 19 1892 #define FW_EQ_CTRL_CMD_CIDXFTHRESHO_V(x) \ 1893 ((x) << FW_EQ_CTRL_CMD_CIDXFTHRESHO_S) 1894 1895 #define FW_EQ_CTRL_CMD_CIDXFTHRESH_S 16 1896 #define FW_EQ_CTRL_CMD_CIDXFTHRESH_V(x) ((x) << FW_EQ_CTRL_CMD_CIDXFTHRESH_S) 1897 1898 #define FW_EQ_CTRL_CMD_EQSIZE_S 0 1899 #define FW_EQ_CTRL_CMD_EQSIZE_V(x) ((x) << FW_EQ_CTRL_CMD_EQSIZE_S) 1900 1901 struct fw_eq_ofld_cmd { 1902 __be32 op_to_vfn; 1903 __be32 alloc_to_len16; 1904 __be32 eqid_pkd; 1905 __be32 physeqid_pkd; 1906 __be32 fetchszm_to_iqid; 1907 __be32 dcaen_to_eqsize; 1908 __be64 eqaddr; 1909 }; 1910 1911 #define FW_EQ_OFLD_CMD_PFN_S 8 1912 #define FW_EQ_OFLD_CMD_PFN_V(x) ((x) << FW_EQ_OFLD_CMD_PFN_S) 1913 1914 #define FW_EQ_OFLD_CMD_VFN_S 0 1915 #define FW_EQ_OFLD_CMD_VFN_V(x) ((x) << FW_EQ_OFLD_CMD_VFN_S) 1916 1917 #define FW_EQ_OFLD_CMD_ALLOC_S 31 1918 #define FW_EQ_OFLD_CMD_ALLOC_V(x) ((x) << FW_EQ_OFLD_CMD_ALLOC_S) 1919 #define FW_EQ_OFLD_CMD_ALLOC_F FW_EQ_OFLD_CMD_ALLOC_V(1U) 1920 1921 #define FW_EQ_OFLD_CMD_FREE_S 30 1922 #define FW_EQ_OFLD_CMD_FREE_V(x) ((x) << FW_EQ_OFLD_CMD_FREE_S) 1923 #define FW_EQ_OFLD_CMD_FREE_F FW_EQ_OFLD_CMD_FREE_V(1U) 1924 1925 #define FW_EQ_OFLD_CMD_MODIFY_S 29 1926 #define FW_EQ_OFLD_CMD_MODIFY_V(x) ((x) << FW_EQ_OFLD_CMD_MODIFY_S) 1927 #define FW_EQ_OFLD_CMD_MODIFY_F FW_EQ_OFLD_CMD_MODIFY_V(1U) 1928 1929 #define FW_EQ_OFLD_CMD_EQSTART_S 28 1930 #define FW_EQ_OFLD_CMD_EQSTART_V(x) ((x) << FW_EQ_OFLD_CMD_EQSTART_S) 1931 #define FW_EQ_OFLD_CMD_EQSTART_F FW_EQ_OFLD_CMD_EQSTART_V(1U) 1932 1933 #define FW_EQ_OFLD_CMD_EQSTOP_S 27 1934 #define FW_EQ_OFLD_CMD_EQSTOP_V(x) ((x) << FW_EQ_OFLD_CMD_EQSTOP_S) 1935 #define FW_EQ_OFLD_CMD_EQSTOP_F FW_EQ_OFLD_CMD_EQSTOP_V(1U) 1936 1937 #define FW_EQ_OFLD_CMD_EQID_S 0 1938 #define FW_EQ_OFLD_CMD_EQID_M 0xfffff 1939 #define FW_EQ_OFLD_CMD_EQID_V(x) ((x) << FW_EQ_OFLD_CMD_EQID_S) 1940 #define FW_EQ_OFLD_CMD_EQID_G(x) \ 1941 (((x) >> FW_EQ_OFLD_CMD_EQID_S) & FW_EQ_OFLD_CMD_EQID_M) 1942 1943 #define FW_EQ_OFLD_CMD_PHYSEQID_S 0 1944 #define FW_EQ_OFLD_CMD_PHYSEQID_M 0xfffff 1945 #define FW_EQ_OFLD_CMD_PHYSEQID_G(x) \ 1946 (((x) >> FW_EQ_OFLD_CMD_PHYSEQID_S) & FW_EQ_OFLD_CMD_PHYSEQID_M) 1947 1948 #define FW_EQ_OFLD_CMD_FETCHSZM_S 26 1949 #define FW_EQ_OFLD_CMD_FETCHSZM_V(x) ((x) << FW_EQ_OFLD_CMD_FETCHSZM_S) 1950 1951 #define FW_EQ_OFLD_CMD_STATUSPGNS_S 25 1952 #define FW_EQ_OFLD_CMD_STATUSPGNS_V(x) ((x) << FW_EQ_OFLD_CMD_STATUSPGNS_S) 1953 1954 #define FW_EQ_OFLD_CMD_STATUSPGRO_S 24 1955 #define FW_EQ_OFLD_CMD_STATUSPGRO_V(x) ((x) << FW_EQ_OFLD_CMD_STATUSPGRO_S) 1956 1957 #define FW_EQ_OFLD_CMD_FETCHNS_S 23 1958 #define FW_EQ_OFLD_CMD_FETCHNS_V(x) ((x) << FW_EQ_OFLD_CMD_FETCHNS_S) 1959 1960 #define FW_EQ_OFLD_CMD_FETCHRO_S 22 1961 #define FW_EQ_OFLD_CMD_FETCHRO_V(x) ((x) << FW_EQ_OFLD_CMD_FETCHRO_S) 1962 #define FW_EQ_OFLD_CMD_FETCHRO_F FW_EQ_OFLD_CMD_FETCHRO_V(1U) 1963 1964 #define FW_EQ_OFLD_CMD_HOSTFCMODE_S 20 1965 #define FW_EQ_OFLD_CMD_HOSTFCMODE_V(x) ((x) << FW_EQ_OFLD_CMD_HOSTFCMODE_S) 1966 1967 #define FW_EQ_OFLD_CMD_CPRIO_S 19 1968 #define FW_EQ_OFLD_CMD_CPRIO_V(x) ((x) << FW_EQ_OFLD_CMD_CPRIO_S) 1969 1970 #define FW_EQ_OFLD_CMD_ONCHIP_S 18 1971 #define FW_EQ_OFLD_CMD_ONCHIP_V(x) ((x) << FW_EQ_OFLD_CMD_ONCHIP_S) 1972 1973 #define FW_EQ_OFLD_CMD_PCIECHN_S 16 1974 #define FW_EQ_OFLD_CMD_PCIECHN_V(x) ((x) << FW_EQ_OFLD_CMD_PCIECHN_S) 1975 1976 #define FW_EQ_OFLD_CMD_IQID_S 0 1977 #define FW_EQ_OFLD_CMD_IQID_V(x) ((x) << FW_EQ_OFLD_CMD_IQID_S) 1978 1979 #define FW_EQ_OFLD_CMD_DCAEN_S 31 1980 #define FW_EQ_OFLD_CMD_DCAEN_V(x) ((x) << FW_EQ_OFLD_CMD_DCAEN_S) 1981 1982 #define FW_EQ_OFLD_CMD_DCACPU_S 26 1983 #define FW_EQ_OFLD_CMD_DCACPU_V(x) ((x) << FW_EQ_OFLD_CMD_DCACPU_S) 1984 1985 #define FW_EQ_OFLD_CMD_FBMIN_S 23 1986 #define FW_EQ_OFLD_CMD_FBMIN_V(x) ((x) << FW_EQ_OFLD_CMD_FBMIN_S) 1987 1988 #define FW_EQ_OFLD_CMD_FBMAX_S 20 1989 #define FW_EQ_OFLD_CMD_FBMAX_V(x) ((x) << FW_EQ_OFLD_CMD_FBMAX_S) 1990 1991 #define FW_EQ_OFLD_CMD_CIDXFTHRESHO_S 19 1992 #define FW_EQ_OFLD_CMD_CIDXFTHRESHO_V(x) \ 1993 ((x) << FW_EQ_OFLD_CMD_CIDXFTHRESHO_S) 1994 1995 #define FW_EQ_OFLD_CMD_CIDXFTHRESH_S 16 1996 #define FW_EQ_OFLD_CMD_CIDXFTHRESH_V(x) ((x) << FW_EQ_OFLD_CMD_CIDXFTHRESH_S) 1997 1998 #define FW_EQ_OFLD_CMD_EQSIZE_S 0 1999 #define FW_EQ_OFLD_CMD_EQSIZE_V(x) ((x) << FW_EQ_OFLD_CMD_EQSIZE_S) 2000 2001 /* 2002 * Macros for VIID parsing: 2003 * VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number 2004 */ 2005 2006 #define FW_VIID_PFN_S 8 2007 #define FW_VIID_PFN_M 0x7 2008 #define FW_VIID_PFN_G(x) (((x) >> FW_VIID_PFN_S) & FW_VIID_PFN_M) 2009 2010 #define FW_VIID_VIVLD_S 7 2011 #define FW_VIID_VIVLD_M 0x1 2012 #define FW_VIID_VIVLD_G(x) (((x) >> FW_VIID_VIVLD_S) & FW_VIID_VIVLD_M) 2013 2014 #define FW_VIID_VIN_S 0 2015 #define FW_VIID_VIN_M 0x7F 2016 #define FW_VIID_VIN_G(x) (((x) >> FW_VIID_VIN_S) & FW_VIID_VIN_M) 2017 2018 struct fw_vi_cmd { 2019 __be32 op_to_vfn; 2020 __be32 alloc_to_len16; 2021 __be16 type_viid; 2022 u8 mac[6]; 2023 u8 portid_pkd; 2024 u8 nmac; 2025 u8 nmac0[6]; 2026 __be16 rsssize_pkd; 2027 u8 nmac1[6]; 2028 __be16 idsiiq_pkd; 2029 u8 nmac2[6]; 2030 __be16 idseiq_pkd; 2031 u8 nmac3[6]; 2032 __be64 r9; 2033 __be64 r10; 2034 }; 2035 2036 #define FW_VI_CMD_PFN_S 8 2037 #define FW_VI_CMD_PFN_V(x) ((x) << FW_VI_CMD_PFN_S) 2038 2039 #define FW_VI_CMD_VFN_S 0 2040 #define FW_VI_CMD_VFN_V(x) ((x) << FW_VI_CMD_VFN_S) 2041 2042 #define FW_VI_CMD_ALLOC_S 31 2043 #define FW_VI_CMD_ALLOC_V(x) ((x) << FW_VI_CMD_ALLOC_S) 2044 #define FW_VI_CMD_ALLOC_F FW_VI_CMD_ALLOC_V(1U) 2045 2046 #define FW_VI_CMD_FREE_S 30 2047 #define FW_VI_CMD_FREE_V(x) ((x) << FW_VI_CMD_FREE_S) 2048 #define FW_VI_CMD_FREE_F FW_VI_CMD_FREE_V(1U) 2049 2050 #define FW_VI_CMD_VIID_S 0 2051 #define FW_VI_CMD_VIID_M 0xfff 2052 #define FW_VI_CMD_VIID_V(x) ((x) << FW_VI_CMD_VIID_S) 2053 #define FW_VI_CMD_VIID_G(x) (((x) >> FW_VI_CMD_VIID_S) & FW_VI_CMD_VIID_M) 2054 2055 #define FW_VI_CMD_PORTID_S 4 2056 #define FW_VI_CMD_PORTID_M 0xf 2057 #define FW_VI_CMD_PORTID_V(x) ((x) << FW_VI_CMD_PORTID_S) 2058 #define FW_VI_CMD_PORTID_G(x) \ 2059 (((x) >> FW_VI_CMD_PORTID_S) & FW_VI_CMD_PORTID_M) 2060 2061 #define FW_VI_CMD_RSSSIZE_S 0 2062 #define FW_VI_CMD_RSSSIZE_M 0x7ff 2063 #define FW_VI_CMD_RSSSIZE_G(x) \ 2064 (((x) >> FW_VI_CMD_RSSSIZE_S) & FW_VI_CMD_RSSSIZE_M) 2065 2066 /* Special VI_MAC command index ids */ 2067 #define FW_VI_MAC_ADD_MAC 0x3FF 2068 #define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE 2069 #define FW_VI_MAC_MAC_BASED_FREE 0x3FD 2070 #define FW_VI_MAC_ID_BASED_FREE 0x3FC 2071 #define FW_CLS_TCAM_NUM_ENTRIES 336 2072 2073 enum fw_vi_mac_smac { 2074 FW_VI_MAC_MPS_TCAM_ENTRY, 2075 FW_VI_MAC_MPS_TCAM_ONLY, 2076 FW_VI_MAC_SMT_ONLY, 2077 FW_VI_MAC_SMT_AND_MPSTCAM 2078 }; 2079 2080 enum fw_vi_mac_result { 2081 FW_VI_MAC_R_SUCCESS, 2082 FW_VI_MAC_R_F_NONEXISTENT_NOMEM, 2083 FW_VI_MAC_R_SMAC_FAIL, 2084 FW_VI_MAC_R_F_ACL_CHECK 2085 }; 2086 2087 enum fw_vi_mac_entry_types { 2088 FW_VI_MAC_TYPE_EXACTMAC, 2089 FW_VI_MAC_TYPE_HASHVEC, 2090 FW_VI_MAC_TYPE_RAW, 2091 FW_VI_MAC_TYPE_EXACTMAC_VNI, 2092 }; 2093 2094 struct fw_vi_mac_cmd { 2095 __be32 op_to_viid; 2096 __be32 freemacs_to_len16; 2097 union fw_vi_mac { 2098 struct fw_vi_mac_exact { 2099 __be16 valid_to_idx; 2100 u8 macaddr[6]; 2101 } exact[7]; 2102 struct fw_vi_mac_hash { 2103 __be64 hashvec; 2104 } hash; 2105 struct fw_vi_mac_raw { 2106 __be32 raw_idx_pkd; 2107 __be32 data0_pkd; 2108 __be32 data1[2]; 2109 __be64 data0m_pkd; 2110 __be32 data1m[2]; 2111 } raw; 2112 } u; 2113 }; 2114 2115 #define FW_VI_MAC_CMD_VIID_S 0 2116 #define FW_VI_MAC_CMD_VIID_V(x) ((x) << FW_VI_MAC_CMD_VIID_S) 2117 2118 #define FW_VI_MAC_CMD_FREEMACS_S 31 2119 #define FW_VI_MAC_CMD_FREEMACS_V(x) ((x) << FW_VI_MAC_CMD_FREEMACS_S) 2120 2121 #define FW_VI_MAC_CMD_ENTRY_TYPE_S 23 2122 #define FW_VI_MAC_CMD_ENTRY_TYPE_M 0x7 2123 #define FW_VI_MAC_CMD_ENTRY_TYPE_V(x) ((x) << FW_VI_MAC_CMD_ENTRY_TYPE_S) 2124 #define FW_VI_MAC_CMD_ENTRY_TYPE_G(x) \ 2125 (((x) >> FW_VI_MAC_CMD_ENTRY_TYPE_S) & FW_VI_MAC_CMD_ENTRY_TYPE_M) 2126 2127 #define FW_VI_MAC_CMD_HASHVECEN_S 23 2128 #define FW_VI_MAC_CMD_HASHVECEN_V(x) ((x) << FW_VI_MAC_CMD_HASHVECEN_S) 2129 #define FW_VI_MAC_CMD_HASHVECEN_F FW_VI_MAC_CMD_HASHVECEN_V(1U) 2130 2131 #define FW_VI_MAC_CMD_HASHUNIEN_S 22 2132 #define FW_VI_MAC_CMD_HASHUNIEN_V(x) ((x) << FW_VI_MAC_CMD_HASHUNIEN_S) 2133 2134 #define FW_VI_MAC_CMD_VALID_S 15 2135 #define FW_VI_MAC_CMD_VALID_V(x) ((x) << FW_VI_MAC_CMD_VALID_S) 2136 #define FW_VI_MAC_CMD_VALID_F FW_VI_MAC_CMD_VALID_V(1U) 2137 2138 #define FW_VI_MAC_CMD_PRIO_S 12 2139 #define FW_VI_MAC_CMD_PRIO_V(x) ((x) << FW_VI_MAC_CMD_PRIO_S) 2140 2141 #define FW_VI_MAC_CMD_SMAC_RESULT_S 10 2142 #define FW_VI_MAC_CMD_SMAC_RESULT_M 0x3 2143 #define FW_VI_MAC_CMD_SMAC_RESULT_V(x) ((x) << FW_VI_MAC_CMD_SMAC_RESULT_S) 2144 #define FW_VI_MAC_CMD_SMAC_RESULT_G(x) \ 2145 (((x) >> FW_VI_MAC_CMD_SMAC_RESULT_S) & FW_VI_MAC_CMD_SMAC_RESULT_M) 2146 2147 #define FW_VI_MAC_CMD_IDX_S 0 2148 #define FW_VI_MAC_CMD_IDX_M 0x3ff 2149 #define FW_VI_MAC_CMD_IDX_V(x) ((x) << FW_VI_MAC_CMD_IDX_S) 2150 #define FW_VI_MAC_CMD_IDX_G(x) \ 2151 (((x) >> FW_VI_MAC_CMD_IDX_S) & FW_VI_MAC_CMD_IDX_M) 2152 2153 #define FW_VI_MAC_CMD_RAW_IDX_S 16 2154 #define FW_VI_MAC_CMD_RAW_IDX_M 0xffff 2155 #define FW_VI_MAC_CMD_RAW_IDX_V(x) ((x) << FW_VI_MAC_CMD_RAW_IDX_S) 2156 #define FW_VI_MAC_CMD_RAW_IDX_G(x) \ 2157 (((x) >> FW_VI_MAC_CMD_RAW_IDX_S) & FW_VI_MAC_CMD_RAW_IDX_M) 2158 2159 #define FW_RXMODE_MTU_NO_CHG 65535 2160 2161 struct fw_vi_rxmode_cmd { 2162 __be32 op_to_viid; 2163 __be32 retval_len16; 2164 __be32 mtu_to_vlanexen; 2165 __be32 r4_lo; 2166 }; 2167 2168 #define FW_VI_RXMODE_CMD_VIID_S 0 2169 #define FW_VI_RXMODE_CMD_VIID_V(x) ((x) << FW_VI_RXMODE_CMD_VIID_S) 2170 2171 #define FW_VI_RXMODE_CMD_MTU_S 16 2172 #define FW_VI_RXMODE_CMD_MTU_M 0xffff 2173 #define FW_VI_RXMODE_CMD_MTU_V(x) ((x) << FW_VI_RXMODE_CMD_MTU_S) 2174 2175 #define FW_VI_RXMODE_CMD_PROMISCEN_S 14 2176 #define FW_VI_RXMODE_CMD_PROMISCEN_M 0x3 2177 #define FW_VI_RXMODE_CMD_PROMISCEN_V(x) ((x) << FW_VI_RXMODE_CMD_PROMISCEN_S) 2178 2179 #define FW_VI_RXMODE_CMD_ALLMULTIEN_S 12 2180 #define FW_VI_RXMODE_CMD_ALLMULTIEN_M 0x3 2181 #define FW_VI_RXMODE_CMD_ALLMULTIEN_V(x) \ 2182 ((x) << FW_VI_RXMODE_CMD_ALLMULTIEN_S) 2183 2184 #define FW_VI_RXMODE_CMD_BROADCASTEN_S 10 2185 #define FW_VI_RXMODE_CMD_BROADCASTEN_M 0x3 2186 #define FW_VI_RXMODE_CMD_BROADCASTEN_V(x) \ 2187 ((x) << FW_VI_RXMODE_CMD_BROADCASTEN_S) 2188 2189 #define FW_VI_RXMODE_CMD_VLANEXEN_S 8 2190 #define FW_VI_RXMODE_CMD_VLANEXEN_M 0x3 2191 #define FW_VI_RXMODE_CMD_VLANEXEN_V(x) ((x) << FW_VI_RXMODE_CMD_VLANEXEN_S) 2192 2193 struct fw_vi_enable_cmd { 2194 __be32 op_to_viid; 2195 __be32 ien_to_len16; 2196 __be16 blinkdur; 2197 __be16 r3; 2198 __be32 r4; 2199 }; 2200 2201 #define FW_VI_ENABLE_CMD_VIID_S 0 2202 #define FW_VI_ENABLE_CMD_VIID_V(x) ((x) << FW_VI_ENABLE_CMD_VIID_S) 2203 2204 #define FW_VI_ENABLE_CMD_IEN_S 31 2205 #define FW_VI_ENABLE_CMD_IEN_V(x) ((x) << FW_VI_ENABLE_CMD_IEN_S) 2206 2207 #define FW_VI_ENABLE_CMD_EEN_S 30 2208 #define FW_VI_ENABLE_CMD_EEN_V(x) ((x) << FW_VI_ENABLE_CMD_EEN_S) 2209 2210 #define FW_VI_ENABLE_CMD_LED_S 29 2211 #define FW_VI_ENABLE_CMD_LED_V(x) ((x) << FW_VI_ENABLE_CMD_LED_S) 2212 #define FW_VI_ENABLE_CMD_LED_F FW_VI_ENABLE_CMD_LED_V(1U) 2213 2214 #define FW_VI_ENABLE_CMD_DCB_INFO_S 28 2215 #define FW_VI_ENABLE_CMD_DCB_INFO_V(x) ((x) << FW_VI_ENABLE_CMD_DCB_INFO_S) 2216 2217 /* VI VF stats offset definitions */ 2218 #define VI_VF_NUM_STATS 16 2219 enum fw_vi_stats_vf_index { 2220 FW_VI_VF_STAT_TX_BCAST_BYTES_IX, 2221 FW_VI_VF_STAT_TX_BCAST_FRAMES_IX, 2222 FW_VI_VF_STAT_TX_MCAST_BYTES_IX, 2223 FW_VI_VF_STAT_TX_MCAST_FRAMES_IX, 2224 FW_VI_VF_STAT_TX_UCAST_BYTES_IX, 2225 FW_VI_VF_STAT_TX_UCAST_FRAMES_IX, 2226 FW_VI_VF_STAT_TX_DROP_FRAMES_IX, 2227 FW_VI_VF_STAT_TX_OFLD_BYTES_IX, 2228 FW_VI_VF_STAT_TX_OFLD_FRAMES_IX, 2229 FW_VI_VF_STAT_RX_BCAST_BYTES_IX, 2230 FW_VI_VF_STAT_RX_BCAST_FRAMES_IX, 2231 FW_VI_VF_STAT_RX_MCAST_BYTES_IX, 2232 FW_VI_VF_STAT_RX_MCAST_FRAMES_IX, 2233 FW_VI_VF_STAT_RX_UCAST_BYTES_IX, 2234 FW_VI_VF_STAT_RX_UCAST_FRAMES_IX, 2235 FW_VI_VF_STAT_RX_ERR_FRAMES_IX 2236 }; 2237 2238 /* VI PF stats offset definitions */ 2239 #define VI_PF_NUM_STATS 17 2240 enum fw_vi_stats_pf_index { 2241 FW_VI_PF_STAT_TX_BCAST_BYTES_IX, 2242 FW_VI_PF_STAT_TX_BCAST_FRAMES_IX, 2243 FW_VI_PF_STAT_TX_MCAST_BYTES_IX, 2244 FW_VI_PF_STAT_TX_MCAST_FRAMES_IX, 2245 FW_VI_PF_STAT_TX_UCAST_BYTES_IX, 2246 FW_VI_PF_STAT_TX_UCAST_FRAMES_IX, 2247 FW_VI_PF_STAT_TX_OFLD_BYTES_IX, 2248 FW_VI_PF_STAT_TX_OFLD_FRAMES_IX, 2249 FW_VI_PF_STAT_RX_BYTES_IX, 2250 FW_VI_PF_STAT_RX_FRAMES_IX, 2251 FW_VI_PF_STAT_RX_BCAST_BYTES_IX, 2252 FW_VI_PF_STAT_RX_BCAST_FRAMES_IX, 2253 FW_VI_PF_STAT_RX_MCAST_BYTES_IX, 2254 FW_VI_PF_STAT_RX_MCAST_FRAMES_IX, 2255 FW_VI_PF_STAT_RX_UCAST_BYTES_IX, 2256 FW_VI_PF_STAT_RX_UCAST_FRAMES_IX, 2257 FW_VI_PF_STAT_RX_ERR_FRAMES_IX 2258 }; 2259 2260 struct fw_vi_stats_cmd { 2261 __be32 op_to_viid; 2262 __be32 retval_len16; 2263 union fw_vi_stats { 2264 struct fw_vi_stats_ctl { 2265 __be16 nstats_ix; 2266 __be16 r6; 2267 __be32 r7; 2268 __be64 stat0; 2269 __be64 stat1; 2270 __be64 stat2; 2271 __be64 stat3; 2272 __be64 stat4; 2273 __be64 stat5; 2274 } ctl; 2275 struct fw_vi_stats_pf { 2276 __be64 tx_bcast_bytes; 2277 __be64 tx_bcast_frames; 2278 __be64 tx_mcast_bytes; 2279 __be64 tx_mcast_frames; 2280 __be64 tx_ucast_bytes; 2281 __be64 tx_ucast_frames; 2282 __be64 tx_offload_bytes; 2283 __be64 tx_offload_frames; 2284 __be64 rx_pf_bytes; 2285 __be64 rx_pf_frames; 2286 __be64 rx_bcast_bytes; 2287 __be64 rx_bcast_frames; 2288 __be64 rx_mcast_bytes; 2289 __be64 rx_mcast_frames; 2290 __be64 rx_ucast_bytes; 2291 __be64 rx_ucast_frames; 2292 __be64 rx_err_frames; 2293 } pf; 2294 struct fw_vi_stats_vf { 2295 __be64 tx_bcast_bytes; 2296 __be64 tx_bcast_frames; 2297 __be64 tx_mcast_bytes; 2298 __be64 tx_mcast_frames; 2299 __be64 tx_ucast_bytes; 2300 __be64 tx_ucast_frames; 2301 __be64 tx_drop_frames; 2302 __be64 tx_offload_bytes; 2303 __be64 tx_offload_frames; 2304 __be64 rx_bcast_bytes; 2305 __be64 rx_bcast_frames; 2306 __be64 rx_mcast_bytes; 2307 __be64 rx_mcast_frames; 2308 __be64 rx_ucast_bytes; 2309 __be64 rx_ucast_frames; 2310 __be64 rx_err_frames; 2311 } vf; 2312 } u; 2313 }; 2314 2315 #define FW_VI_STATS_CMD_VIID_S 0 2316 #define FW_VI_STATS_CMD_VIID_V(x) ((x) << FW_VI_STATS_CMD_VIID_S) 2317 2318 #define FW_VI_STATS_CMD_NSTATS_S 12 2319 #define FW_VI_STATS_CMD_NSTATS_V(x) ((x) << FW_VI_STATS_CMD_NSTATS_S) 2320 2321 #define FW_VI_STATS_CMD_IX_S 0 2322 #define FW_VI_STATS_CMD_IX_V(x) ((x) << FW_VI_STATS_CMD_IX_S) 2323 2324 struct fw_acl_mac_cmd { 2325 __be32 op_to_vfn; 2326 __be32 en_to_len16; 2327 u8 nmac; 2328 u8 r3[7]; 2329 __be16 r4; 2330 u8 macaddr0[6]; 2331 __be16 r5; 2332 u8 macaddr1[6]; 2333 __be16 r6; 2334 u8 macaddr2[6]; 2335 __be16 r7; 2336 u8 macaddr3[6]; 2337 }; 2338 2339 #define FW_ACL_MAC_CMD_PFN_S 8 2340 #define FW_ACL_MAC_CMD_PFN_V(x) ((x) << FW_ACL_MAC_CMD_PFN_S) 2341 2342 #define FW_ACL_MAC_CMD_VFN_S 0 2343 #define FW_ACL_MAC_CMD_VFN_V(x) ((x) << FW_ACL_MAC_CMD_VFN_S) 2344 2345 #define FW_ACL_MAC_CMD_EN_S 31 2346 #define FW_ACL_MAC_CMD_EN_V(x) ((x) << FW_ACL_MAC_CMD_EN_S) 2347 2348 struct fw_acl_vlan_cmd { 2349 __be32 op_to_vfn; 2350 __be32 en_to_len16; 2351 u8 nvlan; 2352 u8 dropnovlan_fm; 2353 u8 r3_lo[6]; 2354 __be16 vlanid[16]; 2355 }; 2356 2357 #define FW_ACL_VLAN_CMD_PFN_S 8 2358 #define FW_ACL_VLAN_CMD_PFN_V(x) ((x) << FW_ACL_VLAN_CMD_PFN_S) 2359 2360 #define FW_ACL_VLAN_CMD_VFN_S 0 2361 #define FW_ACL_VLAN_CMD_VFN_V(x) ((x) << FW_ACL_VLAN_CMD_VFN_S) 2362 2363 #define FW_ACL_VLAN_CMD_EN_S 31 2364 #define FW_ACL_VLAN_CMD_EN_M 0x1 2365 #define FW_ACL_VLAN_CMD_EN_V(x) ((x) << FW_ACL_VLAN_CMD_EN_S) 2366 #define FW_ACL_VLAN_CMD_EN_G(x) \ 2367 (((x) >> S_FW_ACL_VLAN_CMD_EN_S) & FW_ACL_VLAN_CMD_EN_M) 2368 #define FW_ACL_VLAN_CMD_EN_F FW_ACL_VLAN_CMD_EN_V(1U) 2369 2370 #define FW_ACL_VLAN_CMD_DROPNOVLAN_S 7 2371 #define FW_ACL_VLAN_CMD_DROPNOVLAN_V(x) ((x) << FW_ACL_VLAN_CMD_DROPNOVLAN_S) 2372 2373 #define FW_ACL_VLAN_CMD_FM_S 6 2374 #define FW_ACL_VLAN_CMD_FM_M 0x1 2375 #define FW_ACL_VLAN_CMD_FM_V(x) ((x) << FW_ACL_VLAN_CMD_FM_S) 2376 #define FW_ACL_VLAN_CMD_FM_G(x) \ 2377 (((x) >> FW_ACL_VLAN_CMD_FM_S) & FW_ACL_VLAN_CMD_FM_M) 2378 #define FW_ACL_VLAN_CMD_FM_F FW_ACL_VLAN_CMD_FM_V(1U) 2379 2380 /* old 16-bit port capabilities bitmap (fw_port_cap16_t) */ 2381 enum fw_port_cap { 2382 FW_PORT_CAP_SPEED_100M = 0x0001, 2383 FW_PORT_CAP_SPEED_1G = 0x0002, 2384 FW_PORT_CAP_SPEED_25G = 0x0004, 2385 FW_PORT_CAP_SPEED_10G = 0x0008, 2386 FW_PORT_CAP_SPEED_40G = 0x0010, 2387 FW_PORT_CAP_SPEED_100G = 0x0020, 2388 FW_PORT_CAP_FC_RX = 0x0040, 2389 FW_PORT_CAP_FC_TX = 0x0080, 2390 FW_PORT_CAP_ANEG = 0x0100, 2391 FW_PORT_CAP_MDIX = 0x0200, 2392 FW_PORT_CAP_MDIAUTO = 0x0400, 2393 FW_PORT_CAP_FEC_RS = 0x0800, 2394 FW_PORT_CAP_FEC_BASER_RS = 0x1000, 2395 FW_PORT_CAP_FEC_RESERVED = 0x2000, 2396 FW_PORT_CAP_802_3_PAUSE = 0x4000, 2397 FW_PORT_CAP_802_3_ASM_DIR = 0x8000, 2398 }; 2399 2400 #define FW_PORT_CAP_SPEED_S 0 2401 #define FW_PORT_CAP_SPEED_M 0x3f 2402 #define FW_PORT_CAP_SPEED_V(x) ((x) << FW_PORT_CAP_SPEED_S) 2403 #define FW_PORT_CAP_SPEED_G(x) \ 2404 (((x) >> FW_PORT_CAP_SPEED_S) & FW_PORT_CAP_SPEED_M) 2405 2406 enum fw_port_mdi { 2407 FW_PORT_CAP_MDI_UNCHANGED, 2408 FW_PORT_CAP_MDI_AUTO, 2409 FW_PORT_CAP_MDI_F_STRAIGHT, 2410 FW_PORT_CAP_MDI_F_CROSSOVER 2411 }; 2412 2413 #define FW_PORT_CAP_MDI_S 9 2414 #define FW_PORT_CAP_MDI_V(x) ((x) << FW_PORT_CAP_MDI_S) 2415 2416 /* new 32-bit port capabilities bitmap (fw_port_cap32_t) */ 2417 #define FW_PORT_CAP32_SPEED_100M 0x00000001UL 2418 #define FW_PORT_CAP32_SPEED_1G 0x00000002UL 2419 #define FW_PORT_CAP32_SPEED_10G 0x00000004UL 2420 #define FW_PORT_CAP32_SPEED_25G 0x00000008UL 2421 #define FW_PORT_CAP32_SPEED_40G 0x00000010UL 2422 #define FW_PORT_CAP32_SPEED_50G 0x00000020UL 2423 #define FW_PORT_CAP32_SPEED_100G 0x00000040UL 2424 #define FW_PORT_CAP32_SPEED_200G 0x00000080UL 2425 #define FW_PORT_CAP32_SPEED_400G 0x00000100UL 2426 #define FW_PORT_CAP32_SPEED_RESERVED1 0x00000200UL 2427 #define FW_PORT_CAP32_SPEED_RESERVED2 0x00000400UL 2428 #define FW_PORT_CAP32_SPEED_RESERVED3 0x00000800UL 2429 #define FW_PORT_CAP32_RESERVED1 0x0000f000UL 2430 #define FW_PORT_CAP32_FC_RX 0x00010000UL 2431 #define FW_PORT_CAP32_FC_TX 0x00020000UL 2432 #define FW_PORT_CAP32_802_3_PAUSE 0x00040000UL 2433 #define FW_PORT_CAP32_802_3_ASM_DIR 0x00080000UL 2434 #define FW_PORT_CAP32_ANEG 0x00100000UL 2435 #define FW_PORT_CAP32_MDIX 0x00200000UL 2436 #define FW_PORT_CAP32_MDIAUTO 0x00400000UL 2437 #define FW_PORT_CAP32_FEC_RS 0x00800000UL 2438 #define FW_PORT_CAP32_FEC_BASER_RS 0x01000000UL 2439 #define FW_PORT_CAP32_FEC_RESERVED1 0x02000000UL 2440 #define FW_PORT_CAP32_FEC_RESERVED2 0x04000000UL 2441 #define FW_PORT_CAP32_FEC_RESERVED3 0x08000000UL 2442 #define FW_PORT_CAP32_RESERVED2 0xf0000000UL 2443 2444 #define FW_PORT_CAP32_SPEED_S 0 2445 #define FW_PORT_CAP32_SPEED_M 0xfff 2446 #define FW_PORT_CAP32_SPEED_V(x) ((x) << FW_PORT_CAP32_SPEED_S) 2447 #define FW_PORT_CAP32_SPEED_G(x) \ 2448 (((x) >> FW_PORT_CAP32_SPEED_S) & FW_PORT_CAP32_SPEED_M) 2449 2450 #define FW_PORT_CAP32_FC_S 16 2451 #define FW_PORT_CAP32_FC_M 0x3 2452 #define FW_PORT_CAP32_FC_V(x) ((x) << FW_PORT_CAP32_FC_S) 2453 #define FW_PORT_CAP32_FC_G(x) \ 2454 (((x) >> FW_PORT_CAP32_FC_S) & FW_PORT_CAP32_FC_M) 2455 2456 #define FW_PORT_CAP32_802_3_S 18 2457 #define FW_PORT_CAP32_802_3_M 0x3 2458 #define FW_PORT_CAP32_802_3_V(x) ((x) << FW_PORT_CAP32_802_3_S) 2459 #define FW_PORT_CAP32_802_3_G(x) \ 2460 (((x) >> FW_PORT_CAP32_802_3_S) & FW_PORT_CAP32_802_3_M) 2461 2462 #define FW_PORT_CAP32_ANEG_S 20 2463 #define FW_PORT_CAP32_ANEG_M 0x1 2464 #define FW_PORT_CAP32_ANEG_V(x) ((x) << FW_PORT_CAP32_ANEG_S) 2465 #define FW_PORT_CAP32_ANEG_G(x) \ 2466 (((x) >> FW_PORT_CAP32_ANEG_S) & FW_PORT_CAP32_ANEG_M) 2467 2468 enum fw_port_mdi32 { 2469 FW_PORT_CAP32_MDI_UNCHANGED, 2470 FW_PORT_CAP32_MDI_AUTO, 2471 FW_PORT_CAP32_MDI_F_STRAIGHT, 2472 FW_PORT_CAP32_MDI_F_CROSSOVER 2473 }; 2474 2475 #define FW_PORT_CAP32_MDI_S 21 2476 #define FW_PORT_CAP32_MDI_M 3 2477 #define FW_PORT_CAP32_MDI_V(x) ((x) << FW_PORT_CAP32_MDI_S) 2478 #define FW_PORT_CAP32_MDI_G(x) \ 2479 (((x) >> FW_PORT_CAP32_MDI_S) & FW_PORT_CAP32_MDI_M) 2480 2481 #define FW_PORT_CAP32_FEC_S 23 2482 #define FW_PORT_CAP32_FEC_M 0x1f 2483 #define FW_PORT_CAP32_FEC_V(x) ((x) << FW_PORT_CAP32_FEC_S) 2484 #define FW_PORT_CAP32_FEC_G(x) \ 2485 (((x) >> FW_PORT_CAP32_FEC_S) & FW_PORT_CAP32_FEC_M) 2486 2487 /* macros to isolate various 32-bit Port Capabilities sub-fields */ 2488 #define CAP32_SPEED(__cap32) \ 2489 (FW_PORT_CAP32_SPEED_V(FW_PORT_CAP32_SPEED_M) & __cap32) 2490 2491 #define CAP32_FEC(__cap32) \ 2492 (FW_PORT_CAP32_FEC_V(FW_PORT_CAP32_FEC_M) & __cap32) 2493 2494 enum fw_port_action { 2495 FW_PORT_ACTION_L1_CFG = 0x0001, 2496 FW_PORT_ACTION_L2_CFG = 0x0002, 2497 FW_PORT_ACTION_GET_PORT_INFO = 0x0003, 2498 FW_PORT_ACTION_L2_PPP_CFG = 0x0004, 2499 FW_PORT_ACTION_L2_DCB_CFG = 0x0005, 2500 FW_PORT_ACTION_DCB_READ_TRANS = 0x0006, 2501 FW_PORT_ACTION_DCB_READ_RECV = 0x0007, 2502 FW_PORT_ACTION_DCB_READ_DET = 0x0008, 2503 FW_PORT_ACTION_L1_CFG32 = 0x0009, 2504 FW_PORT_ACTION_GET_PORT_INFO32 = 0x000a, 2505 FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010, 2506 FW_PORT_ACTION_L1_LOW_PWR_EN = 0x0011, 2507 FW_PORT_ACTION_L2_WOL_MODE_EN = 0x0012, 2508 FW_PORT_ACTION_LPBK_TO_NORMAL = 0x0020, 2509 FW_PORT_ACTION_L1_LPBK = 0x0021, 2510 FW_PORT_ACTION_L1_PMA_LPBK = 0x0022, 2511 FW_PORT_ACTION_L1_PCS_LPBK = 0x0023, 2512 FW_PORT_ACTION_L1_PHYXS_CSIDE_LPBK = 0x0024, 2513 FW_PORT_ACTION_L1_PHYXS_ESIDE_LPBK = 0x0025, 2514 FW_PORT_ACTION_PHY_RESET = 0x0040, 2515 FW_PORT_ACTION_PMA_RESET = 0x0041, 2516 FW_PORT_ACTION_PCS_RESET = 0x0042, 2517 FW_PORT_ACTION_PHYXS_RESET = 0x0043, 2518 FW_PORT_ACTION_DTEXS_REEST = 0x0044, 2519 FW_PORT_ACTION_AN_RESET = 0x0045 2520 }; 2521 2522 enum fw_port_l2cfg_ctlbf { 2523 FW_PORT_L2_CTLBF_OVLAN0 = 0x01, 2524 FW_PORT_L2_CTLBF_OVLAN1 = 0x02, 2525 FW_PORT_L2_CTLBF_OVLAN2 = 0x04, 2526 FW_PORT_L2_CTLBF_OVLAN3 = 0x08, 2527 FW_PORT_L2_CTLBF_IVLAN = 0x10, 2528 FW_PORT_L2_CTLBF_TXIPG = 0x20 2529 }; 2530 2531 enum fw_port_dcb_versions { 2532 FW_PORT_DCB_VER_UNKNOWN, 2533 FW_PORT_DCB_VER_CEE1D0, 2534 FW_PORT_DCB_VER_CEE1D01, 2535 FW_PORT_DCB_VER_IEEE, 2536 FW_PORT_DCB_VER_AUTO = 7 2537 }; 2538 2539 enum fw_port_dcb_cfg { 2540 FW_PORT_DCB_CFG_PG = 0x01, 2541 FW_PORT_DCB_CFG_PFC = 0x02, 2542 FW_PORT_DCB_CFG_APPL = 0x04 2543 }; 2544 2545 enum fw_port_dcb_cfg_rc { 2546 FW_PORT_DCB_CFG_SUCCESS = 0x0, 2547 FW_PORT_DCB_CFG_ERROR = 0x1 2548 }; 2549 2550 enum fw_port_dcb_type { 2551 FW_PORT_DCB_TYPE_PGID = 0x00, 2552 FW_PORT_DCB_TYPE_PGRATE = 0x01, 2553 FW_PORT_DCB_TYPE_PRIORATE = 0x02, 2554 FW_PORT_DCB_TYPE_PFC = 0x03, 2555 FW_PORT_DCB_TYPE_APP_ID = 0x04, 2556 FW_PORT_DCB_TYPE_CONTROL = 0x05, 2557 }; 2558 2559 enum fw_port_dcb_feature_state { 2560 FW_PORT_DCB_FEATURE_STATE_PENDING = 0x0, 2561 FW_PORT_DCB_FEATURE_STATE_SUCCESS = 0x1, 2562 FW_PORT_DCB_FEATURE_STATE_ERROR = 0x2, 2563 FW_PORT_DCB_FEATURE_STATE_TIMEOUT = 0x3, 2564 }; 2565 2566 struct fw_port_cmd { 2567 __be32 op_to_portid; 2568 __be32 action_to_len16; 2569 union fw_port { 2570 struct fw_port_l1cfg { 2571 __be32 rcap; 2572 __be32 r; 2573 } l1cfg; 2574 struct fw_port_l2cfg { 2575 __u8 ctlbf; 2576 __u8 ovlan3_to_ivlan0; 2577 __be16 ivlantype; 2578 __be16 txipg_force_pinfo; 2579 __be16 mtu; 2580 __be16 ovlan0mask; 2581 __be16 ovlan0type; 2582 __be16 ovlan1mask; 2583 __be16 ovlan1type; 2584 __be16 ovlan2mask; 2585 __be16 ovlan2type; 2586 __be16 ovlan3mask; 2587 __be16 ovlan3type; 2588 } l2cfg; 2589 struct fw_port_info { 2590 __be32 lstatus_to_modtype; 2591 __be16 pcap; 2592 __be16 acap; 2593 __be16 mtu; 2594 __u8 cbllen; 2595 __u8 auxlinfo; 2596 __u8 dcbxdis_pkd; 2597 __u8 r8_lo; 2598 __be16 lpacap; 2599 __be64 r9; 2600 } info; 2601 struct fw_port_diags { 2602 __u8 diagop; 2603 __u8 r[3]; 2604 __be32 diagval; 2605 } diags; 2606 union fw_port_dcb { 2607 struct fw_port_dcb_pgid { 2608 __u8 type; 2609 __u8 apply_pkd; 2610 __u8 r10_lo[2]; 2611 __be32 pgid; 2612 __be64 r11; 2613 } pgid; 2614 struct fw_port_dcb_pgrate { 2615 __u8 type; 2616 __u8 apply_pkd; 2617 __u8 r10_lo[5]; 2618 __u8 num_tcs_supported; 2619 __u8 pgrate[8]; 2620 __u8 tsa[8]; 2621 } pgrate; 2622 struct fw_port_dcb_priorate { 2623 __u8 type; 2624 __u8 apply_pkd; 2625 __u8 r10_lo[6]; 2626 __u8 strict_priorate[8]; 2627 } priorate; 2628 struct fw_port_dcb_pfc { 2629 __u8 type; 2630 __u8 pfcen; 2631 __u8 r10[5]; 2632 __u8 max_pfc_tcs; 2633 __be64 r11; 2634 } pfc; 2635 struct fw_port_app_priority { 2636 __u8 type; 2637 __u8 r10[2]; 2638 __u8 idx; 2639 __u8 user_prio_map; 2640 __u8 sel_field; 2641 __be16 protocolid; 2642 __be64 r12; 2643 } app_priority; 2644 struct fw_port_dcb_control { 2645 __u8 type; 2646 __u8 all_syncd_pkd; 2647 __be16 dcb_version_to_app_state; 2648 __be32 r11; 2649 __be64 r12; 2650 } control; 2651 } dcb; 2652 struct fw_port_l1cfg32 { 2653 __be32 rcap32; 2654 __be32 r; 2655 } l1cfg32; 2656 struct fw_port_info32 { 2657 __be32 lstatus32_to_cbllen32; 2658 __be32 auxlinfo32_mtu32; 2659 __be32 linkattr32; 2660 __be32 pcaps32; 2661 __be32 acaps32; 2662 __be32 lpacaps32; 2663 } info32; 2664 } u; 2665 }; 2666 2667 #define FW_PORT_CMD_READ_S 22 2668 #define FW_PORT_CMD_READ_V(x) ((x) << FW_PORT_CMD_READ_S) 2669 #define FW_PORT_CMD_READ_F FW_PORT_CMD_READ_V(1U) 2670 2671 #define FW_PORT_CMD_PORTID_S 0 2672 #define FW_PORT_CMD_PORTID_M 0xf 2673 #define FW_PORT_CMD_PORTID_V(x) ((x) << FW_PORT_CMD_PORTID_S) 2674 #define FW_PORT_CMD_PORTID_G(x) \ 2675 (((x) >> FW_PORT_CMD_PORTID_S) & FW_PORT_CMD_PORTID_M) 2676 2677 #define FW_PORT_CMD_ACTION_S 16 2678 #define FW_PORT_CMD_ACTION_M 0xffff 2679 #define FW_PORT_CMD_ACTION_V(x) ((x) << FW_PORT_CMD_ACTION_S) 2680 #define FW_PORT_CMD_ACTION_G(x) \ 2681 (((x) >> FW_PORT_CMD_ACTION_S) & FW_PORT_CMD_ACTION_M) 2682 2683 #define FW_PORT_CMD_OVLAN3_S 7 2684 #define FW_PORT_CMD_OVLAN3_V(x) ((x) << FW_PORT_CMD_OVLAN3_S) 2685 2686 #define FW_PORT_CMD_OVLAN2_S 6 2687 #define FW_PORT_CMD_OVLAN2_V(x) ((x) << FW_PORT_CMD_OVLAN2_S) 2688 2689 #define FW_PORT_CMD_OVLAN1_S 5 2690 #define FW_PORT_CMD_OVLAN1_V(x) ((x) << FW_PORT_CMD_OVLAN1_S) 2691 2692 #define FW_PORT_CMD_OVLAN0_S 4 2693 #define FW_PORT_CMD_OVLAN0_V(x) ((x) << FW_PORT_CMD_OVLAN0_S) 2694 2695 #define FW_PORT_CMD_IVLAN0_S 3 2696 #define FW_PORT_CMD_IVLAN0_V(x) ((x) << FW_PORT_CMD_IVLAN0_S) 2697 2698 #define FW_PORT_CMD_TXIPG_S 3 2699 #define FW_PORT_CMD_TXIPG_V(x) ((x) << FW_PORT_CMD_TXIPG_S) 2700 2701 #define FW_PORT_CMD_LSTATUS_S 31 2702 #define FW_PORT_CMD_LSTATUS_M 0x1 2703 #define FW_PORT_CMD_LSTATUS_V(x) ((x) << FW_PORT_CMD_LSTATUS_S) 2704 #define FW_PORT_CMD_LSTATUS_G(x) \ 2705 (((x) >> FW_PORT_CMD_LSTATUS_S) & FW_PORT_CMD_LSTATUS_M) 2706 #define FW_PORT_CMD_LSTATUS_F FW_PORT_CMD_LSTATUS_V(1U) 2707 2708 #define FW_PORT_CMD_LSPEED_S 24 2709 #define FW_PORT_CMD_LSPEED_M 0x3f 2710 #define FW_PORT_CMD_LSPEED_V(x) ((x) << FW_PORT_CMD_LSPEED_S) 2711 #define FW_PORT_CMD_LSPEED_G(x) \ 2712 (((x) >> FW_PORT_CMD_LSPEED_S) & FW_PORT_CMD_LSPEED_M) 2713 2714 #define FW_PORT_CMD_TXPAUSE_S 23 2715 #define FW_PORT_CMD_TXPAUSE_V(x) ((x) << FW_PORT_CMD_TXPAUSE_S) 2716 #define FW_PORT_CMD_TXPAUSE_F FW_PORT_CMD_TXPAUSE_V(1U) 2717 2718 #define FW_PORT_CMD_RXPAUSE_S 22 2719 #define FW_PORT_CMD_RXPAUSE_V(x) ((x) << FW_PORT_CMD_RXPAUSE_S) 2720 #define FW_PORT_CMD_RXPAUSE_F FW_PORT_CMD_RXPAUSE_V(1U) 2721 2722 #define FW_PORT_CMD_MDIOCAP_S 21 2723 #define FW_PORT_CMD_MDIOCAP_V(x) ((x) << FW_PORT_CMD_MDIOCAP_S) 2724 #define FW_PORT_CMD_MDIOCAP_F FW_PORT_CMD_MDIOCAP_V(1U) 2725 2726 #define FW_PORT_CMD_MDIOADDR_S 16 2727 #define FW_PORT_CMD_MDIOADDR_M 0x1f 2728 #define FW_PORT_CMD_MDIOADDR_G(x) \ 2729 (((x) >> FW_PORT_CMD_MDIOADDR_S) & FW_PORT_CMD_MDIOADDR_M) 2730 2731 #define FW_PORT_CMD_LPTXPAUSE_S 15 2732 #define FW_PORT_CMD_LPTXPAUSE_V(x) ((x) << FW_PORT_CMD_LPTXPAUSE_S) 2733 #define FW_PORT_CMD_LPTXPAUSE_F FW_PORT_CMD_LPTXPAUSE_V(1U) 2734 2735 #define FW_PORT_CMD_LPRXPAUSE_S 14 2736 #define FW_PORT_CMD_LPRXPAUSE_V(x) ((x) << FW_PORT_CMD_LPRXPAUSE_S) 2737 #define FW_PORT_CMD_LPRXPAUSE_F FW_PORT_CMD_LPRXPAUSE_V(1U) 2738 2739 #define FW_PORT_CMD_PTYPE_S 8 2740 #define FW_PORT_CMD_PTYPE_M 0x1f 2741 #define FW_PORT_CMD_PTYPE_G(x) \ 2742 (((x) >> FW_PORT_CMD_PTYPE_S) & FW_PORT_CMD_PTYPE_M) 2743 2744 #define FW_PORT_CMD_LINKDNRC_S 5 2745 #define FW_PORT_CMD_LINKDNRC_M 0x7 2746 #define FW_PORT_CMD_LINKDNRC_G(x) \ 2747 (((x) >> FW_PORT_CMD_LINKDNRC_S) & FW_PORT_CMD_LINKDNRC_M) 2748 2749 #define FW_PORT_CMD_MODTYPE_S 0 2750 #define FW_PORT_CMD_MODTYPE_M 0x1f 2751 #define FW_PORT_CMD_MODTYPE_V(x) ((x) << FW_PORT_CMD_MODTYPE_S) 2752 #define FW_PORT_CMD_MODTYPE_G(x) \ 2753 (((x) >> FW_PORT_CMD_MODTYPE_S) & FW_PORT_CMD_MODTYPE_M) 2754 2755 #define FW_PORT_CMD_DCBXDIS_S 7 2756 #define FW_PORT_CMD_DCBXDIS_V(x) ((x) << FW_PORT_CMD_DCBXDIS_S) 2757 #define FW_PORT_CMD_DCBXDIS_F FW_PORT_CMD_DCBXDIS_V(1U) 2758 2759 #define FW_PORT_CMD_APPLY_S 7 2760 #define FW_PORT_CMD_APPLY_V(x) ((x) << FW_PORT_CMD_APPLY_S) 2761 #define FW_PORT_CMD_APPLY_F FW_PORT_CMD_APPLY_V(1U) 2762 2763 #define FW_PORT_CMD_ALL_SYNCD_S 7 2764 #define FW_PORT_CMD_ALL_SYNCD_V(x) ((x) << FW_PORT_CMD_ALL_SYNCD_S) 2765 #define FW_PORT_CMD_ALL_SYNCD_F FW_PORT_CMD_ALL_SYNCD_V(1U) 2766 2767 #define FW_PORT_CMD_DCB_VERSION_S 12 2768 #define FW_PORT_CMD_DCB_VERSION_M 0x7 2769 #define FW_PORT_CMD_DCB_VERSION_G(x) \ 2770 (((x) >> FW_PORT_CMD_DCB_VERSION_S) & FW_PORT_CMD_DCB_VERSION_M) 2771 2772 #define FW_PORT_CMD_LSTATUS32_S 31 2773 #define FW_PORT_CMD_LSTATUS32_M 0x1 2774 #define FW_PORT_CMD_LSTATUS32_V(x) ((x) << FW_PORT_CMD_LSTATUS32_S) 2775 #define FW_PORT_CMD_LSTATUS32_G(x) \ 2776 (((x) >> FW_PORT_CMD_LSTATUS32_S) & FW_PORT_CMD_LSTATUS32_M) 2777 #define FW_PORT_CMD_LSTATUS32_F FW_PORT_CMD_LSTATUS32_V(1U) 2778 2779 #define FW_PORT_CMD_LINKDNRC32_S 28 2780 #define FW_PORT_CMD_LINKDNRC32_M 0x7 2781 #define FW_PORT_CMD_LINKDNRC32_V(x) ((x) << FW_PORT_CMD_LINKDNRC32_S) 2782 #define FW_PORT_CMD_LINKDNRC32_G(x) \ 2783 (((x) >> FW_PORT_CMD_LINKDNRC32_S) & FW_PORT_CMD_LINKDNRC32_M) 2784 2785 #define FW_PORT_CMD_DCBXDIS32_S 27 2786 #define FW_PORT_CMD_DCBXDIS32_M 0x1 2787 #define FW_PORT_CMD_DCBXDIS32_V(x) ((x) << FW_PORT_CMD_DCBXDIS32_S) 2788 #define FW_PORT_CMD_DCBXDIS32_G(x) \ 2789 (((x) >> FW_PORT_CMD_DCBXDIS32_S) & FW_PORT_CMD_DCBXDIS32_M) 2790 #define FW_PORT_CMD_DCBXDIS32_F FW_PORT_CMD_DCBXDIS32_V(1U) 2791 2792 #define FW_PORT_CMD_MDIOCAP32_S 26 2793 #define FW_PORT_CMD_MDIOCAP32_M 0x1 2794 #define FW_PORT_CMD_MDIOCAP32_V(x) ((x) << FW_PORT_CMD_MDIOCAP32_S) 2795 #define FW_PORT_CMD_MDIOCAP32_G(x) \ 2796 (((x) >> FW_PORT_CMD_MDIOCAP32_S) & FW_PORT_CMD_MDIOCAP32_M) 2797 #define FW_PORT_CMD_MDIOCAP32_F FW_PORT_CMD_MDIOCAP32_V(1U) 2798 2799 #define FW_PORT_CMD_MDIOADDR32_S 21 2800 #define FW_PORT_CMD_MDIOADDR32_M 0x1f 2801 #define FW_PORT_CMD_MDIOADDR32_V(x) ((x) << FW_PORT_CMD_MDIOADDR32_S) 2802 #define FW_PORT_CMD_MDIOADDR32_G(x) \ 2803 (((x) >> FW_PORT_CMD_MDIOADDR32_S) & FW_PORT_CMD_MDIOADDR32_M) 2804 2805 #define FW_PORT_CMD_PORTTYPE32_S 13 2806 #define FW_PORT_CMD_PORTTYPE32_M 0xff 2807 #define FW_PORT_CMD_PORTTYPE32_V(x) ((x) << FW_PORT_CMD_PORTTYPE32_S) 2808 #define FW_PORT_CMD_PORTTYPE32_G(x) \ 2809 (((x) >> FW_PORT_CMD_PORTTYPE32_S) & FW_PORT_CMD_PORTTYPE32_M) 2810 2811 #define FW_PORT_CMD_MODTYPE32_S 8 2812 #define FW_PORT_CMD_MODTYPE32_M 0x1f 2813 #define FW_PORT_CMD_MODTYPE32_V(x) ((x) << FW_PORT_CMD_MODTYPE32_S) 2814 #define FW_PORT_CMD_MODTYPE32_G(x) \ 2815 (((x) >> FW_PORT_CMD_MODTYPE32_S) & FW_PORT_CMD_MODTYPE32_M) 2816 2817 #define FW_PORT_CMD_CBLLEN32_S 0 2818 #define FW_PORT_CMD_CBLLEN32_M 0xff 2819 #define FW_PORT_CMD_CBLLEN32_V(x) ((x) << FW_PORT_CMD_CBLLEN32_S) 2820 #define FW_PORT_CMD_CBLLEN32_G(x) \ 2821 (((x) >> FW_PORT_CMD_CBLLEN32_S) & FW_PORT_CMD_CBLLEN32_M) 2822 2823 #define FW_PORT_CMD_AUXLINFO32_S 24 2824 #define FW_PORT_CMD_AUXLINFO32_M 0xff 2825 #define FW_PORT_CMD_AUXLINFO32_V(x) ((x) << FW_PORT_CMD_AUXLINFO32_S) 2826 #define FW_PORT_CMD_AUXLINFO32_G(x) \ 2827 (((x) >> FW_PORT_CMD_AUXLINFO32_S) & FW_PORT_CMD_AUXLINFO32_M) 2828 2829 #define FW_PORT_AUXLINFO32_KX4_S 2 2830 #define FW_PORT_AUXLINFO32_KX4_M 0x1 2831 #define FW_PORT_AUXLINFO32_KX4_V(x) \ 2832 ((x) << FW_PORT_AUXLINFO32_KX4_S) 2833 #define FW_PORT_AUXLINFO32_KX4_G(x) \ 2834 (((x) >> FW_PORT_AUXLINFO32_KX4_S) & FW_PORT_AUXLINFO32_KX4_M) 2835 #define FW_PORT_AUXLINFO32_KX4_F FW_PORT_AUXLINFO32_KX4_V(1U) 2836 2837 #define FW_PORT_AUXLINFO32_KR_S 1 2838 #define FW_PORT_AUXLINFO32_KR_M 0x1 2839 #define FW_PORT_AUXLINFO32_KR_V(x) \ 2840 ((x) << FW_PORT_AUXLINFO32_KR_S) 2841 #define FW_PORT_AUXLINFO32_KR_G(x) \ 2842 (((x) >> FW_PORT_AUXLINFO32_KR_S) & FW_PORT_AUXLINFO32_KR_M) 2843 #define FW_PORT_AUXLINFO32_KR_F FW_PORT_AUXLINFO32_KR_V(1U) 2844 2845 #define FW_PORT_CMD_MTU32_S 0 2846 #define FW_PORT_CMD_MTU32_M 0xffff 2847 #define FW_PORT_CMD_MTU32_V(x) ((x) << FW_PORT_CMD_MTU32_S) 2848 #define FW_PORT_CMD_MTU32_G(x) \ 2849 (((x) >> FW_PORT_CMD_MTU32_S) & FW_PORT_CMD_MTU32_M) 2850 2851 enum fw_port_type { 2852 FW_PORT_TYPE_FIBER_XFI, 2853 FW_PORT_TYPE_FIBER_XAUI, 2854 FW_PORT_TYPE_BT_SGMII, 2855 FW_PORT_TYPE_BT_XFI, 2856 FW_PORT_TYPE_BT_XAUI, 2857 FW_PORT_TYPE_KX4, 2858 FW_PORT_TYPE_CX4, 2859 FW_PORT_TYPE_KX, 2860 FW_PORT_TYPE_KR, 2861 FW_PORT_TYPE_SFP, 2862 FW_PORT_TYPE_BP_AP, 2863 FW_PORT_TYPE_BP4_AP, 2864 FW_PORT_TYPE_QSFP_10G, 2865 FW_PORT_TYPE_QSA, 2866 FW_PORT_TYPE_QSFP, 2867 FW_PORT_TYPE_BP40_BA, 2868 FW_PORT_TYPE_KR4_100G, 2869 FW_PORT_TYPE_CR4_QSFP, 2870 FW_PORT_TYPE_CR_QSFP, 2871 FW_PORT_TYPE_CR2_QSFP, 2872 FW_PORT_TYPE_SFP28, 2873 FW_PORT_TYPE_KR_SFP28, 2874 FW_PORT_TYPE_KR_XLAUI, 2875 2876 FW_PORT_TYPE_NONE = FW_PORT_CMD_PTYPE_M 2877 }; 2878 2879 enum fw_port_module_type { 2880 FW_PORT_MOD_TYPE_NA, 2881 FW_PORT_MOD_TYPE_LR, 2882 FW_PORT_MOD_TYPE_SR, 2883 FW_PORT_MOD_TYPE_ER, 2884 FW_PORT_MOD_TYPE_TWINAX_PASSIVE, 2885 FW_PORT_MOD_TYPE_TWINAX_ACTIVE, 2886 FW_PORT_MOD_TYPE_LRM, 2887 FW_PORT_MOD_TYPE_ERROR = FW_PORT_CMD_MODTYPE_M - 3, 2888 FW_PORT_MOD_TYPE_UNKNOWN = FW_PORT_CMD_MODTYPE_M - 2, 2889 FW_PORT_MOD_TYPE_NOTSUPPORTED = FW_PORT_CMD_MODTYPE_M - 1, 2890 2891 FW_PORT_MOD_TYPE_NONE = FW_PORT_CMD_MODTYPE_M 2892 }; 2893 2894 enum fw_port_mod_sub_type { 2895 FW_PORT_MOD_SUB_TYPE_NA, 2896 FW_PORT_MOD_SUB_TYPE_MV88E114X = 0x1, 2897 FW_PORT_MOD_SUB_TYPE_TN8022 = 0x2, 2898 FW_PORT_MOD_SUB_TYPE_AQ1202 = 0x3, 2899 FW_PORT_MOD_SUB_TYPE_88x3120 = 0x4, 2900 FW_PORT_MOD_SUB_TYPE_BCM84834 = 0x5, 2901 FW_PORT_MOD_SUB_TYPE_BT_VSC8634 = 0x8, 2902 2903 /* The following will never been in the VPD. They are TWINAX cable 2904 * lengths decoded from SFP+ module i2c PROMs. These should 2905 * almost certainly go somewhere else ... 2906 */ 2907 FW_PORT_MOD_SUB_TYPE_TWINAX_1 = 0x9, 2908 FW_PORT_MOD_SUB_TYPE_TWINAX_3 = 0xA, 2909 FW_PORT_MOD_SUB_TYPE_TWINAX_5 = 0xB, 2910 FW_PORT_MOD_SUB_TYPE_TWINAX_7 = 0xC, 2911 }; 2912 2913 enum fw_port_stats_tx_index { 2914 FW_STAT_TX_PORT_BYTES_IX = 0, 2915 FW_STAT_TX_PORT_FRAMES_IX, 2916 FW_STAT_TX_PORT_BCAST_IX, 2917 FW_STAT_TX_PORT_MCAST_IX, 2918 FW_STAT_TX_PORT_UCAST_IX, 2919 FW_STAT_TX_PORT_ERROR_IX, 2920 FW_STAT_TX_PORT_64B_IX, 2921 FW_STAT_TX_PORT_65B_127B_IX, 2922 FW_STAT_TX_PORT_128B_255B_IX, 2923 FW_STAT_TX_PORT_256B_511B_IX, 2924 FW_STAT_TX_PORT_512B_1023B_IX, 2925 FW_STAT_TX_PORT_1024B_1518B_IX, 2926 FW_STAT_TX_PORT_1519B_MAX_IX, 2927 FW_STAT_TX_PORT_DROP_IX, 2928 FW_STAT_TX_PORT_PAUSE_IX, 2929 FW_STAT_TX_PORT_PPP0_IX, 2930 FW_STAT_TX_PORT_PPP1_IX, 2931 FW_STAT_TX_PORT_PPP2_IX, 2932 FW_STAT_TX_PORT_PPP3_IX, 2933 FW_STAT_TX_PORT_PPP4_IX, 2934 FW_STAT_TX_PORT_PPP5_IX, 2935 FW_STAT_TX_PORT_PPP6_IX, 2936 FW_STAT_TX_PORT_PPP7_IX, 2937 FW_NUM_PORT_TX_STATS 2938 }; 2939 2940 enum fw_port_stat_rx_index { 2941 FW_STAT_RX_PORT_BYTES_IX = 0, 2942 FW_STAT_RX_PORT_FRAMES_IX, 2943 FW_STAT_RX_PORT_BCAST_IX, 2944 FW_STAT_RX_PORT_MCAST_IX, 2945 FW_STAT_RX_PORT_UCAST_IX, 2946 FW_STAT_RX_PORT_MTU_ERROR_IX, 2947 FW_STAT_RX_PORT_MTU_CRC_ERROR_IX, 2948 FW_STAT_RX_PORT_CRC_ERROR_IX, 2949 FW_STAT_RX_PORT_LEN_ERROR_IX, 2950 FW_STAT_RX_PORT_SYM_ERROR_IX, 2951 FW_STAT_RX_PORT_64B_IX, 2952 FW_STAT_RX_PORT_65B_127B_IX, 2953 FW_STAT_RX_PORT_128B_255B_IX, 2954 FW_STAT_RX_PORT_256B_511B_IX, 2955 FW_STAT_RX_PORT_512B_1023B_IX, 2956 FW_STAT_RX_PORT_1024B_1518B_IX, 2957 FW_STAT_RX_PORT_1519B_MAX_IX, 2958 FW_STAT_RX_PORT_PAUSE_IX, 2959 FW_STAT_RX_PORT_PPP0_IX, 2960 FW_STAT_RX_PORT_PPP1_IX, 2961 FW_STAT_RX_PORT_PPP2_IX, 2962 FW_STAT_RX_PORT_PPP3_IX, 2963 FW_STAT_RX_PORT_PPP4_IX, 2964 FW_STAT_RX_PORT_PPP5_IX, 2965 FW_STAT_RX_PORT_PPP6_IX, 2966 FW_STAT_RX_PORT_PPP7_IX, 2967 FW_STAT_RX_PORT_LESS_64B_IX, 2968 FW_STAT_RX_PORT_MAC_ERROR_IX, 2969 FW_NUM_PORT_RX_STATS 2970 }; 2971 2972 /* port stats */ 2973 #define FW_NUM_PORT_STATS (FW_NUM_PORT_TX_STATS + FW_NUM_PORT_RX_STATS) 2974 2975 struct fw_port_stats_cmd { 2976 __be32 op_to_portid; 2977 __be32 retval_len16; 2978 union fw_port_stats { 2979 struct fw_port_stats_ctl { 2980 u8 nstats_bg_bm; 2981 u8 tx_ix; 2982 __be16 r6; 2983 __be32 r7; 2984 __be64 stat0; 2985 __be64 stat1; 2986 __be64 stat2; 2987 __be64 stat3; 2988 __be64 stat4; 2989 __be64 stat5; 2990 } ctl; 2991 struct fw_port_stats_all { 2992 __be64 tx_bytes; 2993 __be64 tx_frames; 2994 __be64 tx_bcast; 2995 __be64 tx_mcast; 2996 __be64 tx_ucast; 2997 __be64 tx_error; 2998 __be64 tx_64b; 2999 __be64 tx_65b_127b; 3000 __be64 tx_128b_255b; 3001 __be64 tx_256b_511b; 3002 __be64 tx_512b_1023b; 3003 __be64 tx_1024b_1518b; 3004 __be64 tx_1519b_max; 3005 __be64 tx_drop; 3006 __be64 tx_pause; 3007 __be64 tx_ppp0; 3008 __be64 tx_ppp1; 3009 __be64 tx_ppp2; 3010 __be64 tx_ppp3; 3011 __be64 tx_ppp4; 3012 __be64 tx_ppp5; 3013 __be64 tx_ppp6; 3014 __be64 tx_ppp7; 3015 __be64 rx_bytes; 3016 __be64 rx_frames; 3017 __be64 rx_bcast; 3018 __be64 rx_mcast; 3019 __be64 rx_ucast; 3020 __be64 rx_mtu_error; 3021 __be64 rx_mtu_crc_error; 3022 __be64 rx_crc_error; 3023 __be64 rx_len_error; 3024 __be64 rx_sym_error; 3025 __be64 rx_64b; 3026 __be64 rx_65b_127b; 3027 __be64 rx_128b_255b; 3028 __be64 rx_256b_511b; 3029 __be64 rx_512b_1023b; 3030 __be64 rx_1024b_1518b; 3031 __be64 rx_1519b_max; 3032 __be64 rx_pause; 3033 __be64 rx_ppp0; 3034 __be64 rx_ppp1; 3035 __be64 rx_ppp2; 3036 __be64 rx_ppp3; 3037 __be64 rx_ppp4; 3038 __be64 rx_ppp5; 3039 __be64 rx_ppp6; 3040 __be64 rx_ppp7; 3041 __be64 rx_less_64b; 3042 __be64 rx_bg_drop; 3043 __be64 rx_bg_trunc; 3044 } all; 3045 } u; 3046 }; 3047 3048 /* port loopback stats */ 3049 #define FW_NUM_LB_STATS 16 3050 enum fw_port_lb_stats_index { 3051 FW_STAT_LB_PORT_BYTES_IX, 3052 FW_STAT_LB_PORT_FRAMES_IX, 3053 FW_STAT_LB_PORT_BCAST_IX, 3054 FW_STAT_LB_PORT_MCAST_IX, 3055 FW_STAT_LB_PORT_UCAST_IX, 3056 FW_STAT_LB_PORT_ERROR_IX, 3057 FW_STAT_LB_PORT_64B_IX, 3058 FW_STAT_LB_PORT_65B_127B_IX, 3059 FW_STAT_LB_PORT_128B_255B_IX, 3060 FW_STAT_LB_PORT_256B_511B_IX, 3061 FW_STAT_LB_PORT_512B_1023B_IX, 3062 FW_STAT_LB_PORT_1024B_1518B_IX, 3063 FW_STAT_LB_PORT_1519B_MAX_IX, 3064 FW_STAT_LB_PORT_DROP_FRAMES_IX 3065 }; 3066 3067 struct fw_port_lb_stats_cmd { 3068 __be32 op_to_lbport; 3069 __be32 retval_len16; 3070 union fw_port_lb_stats { 3071 struct fw_port_lb_stats_ctl { 3072 u8 nstats_bg_bm; 3073 u8 ix_pkd; 3074 __be16 r6; 3075 __be32 r7; 3076 __be64 stat0; 3077 __be64 stat1; 3078 __be64 stat2; 3079 __be64 stat3; 3080 __be64 stat4; 3081 __be64 stat5; 3082 } ctl; 3083 struct fw_port_lb_stats_all { 3084 __be64 tx_bytes; 3085 __be64 tx_frames; 3086 __be64 tx_bcast; 3087 __be64 tx_mcast; 3088 __be64 tx_ucast; 3089 __be64 tx_error; 3090 __be64 tx_64b; 3091 __be64 tx_65b_127b; 3092 __be64 tx_128b_255b; 3093 __be64 tx_256b_511b; 3094 __be64 tx_512b_1023b; 3095 __be64 tx_1024b_1518b; 3096 __be64 tx_1519b_max; 3097 __be64 rx_lb_drop; 3098 __be64 rx_lb_trunc; 3099 } all; 3100 } u; 3101 }; 3102 3103 enum fw_ptp_subop { 3104 /* none */ 3105 FW_PTP_SC_INIT_TIMER = 0x00, 3106 FW_PTP_SC_TX_TYPE = 0x01, 3107 /* init */ 3108 FW_PTP_SC_RXTIME_STAMP = 0x08, 3109 FW_PTP_SC_RDRX_TYPE = 0x09, 3110 /* ts */ 3111 FW_PTP_SC_ADJ_FREQ = 0x10, 3112 FW_PTP_SC_ADJ_TIME = 0x11, 3113 FW_PTP_SC_ADJ_FTIME = 0x12, 3114 FW_PTP_SC_WALL_CLOCK = 0x13, 3115 FW_PTP_SC_GET_TIME = 0x14, 3116 FW_PTP_SC_SET_TIME = 0x15, 3117 }; 3118 3119 struct fw_ptp_cmd { 3120 __be32 op_to_portid; 3121 __be32 retval_len16; 3122 union fw_ptp { 3123 struct fw_ptp_sc { 3124 __u8 sc; 3125 __u8 r3[7]; 3126 } scmd; 3127 struct fw_ptp_init { 3128 __u8 sc; 3129 __u8 txchan; 3130 __be16 absid; 3131 __be16 mode; 3132 __be16 r3; 3133 } init; 3134 struct fw_ptp_ts { 3135 __u8 sc; 3136 __u8 sign; 3137 __be16 r3; 3138 __be32 ppb; 3139 __be64 tm; 3140 } ts; 3141 } u; 3142 __be64 r3; 3143 }; 3144 3145 #define FW_PTP_CMD_PORTID_S 0 3146 #define FW_PTP_CMD_PORTID_M 0xf 3147 #define FW_PTP_CMD_PORTID_V(x) ((x) << FW_PTP_CMD_PORTID_S) 3148 #define FW_PTP_CMD_PORTID_G(x) \ 3149 (((x) >> FW_PTP_CMD_PORTID_S) & FW_PTP_CMD_PORTID_M) 3150 3151 struct fw_rss_ind_tbl_cmd { 3152 __be32 op_to_viid; 3153 __be32 retval_len16; 3154 __be16 niqid; 3155 __be16 startidx; 3156 __be32 r3; 3157 __be32 iq0_to_iq2; 3158 __be32 iq3_to_iq5; 3159 __be32 iq6_to_iq8; 3160 __be32 iq9_to_iq11; 3161 __be32 iq12_to_iq14; 3162 __be32 iq15_to_iq17; 3163 __be32 iq18_to_iq20; 3164 __be32 iq21_to_iq23; 3165 __be32 iq24_to_iq26; 3166 __be32 iq27_to_iq29; 3167 __be32 iq30_iq31; 3168 __be32 r15_lo; 3169 }; 3170 3171 #define FW_RSS_IND_TBL_CMD_VIID_S 0 3172 #define FW_RSS_IND_TBL_CMD_VIID_V(x) ((x) << FW_RSS_IND_TBL_CMD_VIID_S) 3173 3174 #define FW_RSS_IND_TBL_CMD_IQ0_S 20 3175 #define FW_RSS_IND_TBL_CMD_IQ0_V(x) ((x) << FW_RSS_IND_TBL_CMD_IQ0_S) 3176 3177 #define FW_RSS_IND_TBL_CMD_IQ1_S 10 3178 #define FW_RSS_IND_TBL_CMD_IQ1_V(x) ((x) << FW_RSS_IND_TBL_CMD_IQ1_S) 3179 3180 #define FW_RSS_IND_TBL_CMD_IQ2_S 0 3181 #define FW_RSS_IND_TBL_CMD_IQ2_V(x) ((x) << FW_RSS_IND_TBL_CMD_IQ2_S) 3182 3183 struct fw_rss_glb_config_cmd { 3184 __be32 op_to_write; 3185 __be32 retval_len16; 3186 union fw_rss_glb_config { 3187 struct fw_rss_glb_config_manual { 3188 __be32 mode_pkd; 3189 __be32 r3; 3190 __be64 r4; 3191 __be64 r5; 3192 } manual; 3193 struct fw_rss_glb_config_basicvirtual { 3194 __be32 mode_pkd; 3195 __be32 synmapen_to_hashtoeplitz; 3196 __be64 r8; 3197 __be64 r9; 3198 } basicvirtual; 3199 } u; 3200 }; 3201 3202 #define FW_RSS_GLB_CONFIG_CMD_MODE_S 28 3203 #define FW_RSS_GLB_CONFIG_CMD_MODE_M 0xf 3204 #define FW_RSS_GLB_CONFIG_CMD_MODE_V(x) ((x) << FW_RSS_GLB_CONFIG_CMD_MODE_S) 3205 #define FW_RSS_GLB_CONFIG_CMD_MODE_G(x) \ 3206 (((x) >> FW_RSS_GLB_CONFIG_CMD_MODE_S) & FW_RSS_GLB_CONFIG_CMD_MODE_M) 3207 3208 #define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL 0 3209 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1 3210 3211 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_S 8 3212 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_V(x) \ 3213 ((x) << FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_S) 3214 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_F \ 3215 FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_V(1U) 3216 3217 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_S 7 3218 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_V(x) \ 3219 ((x) << FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_S) 3220 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_F \ 3221 FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_V(1U) 3222 3223 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_S 6 3224 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_V(x) \ 3225 ((x) << FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_S) 3226 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_F \ 3227 FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_V(1U) 3228 3229 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_S 5 3230 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_V(x) \ 3231 ((x) << FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_S) 3232 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_F \ 3233 FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_V(1U) 3234 3235 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_S 4 3236 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_V(x) \ 3237 ((x) << FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_S) 3238 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_F \ 3239 FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_V(1U) 3240 3241 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_S 3 3242 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_V(x) \ 3243 ((x) << FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_S) 3244 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_F \ 3245 FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_V(1U) 3246 3247 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_S 2 3248 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_V(x) \ 3249 ((x) << FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_S) 3250 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F \ 3251 FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_V(1U) 3252 3253 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_S 1 3254 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_V(x) \ 3255 ((x) << FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_S) 3256 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F \ 3257 FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_V(1U) 3258 3259 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_S 0 3260 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_V(x) \ 3261 ((x) << FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_S) 3262 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_F \ 3263 FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_V(1U) 3264 3265 struct fw_rss_vi_config_cmd { 3266 __be32 op_to_viid; 3267 #define FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << 0) 3268 __be32 retval_len16; 3269 union fw_rss_vi_config { 3270 struct fw_rss_vi_config_manual { 3271 __be64 r3; 3272 __be64 r4; 3273 __be64 r5; 3274 } manual; 3275 struct fw_rss_vi_config_basicvirtual { 3276 __be32 r6; 3277 __be32 defaultq_to_udpen; 3278 __be64 r9; 3279 __be64 r10; 3280 } basicvirtual; 3281 } u; 3282 }; 3283 3284 #define FW_RSS_VI_CONFIG_CMD_VIID_S 0 3285 #define FW_RSS_VI_CONFIG_CMD_VIID_V(x) ((x) << FW_RSS_VI_CONFIG_CMD_VIID_S) 3286 3287 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S 16 3288 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_M 0x3ff 3289 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_V(x) \ 3290 ((x) << FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S) 3291 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_G(x) \ 3292 (((x) >> FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S) & \ 3293 FW_RSS_VI_CONFIG_CMD_DEFAULTQ_M) 3294 3295 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_S 4 3296 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_V(x) \ 3297 ((x) << FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_S) 3298 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F \ 3299 FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_V(1U) 3300 3301 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_S 3 3302 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_V(x) \ 3303 ((x) << FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_S) 3304 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F \ 3305 FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_V(1U) 3306 3307 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_S 2 3308 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_V(x) \ 3309 ((x) << FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_S) 3310 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F \ 3311 FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_V(1U) 3312 3313 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_S 1 3314 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_V(x) \ 3315 ((x) << FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_S) 3316 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F \ 3317 FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_V(1U) 3318 3319 #define FW_RSS_VI_CONFIG_CMD_UDPEN_S 0 3320 #define FW_RSS_VI_CONFIG_CMD_UDPEN_V(x) ((x) << FW_RSS_VI_CONFIG_CMD_UDPEN_S) 3321 #define FW_RSS_VI_CONFIG_CMD_UDPEN_F FW_RSS_VI_CONFIG_CMD_UDPEN_V(1U) 3322 3323 enum fw_sched_sc { 3324 FW_SCHED_SC_PARAMS = 1, 3325 }; 3326 3327 struct fw_sched_cmd { 3328 __be32 op_to_write; 3329 __be32 retval_len16; 3330 union fw_sched { 3331 struct fw_sched_config { 3332 __u8 sc; 3333 __u8 type; 3334 __u8 minmaxen; 3335 __u8 r3[5]; 3336 __u8 nclasses[4]; 3337 __be32 r4; 3338 } config; 3339 struct fw_sched_params { 3340 __u8 sc; 3341 __u8 type; 3342 __u8 level; 3343 __u8 mode; 3344 __u8 unit; 3345 __u8 rate; 3346 __u8 ch; 3347 __u8 cl; 3348 __be32 min; 3349 __be32 max; 3350 __be16 weight; 3351 __be16 pktsize; 3352 __be16 burstsize; 3353 __be16 r4; 3354 } params; 3355 } u; 3356 }; 3357 3358 struct fw_clip_cmd { 3359 __be32 op_to_write; 3360 __be32 alloc_to_len16; 3361 __be64 ip_hi; 3362 __be64 ip_lo; 3363 __be32 r4[2]; 3364 }; 3365 3366 #define FW_CLIP_CMD_ALLOC_S 31 3367 #define FW_CLIP_CMD_ALLOC_V(x) ((x) << FW_CLIP_CMD_ALLOC_S) 3368 #define FW_CLIP_CMD_ALLOC_F FW_CLIP_CMD_ALLOC_V(1U) 3369 3370 #define FW_CLIP_CMD_FREE_S 30 3371 #define FW_CLIP_CMD_FREE_V(x) ((x) << FW_CLIP_CMD_FREE_S) 3372 #define FW_CLIP_CMD_FREE_F FW_CLIP_CMD_FREE_V(1U) 3373 3374 enum fw_error_type { 3375 FW_ERROR_TYPE_EXCEPTION = 0x0, 3376 FW_ERROR_TYPE_HWMODULE = 0x1, 3377 FW_ERROR_TYPE_WR = 0x2, 3378 FW_ERROR_TYPE_ACL = 0x3, 3379 }; 3380 3381 struct fw_error_cmd { 3382 __be32 op_to_type; 3383 __be32 len16_pkd; 3384 union fw_error { 3385 struct fw_error_exception { 3386 __be32 info[6]; 3387 } exception; 3388 struct fw_error_hwmodule { 3389 __be32 regaddr; 3390 __be32 regval; 3391 } hwmodule; 3392 struct fw_error_wr { 3393 __be16 cidx; 3394 __be16 pfn_vfn; 3395 __be32 eqid; 3396 u8 wrhdr[16]; 3397 } wr; 3398 struct fw_error_acl { 3399 __be16 cidx; 3400 __be16 pfn_vfn; 3401 __be32 eqid; 3402 __be16 mv_pkd; 3403 u8 val[6]; 3404 __be64 r4; 3405 } acl; 3406 } u; 3407 }; 3408 3409 struct fw_debug_cmd { 3410 __be32 op_type; 3411 __be32 len16_pkd; 3412 union fw_debug { 3413 struct fw_debug_assert { 3414 __be32 fcid; 3415 __be32 line; 3416 __be32 x; 3417 __be32 y; 3418 u8 filename_0_7[8]; 3419 u8 filename_8_15[8]; 3420 __be64 r3; 3421 } assert; 3422 struct fw_debug_prt { 3423 __be16 dprtstridx; 3424 __be16 r3[3]; 3425 __be32 dprtstrparam0; 3426 __be32 dprtstrparam1; 3427 __be32 dprtstrparam2; 3428 __be32 dprtstrparam3; 3429 } prt; 3430 } u; 3431 }; 3432 3433 #define FW_DEBUG_CMD_TYPE_S 0 3434 #define FW_DEBUG_CMD_TYPE_M 0xff 3435 #define FW_DEBUG_CMD_TYPE_G(x) \ 3436 (((x) >> FW_DEBUG_CMD_TYPE_S) & FW_DEBUG_CMD_TYPE_M) 3437 3438 enum pcie_fw_eval { 3439 PCIE_FW_EVAL_CRASH = 0, 3440 }; 3441 3442 #define PCIE_FW_ERR_S 31 3443 #define PCIE_FW_ERR_V(x) ((x) << PCIE_FW_ERR_S) 3444 #define PCIE_FW_ERR_F PCIE_FW_ERR_V(1U) 3445 3446 #define PCIE_FW_INIT_S 30 3447 #define PCIE_FW_INIT_V(x) ((x) << PCIE_FW_INIT_S) 3448 #define PCIE_FW_INIT_F PCIE_FW_INIT_V(1U) 3449 3450 #define PCIE_FW_HALT_S 29 3451 #define PCIE_FW_HALT_V(x) ((x) << PCIE_FW_HALT_S) 3452 #define PCIE_FW_HALT_F PCIE_FW_HALT_V(1U) 3453 3454 #define PCIE_FW_EVAL_S 24 3455 #define PCIE_FW_EVAL_M 0x7 3456 #define PCIE_FW_EVAL_G(x) (((x) >> PCIE_FW_EVAL_S) & PCIE_FW_EVAL_M) 3457 3458 #define PCIE_FW_MASTER_VLD_S 15 3459 #define PCIE_FW_MASTER_VLD_V(x) ((x) << PCIE_FW_MASTER_VLD_S) 3460 #define PCIE_FW_MASTER_VLD_F PCIE_FW_MASTER_VLD_V(1U) 3461 3462 #define PCIE_FW_MASTER_S 12 3463 #define PCIE_FW_MASTER_M 0x7 3464 #define PCIE_FW_MASTER_V(x) ((x) << PCIE_FW_MASTER_S) 3465 #define PCIE_FW_MASTER_G(x) (((x) >> PCIE_FW_MASTER_S) & PCIE_FW_MASTER_M) 3466 3467 struct fw_hdr { 3468 u8 ver; 3469 u8 chip; /* terminator chip type */ 3470 __be16 len512; /* bin length in units of 512-bytes */ 3471 __be32 fw_ver; /* firmware version */ 3472 __be32 tp_microcode_ver; 3473 u8 intfver_nic; 3474 u8 intfver_vnic; 3475 u8 intfver_ofld; 3476 u8 intfver_ri; 3477 u8 intfver_iscsipdu; 3478 u8 intfver_iscsi; 3479 u8 intfver_fcoepdu; 3480 u8 intfver_fcoe; 3481 __u32 reserved2; 3482 __u32 reserved3; 3483 __u32 reserved4; 3484 __be32 flags; 3485 __be32 reserved6[23]; 3486 }; 3487 3488 enum fw_hdr_chip { 3489 FW_HDR_CHIP_T4, 3490 FW_HDR_CHIP_T5, 3491 FW_HDR_CHIP_T6 3492 }; 3493 3494 #define FW_HDR_FW_VER_MAJOR_S 24 3495 #define FW_HDR_FW_VER_MAJOR_M 0xff 3496 #define FW_HDR_FW_VER_MAJOR_V(x) \ 3497 ((x) << FW_HDR_FW_VER_MAJOR_S) 3498 #define FW_HDR_FW_VER_MAJOR_G(x) \ 3499 (((x) >> FW_HDR_FW_VER_MAJOR_S) & FW_HDR_FW_VER_MAJOR_M) 3500 3501 #define FW_HDR_FW_VER_MINOR_S 16 3502 #define FW_HDR_FW_VER_MINOR_M 0xff 3503 #define FW_HDR_FW_VER_MINOR_V(x) \ 3504 ((x) << FW_HDR_FW_VER_MINOR_S) 3505 #define FW_HDR_FW_VER_MINOR_G(x) \ 3506 (((x) >> FW_HDR_FW_VER_MINOR_S) & FW_HDR_FW_VER_MINOR_M) 3507 3508 #define FW_HDR_FW_VER_MICRO_S 8 3509 #define FW_HDR_FW_VER_MICRO_M 0xff 3510 #define FW_HDR_FW_VER_MICRO_V(x) \ 3511 ((x) << FW_HDR_FW_VER_MICRO_S) 3512 #define FW_HDR_FW_VER_MICRO_G(x) \ 3513 (((x) >> FW_HDR_FW_VER_MICRO_S) & FW_HDR_FW_VER_MICRO_M) 3514 3515 #define FW_HDR_FW_VER_BUILD_S 0 3516 #define FW_HDR_FW_VER_BUILD_M 0xff 3517 #define FW_HDR_FW_VER_BUILD_V(x) \ 3518 ((x) << FW_HDR_FW_VER_BUILD_S) 3519 #define FW_HDR_FW_VER_BUILD_G(x) \ 3520 (((x) >> FW_HDR_FW_VER_BUILD_S) & FW_HDR_FW_VER_BUILD_M) 3521 3522 enum fw_hdr_intfver { 3523 FW_HDR_INTFVER_NIC = 0x00, 3524 FW_HDR_INTFVER_VNIC = 0x00, 3525 FW_HDR_INTFVER_OFLD = 0x00, 3526 FW_HDR_INTFVER_RI = 0x00, 3527 FW_HDR_INTFVER_ISCSIPDU = 0x00, 3528 FW_HDR_INTFVER_ISCSI = 0x00, 3529 FW_HDR_INTFVER_FCOEPDU = 0x00, 3530 FW_HDR_INTFVER_FCOE = 0x00, 3531 }; 3532 3533 enum fw_hdr_flags { 3534 FW_HDR_FLAGS_RESET_HALT = 0x00000001, 3535 }; 3536 3537 /* length of the formatting string */ 3538 #define FW_DEVLOG_FMT_LEN 192 3539 3540 /* maximum number of the formatting string parameters */ 3541 #define FW_DEVLOG_FMT_PARAMS_NUM 8 3542 3543 /* priority levels */ 3544 enum fw_devlog_level { 3545 FW_DEVLOG_LEVEL_EMERG = 0x0, 3546 FW_DEVLOG_LEVEL_CRIT = 0x1, 3547 FW_DEVLOG_LEVEL_ERR = 0x2, 3548 FW_DEVLOG_LEVEL_NOTICE = 0x3, 3549 FW_DEVLOG_LEVEL_INFO = 0x4, 3550 FW_DEVLOG_LEVEL_DEBUG = 0x5, 3551 FW_DEVLOG_LEVEL_MAX = 0x5, 3552 }; 3553 3554 /* facilities that may send a log message */ 3555 enum fw_devlog_facility { 3556 FW_DEVLOG_FACILITY_CORE = 0x00, 3557 FW_DEVLOG_FACILITY_CF = 0x01, 3558 FW_DEVLOG_FACILITY_SCHED = 0x02, 3559 FW_DEVLOG_FACILITY_TIMER = 0x04, 3560 FW_DEVLOG_FACILITY_RES = 0x06, 3561 FW_DEVLOG_FACILITY_HW = 0x08, 3562 FW_DEVLOG_FACILITY_FLR = 0x10, 3563 FW_DEVLOG_FACILITY_DMAQ = 0x12, 3564 FW_DEVLOG_FACILITY_PHY = 0x14, 3565 FW_DEVLOG_FACILITY_MAC = 0x16, 3566 FW_DEVLOG_FACILITY_PORT = 0x18, 3567 FW_DEVLOG_FACILITY_VI = 0x1A, 3568 FW_DEVLOG_FACILITY_FILTER = 0x1C, 3569 FW_DEVLOG_FACILITY_ACL = 0x1E, 3570 FW_DEVLOG_FACILITY_TM = 0x20, 3571 FW_DEVLOG_FACILITY_QFC = 0x22, 3572 FW_DEVLOG_FACILITY_DCB = 0x24, 3573 FW_DEVLOG_FACILITY_ETH = 0x26, 3574 FW_DEVLOG_FACILITY_OFLD = 0x28, 3575 FW_DEVLOG_FACILITY_RI = 0x2A, 3576 FW_DEVLOG_FACILITY_ISCSI = 0x2C, 3577 FW_DEVLOG_FACILITY_FCOE = 0x2E, 3578 FW_DEVLOG_FACILITY_FOISCSI = 0x30, 3579 FW_DEVLOG_FACILITY_FOFCOE = 0x32, 3580 FW_DEVLOG_FACILITY_CHNET = 0x34, 3581 FW_DEVLOG_FACILITY_MAX = 0x34, 3582 }; 3583 3584 /* log message format */ 3585 struct fw_devlog_e { 3586 __be64 timestamp; 3587 __be32 seqno; 3588 __be16 reserved1; 3589 __u8 level; 3590 __u8 facility; 3591 __u8 fmt[FW_DEVLOG_FMT_LEN]; 3592 __be32 params[FW_DEVLOG_FMT_PARAMS_NUM]; 3593 __be32 reserved3[4]; 3594 }; 3595 3596 struct fw_devlog_cmd { 3597 __be32 op_to_write; 3598 __be32 retval_len16; 3599 __u8 level; 3600 __u8 r2[7]; 3601 __be32 memtype_devlog_memaddr16_devlog; 3602 __be32 memsize_devlog; 3603 __be32 r3[2]; 3604 }; 3605 3606 #define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_S 28 3607 #define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_M 0xf 3608 #define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(x) \ 3609 (((x) >> FW_DEVLOG_CMD_MEMTYPE_DEVLOG_S) & \ 3610 FW_DEVLOG_CMD_MEMTYPE_DEVLOG_M) 3611 3612 #define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_S 0 3613 #define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_M 0xfffffff 3614 #define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(x) \ 3615 (((x) >> FW_DEVLOG_CMD_MEMADDR16_DEVLOG_S) & \ 3616 FW_DEVLOG_CMD_MEMADDR16_DEVLOG_M) 3617 3618 /* P C I E F W P F 7 R E G I S T E R */ 3619 3620 /* PF7 stores the Firmware Device Log parameters which allows Host Drivers to 3621 * access the "devlog" which needing to contact firmware. The encoding is 3622 * mostly the same as that returned by the DEVLOG command except for the size 3623 * which is encoded as the number of entries in multiples-1 of 128 here rather 3624 * than the memory size as is done in the DEVLOG command. Thus, 0 means 128 3625 * and 15 means 2048. This of course in turn constrains the allowed values 3626 * for the devlog size ... 3627 */ 3628 #define PCIE_FW_PF_DEVLOG 7 3629 3630 #define PCIE_FW_PF_DEVLOG_NENTRIES128_S 28 3631 #define PCIE_FW_PF_DEVLOG_NENTRIES128_M 0xf 3632 #define PCIE_FW_PF_DEVLOG_NENTRIES128_V(x) \ 3633 ((x) << PCIE_FW_PF_DEVLOG_NENTRIES128_S) 3634 #define PCIE_FW_PF_DEVLOG_NENTRIES128_G(x) \ 3635 (((x) >> PCIE_FW_PF_DEVLOG_NENTRIES128_S) & \ 3636 PCIE_FW_PF_DEVLOG_NENTRIES128_M) 3637 3638 #define PCIE_FW_PF_DEVLOG_ADDR16_S 4 3639 #define PCIE_FW_PF_DEVLOG_ADDR16_M 0xffffff 3640 #define PCIE_FW_PF_DEVLOG_ADDR16_V(x) ((x) << PCIE_FW_PF_DEVLOG_ADDR16_S) 3641 #define PCIE_FW_PF_DEVLOG_ADDR16_G(x) \ 3642 (((x) >> PCIE_FW_PF_DEVLOG_ADDR16_S) & PCIE_FW_PF_DEVLOG_ADDR16_M) 3643 3644 #define PCIE_FW_PF_DEVLOG_MEMTYPE_S 0 3645 #define PCIE_FW_PF_DEVLOG_MEMTYPE_M 0xf 3646 #define PCIE_FW_PF_DEVLOG_MEMTYPE_V(x) ((x) << PCIE_FW_PF_DEVLOG_MEMTYPE_S) 3647 #define PCIE_FW_PF_DEVLOG_MEMTYPE_G(x) \ 3648 (((x) >> PCIE_FW_PF_DEVLOG_MEMTYPE_S) & PCIE_FW_PF_DEVLOG_MEMTYPE_M) 3649 3650 #define MAX_IMM_OFLD_TX_DATA_WR_LEN (0xff + sizeof(struct fw_ofld_tx_data_wr)) 3651 3652 struct fw_crypto_lookaside_wr { 3653 __be32 op_to_cctx_size; 3654 __be32 len16_pkd; 3655 __be32 session_id; 3656 __be32 rx_chid_to_rx_q_id; 3657 __be32 key_addr; 3658 __be32 pld_size_hash_size; 3659 __be64 cookie; 3660 }; 3661 3662 #define FW_CRYPTO_LOOKASIDE_WR_OPCODE_S 24 3663 #define FW_CRYPTO_LOOKASIDE_WR_OPCODE_M 0xff 3664 #define FW_CRYPTO_LOOKASIDE_WR_OPCODE_V(x) \ 3665 ((x) << FW_CRYPTO_LOOKASIDE_WR_OPCODE_S) 3666 #define FW_CRYPTO_LOOKASIDE_WR_OPCODE_G(x) \ 3667 (((x) >> FW_CRYPTO_LOOKASIDE_WR_OPCODE_S) & \ 3668 FW_CRYPTO_LOOKASIDE_WR_OPCODE_M) 3669 3670 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_S 23 3671 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_M 0x1 3672 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_V(x) \ 3673 ((x) << FW_CRYPTO_LOOKASIDE_WR_COMPL_S) 3674 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_G(x) \ 3675 (((x) >> FW_CRYPTO_LOOKASIDE_WR_COMPL_S) & \ 3676 FW_CRYPTO_LOOKASIDE_WR_COMPL_M) 3677 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_F FW_CRYPTO_LOOKASIDE_WR_COMPL_V(1U) 3678 3679 #define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_S 15 3680 #define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_M 0xff 3681 #define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_V(x) \ 3682 ((x) << FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_S) 3683 #define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_G(x) \ 3684 (((x) >> FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_S) & \ 3685 FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_M) 3686 3687 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_S 5 3688 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_M 0x3 3689 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_V(x) \ 3690 ((x) << FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_S) 3691 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_G(x) \ 3692 (((x) >> FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_S) & \ 3693 FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_M) 3694 3695 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_S 0 3696 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_M 0x1f 3697 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_V(x) \ 3698 ((x) << FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_S) 3699 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_G(x) \ 3700 (((x) >> FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_S) & \ 3701 FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_M) 3702 3703 #define FW_CRYPTO_LOOKASIDE_WR_LEN16_S 0 3704 #define FW_CRYPTO_LOOKASIDE_WR_LEN16_M 0xff 3705 #define FW_CRYPTO_LOOKASIDE_WR_LEN16_V(x) \ 3706 ((x) << FW_CRYPTO_LOOKASIDE_WR_LEN16_S) 3707 #define FW_CRYPTO_LOOKASIDE_WR_LEN16_G(x) \ 3708 (((x) >> FW_CRYPTO_LOOKASIDE_WR_LEN16_S) & \ 3709 FW_CRYPTO_LOOKASIDE_WR_LEN16_M) 3710 3711 #define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_S 29 3712 #define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_M 0x3 3713 #define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_V(x) \ 3714 ((x) << FW_CRYPTO_LOOKASIDE_WR_RX_CHID_S) 3715 #define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_G(x) \ 3716 (((x) >> FW_CRYPTO_LOOKASIDE_WR_RX_CHID_S) & \ 3717 FW_CRYPTO_LOOKASIDE_WR_RX_CHID_M) 3718 3719 #define FW_CRYPTO_LOOKASIDE_WR_LCB_S 27 3720 #define FW_CRYPTO_LOOKASIDE_WR_LCB_M 0x3 3721 #define FW_CRYPTO_LOOKASIDE_WR_LCB_V(x) \ 3722 ((x) << FW_CRYPTO_LOOKASIDE_WR_LCB_S) 3723 #define FW_CRYPTO_LOOKASIDE_WR_LCB_G(x) \ 3724 (((x) >> FW_CRYPTO_LOOKASIDE_WR_LCB_S) & FW_CRYPTO_LOOKASIDE_WR_LCB_M) 3725 3726 #define FW_CRYPTO_LOOKASIDE_WR_PHASH_S 25 3727 #define FW_CRYPTO_LOOKASIDE_WR_PHASH_M 0x3 3728 #define FW_CRYPTO_LOOKASIDE_WR_PHASH_V(x) \ 3729 ((x) << FW_CRYPTO_LOOKASIDE_WR_PHASH_S) 3730 #define FW_CRYPTO_LOOKASIDE_WR_PHASH_G(x) \ 3731 (((x) >> FW_CRYPTO_LOOKASIDE_WR_PHASH_S) & \ 3732 FW_CRYPTO_LOOKASIDE_WR_PHASH_M) 3733 3734 #define FW_CRYPTO_LOOKASIDE_WR_IV_S 23 3735 #define FW_CRYPTO_LOOKASIDE_WR_IV_M 0x3 3736 #define FW_CRYPTO_LOOKASIDE_WR_IV_V(x) \ 3737 ((x) << FW_CRYPTO_LOOKASIDE_WR_IV_S) 3738 #define FW_CRYPTO_LOOKASIDE_WR_IV_G(x) \ 3739 (((x) >> FW_CRYPTO_LOOKASIDE_WR_IV_S) & FW_CRYPTO_LOOKASIDE_WR_IV_M) 3740 3741 #define FW_CRYPTO_LOOKASIDE_WR_FQIDX_S 15 3742 #define FW_CRYPTO_LOOKASIDE_WR_FQIDX_M 0xff 3743 #define FW_CRYPTO_LOOKASIDE_WR_FQIDX_V(x) \ 3744 ((x) << FW_CRYPTO_LOOKASIDE_WR_FQIDX_S) 3745 #define FW_CRYPTO_LOOKASIDE_WR_FQIDX_G(x) \ 3746 (((x) >> FW_CRYPTO_LOOKASIDE_WR_FQIDX_S) & \ 3747 FW_CRYPTO_LOOKASIDE_WR_FQIDX_M) 3748 3749 #define FW_CRYPTO_LOOKASIDE_WR_TX_CH_S 10 3750 #define FW_CRYPTO_LOOKASIDE_WR_TX_CH_M 0x3 3751 #define FW_CRYPTO_LOOKASIDE_WR_TX_CH_V(x) \ 3752 ((x) << FW_CRYPTO_LOOKASIDE_WR_TX_CH_S) 3753 #define FW_CRYPTO_LOOKASIDE_WR_TX_CH_G(x) \ 3754 (((x) >> FW_CRYPTO_LOOKASIDE_WR_TX_CH_S) & \ 3755 FW_CRYPTO_LOOKASIDE_WR_TX_CH_M) 3756 3757 #define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_S 0 3758 #define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_M 0x3ff 3759 #define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_V(x) \ 3760 ((x) << FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_S) 3761 #define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_G(x) \ 3762 (((x) >> FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_S) & \ 3763 FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_M) 3764 3765 #define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_S 24 3766 #define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_M 0xff 3767 #define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_V(x) \ 3768 ((x) << FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_S) 3769 #define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_G(x) \ 3770 (((x) >> FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_S) & \ 3771 FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_M) 3772 3773 #define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_S 17 3774 #define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_M 0x7f 3775 #define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_V(x) \ 3776 ((x) << FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_S) 3777 #define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_G(x) \ 3778 (((x) >> FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_S) & \ 3779 FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_M) 3780 3781 #endif /* _T4FW_INTERFACE_H_ */ 3782