xref: /linux/drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h (revision bfd5bb6f90af092aa345b15cd78143956a13c2a8)
1 /*
2  * This file is part of the Chelsio T4 Ethernet driver for Linux.
3  *
4  * Copyright (c) 2009-2016 Chelsio Communications, Inc. All rights reserved.
5  *
6  * This software is available to you under a choice of one of two
7  * licenses.  You may choose to be licensed under the terms of the GNU
8  * General Public License (GPL) Version 2, available from the file
9  * COPYING in the main directory of this source tree, or the
10  * OpenIB.org BSD license below:
11  *
12  *     Redistribution and use in source and binary forms, with or
13  *     without modification, are permitted provided that the following
14  *     conditions are met:
15  *
16  *      - Redistributions of source code must retain the above
17  *        copyright notice, this list of conditions and the following
18  *        disclaimer.
19  *
20  *      - Redistributions in binary form must reproduce the above
21  *        copyright notice, this list of conditions and the following
22  *        disclaimer in the documentation and/or other materials
23  *        provided with the distribution.
24  *
25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32  * SOFTWARE.
33  */
34 
35 #ifndef _T4FW_INTERFACE_H_
36 #define _T4FW_INTERFACE_H_
37 
38 enum fw_retval {
39 	FW_SUCCESS		= 0,	/* completed successfully */
40 	FW_EPERM		= 1,	/* operation not permitted */
41 	FW_ENOENT		= 2,	/* no such file or directory */
42 	FW_EIO			= 5,	/* input/output error; hw bad */
43 	FW_ENOEXEC		= 8,	/* exec format error; inv microcode */
44 	FW_EAGAIN		= 11,	/* try again */
45 	FW_ENOMEM		= 12,	/* out of memory */
46 	FW_EFAULT		= 14,	/* bad address; fw bad */
47 	FW_EBUSY		= 16,	/* resource busy */
48 	FW_EEXIST		= 17,	/* file exists */
49 	FW_ENODEV		= 19,	/* no such device */
50 	FW_EINVAL		= 22,	/* invalid argument */
51 	FW_ENOSPC		= 28,	/* no space left on device */
52 	FW_ENOSYS		= 38,	/* functionality not implemented */
53 	FW_ENODATA		= 61,	/* no data available */
54 	FW_EPROTO		= 71,	/* protocol error */
55 	FW_EADDRINUSE		= 98,	/* address already in use */
56 	FW_EADDRNOTAVAIL	= 99,	/* cannot assigned requested address */
57 	FW_ENETDOWN		= 100,	/* network is down */
58 	FW_ENETUNREACH		= 101,	/* network is unreachable */
59 	FW_ENOBUFS		= 105,	/* no buffer space available */
60 	FW_ETIMEDOUT		= 110,	/* timeout */
61 	FW_EINPROGRESS		= 115,	/* fw internal */
62 	FW_SCSI_ABORT_REQUESTED	= 128,	/* */
63 	FW_SCSI_ABORT_TIMEDOUT	= 129,	/* */
64 	FW_SCSI_ABORTED		= 130,	/* */
65 	FW_SCSI_CLOSE_REQUESTED	= 131,	/* */
66 	FW_ERR_LINK_DOWN	= 132,	/* */
67 	FW_RDEV_NOT_READY	= 133,	/* */
68 	FW_ERR_RDEV_LOST	= 134,	/* */
69 	FW_ERR_RDEV_LOGO	= 135,	/* */
70 	FW_FCOE_NO_XCHG		= 136,	/* */
71 	FW_SCSI_RSP_ERR		= 137,	/* */
72 	FW_ERR_RDEV_IMPL_LOGO	= 138,	/* */
73 	FW_SCSI_UNDER_FLOW_ERR  = 139,	/* */
74 	FW_SCSI_OVER_FLOW_ERR   = 140,	/* */
75 	FW_SCSI_DDP_ERR		= 141,	/* DDP error*/
76 	FW_SCSI_TASK_ERR	= 142,	/* No SCSI tasks available */
77 };
78 
79 #define FW_T4VF_SGE_BASE_ADDR      0x0000
80 #define FW_T4VF_MPS_BASE_ADDR      0x0100
81 #define FW_T4VF_PL_BASE_ADDR       0x0200
82 #define FW_T4VF_MBDATA_BASE_ADDR   0x0240
83 #define FW_T4VF_CIM_BASE_ADDR      0x0300
84 
85 enum fw_wr_opcodes {
86 	FW_FILTER_WR                   = 0x02,
87 	FW_ULPTX_WR                    = 0x04,
88 	FW_TP_WR                       = 0x05,
89 	FW_ETH_TX_PKT_WR               = 0x08,
90 	FW_OFLD_CONNECTION_WR          = 0x2f,
91 	FW_FLOWC_WR                    = 0x0a,
92 	FW_OFLD_TX_DATA_WR             = 0x0b,
93 	FW_CMD_WR                      = 0x10,
94 	FW_ETH_TX_PKT_VM_WR            = 0x11,
95 	FW_RI_RES_WR                   = 0x0c,
96 	FW_RI_INIT_WR                  = 0x0d,
97 	FW_RI_RDMA_WRITE_WR            = 0x14,
98 	FW_RI_SEND_WR                  = 0x15,
99 	FW_RI_RDMA_READ_WR             = 0x16,
100 	FW_RI_RECV_WR                  = 0x17,
101 	FW_RI_BIND_MW_WR               = 0x18,
102 	FW_RI_FR_NSMR_WR               = 0x19,
103 	FW_RI_FR_NSMR_TPTE_WR	       = 0x20,
104 	FW_RI_RDMA_WRITE_CMPL_WR       = 0x21,
105 	FW_RI_INV_LSTAG_WR             = 0x1a,
106 	FW_ISCSI_TX_DATA_WR	       = 0x45,
107 	FW_PTP_TX_PKT_WR               = 0x46,
108 	FW_TLSTX_DATA_WR	       = 0x68,
109 	FW_CRYPTO_LOOKASIDE_WR         = 0X6d,
110 	FW_LASTC2E_WR                  = 0x70,
111 	FW_FILTER2_WR		       = 0x77
112 };
113 
114 struct fw_wr_hdr {
115 	__be32 hi;
116 	__be32 lo;
117 };
118 
119 /* work request opcode (hi) */
120 #define FW_WR_OP_S	24
121 #define FW_WR_OP_M      0xff
122 #define FW_WR_OP_V(x)   ((x) << FW_WR_OP_S)
123 #define FW_WR_OP_G(x)   (((x) >> FW_WR_OP_S) & FW_WR_OP_M)
124 
125 /* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER */
126 #define FW_WR_ATOMIC_S		23
127 #define FW_WR_ATOMIC_V(x)	((x) << FW_WR_ATOMIC_S)
128 
129 /* flush flag (hi) - firmware flushes flushable work request buffered
130  * in the flow context.
131  */
132 #define FW_WR_FLUSH_S     22
133 #define FW_WR_FLUSH_V(x)  ((x) << FW_WR_FLUSH_S)
134 
135 /* completion flag (hi) - firmware generates a cpl_fw6_ack */
136 #define FW_WR_COMPL_S     21
137 #define FW_WR_COMPL_V(x)  ((x) << FW_WR_COMPL_S)
138 #define FW_WR_COMPL_F     FW_WR_COMPL_V(1U)
139 
140 /* work request immediate data length (hi) */
141 #define FW_WR_IMMDLEN_S 0
142 #define FW_WR_IMMDLEN_M 0xff
143 #define FW_WR_IMMDLEN_V(x)      ((x) << FW_WR_IMMDLEN_S)
144 
145 /* egress queue status update to associated ingress queue entry (lo) */
146 #define FW_WR_EQUIQ_S           31
147 #define FW_WR_EQUIQ_V(x)        ((x) << FW_WR_EQUIQ_S)
148 #define FW_WR_EQUIQ_F           FW_WR_EQUIQ_V(1U)
149 
150 /* egress queue status update to egress queue status entry (lo) */
151 #define FW_WR_EQUEQ_S           30
152 #define FW_WR_EQUEQ_V(x)        ((x) << FW_WR_EQUEQ_S)
153 #define FW_WR_EQUEQ_F           FW_WR_EQUEQ_V(1U)
154 
155 /* flow context identifier (lo) */
156 #define FW_WR_FLOWID_S          8
157 #define FW_WR_FLOWID_V(x)       ((x) << FW_WR_FLOWID_S)
158 
159 /* length in units of 16-bytes (lo) */
160 #define FW_WR_LEN16_S           0
161 #define FW_WR_LEN16_V(x)        ((x) << FW_WR_LEN16_S)
162 
163 #define HW_TPL_FR_MT_PR_IV_P_FC         0X32B
164 #define HW_TPL_FR_MT_PR_OV_P_FC         0X327
165 
166 /* filter wr reply code in cookie in CPL_SET_TCB_RPL */
167 enum fw_filter_wr_cookie {
168 	FW_FILTER_WR_SUCCESS,
169 	FW_FILTER_WR_FLT_ADDED,
170 	FW_FILTER_WR_FLT_DELETED,
171 	FW_FILTER_WR_SMT_TBL_FULL,
172 	FW_FILTER_WR_EINVAL,
173 };
174 
175 struct fw_filter_wr {
176 	__be32 op_pkd;
177 	__be32 len16_pkd;
178 	__be64 r3;
179 	__be32 tid_to_iq;
180 	__be32 del_filter_to_l2tix;
181 	__be16 ethtype;
182 	__be16 ethtypem;
183 	__u8   frag_to_ovlan_vldm;
184 	__u8   smac_sel;
185 	__be16 rx_chan_rx_rpl_iq;
186 	__be32 maci_to_matchtypem;
187 	__u8   ptcl;
188 	__u8   ptclm;
189 	__u8   ttyp;
190 	__u8   ttypm;
191 	__be16 ivlan;
192 	__be16 ivlanm;
193 	__be16 ovlan;
194 	__be16 ovlanm;
195 	__u8   lip[16];
196 	__u8   lipm[16];
197 	__u8   fip[16];
198 	__u8   fipm[16];
199 	__be16 lp;
200 	__be16 lpm;
201 	__be16 fp;
202 	__be16 fpm;
203 	__be16 r7;
204 	__u8   sma[6];
205 };
206 
207 struct fw_filter2_wr {
208 	__be32 op_pkd;
209 	__be32 len16_pkd;
210 	__be64 r3;
211 	__be32 tid_to_iq;
212 	__be32 del_filter_to_l2tix;
213 	__be16 ethtype;
214 	__be16 ethtypem;
215 	__u8   frag_to_ovlan_vldm;
216 	__u8   smac_sel;
217 	__be16 rx_chan_rx_rpl_iq;
218 	__be32 maci_to_matchtypem;
219 	__u8   ptcl;
220 	__u8   ptclm;
221 	__u8   ttyp;
222 	__u8   ttypm;
223 	__be16 ivlan;
224 	__be16 ivlanm;
225 	__be16 ovlan;
226 	__be16 ovlanm;
227 	__u8   lip[16];
228 	__u8   lipm[16];
229 	__u8   fip[16];
230 	__u8   fipm[16];
231 	__be16 lp;
232 	__be16 lpm;
233 	__be16 fp;
234 	__be16 fpm;
235 	__be16 r7;
236 	__u8   sma[6];
237 	__be16 r8;
238 	__u8   filter_type_swapmac;
239 	__u8   natmode_to_ulp_type;
240 	__be16 newlport;
241 	__be16 newfport;
242 	__u8   newlip[16];
243 	__u8   newfip[16];
244 	__be32 natseqcheck;
245 	__be32 r9;
246 	__be64 r10;
247 	__be64 r11;
248 	__be64 r12;
249 	__be64 r13;
250 };
251 
252 #define FW_FILTER_WR_TID_S      12
253 #define FW_FILTER_WR_TID_M      0xfffff
254 #define FW_FILTER_WR_TID_V(x)   ((x) << FW_FILTER_WR_TID_S)
255 #define FW_FILTER_WR_TID_G(x)   \
256 	(((x) >> FW_FILTER_WR_TID_S) & FW_FILTER_WR_TID_M)
257 
258 #define FW_FILTER_WR_RQTYPE_S           11
259 #define FW_FILTER_WR_RQTYPE_M           0x1
260 #define FW_FILTER_WR_RQTYPE_V(x)        ((x) << FW_FILTER_WR_RQTYPE_S)
261 #define FW_FILTER_WR_RQTYPE_G(x)        \
262 	(((x) >> FW_FILTER_WR_RQTYPE_S) & FW_FILTER_WR_RQTYPE_M)
263 #define FW_FILTER_WR_RQTYPE_F   FW_FILTER_WR_RQTYPE_V(1U)
264 
265 #define FW_FILTER_WR_NOREPLY_S          10
266 #define FW_FILTER_WR_NOREPLY_M          0x1
267 #define FW_FILTER_WR_NOREPLY_V(x)       ((x) << FW_FILTER_WR_NOREPLY_S)
268 #define FW_FILTER_WR_NOREPLY_G(x)       \
269 	(((x) >> FW_FILTER_WR_NOREPLY_S) & FW_FILTER_WR_NOREPLY_M)
270 #define FW_FILTER_WR_NOREPLY_F  FW_FILTER_WR_NOREPLY_V(1U)
271 
272 #define FW_FILTER_WR_IQ_S       0
273 #define FW_FILTER_WR_IQ_M       0x3ff
274 #define FW_FILTER_WR_IQ_V(x)    ((x) << FW_FILTER_WR_IQ_S)
275 #define FW_FILTER_WR_IQ_G(x)    \
276 	(((x) >> FW_FILTER_WR_IQ_S) & FW_FILTER_WR_IQ_M)
277 
278 #define FW_FILTER_WR_DEL_FILTER_S       31
279 #define FW_FILTER_WR_DEL_FILTER_M       0x1
280 #define FW_FILTER_WR_DEL_FILTER_V(x)    ((x) << FW_FILTER_WR_DEL_FILTER_S)
281 #define FW_FILTER_WR_DEL_FILTER_G(x)    \
282 	(((x) >> FW_FILTER_WR_DEL_FILTER_S) & FW_FILTER_WR_DEL_FILTER_M)
283 #define FW_FILTER_WR_DEL_FILTER_F       FW_FILTER_WR_DEL_FILTER_V(1U)
284 
285 #define FW_FILTER_WR_RPTTID_S           25
286 #define FW_FILTER_WR_RPTTID_M           0x1
287 #define FW_FILTER_WR_RPTTID_V(x)        ((x) << FW_FILTER_WR_RPTTID_S)
288 #define FW_FILTER_WR_RPTTID_G(x)        \
289 	(((x) >> FW_FILTER_WR_RPTTID_S) & FW_FILTER_WR_RPTTID_M)
290 #define FW_FILTER_WR_RPTTID_F   FW_FILTER_WR_RPTTID_V(1U)
291 
292 #define FW_FILTER_WR_DROP_S     24
293 #define FW_FILTER_WR_DROP_M     0x1
294 #define FW_FILTER_WR_DROP_V(x)  ((x) << FW_FILTER_WR_DROP_S)
295 #define FW_FILTER_WR_DROP_G(x)  \
296 	(((x) >> FW_FILTER_WR_DROP_S) & FW_FILTER_WR_DROP_M)
297 #define FW_FILTER_WR_DROP_F     FW_FILTER_WR_DROP_V(1U)
298 
299 #define FW_FILTER_WR_DIRSTEER_S         23
300 #define FW_FILTER_WR_DIRSTEER_M         0x1
301 #define FW_FILTER_WR_DIRSTEER_V(x)      ((x) << FW_FILTER_WR_DIRSTEER_S)
302 #define FW_FILTER_WR_DIRSTEER_G(x)      \
303 	(((x) >> FW_FILTER_WR_DIRSTEER_S) & FW_FILTER_WR_DIRSTEER_M)
304 #define FW_FILTER_WR_DIRSTEER_F FW_FILTER_WR_DIRSTEER_V(1U)
305 
306 #define FW_FILTER_WR_MASKHASH_S         22
307 #define FW_FILTER_WR_MASKHASH_M         0x1
308 #define FW_FILTER_WR_MASKHASH_V(x)      ((x) << FW_FILTER_WR_MASKHASH_S)
309 #define FW_FILTER_WR_MASKHASH_G(x)      \
310 	(((x) >> FW_FILTER_WR_MASKHASH_S) & FW_FILTER_WR_MASKHASH_M)
311 #define FW_FILTER_WR_MASKHASH_F FW_FILTER_WR_MASKHASH_V(1U)
312 
313 #define FW_FILTER_WR_DIRSTEERHASH_S     21
314 #define FW_FILTER_WR_DIRSTEERHASH_M     0x1
315 #define FW_FILTER_WR_DIRSTEERHASH_V(x)  ((x) << FW_FILTER_WR_DIRSTEERHASH_S)
316 #define FW_FILTER_WR_DIRSTEERHASH_G(x)  \
317 	(((x) >> FW_FILTER_WR_DIRSTEERHASH_S) & FW_FILTER_WR_DIRSTEERHASH_M)
318 #define FW_FILTER_WR_DIRSTEERHASH_F     FW_FILTER_WR_DIRSTEERHASH_V(1U)
319 
320 #define FW_FILTER_WR_LPBK_S     20
321 #define FW_FILTER_WR_LPBK_M     0x1
322 #define FW_FILTER_WR_LPBK_V(x)  ((x) << FW_FILTER_WR_LPBK_S)
323 #define FW_FILTER_WR_LPBK_G(x)  \
324 	(((x) >> FW_FILTER_WR_LPBK_S) & FW_FILTER_WR_LPBK_M)
325 #define FW_FILTER_WR_LPBK_F     FW_FILTER_WR_LPBK_V(1U)
326 
327 #define FW_FILTER_WR_DMAC_S     19
328 #define FW_FILTER_WR_DMAC_M     0x1
329 #define FW_FILTER_WR_DMAC_V(x)  ((x) << FW_FILTER_WR_DMAC_S)
330 #define FW_FILTER_WR_DMAC_G(x)  \
331 	(((x) >> FW_FILTER_WR_DMAC_S) & FW_FILTER_WR_DMAC_M)
332 #define FW_FILTER_WR_DMAC_F     FW_FILTER_WR_DMAC_V(1U)
333 
334 #define FW_FILTER_WR_SMAC_S     18
335 #define FW_FILTER_WR_SMAC_M     0x1
336 #define FW_FILTER_WR_SMAC_V(x)  ((x) << FW_FILTER_WR_SMAC_S)
337 #define FW_FILTER_WR_SMAC_G(x)  \
338 	(((x) >> FW_FILTER_WR_SMAC_S) & FW_FILTER_WR_SMAC_M)
339 #define FW_FILTER_WR_SMAC_F     FW_FILTER_WR_SMAC_V(1U)
340 
341 #define FW_FILTER_WR_INSVLAN_S          17
342 #define FW_FILTER_WR_INSVLAN_M          0x1
343 #define FW_FILTER_WR_INSVLAN_V(x)       ((x) << FW_FILTER_WR_INSVLAN_S)
344 #define FW_FILTER_WR_INSVLAN_G(x)       \
345 	(((x) >> FW_FILTER_WR_INSVLAN_S) & FW_FILTER_WR_INSVLAN_M)
346 #define FW_FILTER_WR_INSVLAN_F  FW_FILTER_WR_INSVLAN_V(1U)
347 
348 #define FW_FILTER_WR_RMVLAN_S           16
349 #define FW_FILTER_WR_RMVLAN_M           0x1
350 #define FW_FILTER_WR_RMVLAN_V(x)        ((x) << FW_FILTER_WR_RMVLAN_S)
351 #define FW_FILTER_WR_RMVLAN_G(x)        \
352 	(((x) >> FW_FILTER_WR_RMVLAN_S) & FW_FILTER_WR_RMVLAN_M)
353 #define FW_FILTER_WR_RMVLAN_F   FW_FILTER_WR_RMVLAN_V(1U)
354 
355 #define FW_FILTER_WR_HITCNTS_S          15
356 #define FW_FILTER_WR_HITCNTS_M          0x1
357 #define FW_FILTER_WR_HITCNTS_V(x)       ((x) << FW_FILTER_WR_HITCNTS_S)
358 #define FW_FILTER_WR_HITCNTS_G(x)       \
359 	(((x) >> FW_FILTER_WR_HITCNTS_S) & FW_FILTER_WR_HITCNTS_M)
360 #define FW_FILTER_WR_HITCNTS_F  FW_FILTER_WR_HITCNTS_V(1U)
361 
362 #define FW_FILTER_WR_TXCHAN_S           13
363 #define FW_FILTER_WR_TXCHAN_M           0x3
364 #define FW_FILTER_WR_TXCHAN_V(x)        ((x) << FW_FILTER_WR_TXCHAN_S)
365 #define FW_FILTER_WR_TXCHAN_G(x)        \
366 	(((x) >> FW_FILTER_WR_TXCHAN_S) & FW_FILTER_WR_TXCHAN_M)
367 
368 #define FW_FILTER_WR_PRIO_S     12
369 #define FW_FILTER_WR_PRIO_M     0x1
370 #define FW_FILTER_WR_PRIO_V(x)  ((x) << FW_FILTER_WR_PRIO_S)
371 #define FW_FILTER_WR_PRIO_G(x)  \
372 	(((x) >> FW_FILTER_WR_PRIO_S) & FW_FILTER_WR_PRIO_M)
373 #define FW_FILTER_WR_PRIO_F     FW_FILTER_WR_PRIO_V(1U)
374 
375 #define FW_FILTER_WR_L2TIX_S    0
376 #define FW_FILTER_WR_L2TIX_M    0xfff
377 #define FW_FILTER_WR_L2TIX_V(x) ((x) << FW_FILTER_WR_L2TIX_S)
378 #define FW_FILTER_WR_L2TIX_G(x) \
379 	(((x) >> FW_FILTER_WR_L2TIX_S) & FW_FILTER_WR_L2TIX_M)
380 
381 #define FW_FILTER_WR_FRAG_S     7
382 #define FW_FILTER_WR_FRAG_M     0x1
383 #define FW_FILTER_WR_FRAG_V(x)  ((x) << FW_FILTER_WR_FRAG_S)
384 #define FW_FILTER_WR_FRAG_G(x)  \
385 	(((x) >> FW_FILTER_WR_FRAG_S) & FW_FILTER_WR_FRAG_M)
386 #define FW_FILTER_WR_FRAG_F     FW_FILTER_WR_FRAG_V(1U)
387 
388 #define FW_FILTER_WR_FRAGM_S    6
389 #define FW_FILTER_WR_FRAGM_M    0x1
390 #define FW_FILTER_WR_FRAGM_V(x) ((x) << FW_FILTER_WR_FRAGM_S)
391 #define FW_FILTER_WR_FRAGM_G(x) \
392 	(((x) >> FW_FILTER_WR_FRAGM_S) & FW_FILTER_WR_FRAGM_M)
393 #define FW_FILTER_WR_FRAGM_F    FW_FILTER_WR_FRAGM_V(1U)
394 
395 #define FW_FILTER_WR_IVLAN_VLD_S        5
396 #define FW_FILTER_WR_IVLAN_VLD_M        0x1
397 #define FW_FILTER_WR_IVLAN_VLD_V(x)     ((x) << FW_FILTER_WR_IVLAN_VLD_S)
398 #define FW_FILTER_WR_IVLAN_VLD_G(x)     \
399 	(((x) >> FW_FILTER_WR_IVLAN_VLD_S) & FW_FILTER_WR_IVLAN_VLD_M)
400 #define FW_FILTER_WR_IVLAN_VLD_F        FW_FILTER_WR_IVLAN_VLD_V(1U)
401 
402 #define FW_FILTER_WR_OVLAN_VLD_S        4
403 #define FW_FILTER_WR_OVLAN_VLD_M        0x1
404 #define FW_FILTER_WR_OVLAN_VLD_V(x)     ((x) << FW_FILTER_WR_OVLAN_VLD_S)
405 #define FW_FILTER_WR_OVLAN_VLD_G(x)     \
406 	(((x) >> FW_FILTER_WR_OVLAN_VLD_S) & FW_FILTER_WR_OVLAN_VLD_M)
407 #define FW_FILTER_WR_OVLAN_VLD_F        FW_FILTER_WR_OVLAN_VLD_V(1U)
408 
409 #define FW_FILTER_WR_IVLAN_VLDM_S       3
410 #define FW_FILTER_WR_IVLAN_VLDM_M       0x1
411 #define FW_FILTER_WR_IVLAN_VLDM_V(x)    ((x) << FW_FILTER_WR_IVLAN_VLDM_S)
412 #define FW_FILTER_WR_IVLAN_VLDM_G(x)    \
413 	(((x) >> FW_FILTER_WR_IVLAN_VLDM_S) & FW_FILTER_WR_IVLAN_VLDM_M)
414 #define FW_FILTER_WR_IVLAN_VLDM_F       FW_FILTER_WR_IVLAN_VLDM_V(1U)
415 
416 #define FW_FILTER_WR_OVLAN_VLDM_S       2
417 #define FW_FILTER_WR_OVLAN_VLDM_M       0x1
418 #define FW_FILTER_WR_OVLAN_VLDM_V(x)    ((x) << FW_FILTER_WR_OVLAN_VLDM_S)
419 #define FW_FILTER_WR_OVLAN_VLDM_G(x)    \
420 	(((x) >> FW_FILTER_WR_OVLAN_VLDM_S) & FW_FILTER_WR_OVLAN_VLDM_M)
421 #define FW_FILTER_WR_OVLAN_VLDM_F       FW_FILTER_WR_OVLAN_VLDM_V(1U)
422 
423 #define FW_FILTER_WR_RX_CHAN_S          15
424 #define FW_FILTER_WR_RX_CHAN_M          0x1
425 #define FW_FILTER_WR_RX_CHAN_V(x)       ((x) << FW_FILTER_WR_RX_CHAN_S)
426 #define FW_FILTER_WR_RX_CHAN_G(x)       \
427 	(((x) >> FW_FILTER_WR_RX_CHAN_S) & FW_FILTER_WR_RX_CHAN_M)
428 #define FW_FILTER_WR_RX_CHAN_F  FW_FILTER_WR_RX_CHAN_V(1U)
429 
430 #define FW_FILTER_WR_RX_RPL_IQ_S        0
431 #define FW_FILTER_WR_RX_RPL_IQ_M        0x3ff
432 #define FW_FILTER_WR_RX_RPL_IQ_V(x)     ((x) << FW_FILTER_WR_RX_RPL_IQ_S)
433 #define FW_FILTER_WR_RX_RPL_IQ_G(x)     \
434 	(((x) >> FW_FILTER_WR_RX_RPL_IQ_S) & FW_FILTER_WR_RX_RPL_IQ_M)
435 
436 #define FW_FILTER2_WR_FILTER_TYPE_S	1
437 #define FW_FILTER2_WR_FILTER_TYPE_M	0x1
438 #define FW_FILTER2_WR_FILTER_TYPE_V(x)	((x) << FW_FILTER2_WR_FILTER_TYPE_S)
439 #define FW_FILTER2_WR_FILTER_TYPE_G(x)  \
440 	(((x) >> FW_FILTER2_WR_FILTER_TYPE_S) & FW_FILTER2_WR_FILTER_TYPE_M)
441 #define FW_FILTER2_WR_FILTER_TYPE_F	FW_FILTER2_WR_FILTER_TYPE_V(1U)
442 
443 #define FW_FILTER2_WR_NATMODE_S		5
444 #define FW_FILTER2_WR_NATMODE_M		0x7
445 #define FW_FILTER2_WR_NATMODE_V(x)	((x) << FW_FILTER2_WR_NATMODE_S)
446 #define FW_FILTER2_WR_NATMODE_G(x)      \
447 	(((x) >> FW_FILTER2_WR_NATMODE_S) & FW_FILTER2_WR_NATMODE_M)
448 
449 #define FW_FILTER2_WR_NATFLAGCHECK_S	4
450 #define FW_FILTER2_WR_NATFLAGCHECK_M	0x1
451 #define FW_FILTER2_WR_NATFLAGCHECK_V(x)	((x) << FW_FILTER2_WR_NATFLAGCHECK_S)
452 #define FW_FILTER2_WR_NATFLAGCHECK_G(x) \
453 	(((x) >> FW_FILTER2_WR_NATFLAGCHECK_S) & FW_FILTER2_WR_NATFLAGCHECK_M)
454 #define FW_FILTER2_WR_NATFLAGCHECK_F	FW_FILTER2_WR_NATFLAGCHECK_V(1U)
455 
456 #define FW_FILTER2_WR_ULP_TYPE_S	0
457 #define FW_FILTER2_WR_ULP_TYPE_M	0xf
458 #define FW_FILTER2_WR_ULP_TYPE_V(x)	((x) << FW_FILTER2_WR_ULP_TYPE_S)
459 #define FW_FILTER2_WR_ULP_TYPE_G(x)     \
460 	(((x) >> FW_FILTER2_WR_ULP_TYPE_S) & FW_FILTER2_WR_ULP_TYPE_M)
461 
462 #define FW_FILTER_WR_MACI_S     23
463 #define FW_FILTER_WR_MACI_M     0x1ff
464 #define FW_FILTER_WR_MACI_V(x)  ((x) << FW_FILTER_WR_MACI_S)
465 #define FW_FILTER_WR_MACI_G(x)  \
466 	(((x) >> FW_FILTER_WR_MACI_S) & FW_FILTER_WR_MACI_M)
467 
468 #define FW_FILTER_WR_MACIM_S    14
469 #define FW_FILTER_WR_MACIM_M    0x1ff
470 #define FW_FILTER_WR_MACIM_V(x) ((x) << FW_FILTER_WR_MACIM_S)
471 #define FW_FILTER_WR_MACIM_G(x) \
472 	(((x) >> FW_FILTER_WR_MACIM_S) & FW_FILTER_WR_MACIM_M)
473 
474 #define FW_FILTER_WR_FCOE_S     13
475 #define FW_FILTER_WR_FCOE_M     0x1
476 #define FW_FILTER_WR_FCOE_V(x)  ((x) << FW_FILTER_WR_FCOE_S)
477 #define FW_FILTER_WR_FCOE_G(x)  \
478 	(((x) >> FW_FILTER_WR_FCOE_S) & FW_FILTER_WR_FCOE_M)
479 #define FW_FILTER_WR_FCOE_F     FW_FILTER_WR_FCOE_V(1U)
480 
481 #define FW_FILTER_WR_FCOEM_S    12
482 #define FW_FILTER_WR_FCOEM_M    0x1
483 #define FW_FILTER_WR_FCOEM_V(x) ((x) << FW_FILTER_WR_FCOEM_S)
484 #define FW_FILTER_WR_FCOEM_G(x) \
485 	(((x) >> FW_FILTER_WR_FCOEM_S) & FW_FILTER_WR_FCOEM_M)
486 #define FW_FILTER_WR_FCOEM_F    FW_FILTER_WR_FCOEM_V(1U)
487 
488 #define FW_FILTER_WR_PORT_S     9
489 #define FW_FILTER_WR_PORT_M     0x7
490 #define FW_FILTER_WR_PORT_V(x)  ((x) << FW_FILTER_WR_PORT_S)
491 #define FW_FILTER_WR_PORT_G(x)  \
492 	(((x) >> FW_FILTER_WR_PORT_S) & FW_FILTER_WR_PORT_M)
493 
494 #define FW_FILTER_WR_PORTM_S    6
495 #define FW_FILTER_WR_PORTM_M    0x7
496 #define FW_FILTER_WR_PORTM_V(x) ((x) << FW_FILTER_WR_PORTM_S)
497 #define FW_FILTER_WR_PORTM_G(x) \
498 	(((x) >> FW_FILTER_WR_PORTM_S) & FW_FILTER_WR_PORTM_M)
499 
500 #define FW_FILTER_WR_MATCHTYPE_S        3
501 #define FW_FILTER_WR_MATCHTYPE_M        0x7
502 #define FW_FILTER_WR_MATCHTYPE_V(x)     ((x) << FW_FILTER_WR_MATCHTYPE_S)
503 #define FW_FILTER_WR_MATCHTYPE_G(x)     \
504 	(((x) >> FW_FILTER_WR_MATCHTYPE_S) & FW_FILTER_WR_MATCHTYPE_M)
505 
506 #define FW_FILTER_WR_MATCHTYPEM_S       0
507 #define FW_FILTER_WR_MATCHTYPEM_M       0x7
508 #define FW_FILTER_WR_MATCHTYPEM_V(x)    ((x) << FW_FILTER_WR_MATCHTYPEM_S)
509 #define FW_FILTER_WR_MATCHTYPEM_G(x)    \
510 	(((x) >> FW_FILTER_WR_MATCHTYPEM_S) & FW_FILTER_WR_MATCHTYPEM_M)
511 
512 struct fw_ulptx_wr {
513 	__be32 op_to_compl;
514 	__be32 flowid_len16;
515 	u64 cookie;
516 };
517 
518 #define FW_ULPTX_WR_DATA_S      28
519 #define FW_ULPTX_WR_DATA_M      0x1
520 #define FW_ULPTX_WR_DATA_V(x)   ((x) << FW_ULPTX_WR_DATA_S)
521 #define FW_ULPTX_WR_DATA_G(x)   \
522 	(((x) >> FW_ULPTX_WR_DATA_S) & FW_ULPTX_WR_DATA_M)
523 #define FW_ULPTX_WR_DATA_F      FW_ULPTX_WR_DATA_V(1U)
524 
525 struct fw_tp_wr {
526 	__be32 op_to_immdlen;
527 	__be32 flowid_len16;
528 	u64 cookie;
529 };
530 
531 struct fw_eth_tx_pkt_wr {
532 	__be32 op_immdlen;
533 	__be32 equiq_to_len16;
534 	__be64 r3;
535 };
536 
537 struct fw_ofld_connection_wr {
538 	__be32 op_compl;
539 	__be32 len16_pkd;
540 	__u64  cookie;
541 	__be64 r2;
542 	__be64 r3;
543 	struct fw_ofld_connection_le {
544 		__be32 version_cpl;
545 		__be32 filter;
546 		__be32 r1;
547 		__be16 lport;
548 		__be16 pport;
549 		union fw_ofld_connection_leip {
550 			struct fw_ofld_connection_le_ipv4 {
551 				__be32 pip;
552 				__be32 lip;
553 				__be64 r0;
554 				__be64 r1;
555 				__be64 r2;
556 			} ipv4;
557 			struct fw_ofld_connection_le_ipv6 {
558 				__be64 pip_hi;
559 				__be64 pip_lo;
560 				__be64 lip_hi;
561 				__be64 lip_lo;
562 			} ipv6;
563 		} u;
564 	} le;
565 	struct fw_ofld_connection_tcb {
566 		__be32 t_state_to_astid;
567 		__be16 cplrxdataack_cplpassacceptrpl;
568 		__be16 rcv_adv;
569 		__be32 rcv_nxt;
570 		__be32 tx_max;
571 		__be64 opt0;
572 		__be32 opt2;
573 		__be32 r1;
574 		__be64 r2;
575 		__be64 r3;
576 	} tcb;
577 };
578 
579 #define FW_OFLD_CONNECTION_WR_VERSION_S                31
580 #define FW_OFLD_CONNECTION_WR_VERSION_M                0x1
581 #define FW_OFLD_CONNECTION_WR_VERSION_V(x)     \
582 	((x) << FW_OFLD_CONNECTION_WR_VERSION_S)
583 #define FW_OFLD_CONNECTION_WR_VERSION_G(x)     \
584 	(((x) >> FW_OFLD_CONNECTION_WR_VERSION_S) & \
585 	FW_OFLD_CONNECTION_WR_VERSION_M)
586 #define FW_OFLD_CONNECTION_WR_VERSION_F        \
587 	FW_OFLD_CONNECTION_WR_VERSION_V(1U)
588 
589 #define FW_OFLD_CONNECTION_WR_CPL_S    30
590 #define FW_OFLD_CONNECTION_WR_CPL_M    0x1
591 #define FW_OFLD_CONNECTION_WR_CPL_V(x) ((x) << FW_OFLD_CONNECTION_WR_CPL_S)
592 #define FW_OFLD_CONNECTION_WR_CPL_G(x) \
593 	(((x) >> FW_OFLD_CONNECTION_WR_CPL_S) & FW_OFLD_CONNECTION_WR_CPL_M)
594 #define FW_OFLD_CONNECTION_WR_CPL_F    FW_OFLD_CONNECTION_WR_CPL_V(1U)
595 
596 #define FW_OFLD_CONNECTION_WR_T_STATE_S                28
597 #define FW_OFLD_CONNECTION_WR_T_STATE_M                0xf
598 #define FW_OFLD_CONNECTION_WR_T_STATE_V(x)     \
599 	((x) << FW_OFLD_CONNECTION_WR_T_STATE_S)
600 #define FW_OFLD_CONNECTION_WR_T_STATE_G(x)     \
601 	(((x) >> FW_OFLD_CONNECTION_WR_T_STATE_S) & \
602 	FW_OFLD_CONNECTION_WR_T_STATE_M)
603 
604 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_S      24
605 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_M      0xf
606 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_V(x)   \
607 	((x) << FW_OFLD_CONNECTION_WR_RCV_SCALE_S)
608 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_G(x)   \
609 	(((x) >> FW_OFLD_CONNECTION_WR_RCV_SCALE_S) & \
610 	FW_OFLD_CONNECTION_WR_RCV_SCALE_M)
611 
612 #define FW_OFLD_CONNECTION_WR_ASTID_S          0
613 #define FW_OFLD_CONNECTION_WR_ASTID_M          0xffffff
614 #define FW_OFLD_CONNECTION_WR_ASTID_V(x)       \
615 	((x) << FW_OFLD_CONNECTION_WR_ASTID_S)
616 #define FW_OFLD_CONNECTION_WR_ASTID_G(x)       \
617 	(((x) >> FW_OFLD_CONNECTION_WR_ASTID_S) & FW_OFLD_CONNECTION_WR_ASTID_M)
618 
619 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S   15
620 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_M   0x1
621 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_V(x)        \
622 	((x) << FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S)
623 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_G(x)        \
624 	(((x) >> FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S) & \
625 	FW_OFLD_CONNECTION_WR_CPLRXDATAACK_M)
626 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_F   \
627 	FW_OFLD_CONNECTION_WR_CPLRXDATAACK_V(1U)
628 
629 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S       14
630 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_M       0x1
631 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_V(x)    \
632 	((x) << FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S)
633 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_G(x)    \
634 	(((x) >> FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S) & \
635 	FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_M)
636 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_F       \
637 	FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_V(1U)
638 
639 enum fw_flowc_mnem_tcpstate {
640 	FW_FLOWC_MNEM_TCPSTATE_CLOSED   = 0, /* illegal */
641 	FW_FLOWC_MNEM_TCPSTATE_LISTEN   = 1, /* illegal */
642 	FW_FLOWC_MNEM_TCPSTATE_SYNSENT  = 2, /* illegal */
643 	FW_FLOWC_MNEM_TCPSTATE_SYNRECEIVED = 3, /* illegal */
644 	FW_FLOWC_MNEM_TCPSTATE_ESTABLISHED = 4, /* default */
645 	FW_FLOWC_MNEM_TCPSTATE_CLOSEWAIT = 5, /* got peer close already */
646 	FW_FLOWC_MNEM_TCPSTATE_FINWAIT1 = 6, /* haven't gotten ACK for FIN and
647 					      * will resend FIN - equiv ESTAB
648 					      */
649 	FW_FLOWC_MNEM_TCPSTATE_CLOSING  = 7, /* haven't gotten ACK for FIN and
650 					      * will resend FIN but have
651 					      * received FIN
652 					      */
653 	FW_FLOWC_MNEM_TCPSTATE_LASTACK  = 8, /* haven't gotten ACK for FIN and
654 					      * will resend FIN but have
655 					      * received FIN
656 					      */
657 	FW_FLOWC_MNEM_TCPSTATE_FINWAIT2 = 9, /* sent FIN and got FIN + ACK,
658 					      * waiting for FIN
659 					      */
660 	FW_FLOWC_MNEM_TCPSTATE_TIMEWAIT = 10, /* not expected */
661 };
662 
663 enum fw_flowc_mnem {
664 	FW_FLOWC_MNEM_PFNVFN,		/* PFN [15:8] VFN [7:0] */
665 	FW_FLOWC_MNEM_CH,
666 	FW_FLOWC_MNEM_PORT,
667 	FW_FLOWC_MNEM_IQID,
668 	FW_FLOWC_MNEM_SNDNXT,
669 	FW_FLOWC_MNEM_RCVNXT,
670 	FW_FLOWC_MNEM_SNDBUF,
671 	FW_FLOWC_MNEM_MSS,
672 	FW_FLOWC_MNEM_TXDATAPLEN_MAX,
673 	FW_FLOWC_MNEM_TCPSTATE,
674 	FW_FLOWC_MNEM_EOSTATE,
675 	FW_FLOWC_MNEM_SCHEDCLASS,
676 	FW_FLOWC_MNEM_DCBPRIO,
677 	FW_FLOWC_MNEM_SND_SCALE,
678 	FW_FLOWC_MNEM_RCV_SCALE,
679 	FW_FLOWC_MNEM_ULD_MODE,
680 	FW_FLOWC_MNEM_MAX,
681 };
682 
683 struct fw_flowc_mnemval {
684 	u8 mnemonic;
685 	u8 r4[3];
686 	__be32 val;
687 };
688 
689 struct fw_flowc_wr {
690 	__be32 op_to_nparams;
691 	__be32 flowid_len16;
692 	struct fw_flowc_mnemval mnemval[0];
693 };
694 
695 #define FW_FLOWC_WR_NPARAMS_S           0
696 #define FW_FLOWC_WR_NPARAMS_V(x)        ((x) << FW_FLOWC_WR_NPARAMS_S)
697 
698 struct fw_ofld_tx_data_wr {
699 	__be32 op_to_immdlen;
700 	__be32 flowid_len16;
701 	__be32 plen;
702 	__be32 tunnel_to_proxy;
703 };
704 
705 #define FW_OFLD_TX_DATA_WR_ALIGNPLD_S   30
706 #define FW_OFLD_TX_DATA_WR_ALIGNPLD_V(x) ((x) << FW_OFLD_TX_DATA_WR_ALIGNPLD_S)
707 #define FW_OFLD_TX_DATA_WR_ALIGNPLD_F   FW_OFLD_TX_DATA_WR_ALIGNPLD_V(1U)
708 
709 #define FW_OFLD_TX_DATA_WR_SHOVE_S      29
710 #define FW_OFLD_TX_DATA_WR_SHOVE_V(x)   ((x) << FW_OFLD_TX_DATA_WR_SHOVE_S)
711 #define FW_OFLD_TX_DATA_WR_SHOVE_F      FW_OFLD_TX_DATA_WR_SHOVE_V(1U)
712 
713 #define FW_OFLD_TX_DATA_WR_TUNNEL_S     19
714 #define FW_OFLD_TX_DATA_WR_TUNNEL_V(x)  ((x) << FW_OFLD_TX_DATA_WR_TUNNEL_S)
715 
716 #define FW_OFLD_TX_DATA_WR_SAVE_S       18
717 #define FW_OFLD_TX_DATA_WR_SAVE_V(x)    ((x) << FW_OFLD_TX_DATA_WR_SAVE_S)
718 
719 #define FW_OFLD_TX_DATA_WR_FLUSH_S      17
720 #define FW_OFLD_TX_DATA_WR_FLUSH_V(x)   ((x) << FW_OFLD_TX_DATA_WR_FLUSH_S)
721 #define FW_OFLD_TX_DATA_WR_FLUSH_F      FW_OFLD_TX_DATA_WR_FLUSH_V(1U)
722 
723 #define FW_OFLD_TX_DATA_WR_URGENT_S     16
724 #define FW_OFLD_TX_DATA_WR_URGENT_V(x)  ((x) << FW_OFLD_TX_DATA_WR_URGENT_S)
725 
726 #define FW_OFLD_TX_DATA_WR_MORE_S       15
727 #define FW_OFLD_TX_DATA_WR_MORE_V(x)    ((x) << FW_OFLD_TX_DATA_WR_MORE_S)
728 
729 #define FW_OFLD_TX_DATA_WR_ULPMODE_S    10
730 #define FW_OFLD_TX_DATA_WR_ULPMODE_V(x) ((x) << FW_OFLD_TX_DATA_WR_ULPMODE_S)
731 
732 #define FW_OFLD_TX_DATA_WR_ULPSUBMODE_S         6
733 #define FW_OFLD_TX_DATA_WR_ULPSUBMODE_V(x)      \
734 	((x) << FW_OFLD_TX_DATA_WR_ULPSUBMODE_S)
735 
736 struct fw_cmd_wr {
737 	__be32 op_dma;
738 	__be32 len16_pkd;
739 	__be64 cookie_daddr;
740 };
741 
742 #define FW_CMD_WR_DMA_S         17
743 #define FW_CMD_WR_DMA_V(x)      ((x) << FW_CMD_WR_DMA_S)
744 
745 struct fw_eth_tx_pkt_vm_wr {
746 	__be32 op_immdlen;
747 	__be32 equiq_to_len16;
748 	__be32 r3[2];
749 	u8 ethmacdst[6];
750 	u8 ethmacsrc[6];
751 	__be16 ethtype;
752 	__be16 vlantci;
753 };
754 
755 #define FW_CMD_MAX_TIMEOUT 10000
756 
757 /*
758  * If a host driver does a HELLO and discovers that there's already a MASTER
759  * selected, we may have to wait for that MASTER to finish issuing RESET,
760  * configuration and INITIALIZE commands.  Also, there's a possibility that
761  * our own HELLO may get lost if it happens right as the MASTER is issuign a
762  * RESET command, so we need to be willing to make a few retries of our HELLO.
763  */
764 #define FW_CMD_HELLO_TIMEOUT	(3 * FW_CMD_MAX_TIMEOUT)
765 #define FW_CMD_HELLO_RETRIES	3
766 
767 
768 enum fw_cmd_opcodes {
769 	FW_LDST_CMD                    = 0x01,
770 	FW_RESET_CMD                   = 0x03,
771 	FW_HELLO_CMD                   = 0x04,
772 	FW_BYE_CMD                     = 0x05,
773 	FW_INITIALIZE_CMD              = 0x06,
774 	FW_CAPS_CONFIG_CMD             = 0x07,
775 	FW_PARAMS_CMD                  = 0x08,
776 	FW_PFVF_CMD                    = 0x09,
777 	FW_IQ_CMD                      = 0x10,
778 	FW_EQ_MNGT_CMD                 = 0x11,
779 	FW_EQ_ETH_CMD                  = 0x12,
780 	FW_EQ_CTRL_CMD                 = 0x13,
781 	FW_EQ_OFLD_CMD                 = 0x21,
782 	FW_VI_CMD                      = 0x14,
783 	FW_VI_MAC_CMD                  = 0x15,
784 	FW_VI_RXMODE_CMD               = 0x16,
785 	FW_VI_ENABLE_CMD               = 0x17,
786 	FW_ACL_MAC_CMD                 = 0x18,
787 	FW_ACL_VLAN_CMD                = 0x19,
788 	FW_VI_STATS_CMD                = 0x1a,
789 	FW_PORT_CMD                    = 0x1b,
790 	FW_PORT_STATS_CMD              = 0x1c,
791 	FW_PORT_LB_STATS_CMD           = 0x1d,
792 	FW_PORT_TRACE_CMD              = 0x1e,
793 	FW_PORT_TRACE_MMAP_CMD         = 0x1f,
794 	FW_RSS_IND_TBL_CMD             = 0x20,
795 	FW_RSS_GLB_CONFIG_CMD          = 0x22,
796 	FW_RSS_VI_CONFIG_CMD           = 0x23,
797 	FW_SCHED_CMD                   = 0x24,
798 	FW_DEVLOG_CMD                  = 0x25,
799 	FW_CLIP_CMD                    = 0x28,
800 	FW_PTP_CMD                     = 0x3e,
801 	FW_HMA_CMD                     = 0x3f,
802 	FW_LASTC2E_CMD                 = 0x40,
803 	FW_ERROR_CMD                   = 0x80,
804 	FW_DEBUG_CMD                   = 0x81,
805 };
806 
807 enum fw_cmd_cap {
808 	FW_CMD_CAP_PF                  = 0x01,
809 	FW_CMD_CAP_DMAQ                = 0x02,
810 	FW_CMD_CAP_PORT                = 0x04,
811 	FW_CMD_CAP_PORTPROMISC         = 0x08,
812 	FW_CMD_CAP_PORTSTATS           = 0x10,
813 	FW_CMD_CAP_VF                  = 0x80,
814 };
815 
816 /*
817  * Generic command header flit0
818  */
819 struct fw_cmd_hdr {
820 	__be32 hi;
821 	__be32 lo;
822 };
823 
824 #define FW_CMD_OP_S             24
825 #define FW_CMD_OP_M             0xff
826 #define FW_CMD_OP_V(x)          ((x) << FW_CMD_OP_S)
827 #define FW_CMD_OP_G(x)          (((x) >> FW_CMD_OP_S) & FW_CMD_OP_M)
828 
829 #define FW_CMD_REQUEST_S        23
830 #define FW_CMD_REQUEST_V(x)     ((x) << FW_CMD_REQUEST_S)
831 #define FW_CMD_REQUEST_F        FW_CMD_REQUEST_V(1U)
832 
833 #define FW_CMD_READ_S           22
834 #define FW_CMD_READ_V(x)        ((x) << FW_CMD_READ_S)
835 #define FW_CMD_READ_F           FW_CMD_READ_V(1U)
836 
837 #define FW_CMD_WRITE_S          21
838 #define FW_CMD_WRITE_V(x)       ((x) << FW_CMD_WRITE_S)
839 #define FW_CMD_WRITE_F          FW_CMD_WRITE_V(1U)
840 
841 #define FW_CMD_EXEC_S           20
842 #define FW_CMD_EXEC_V(x)        ((x) << FW_CMD_EXEC_S)
843 #define FW_CMD_EXEC_F           FW_CMD_EXEC_V(1U)
844 
845 #define FW_CMD_RAMASK_S         20
846 #define FW_CMD_RAMASK_V(x)      ((x) << FW_CMD_RAMASK_S)
847 
848 #define FW_CMD_RETVAL_S         8
849 #define FW_CMD_RETVAL_M         0xff
850 #define FW_CMD_RETVAL_V(x)      ((x) << FW_CMD_RETVAL_S)
851 #define FW_CMD_RETVAL_G(x)      (((x) >> FW_CMD_RETVAL_S) & FW_CMD_RETVAL_M)
852 
853 #define FW_CMD_LEN16_S          0
854 #define FW_CMD_LEN16_V(x)       ((x) << FW_CMD_LEN16_S)
855 
856 #define FW_LEN16(fw_struct)	FW_CMD_LEN16_V(sizeof(fw_struct) / 16)
857 
858 enum fw_ldst_addrspc {
859 	FW_LDST_ADDRSPC_FIRMWARE  = 0x0001,
860 	FW_LDST_ADDRSPC_SGE_EGRC  = 0x0008,
861 	FW_LDST_ADDRSPC_SGE_INGC  = 0x0009,
862 	FW_LDST_ADDRSPC_SGE_FLMC  = 0x000a,
863 	FW_LDST_ADDRSPC_SGE_CONMC = 0x000b,
864 	FW_LDST_ADDRSPC_TP_PIO    = 0x0010,
865 	FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011,
866 	FW_LDST_ADDRSPC_TP_MIB    = 0x0012,
867 	FW_LDST_ADDRSPC_MDIO      = 0x0018,
868 	FW_LDST_ADDRSPC_MPS       = 0x0020,
869 	FW_LDST_ADDRSPC_FUNC      = 0x0028,
870 	FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029,
871 	FW_LDST_ADDRSPC_I2C       = 0x0038,
872 };
873 
874 enum fw_ldst_mps_fid {
875 	FW_LDST_MPS_ATRB,
876 	FW_LDST_MPS_RPLC
877 };
878 
879 enum fw_ldst_func_access_ctl {
880 	FW_LDST_FUNC_ACC_CTL_VIID,
881 	FW_LDST_FUNC_ACC_CTL_FID
882 };
883 
884 enum fw_ldst_func_mod_index {
885 	FW_LDST_FUNC_MPS
886 };
887 
888 struct fw_ldst_cmd {
889 	__be32 op_to_addrspace;
890 	__be32 cycles_to_len16;
891 	union fw_ldst {
892 		struct fw_ldst_addrval {
893 			__be32 addr;
894 			__be32 val;
895 		} addrval;
896 		struct fw_ldst_idctxt {
897 			__be32 physid;
898 			__be32 msg_ctxtflush;
899 			__be32 ctxt_data7;
900 			__be32 ctxt_data6;
901 			__be32 ctxt_data5;
902 			__be32 ctxt_data4;
903 			__be32 ctxt_data3;
904 			__be32 ctxt_data2;
905 			__be32 ctxt_data1;
906 			__be32 ctxt_data0;
907 		} idctxt;
908 		struct fw_ldst_mdio {
909 			__be16 paddr_mmd;
910 			__be16 raddr;
911 			__be16 vctl;
912 			__be16 rval;
913 		} mdio;
914 		struct fw_ldst_cim_rq {
915 			u8 req_first64[8];
916 			u8 req_second64[8];
917 			u8 resp_first64[8];
918 			u8 resp_second64[8];
919 			__be32 r3[2];
920 		} cim_rq;
921 		union fw_ldst_mps {
922 			struct fw_ldst_mps_rplc {
923 				__be16 fid_idx;
924 				__be16 rplcpf_pkd;
925 				__be32 rplc255_224;
926 				__be32 rplc223_192;
927 				__be32 rplc191_160;
928 				__be32 rplc159_128;
929 				__be32 rplc127_96;
930 				__be32 rplc95_64;
931 				__be32 rplc63_32;
932 				__be32 rplc31_0;
933 			} rplc;
934 			struct fw_ldst_mps_atrb {
935 				__be16 fid_mpsid;
936 				__be16 r2[3];
937 				__be32 r3[2];
938 				__be32 r4;
939 				__be32 atrb;
940 				__be16 vlan[16];
941 			} atrb;
942 		} mps;
943 		struct fw_ldst_func {
944 			u8 access_ctl;
945 			u8 mod_index;
946 			__be16 ctl_id;
947 			__be32 offset;
948 			__be64 data0;
949 			__be64 data1;
950 		} func;
951 		struct fw_ldst_pcie {
952 			u8 ctrl_to_fn;
953 			u8 bnum;
954 			u8 r;
955 			u8 ext_r;
956 			u8 select_naccess;
957 			u8 pcie_fn;
958 			__be16 nset_pkd;
959 			__be32 data[12];
960 		} pcie;
961 		struct fw_ldst_i2c_deprecated {
962 			u8 pid_pkd;
963 			u8 base;
964 			u8 boffset;
965 			u8 data;
966 			__be32 r9;
967 		} i2c_deprecated;
968 		struct fw_ldst_i2c {
969 			u8 pid;
970 			u8 did;
971 			u8 boffset;
972 			u8 blen;
973 			__be32 r9;
974 			__u8   data[48];
975 		} i2c;
976 		struct fw_ldst_le {
977 			__be32 index;
978 			__be32 r9;
979 			u8 val[33];
980 			u8 r11[7];
981 		} le;
982 	} u;
983 };
984 
985 #define FW_LDST_CMD_ADDRSPACE_S		0
986 #define FW_LDST_CMD_ADDRSPACE_V(x)	((x) << FW_LDST_CMD_ADDRSPACE_S)
987 
988 #define FW_LDST_CMD_MSG_S       31
989 #define FW_LDST_CMD_MSG_V(x)	((x) << FW_LDST_CMD_MSG_S)
990 
991 #define FW_LDST_CMD_CTXTFLUSH_S		30
992 #define FW_LDST_CMD_CTXTFLUSH_V(x)	((x) << FW_LDST_CMD_CTXTFLUSH_S)
993 #define FW_LDST_CMD_CTXTFLUSH_F		FW_LDST_CMD_CTXTFLUSH_V(1U)
994 
995 #define FW_LDST_CMD_PADDR_S     8
996 #define FW_LDST_CMD_PADDR_V(x)	((x) << FW_LDST_CMD_PADDR_S)
997 
998 #define FW_LDST_CMD_MMD_S       0
999 #define FW_LDST_CMD_MMD_V(x)	((x) << FW_LDST_CMD_MMD_S)
1000 
1001 #define FW_LDST_CMD_FID_S       15
1002 #define FW_LDST_CMD_FID_V(x)	((x) << FW_LDST_CMD_FID_S)
1003 
1004 #define FW_LDST_CMD_IDX_S	0
1005 #define FW_LDST_CMD_IDX_V(x)	((x) << FW_LDST_CMD_IDX_S)
1006 
1007 #define FW_LDST_CMD_RPLCPF_S    0
1008 #define FW_LDST_CMD_RPLCPF_V(x)	((x) << FW_LDST_CMD_RPLCPF_S)
1009 
1010 #define FW_LDST_CMD_LC_S        4
1011 #define FW_LDST_CMD_LC_V(x)     ((x) << FW_LDST_CMD_LC_S)
1012 #define FW_LDST_CMD_LC_F	FW_LDST_CMD_LC_V(1U)
1013 
1014 #define FW_LDST_CMD_FN_S        0
1015 #define FW_LDST_CMD_FN_V(x)	((x) << FW_LDST_CMD_FN_S)
1016 
1017 #define FW_LDST_CMD_NACCESS_S           0
1018 #define FW_LDST_CMD_NACCESS_V(x)	((x) << FW_LDST_CMD_NACCESS_S)
1019 
1020 struct fw_reset_cmd {
1021 	__be32 op_to_write;
1022 	__be32 retval_len16;
1023 	__be32 val;
1024 	__be32 halt_pkd;
1025 };
1026 
1027 #define FW_RESET_CMD_HALT_S	31
1028 #define FW_RESET_CMD_HALT_M     0x1
1029 #define FW_RESET_CMD_HALT_V(x)	((x) << FW_RESET_CMD_HALT_S)
1030 #define FW_RESET_CMD_HALT_G(x)  \
1031 	(((x) >> FW_RESET_CMD_HALT_S) & FW_RESET_CMD_HALT_M)
1032 #define FW_RESET_CMD_HALT_F	FW_RESET_CMD_HALT_V(1U)
1033 
1034 enum fw_hellow_cmd {
1035 	fw_hello_cmd_stage_os		= 0x0
1036 };
1037 
1038 struct fw_hello_cmd {
1039 	__be32 op_to_write;
1040 	__be32 retval_len16;
1041 	__be32 err_to_clearinit;
1042 	__be32 fwrev;
1043 };
1044 
1045 #define FW_HELLO_CMD_ERR_S      31
1046 #define FW_HELLO_CMD_ERR_V(x)   ((x) << FW_HELLO_CMD_ERR_S)
1047 #define FW_HELLO_CMD_ERR_F	FW_HELLO_CMD_ERR_V(1U)
1048 
1049 #define FW_HELLO_CMD_INIT_S     30
1050 #define FW_HELLO_CMD_INIT_V(x)  ((x) << FW_HELLO_CMD_INIT_S)
1051 #define FW_HELLO_CMD_INIT_F	FW_HELLO_CMD_INIT_V(1U)
1052 
1053 #define FW_HELLO_CMD_MASTERDIS_S	29
1054 #define FW_HELLO_CMD_MASTERDIS_V(x)	((x) << FW_HELLO_CMD_MASTERDIS_S)
1055 
1056 #define FW_HELLO_CMD_MASTERFORCE_S      28
1057 #define FW_HELLO_CMD_MASTERFORCE_V(x)	((x) << FW_HELLO_CMD_MASTERFORCE_S)
1058 
1059 #define FW_HELLO_CMD_MBMASTER_S		24
1060 #define FW_HELLO_CMD_MBMASTER_M		0xfU
1061 #define FW_HELLO_CMD_MBMASTER_V(x)	((x) << FW_HELLO_CMD_MBMASTER_S)
1062 #define FW_HELLO_CMD_MBMASTER_G(x)	\
1063 	(((x) >> FW_HELLO_CMD_MBMASTER_S) & FW_HELLO_CMD_MBMASTER_M)
1064 
1065 #define FW_HELLO_CMD_MBASYNCNOTINT_S    23
1066 #define FW_HELLO_CMD_MBASYNCNOTINT_V(x)	((x) << FW_HELLO_CMD_MBASYNCNOTINT_S)
1067 
1068 #define FW_HELLO_CMD_MBASYNCNOT_S       20
1069 #define FW_HELLO_CMD_MBASYNCNOT_V(x)	((x) << FW_HELLO_CMD_MBASYNCNOT_S)
1070 
1071 #define FW_HELLO_CMD_STAGE_S		17
1072 #define FW_HELLO_CMD_STAGE_V(x)		((x) << FW_HELLO_CMD_STAGE_S)
1073 
1074 #define FW_HELLO_CMD_CLEARINIT_S        16
1075 #define FW_HELLO_CMD_CLEARINIT_V(x)     ((x) << FW_HELLO_CMD_CLEARINIT_S)
1076 #define FW_HELLO_CMD_CLEARINIT_F	FW_HELLO_CMD_CLEARINIT_V(1U)
1077 
1078 struct fw_bye_cmd {
1079 	__be32 op_to_write;
1080 	__be32 retval_len16;
1081 	__be64 r3;
1082 };
1083 
1084 struct fw_initialize_cmd {
1085 	__be32 op_to_write;
1086 	__be32 retval_len16;
1087 	__be64 r3;
1088 };
1089 
1090 enum fw_caps_config_hm {
1091 	FW_CAPS_CONFIG_HM_PCIE		= 0x00000001,
1092 	FW_CAPS_CONFIG_HM_PL		= 0x00000002,
1093 	FW_CAPS_CONFIG_HM_SGE		= 0x00000004,
1094 	FW_CAPS_CONFIG_HM_CIM		= 0x00000008,
1095 	FW_CAPS_CONFIG_HM_ULPTX		= 0x00000010,
1096 	FW_CAPS_CONFIG_HM_TP		= 0x00000020,
1097 	FW_CAPS_CONFIG_HM_ULPRX		= 0x00000040,
1098 	FW_CAPS_CONFIG_HM_PMRX		= 0x00000080,
1099 	FW_CAPS_CONFIG_HM_PMTX		= 0x00000100,
1100 	FW_CAPS_CONFIG_HM_MC		= 0x00000200,
1101 	FW_CAPS_CONFIG_HM_LE		= 0x00000400,
1102 	FW_CAPS_CONFIG_HM_MPS		= 0x00000800,
1103 	FW_CAPS_CONFIG_HM_XGMAC		= 0x00001000,
1104 	FW_CAPS_CONFIG_HM_CPLSWITCH	= 0x00002000,
1105 	FW_CAPS_CONFIG_HM_T4DBG		= 0x00004000,
1106 	FW_CAPS_CONFIG_HM_MI		= 0x00008000,
1107 	FW_CAPS_CONFIG_HM_I2CM		= 0x00010000,
1108 	FW_CAPS_CONFIG_HM_NCSI		= 0x00020000,
1109 	FW_CAPS_CONFIG_HM_SMB		= 0x00040000,
1110 	FW_CAPS_CONFIG_HM_MA		= 0x00080000,
1111 	FW_CAPS_CONFIG_HM_EDRAM		= 0x00100000,
1112 	FW_CAPS_CONFIG_HM_PMU		= 0x00200000,
1113 	FW_CAPS_CONFIG_HM_UART		= 0x00400000,
1114 	FW_CAPS_CONFIG_HM_SF		= 0x00800000,
1115 };
1116 
1117 enum fw_caps_config_nbm {
1118 	FW_CAPS_CONFIG_NBM_IPMI		= 0x00000001,
1119 	FW_CAPS_CONFIG_NBM_NCSI		= 0x00000002,
1120 };
1121 
1122 enum fw_caps_config_link {
1123 	FW_CAPS_CONFIG_LINK_PPP		= 0x00000001,
1124 	FW_CAPS_CONFIG_LINK_QFC		= 0x00000002,
1125 	FW_CAPS_CONFIG_LINK_DCBX	= 0x00000004,
1126 };
1127 
1128 enum fw_caps_config_switch {
1129 	FW_CAPS_CONFIG_SWITCH_INGRESS	= 0x00000001,
1130 	FW_CAPS_CONFIG_SWITCH_EGRESS	= 0x00000002,
1131 };
1132 
1133 enum fw_caps_config_nic {
1134 	FW_CAPS_CONFIG_NIC		= 0x00000001,
1135 	FW_CAPS_CONFIG_NIC_VM		= 0x00000002,
1136 	FW_CAPS_CONFIG_NIC_HASHFILTER	= 0x00000020,
1137 };
1138 
1139 enum fw_caps_config_ofld {
1140 	FW_CAPS_CONFIG_OFLD		= 0x00000001,
1141 };
1142 
1143 enum fw_caps_config_rdma {
1144 	FW_CAPS_CONFIG_RDMA_RDDP	= 0x00000001,
1145 	FW_CAPS_CONFIG_RDMA_RDMAC	= 0x00000002,
1146 };
1147 
1148 enum fw_caps_config_iscsi {
1149 	FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU = 0x00000001,
1150 	FW_CAPS_CONFIG_ISCSI_TARGET_PDU = 0x00000002,
1151 	FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD = 0x00000004,
1152 	FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008,
1153 };
1154 
1155 enum fw_caps_config_crypto {
1156 	FW_CAPS_CONFIG_CRYPTO_LOOKASIDE = 0x00000001,
1157 	FW_CAPS_CONFIG_TLS_INLINE = 0x00000002,
1158 	FW_CAPS_CONFIG_IPSEC_INLINE = 0x00000004,
1159 };
1160 
1161 enum fw_caps_config_fcoe {
1162 	FW_CAPS_CONFIG_FCOE_INITIATOR	= 0x00000001,
1163 	FW_CAPS_CONFIG_FCOE_TARGET	= 0x00000002,
1164 	FW_CAPS_CONFIG_FCOE_CTRL_OFLD	= 0x00000004,
1165 };
1166 
1167 enum fw_memtype_cf {
1168 	FW_MEMTYPE_CF_EDC0		= 0x0,
1169 	FW_MEMTYPE_CF_EDC1		= 0x1,
1170 	FW_MEMTYPE_CF_EXTMEM		= 0x2,
1171 	FW_MEMTYPE_CF_FLASH		= 0x4,
1172 	FW_MEMTYPE_CF_INTERNAL		= 0x5,
1173 	FW_MEMTYPE_CF_EXTMEM1           = 0x6,
1174 	FW_MEMTYPE_CF_HMA		= 0x7,
1175 };
1176 
1177 struct fw_caps_config_cmd {
1178 	__be32 op_to_write;
1179 	__be32 cfvalid_to_len16;
1180 	__be32 r2;
1181 	__be32 hwmbitmap;
1182 	__be16 nbmcaps;
1183 	__be16 linkcaps;
1184 	__be16 switchcaps;
1185 	__be16 r3;
1186 	__be16 niccaps;
1187 	__be16 ofldcaps;
1188 	__be16 rdmacaps;
1189 	__be16 cryptocaps;
1190 	__be16 iscsicaps;
1191 	__be16 fcoecaps;
1192 	__be32 cfcsum;
1193 	__be32 finiver;
1194 	__be32 finicsum;
1195 };
1196 
1197 #define FW_CAPS_CONFIG_CMD_CFVALID_S    27
1198 #define FW_CAPS_CONFIG_CMD_CFVALID_V(x) ((x) << FW_CAPS_CONFIG_CMD_CFVALID_S)
1199 #define FW_CAPS_CONFIG_CMD_CFVALID_F    FW_CAPS_CONFIG_CMD_CFVALID_V(1U)
1200 
1201 #define FW_CAPS_CONFIG_CMD_MEMTYPE_CF_S		24
1202 #define FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(x)	\
1203 	((x) << FW_CAPS_CONFIG_CMD_MEMTYPE_CF_S)
1204 
1205 #define FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_S      16
1206 #define FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(x)	\
1207 	((x) << FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_S)
1208 
1209 /*
1210  * params command mnemonics
1211  */
1212 enum fw_params_mnem {
1213 	FW_PARAMS_MNEM_DEV		= 1,	/* device params */
1214 	FW_PARAMS_MNEM_PFVF		= 2,	/* function params */
1215 	FW_PARAMS_MNEM_REG		= 3,	/* limited register access */
1216 	FW_PARAMS_MNEM_DMAQ		= 4,	/* dma queue params */
1217 	FW_PARAMS_MNEM_CHNET            = 5,    /* chnet params */
1218 	FW_PARAMS_MNEM_LAST
1219 };
1220 
1221 /*
1222  * device parameters
1223  */
1224 enum fw_params_param_dev {
1225 	FW_PARAMS_PARAM_DEV_CCLK	= 0x00, /* chip core clock in khz */
1226 	FW_PARAMS_PARAM_DEV_PORTVEC	= 0x01, /* the port vector */
1227 	FW_PARAMS_PARAM_DEV_NTID	= 0x02, /* reads the number of TIDs
1228 						 * allocated by the device's
1229 						 * Lookup Engine
1230 						 */
1231 	FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03,
1232 	FW_PARAMS_PARAM_DEV_INTVER_NIC	= 0x04,
1233 	FW_PARAMS_PARAM_DEV_INTVER_VNIC = 0x05,
1234 	FW_PARAMS_PARAM_DEV_INTVER_OFLD = 0x06,
1235 	FW_PARAMS_PARAM_DEV_INTVER_RI	= 0x07,
1236 	FW_PARAMS_PARAM_DEV_INTVER_ISCSIPDU = 0x08,
1237 	FW_PARAMS_PARAM_DEV_INTVER_ISCSI = 0x09,
1238 	FW_PARAMS_PARAM_DEV_INTVER_FCOE = 0x0A,
1239 	FW_PARAMS_PARAM_DEV_FWREV = 0x0B,
1240 	FW_PARAMS_PARAM_DEV_TPREV = 0x0C,
1241 	FW_PARAMS_PARAM_DEV_CF = 0x0D,
1242 	FW_PARAMS_PARAM_DEV_PHYFW = 0x0F,
1243 	FW_PARAMS_PARAM_DEV_DIAG = 0x11,
1244 	FW_PARAMS_PARAM_DEV_MAXORDIRD_QP = 0x13, /* max supported QP IRD/ORD */
1245 	FW_PARAMS_PARAM_DEV_MAXIRD_ADAPTER = 0x14, /* max supported adap IRD */
1246 	FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17,
1247 	FW_PARAMS_PARAM_DEV_FWCACHE = 0x18,
1248 	FW_PARAMS_PARAM_DEV_SCFGREV = 0x1A,
1249 	FW_PARAMS_PARAM_DEV_VPDREV = 0x1B,
1250 	FW_PARAMS_PARAM_DEV_RI_FR_NSMR_TPTE_WR	= 0x1C,
1251 	FW_PARAMS_PARAM_DEV_FILTER2_WR  = 0x1D,
1252 	FW_PARAMS_PARAM_DEV_MPSBGMAP	= 0x1E,
1253 	FW_PARAMS_PARAM_DEV_HMA_SIZE	= 0x20,
1254 	FW_PARAMS_PARAM_DEV_RDMA_WRITE_WITH_IMM = 0x21,
1255 	FW_PARAMS_PARAM_DEV_RI_WRITE_CMPL_WR    = 0x24,
1256 };
1257 
1258 /*
1259  * physical and virtual function parameters
1260  */
1261 enum fw_params_param_pfvf {
1262 	FW_PARAMS_PARAM_PFVF_RWXCAPS	= 0x00,
1263 	FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01,
1264 	FW_PARAMS_PARAM_PFVF_ROUTE_END = 0x02,
1265 	FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03,
1266 	FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04,
1267 	FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05,
1268 	FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06,
1269 	FW_PARAMS_PARAM_PFVF_SERVER_START = 0x07,
1270 	FW_PARAMS_PARAM_PFVF_SERVER_END = 0x08,
1271 	FW_PARAMS_PARAM_PFVF_TDDP_START = 0x09,
1272 	FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A,
1273 	FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B,
1274 	FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C,
1275 	FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D,
1276 	FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E,
1277 	FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F,
1278 	FW_PARAMS_PARAM_PFVF_RQ_END	= 0x10,
1279 	FW_PARAMS_PARAM_PFVF_PBL_START = 0x11,
1280 	FW_PARAMS_PARAM_PFVF_PBL_END	= 0x12,
1281 	FW_PARAMS_PARAM_PFVF_L2T_START = 0x13,
1282 	FW_PARAMS_PARAM_PFVF_L2T_END = 0x14,
1283 	FW_PARAMS_PARAM_PFVF_SQRQ_START = 0x15,
1284 	FW_PARAMS_PARAM_PFVF_SQRQ_END	= 0x16,
1285 	FW_PARAMS_PARAM_PFVF_CQ_START	= 0x17,
1286 	FW_PARAMS_PARAM_PFVF_CQ_END	= 0x18,
1287 	FW_PARAMS_PARAM_PFVF_SRQ_START  = 0x19,
1288 	FW_PARAMS_PARAM_PFVF_SRQ_END    = 0x1A,
1289 	FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20,
1290 	FW_PARAMS_PARAM_PFVF_VIID       = 0x24,
1291 	FW_PARAMS_PARAM_PFVF_CPMASK     = 0x25,
1292 	FW_PARAMS_PARAM_PFVF_OCQ_START  = 0x26,
1293 	FW_PARAMS_PARAM_PFVF_OCQ_END    = 0x27,
1294 	FW_PARAMS_PARAM_PFVF_CONM_MAP   = 0x28,
1295 	FW_PARAMS_PARAM_PFVF_IQFLINT_START = 0x29,
1296 	FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A,
1297 	FW_PARAMS_PARAM_PFVF_EQ_START	= 0x2B,
1298 	FW_PARAMS_PARAM_PFVF_EQ_END	= 0x2C,
1299 	FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D,
1300 	FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E,
1301 	FW_PARAMS_PARAM_PFVF_ETHOFLD_START = 0x2F,
1302 	FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30,
1303 	FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31,
1304 	FW_PARAMS_PARAM_PFVF_HPFILTER_START = 0x32,
1305 	FW_PARAMS_PARAM_PFVF_HPFILTER_END = 0x33,
1306 	FW_PARAMS_PARAM_PFVF_TLS_START = 0x34,
1307 	FW_PARAMS_PARAM_PFVF_TLS_END = 0x35,
1308 	FW_PARAMS_PARAM_PFVF_RAWF_START = 0x36,
1309 	FW_PARAMS_PARAM_PFVF_RAWF_END = 0x37,
1310 	FW_PARAMS_PARAM_PFVF_NCRYPTO_LOOKASIDE = 0x39,
1311 	FW_PARAMS_PARAM_PFVF_PORT_CAPS32 = 0x3A,
1312 };
1313 
1314 /*
1315  * dma queue parameters
1316  */
1317 enum fw_params_param_dmaq {
1318 	FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00,
1319 	FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01,
1320 	FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10,
1321 	FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11,
1322 	FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12,
1323 	FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13,
1324 	FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20,
1325 };
1326 
1327 enum fw_params_param_dev_phyfw {
1328 	FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD = 0x00,
1329 	FW_PARAMS_PARAM_DEV_PHYFW_VERSION = 0x01,
1330 };
1331 
1332 enum fw_params_param_dev_diag {
1333 	FW_PARAM_DEV_DIAG_TMP		= 0x00,
1334 	FW_PARAM_DEV_DIAG_VDD		= 0x01,
1335 };
1336 
1337 enum fw_params_param_dev_fwcache {
1338 	FW_PARAM_DEV_FWCACHE_FLUSH      = 0x00,
1339 	FW_PARAM_DEV_FWCACHE_FLUSHINV   = 0x01,
1340 };
1341 
1342 #define FW_PARAMS_MNEM_S	24
1343 #define FW_PARAMS_MNEM_V(x)	((x) << FW_PARAMS_MNEM_S)
1344 
1345 #define FW_PARAMS_PARAM_X_S     16
1346 #define FW_PARAMS_PARAM_X_V(x)	((x) << FW_PARAMS_PARAM_X_S)
1347 
1348 #define FW_PARAMS_PARAM_Y_S	8
1349 #define FW_PARAMS_PARAM_Y_M	0xffU
1350 #define FW_PARAMS_PARAM_Y_V(x)	((x) << FW_PARAMS_PARAM_Y_S)
1351 #define FW_PARAMS_PARAM_Y_G(x)	(((x) >> FW_PARAMS_PARAM_Y_S) &\
1352 		FW_PARAMS_PARAM_Y_M)
1353 
1354 #define FW_PARAMS_PARAM_Z_S	0
1355 #define FW_PARAMS_PARAM_Z_M	0xffu
1356 #define FW_PARAMS_PARAM_Z_V(x)	((x) << FW_PARAMS_PARAM_Z_S)
1357 #define FW_PARAMS_PARAM_Z_G(x)	(((x) >> FW_PARAMS_PARAM_Z_S) &\
1358 		FW_PARAMS_PARAM_Z_M)
1359 
1360 #define FW_PARAMS_PARAM_XYZ_S		0
1361 #define FW_PARAMS_PARAM_XYZ_V(x)	((x) << FW_PARAMS_PARAM_XYZ_S)
1362 
1363 #define FW_PARAMS_PARAM_YZ_S		0
1364 #define FW_PARAMS_PARAM_YZ_V(x)		((x) << FW_PARAMS_PARAM_YZ_S)
1365 
1366 struct fw_params_cmd {
1367 	__be32 op_to_vfn;
1368 	__be32 retval_len16;
1369 	struct fw_params_param {
1370 		__be32 mnem;
1371 		__be32 val;
1372 	} param[7];
1373 };
1374 
1375 #define FW_PARAMS_CMD_PFN_S     8
1376 #define FW_PARAMS_CMD_PFN_V(x)	((x) << FW_PARAMS_CMD_PFN_S)
1377 
1378 #define FW_PARAMS_CMD_VFN_S     0
1379 #define FW_PARAMS_CMD_VFN_V(x)	((x) << FW_PARAMS_CMD_VFN_S)
1380 
1381 struct fw_pfvf_cmd {
1382 	__be32 op_to_vfn;
1383 	__be32 retval_len16;
1384 	__be32 niqflint_niq;
1385 	__be32 type_to_neq;
1386 	__be32 tc_to_nexactf;
1387 	__be32 r_caps_to_nethctrl;
1388 	__be16 nricq;
1389 	__be16 nriqp;
1390 	__be32 r4;
1391 };
1392 
1393 #define FW_PFVF_CMD_PFN_S	8
1394 #define FW_PFVF_CMD_PFN_V(x)	((x) << FW_PFVF_CMD_PFN_S)
1395 
1396 #define FW_PFVF_CMD_VFN_S       0
1397 #define FW_PFVF_CMD_VFN_V(x)	((x) << FW_PFVF_CMD_VFN_S)
1398 
1399 #define FW_PFVF_CMD_NIQFLINT_S          20
1400 #define FW_PFVF_CMD_NIQFLINT_M          0xfff
1401 #define FW_PFVF_CMD_NIQFLINT_V(x)	((x) << FW_PFVF_CMD_NIQFLINT_S)
1402 #define FW_PFVF_CMD_NIQFLINT_G(x)	\
1403 	(((x) >> FW_PFVF_CMD_NIQFLINT_S) & FW_PFVF_CMD_NIQFLINT_M)
1404 
1405 #define FW_PFVF_CMD_NIQ_S       0
1406 #define FW_PFVF_CMD_NIQ_M       0xfffff
1407 #define FW_PFVF_CMD_NIQ_V(x)	((x) << FW_PFVF_CMD_NIQ_S)
1408 #define FW_PFVF_CMD_NIQ_G(x)	\
1409 	(((x) >> FW_PFVF_CMD_NIQ_S) & FW_PFVF_CMD_NIQ_M)
1410 
1411 #define FW_PFVF_CMD_TYPE_S      31
1412 #define FW_PFVF_CMD_TYPE_M      0x1
1413 #define FW_PFVF_CMD_TYPE_V(x)   ((x) << FW_PFVF_CMD_TYPE_S)
1414 #define FW_PFVF_CMD_TYPE_G(x)	\
1415 	(((x) >> FW_PFVF_CMD_TYPE_S) & FW_PFVF_CMD_TYPE_M)
1416 #define FW_PFVF_CMD_TYPE_F      FW_PFVF_CMD_TYPE_V(1U)
1417 
1418 #define FW_PFVF_CMD_CMASK_S     24
1419 #define FW_PFVF_CMD_CMASK_M	0xf
1420 #define FW_PFVF_CMD_CMASK_V(x)	((x) << FW_PFVF_CMD_CMASK_S)
1421 #define FW_PFVF_CMD_CMASK_G(x)	\
1422 	(((x) >> FW_PFVF_CMD_CMASK_S) & FW_PFVF_CMD_CMASK_M)
1423 
1424 #define FW_PFVF_CMD_PMASK_S     20
1425 #define FW_PFVF_CMD_PMASK_M	0xf
1426 #define FW_PFVF_CMD_PMASK_V(x)	((x) << FW_PFVF_CMD_PMASK_S)
1427 #define FW_PFVF_CMD_PMASK_G(x) \
1428 	(((x) >> FW_PFVF_CMD_PMASK_S) & FW_PFVF_CMD_PMASK_M)
1429 
1430 #define FW_PFVF_CMD_NEQ_S       0
1431 #define FW_PFVF_CMD_NEQ_M       0xfffff
1432 #define FW_PFVF_CMD_NEQ_V(x)	((x) << FW_PFVF_CMD_NEQ_S)
1433 #define FW_PFVF_CMD_NEQ_G(x)	\
1434 	(((x) >> FW_PFVF_CMD_NEQ_S) & FW_PFVF_CMD_NEQ_M)
1435 
1436 #define FW_PFVF_CMD_TC_S        24
1437 #define FW_PFVF_CMD_TC_M        0xff
1438 #define FW_PFVF_CMD_TC_V(x)	((x) << FW_PFVF_CMD_TC_S)
1439 #define FW_PFVF_CMD_TC_G(x)	(((x) >> FW_PFVF_CMD_TC_S) & FW_PFVF_CMD_TC_M)
1440 
1441 #define FW_PFVF_CMD_NVI_S       16
1442 #define FW_PFVF_CMD_NVI_M       0xff
1443 #define FW_PFVF_CMD_NVI_V(x)	((x) << FW_PFVF_CMD_NVI_S)
1444 #define FW_PFVF_CMD_NVI_G(x)	(((x) >> FW_PFVF_CMD_NVI_S) & FW_PFVF_CMD_NVI_M)
1445 
1446 #define FW_PFVF_CMD_NEXACTF_S           0
1447 #define FW_PFVF_CMD_NEXACTF_M           0xffff
1448 #define FW_PFVF_CMD_NEXACTF_V(x)	((x) << FW_PFVF_CMD_NEXACTF_S)
1449 #define FW_PFVF_CMD_NEXACTF_G(x)	\
1450 	(((x) >> FW_PFVF_CMD_NEXACTF_S) & FW_PFVF_CMD_NEXACTF_M)
1451 
1452 #define FW_PFVF_CMD_R_CAPS_S    24
1453 #define FW_PFVF_CMD_R_CAPS_M    0xff
1454 #define FW_PFVF_CMD_R_CAPS_V(x) ((x) << FW_PFVF_CMD_R_CAPS_S)
1455 #define FW_PFVF_CMD_R_CAPS_G(x) \
1456 	(((x) >> FW_PFVF_CMD_R_CAPS_S) & FW_PFVF_CMD_R_CAPS_M)
1457 
1458 #define FW_PFVF_CMD_WX_CAPS_S           16
1459 #define FW_PFVF_CMD_WX_CAPS_M           0xff
1460 #define FW_PFVF_CMD_WX_CAPS_V(x)	((x) << FW_PFVF_CMD_WX_CAPS_S)
1461 #define FW_PFVF_CMD_WX_CAPS_G(x)	\
1462 	(((x) >> FW_PFVF_CMD_WX_CAPS_S) & FW_PFVF_CMD_WX_CAPS_M)
1463 
1464 #define FW_PFVF_CMD_NETHCTRL_S          0
1465 #define FW_PFVF_CMD_NETHCTRL_M          0xffff
1466 #define FW_PFVF_CMD_NETHCTRL_V(x)	((x) << FW_PFVF_CMD_NETHCTRL_S)
1467 #define FW_PFVF_CMD_NETHCTRL_G(x)	\
1468 	(((x) >> FW_PFVF_CMD_NETHCTRL_S) & FW_PFVF_CMD_NETHCTRL_M)
1469 
1470 enum fw_iq_type {
1471 	FW_IQ_TYPE_FL_INT_CAP,
1472 	FW_IQ_TYPE_NO_FL_INT_CAP
1473 };
1474 
1475 struct fw_iq_cmd {
1476 	__be32 op_to_vfn;
1477 	__be32 alloc_to_len16;
1478 	__be16 physiqid;
1479 	__be16 iqid;
1480 	__be16 fl0id;
1481 	__be16 fl1id;
1482 	__be32 type_to_iqandstindex;
1483 	__be16 iqdroprss_to_iqesize;
1484 	__be16 iqsize;
1485 	__be64 iqaddr;
1486 	__be32 iqns_to_fl0congen;
1487 	__be16 fl0dcaen_to_fl0cidxfthresh;
1488 	__be16 fl0size;
1489 	__be64 fl0addr;
1490 	__be32 fl1cngchmap_to_fl1congen;
1491 	__be16 fl1dcaen_to_fl1cidxfthresh;
1492 	__be16 fl1size;
1493 	__be64 fl1addr;
1494 };
1495 
1496 #define FW_IQ_CMD_PFN_S		8
1497 #define FW_IQ_CMD_PFN_V(x)	((x) << FW_IQ_CMD_PFN_S)
1498 
1499 #define FW_IQ_CMD_VFN_S		0
1500 #define FW_IQ_CMD_VFN_V(x)	((x) << FW_IQ_CMD_VFN_S)
1501 
1502 #define FW_IQ_CMD_ALLOC_S	31
1503 #define FW_IQ_CMD_ALLOC_V(x)	((x) << FW_IQ_CMD_ALLOC_S)
1504 #define FW_IQ_CMD_ALLOC_F	FW_IQ_CMD_ALLOC_V(1U)
1505 
1506 #define FW_IQ_CMD_FREE_S	30
1507 #define FW_IQ_CMD_FREE_V(x)	((x) << FW_IQ_CMD_FREE_S)
1508 #define FW_IQ_CMD_FREE_F	FW_IQ_CMD_FREE_V(1U)
1509 
1510 #define FW_IQ_CMD_MODIFY_S	29
1511 #define FW_IQ_CMD_MODIFY_V(x)	((x) << FW_IQ_CMD_MODIFY_S)
1512 #define FW_IQ_CMD_MODIFY_F	FW_IQ_CMD_MODIFY_V(1U)
1513 
1514 #define FW_IQ_CMD_IQSTART_S	28
1515 #define FW_IQ_CMD_IQSTART_V(x)	((x) << FW_IQ_CMD_IQSTART_S)
1516 #define FW_IQ_CMD_IQSTART_F	FW_IQ_CMD_IQSTART_V(1U)
1517 
1518 #define FW_IQ_CMD_IQSTOP_S	27
1519 #define FW_IQ_CMD_IQSTOP_V(x)	((x) << FW_IQ_CMD_IQSTOP_S)
1520 #define FW_IQ_CMD_IQSTOP_F	FW_IQ_CMD_IQSTOP_V(1U)
1521 
1522 #define FW_IQ_CMD_TYPE_S	29
1523 #define FW_IQ_CMD_TYPE_V(x)	((x) << FW_IQ_CMD_TYPE_S)
1524 
1525 #define FW_IQ_CMD_IQASYNCH_S	28
1526 #define FW_IQ_CMD_IQASYNCH_V(x)	((x) << FW_IQ_CMD_IQASYNCH_S)
1527 
1528 #define FW_IQ_CMD_VIID_S	16
1529 #define FW_IQ_CMD_VIID_V(x)	((x) << FW_IQ_CMD_VIID_S)
1530 
1531 #define FW_IQ_CMD_IQANDST_S	15
1532 #define FW_IQ_CMD_IQANDST_V(x)	((x) << FW_IQ_CMD_IQANDST_S)
1533 
1534 #define FW_IQ_CMD_IQANUS_S	14
1535 #define FW_IQ_CMD_IQANUS_V(x)	((x) << FW_IQ_CMD_IQANUS_S)
1536 
1537 #define FW_IQ_CMD_IQANUD_S	12
1538 #define FW_IQ_CMD_IQANUD_V(x)	((x) << FW_IQ_CMD_IQANUD_S)
1539 
1540 #define FW_IQ_CMD_IQANDSTINDEX_S	0
1541 #define FW_IQ_CMD_IQANDSTINDEX_V(x)	((x) << FW_IQ_CMD_IQANDSTINDEX_S)
1542 
1543 #define FW_IQ_CMD_IQDROPRSS_S		15
1544 #define FW_IQ_CMD_IQDROPRSS_V(x)	((x) << FW_IQ_CMD_IQDROPRSS_S)
1545 #define FW_IQ_CMD_IQDROPRSS_F	FW_IQ_CMD_IQDROPRSS_V(1U)
1546 
1547 #define FW_IQ_CMD_IQGTSMODE_S		14
1548 #define FW_IQ_CMD_IQGTSMODE_V(x)	((x) << FW_IQ_CMD_IQGTSMODE_S)
1549 #define FW_IQ_CMD_IQGTSMODE_F		FW_IQ_CMD_IQGTSMODE_V(1U)
1550 
1551 #define FW_IQ_CMD_IQPCIECH_S	12
1552 #define FW_IQ_CMD_IQPCIECH_V(x)	((x) << FW_IQ_CMD_IQPCIECH_S)
1553 
1554 #define FW_IQ_CMD_IQDCAEN_S	11
1555 #define FW_IQ_CMD_IQDCAEN_V(x)	((x) << FW_IQ_CMD_IQDCAEN_S)
1556 
1557 #define FW_IQ_CMD_IQDCACPU_S	6
1558 #define FW_IQ_CMD_IQDCACPU_V(x)	((x) << FW_IQ_CMD_IQDCACPU_S)
1559 
1560 #define FW_IQ_CMD_IQINTCNTTHRESH_S	4
1561 #define FW_IQ_CMD_IQINTCNTTHRESH_V(x)	((x) << FW_IQ_CMD_IQINTCNTTHRESH_S)
1562 
1563 #define FW_IQ_CMD_IQO_S		3
1564 #define FW_IQ_CMD_IQO_V(x)	((x) << FW_IQ_CMD_IQO_S)
1565 #define FW_IQ_CMD_IQO_F		FW_IQ_CMD_IQO_V(1U)
1566 
1567 #define FW_IQ_CMD_IQCPRIO_S	2
1568 #define FW_IQ_CMD_IQCPRIO_V(x)	((x) << FW_IQ_CMD_IQCPRIO_S)
1569 
1570 #define FW_IQ_CMD_IQESIZE_S	0
1571 #define FW_IQ_CMD_IQESIZE_V(x)	((x) << FW_IQ_CMD_IQESIZE_S)
1572 
1573 #define FW_IQ_CMD_IQNS_S	31
1574 #define FW_IQ_CMD_IQNS_V(x)	((x) << FW_IQ_CMD_IQNS_S)
1575 
1576 #define FW_IQ_CMD_IQRO_S	30
1577 #define FW_IQ_CMD_IQRO_V(x)	((x) << FW_IQ_CMD_IQRO_S)
1578 
1579 #define FW_IQ_CMD_IQFLINTIQHSEN_S	28
1580 #define FW_IQ_CMD_IQFLINTIQHSEN_V(x)	((x) << FW_IQ_CMD_IQFLINTIQHSEN_S)
1581 
1582 #define FW_IQ_CMD_IQFLINTCONGEN_S	27
1583 #define FW_IQ_CMD_IQFLINTCONGEN_V(x)	((x) << FW_IQ_CMD_IQFLINTCONGEN_S)
1584 #define FW_IQ_CMD_IQFLINTCONGEN_F	FW_IQ_CMD_IQFLINTCONGEN_V(1U)
1585 
1586 #define FW_IQ_CMD_IQFLINTISCSIC_S	26
1587 #define FW_IQ_CMD_IQFLINTISCSIC_V(x)	((x) << FW_IQ_CMD_IQFLINTISCSIC_S)
1588 
1589 #define FW_IQ_CMD_FL0CNGCHMAP_S		20
1590 #define FW_IQ_CMD_FL0CNGCHMAP_V(x)	((x) << FW_IQ_CMD_FL0CNGCHMAP_S)
1591 
1592 #define FW_IQ_CMD_FL0CACHELOCK_S	15
1593 #define FW_IQ_CMD_FL0CACHELOCK_V(x)	((x) << FW_IQ_CMD_FL0CACHELOCK_S)
1594 
1595 #define FW_IQ_CMD_FL0DBP_S	14
1596 #define FW_IQ_CMD_FL0DBP_V(x)	((x) << FW_IQ_CMD_FL0DBP_S)
1597 
1598 #define FW_IQ_CMD_FL0DATANS_S		13
1599 #define FW_IQ_CMD_FL0DATANS_V(x)	((x) << FW_IQ_CMD_FL0DATANS_S)
1600 
1601 #define FW_IQ_CMD_FL0DATARO_S		12
1602 #define FW_IQ_CMD_FL0DATARO_V(x)	((x) << FW_IQ_CMD_FL0DATARO_S)
1603 #define FW_IQ_CMD_FL0DATARO_F		FW_IQ_CMD_FL0DATARO_V(1U)
1604 
1605 #define FW_IQ_CMD_FL0CONGCIF_S		11
1606 #define FW_IQ_CMD_FL0CONGCIF_V(x)	((x) << FW_IQ_CMD_FL0CONGCIF_S)
1607 #define FW_IQ_CMD_FL0CONGCIF_F		FW_IQ_CMD_FL0CONGCIF_V(1U)
1608 
1609 #define FW_IQ_CMD_FL0ONCHIP_S		10
1610 #define FW_IQ_CMD_FL0ONCHIP_V(x)	((x) << FW_IQ_CMD_FL0ONCHIP_S)
1611 
1612 #define FW_IQ_CMD_FL0STATUSPGNS_S	9
1613 #define FW_IQ_CMD_FL0STATUSPGNS_V(x)	((x) << FW_IQ_CMD_FL0STATUSPGNS_S)
1614 
1615 #define FW_IQ_CMD_FL0STATUSPGRO_S	8
1616 #define FW_IQ_CMD_FL0STATUSPGRO_V(x)	((x) << FW_IQ_CMD_FL0STATUSPGRO_S)
1617 
1618 #define FW_IQ_CMD_FL0FETCHNS_S		7
1619 #define FW_IQ_CMD_FL0FETCHNS_V(x)	((x) << FW_IQ_CMD_FL0FETCHNS_S)
1620 
1621 #define FW_IQ_CMD_FL0FETCHRO_S		6
1622 #define FW_IQ_CMD_FL0FETCHRO_V(x)	((x) << FW_IQ_CMD_FL0FETCHRO_S)
1623 #define FW_IQ_CMD_FL0FETCHRO_F		FW_IQ_CMD_FL0FETCHRO_V(1U)
1624 
1625 #define FW_IQ_CMD_FL0HOSTFCMODE_S	4
1626 #define FW_IQ_CMD_FL0HOSTFCMODE_V(x)	((x) << FW_IQ_CMD_FL0HOSTFCMODE_S)
1627 
1628 #define FW_IQ_CMD_FL0CPRIO_S	3
1629 #define FW_IQ_CMD_FL0CPRIO_V(x)	((x) << FW_IQ_CMD_FL0CPRIO_S)
1630 
1631 #define FW_IQ_CMD_FL0PADEN_S	2
1632 #define FW_IQ_CMD_FL0PADEN_V(x)	((x) << FW_IQ_CMD_FL0PADEN_S)
1633 #define FW_IQ_CMD_FL0PADEN_F	FW_IQ_CMD_FL0PADEN_V(1U)
1634 
1635 #define FW_IQ_CMD_FL0PACKEN_S		1
1636 #define FW_IQ_CMD_FL0PACKEN_V(x)	((x) << FW_IQ_CMD_FL0PACKEN_S)
1637 #define FW_IQ_CMD_FL0PACKEN_F		FW_IQ_CMD_FL0PACKEN_V(1U)
1638 
1639 #define FW_IQ_CMD_FL0CONGEN_S		0
1640 #define FW_IQ_CMD_FL0CONGEN_V(x)	((x) << FW_IQ_CMD_FL0CONGEN_S)
1641 #define FW_IQ_CMD_FL0CONGEN_F		FW_IQ_CMD_FL0CONGEN_V(1U)
1642 
1643 #define FW_IQ_CMD_FL0DCAEN_S	15
1644 #define FW_IQ_CMD_FL0DCAEN_V(x)	((x) << FW_IQ_CMD_FL0DCAEN_S)
1645 
1646 #define FW_IQ_CMD_FL0DCACPU_S		10
1647 #define FW_IQ_CMD_FL0DCACPU_V(x)	((x) << FW_IQ_CMD_FL0DCACPU_S)
1648 
1649 #define FW_IQ_CMD_FL0FBMIN_S	7
1650 #define FW_IQ_CMD_FL0FBMIN_V(x)	((x) << FW_IQ_CMD_FL0FBMIN_S)
1651 
1652 #define FW_IQ_CMD_FL0FBMAX_S	4
1653 #define FW_IQ_CMD_FL0FBMAX_V(x)	((x) << FW_IQ_CMD_FL0FBMAX_S)
1654 
1655 #define FW_IQ_CMD_FL0CIDXFTHRESHO_S	3
1656 #define FW_IQ_CMD_FL0CIDXFTHRESHO_V(x)	((x) << FW_IQ_CMD_FL0CIDXFTHRESHO_S)
1657 #define FW_IQ_CMD_FL0CIDXFTHRESHO_F	FW_IQ_CMD_FL0CIDXFTHRESHO_V(1U)
1658 
1659 #define FW_IQ_CMD_FL0CIDXFTHRESH_S	0
1660 #define FW_IQ_CMD_FL0CIDXFTHRESH_V(x)	((x) << FW_IQ_CMD_FL0CIDXFTHRESH_S)
1661 
1662 #define FW_IQ_CMD_FL1CNGCHMAP_S		20
1663 #define FW_IQ_CMD_FL1CNGCHMAP_V(x)	((x) << FW_IQ_CMD_FL1CNGCHMAP_S)
1664 
1665 #define FW_IQ_CMD_FL1CACHELOCK_S	15
1666 #define FW_IQ_CMD_FL1CACHELOCK_V(x)	((x) << FW_IQ_CMD_FL1CACHELOCK_S)
1667 
1668 #define FW_IQ_CMD_FL1DBP_S	14
1669 #define FW_IQ_CMD_FL1DBP_V(x)	((x) << FW_IQ_CMD_FL1DBP_S)
1670 
1671 #define FW_IQ_CMD_FL1DATANS_S		13
1672 #define FW_IQ_CMD_FL1DATANS_V(x)	((x) << FW_IQ_CMD_FL1DATANS_S)
1673 
1674 #define FW_IQ_CMD_FL1DATARO_S		12
1675 #define FW_IQ_CMD_FL1DATARO_V(x)	((x) << FW_IQ_CMD_FL1DATARO_S)
1676 
1677 #define FW_IQ_CMD_FL1CONGCIF_S		11
1678 #define FW_IQ_CMD_FL1CONGCIF_V(x)	((x) << FW_IQ_CMD_FL1CONGCIF_S)
1679 
1680 #define FW_IQ_CMD_FL1ONCHIP_S		10
1681 #define FW_IQ_CMD_FL1ONCHIP_V(x)	((x) << FW_IQ_CMD_FL1ONCHIP_S)
1682 
1683 #define FW_IQ_CMD_FL1STATUSPGNS_S	9
1684 #define FW_IQ_CMD_FL1STATUSPGNS_V(x)	((x) << FW_IQ_CMD_FL1STATUSPGNS_S)
1685 
1686 #define FW_IQ_CMD_FL1STATUSPGRO_S	8
1687 #define FW_IQ_CMD_FL1STATUSPGRO_V(x)	((x) << FW_IQ_CMD_FL1STATUSPGRO_S)
1688 
1689 #define FW_IQ_CMD_FL1FETCHNS_S		7
1690 #define FW_IQ_CMD_FL1FETCHNS_V(x)	((x) << FW_IQ_CMD_FL1FETCHNS_S)
1691 
1692 #define FW_IQ_CMD_FL1FETCHRO_S		6
1693 #define FW_IQ_CMD_FL1FETCHRO_V(x)	((x) << FW_IQ_CMD_FL1FETCHRO_S)
1694 
1695 #define FW_IQ_CMD_FL1HOSTFCMODE_S	4
1696 #define FW_IQ_CMD_FL1HOSTFCMODE_V(x)	((x) << FW_IQ_CMD_FL1HOSTFCMODE_S)
1697 
1698 #define FW_IQ_CMD_FL1CPRIO_S	3
1699 #define FW_IQ_CMD_FL1CPRIO_V(x)	((x) << FW_IQ_CMD_FL1CPRIO_S)
1700 
1701 #define FW_IQ_CMD_FL1PADEN_S	2
1702 #define FW_IQ_CMD_FL1PADEN_V(x)	((x) << FW_IQ_CMD_FL1PADEN_S)
1703 #define FW_IQ_CMD_FL1PADEN_F	FW_IQ_CMD_FL1PADEN_V(1U)
1704 
1705 #define FW_IQ_CMD_FL1PACKEN_S		1
1706 #define FW_IQ_CMD_FL1PACKEN_V(x)	((x) << FW_IQ_CMD_FL1PACKEN_S)
1707 #define FW_IQ_CMD_FL1PACKEN_F	FW_IQ_CMD_FL1PACKEN_V(1U)
1708 
1709 #define FW_IQ_CMD_FL1CONGEN_S		0
1710 #define FW_IQ_CMD_FL1CONGEN_V(x)	((x) << FW_IQ_CMD_FL1CONGEN_S)
1711 #define FW_IQ_CMD_FL1CONGEN_F	FW_IQ_CMD_FL1CONGEN_V(1U)
1712 
1713 #define FW_IQ_CMD_FL1DCAEN_S	15
1714 #define FW_IQ_CMD_FL1DCAEN_V(x)	((x) << FW_IQ_CMD_FL1DCAEN_S)
1715 
1716 #define FW_IQ_CMD_FL1DCACPU_S		10
1717 #define FW_IQ_CMD_FL1DCACPU_V(x)	((x) << FW_IQ_CMD_FL1DCACPU_S)
1718 
1719 #define FW_IQ_CMD_FL1FBMIN_S	7
1720 #define FW_IQ_CMD_FL1FBMIN_V(x)	((x) << FW_IQ_CMD_FL1FBMIN_S)
1721 
1722 #define FW_IQ_CMD_FL1FBMAX_S	4
1723 #define FW_IQ_CMD_FL1FBMAX_V(x)	((x) << FW_IQ_CMD_FL1FBMAX_S)
1724 
1725 #define FW_IQ_CMD_FL1CIDXFTHRESHO_S	3
1726 #define FW_IQ_CMD_FL1CIDXFTHRESHO_V(x)	((x) << FW_IQ_CMD_FL1CIDXFTHRESHO_S)
1727 #define FW_IQ_CMD_FL1CIDXFTHRESHO_F	FW_IQ_CMD_FL1CIDXFTHRESHO_V(1U)
1728 
1729 #define FW_IQ_CMD_FL1CIDXFTHRESH_S	0
1730 #define FW_IQ_CMD_FL1CIDXFTHRESH_V(x)	((x) << FW_IQ_CMD_FL1CIDXFTHRESH_S)
1731 
1732 struct fw_eq_eth_cmd {
1733 	__be32 op_to_vfn;
1734 	__be32 alloc_to_len16;
1735 	__be32 eqid_pkd;
1736 	__be32 physeqid_pkd;
1737 	__be32 fetchszm_to_iqid;
1738 	__be32 dcaen_to_eqsize;
1739 	__be64 eqaddr;
1740 	__be32 viid_pkd;
1741 	__be32 r8_lo;
1742 	__be64 r9;
1743 };
1744 
1745 #define FW_EQ_ETH_CMD_PFN_S	8
1746 #define FW_EQ_ETH_CMD_PFN_V(x)	((x) << FW_EQ_ETH_CMD_PFN_S)
1747 
1748 #define FW_EQ_ETH_CMD_VFN_S	0
1749 #define FW_EQ_ETH_CMD_VFN_V(x)	((x) << FW_EQ_ETH_CMD_VFN_S)
1750 
1751 #define FW_EQ_ETH_CMD_ALLOC_S		31
1752 #define FW_EQ_ETH_CMD_ALLOC_V(x)	((x) << FW_EQ_ETH_CMD_ALLOC_S)
1753 #define FW_EQ_ETH_CMD_ALLOC_F	FW_EQ_ETH_CMD_ALLOC_V(1U)
1754 
1755 #define FW_EQ_ETH_CMD_FREE_S	30
1756 #define FW_EQ_ETH_CMD_FREE_V(x)	((x) << FW_EQ_ETH_CMD_FREE_S)
1757 #define FW_EQ_ETH_CMD_FREE_F	FW_EQ_ETH_CMD_FREE_V(1U)
1758 
1759 #define FW_EQ_ETH_CMD_MODIFY_S		29
1760 #define FW_EQ_ETH_CMD_MODIFY_V(x)	((x) << FW_EQ_ETH_CMD_MODIFY_S)
1761 #define FW_EQ_ETH_CMD_MODIFY_F	FW_EQ_ETH_CMD_MODIFY_V(1U)
1762 
1763 #define FW_EQ_ETH_CMD_EQSTART_S		28
1764 #define FW_EQ_ETH_CMD_EQSTART_V(x)	((x) << FW_EQ_ETH_CMD_EQSTART_S)
1765 #define FW_EQ_ETH_CMD_EQSTART_F	FW_EQ_ETH_CMD_EQSTART_V(1U)
1766 
1767 #define FW_EQ_ETH_CMD_EQSTOP_S		27
1768 #define FW_EQ_ETH_CMD_EQSTOP_V(x)	((x) << FW_EQ_ETH_CMD_EQSTOP_S)
1769 #define FW_EQ_ETH_CMD_EQSTOP_F	FW_EQ_ETH_CMD_EQSTOP_V(1U)
1770 
1771 #define FW_EQ_ETH_CMD_EQID_S	0
1772 #define FW_EQ_ETH_CMD_EQID_M	0xfffff
1773 #define FW_EQ_ETH_CMD_EQID_V(x)	((x) << FW_EQ_ETH_CMD_EQID_S)
1774 #define FW_EQ_ETH_CMD_EQID_G(x)	\
1775 	(((x) >> FW_EQ_ETH_CMD_EQID_S) & FW_EQ_ETH_CMD_EQID_M)
1776 
1777 #define FW_EQ_ETH_CMD_PHYSEQID_S	0
1778 #define FW_EQ_ETH_CMD_PHYSEQID_M	0xfffff
1779 #define FW_EQ_ETH_CMD_PHYSEQID_V(x)	((x) << FW_EQ_ETH_CMD_PHYSEQID_S)
1780 #define FW_EQ_ETH_CMD_PHYSEQID_G(x)	\
1781 	(((x) >> FW_EQ_ETH_CMD_PHYSEQID_S) & FW_EQ_ETH_CMD_PHYSEQID_M)
1782 
1783 #define FW_EQ_ETH_CMD_FETCHSZM_S	26
1784 #define FW_EQ_ETH_CMD_FETCHSZM_V(x)	((x) << FW_EQ_ETH_CMD_FETCHSZM_S)
1785 #define FW_EQ_ETH_CMD_FETCHSZM_F	FW_EQ_ETH_CMD_FETCHSZM_V(1U)
1786 
1787 #define FW_EQ_ETH_CMD_STATUSPGNS_S	25
1788 #define FW_EQ_ETH_CMD_STATUSPGNS_V(x)	((x) << FW_EQ_ETH_CMD_STATUSPGNS_S)
1789 
1790 #define FW_EQ_ETH_CMD_STATUSPGRO_S	24
1791 #define FW_EQ_ETH_CMD_STATUSPGRO_V(x)	((x) << FW_EQ_ETH_CMD_STATUSPGRO_S)
1792 
1793 #define FW_EQ_ETH_CMD_FETCHNS_S		23
1794 #define FW_EQ_ETH_CMD_FETCHNS_V(x)	((x) << FW_EQ_ETH_CMD_FETCHNS_S)
1795 
1796 #define FW_EQ_ETH_CMD_FETCHRO_S		22
1797 #define FW_EQ_ETH_CMD_FETCHRO_V(x)	((x) << FW_EQ_ETH_CMD_FETCHRO_S)
1798 #define FW_EQ_ETH_CMD_FETCHRO_F		FW_EQ_ETH_CMD_FETCHRO_V(1U)
1799 
1800 #define FW_EQ_ETH_CMD_HOSTFCMODE_S	20
1801 #define FW_EQ_ETH_CMD_HOSTFCMODE_V(x)	((x) << FW_EQ_ETH_CMD_HOSTFCMODE_S)
1802 
1803 #define FW_EQ_ETH_CMD_CPRIO_S		19
1804 #define FW_EQ_ETH_CMD_CPRIO_V(x)	((x) << FW_EQ_ETH_CMD_CPRIO_S)
1805 
1806 #define FW_EQ_ETH_CMD_ONCHIP_S		18
1807 #define FW_EQ_ETH_CMD_ONCHIP_V(x)	((x) << FW_EQ_ETH_CMD_ONCHIP_S)
1808 
1809 #define FW_EQ_ETH_CMD_PCIECHN_S		16
1810 #define FW_EQ_ETH_CMD_PCIECHN_V(x)	((x) << FW_EQ_ETH_CMD_PCIECHN_S)
1811 
1812 #define FW_EQ_ETH_CMD_IQID_S	0
1813 #define FW_EQ_ETH_CMD_IQID_V(x)	((x) << FW_EQ_ETH_CMD_IQID_S)
1814 
1815 #define FW_EQ_ETH_CMD_DCAEN_S		31
1816 #define FW_EQ_ETH_CMD_DCAEN_V(x)	((x) << FW_EQ_ETH_CMD_DCAEN_S)
1817 
1818 #define FW_EQ_ETH_CMD_DCACPU_S		26
1819 #define FW_EQ_ETH_CMD_DCACPU_V(x)	((x) << FW_EQ_ETH_CMD_DCACPU_S)
1820 
1821 #define FW_EQ_ETH_CMD_FBMIN_S		23
1822 #define FW_EQ_ETH_CMD_FBMIN_V(x)	((x) << FW_EQ_ETH_CMD_FBMIN_S)
1823 
1824 #define FW_EQ_ETH_CMD_FBMAX_S		20
1825 #define FW_EQ_ETH_CMD_FBMAX_V(x)	((x) << FW_EQ_ETH_CMD_FBMAX_S)
1826 
1827 #define FW_EQ_ETH_CMD_CIDXFTHRESHO_S	19
1828 #define FW_EQ_ETH_CMD_CIDXFTHRESHO_V(x)	((x) << FW_EQ_ETH_CMD_CIDXFTHRESHO_S)
1829 
1830 #define FW_EQ_ETH_CMD_CIDXFTHRESH_S	16
1831 #define FW_EQ_ETH_CMD_CIDXFTHRESH_V(x)	((x) << FW_EQ_ETH_CMD_CIDXFTHRESH_S)
1832 
1833 #define FW_EQ_ETH_CMD_EQSIZE_S		0
1834 #define FW_EQ_ETH_CMD_EQSIZE_V(x)	((x) << FW_EQ_ETH_CMD_EQSIZE_S)
1835 
1836 #define FW_EQ_ETH_CMD_AUTOEQUEQE_S	30
1837 #define FW_EQ_ETH_CMD_AUTOEQUEQE_V(x)	((x) << FW_EQ_ETH_CMD_AUTOEQUEQE_S)
1838 #define FW_EQ_ETH_CMD_AUTOEQUEQE_F	FW_EQ_ETH_CMD_AUTOEQUEQE_V(1U)
1839 
1840 #define FW_EQ_ETH_CMD_VIID_S	16
1841 #define FW_EQ_ETH_CMD_VIID_V(x)	((x) << FW_EQ_ETH_CMD_VIID_S)
1842 
1843 struct fw_eq_ctrl_cmd {
1844 	__be32 op_to_vfn;
1845 	__be32 alloc_to_len16;
1846 	__be32 cmpliqid_eqid;
1847 	__be32 physeqid_pkd;
1848 	__be32 fetchszm_to_iqid;
1849 	__be32 dcaen_to_eqsize;
1850 	__be64 eqaddr;
1851 };
1852 
1853 #define FW_EQ_CTRL_CMD_PFN_S	8
1854 #define FW_EQ_CTRL_CMD_PFN_V(x)	((x) << FW_EQ_CTRL_CMD_PFN_S)
1855 
1856 #define FW_EQ_CTRL_CMD_VFN_S	0
1857 #define FW_EQ_CTRL_CMD_VFN_V(x)	((x) << FW_EQ_CTRL_CMD_VFN_S)
1858 
1859 #define FW_EQ_CTRL_CMD_ALLOC_S		31
1860 #define FW_EQ_CTRL_CMD_ALLOC_V(x)	((x) << FW_EQ_CTRL_CMD_ALLOC_S)
1861 #define FW_EQ_CTRL_CMD_ALLOC_F		FW_EQ_CTRL_CMD_ALLOC_V(1U)
1862 
1863 #define FW_EQ_CTRL_CMD_FREE_S		30
1864 #define FW_EQ_CTRL_CMD_FREE_V(x)	((x) << FW_EQ_CTRL_CMD_FREE_S)
1865 #define FW_EQ_CTRL_CMD_FREE_F		FW_EQ_CTRL_CMD_FREE_V(1U)
1866 
1867 #define FW_EQ_CTRL_CMD_MODIFY_S		29
1868 #define FW_EQ_CTRL_CMD_MODIFY_V(x)	((x) << FW_EQ_CTRL_CMD_MODIFY_S)
1869 #define FW_EQ_CTRL_CMD_MODIFY_F		FW_EQ_CTRL_CMD_MODIFY_V(1U)
1870 
1871 #define FW_EQ_CTRL_CMD_EQSTART_S	28
1872 #define FW_EQ_CTRL_CMD_EQSTART_V(x)	((x) << FW_EQ_CTRL_CMD_EQSTART_S)
1873 #define FW_EQ_CTRL_CMD_EQSTART_F	FW_EQ_CTRL_CMD_EQSTART_V(1U)
1874 
1875 #define FW_EQ_CTRL_CMD_EQSTOP_S		27
1876 #define FW_EQ_CTRL_CMD_EQSTOP_V(x)	((x) << FW_EQ_CTRL_CMD_EQSTOP_S)
1877 #define FW_EQ_CTRL_CMD_EQSTOP_F		FW_EQ_CTRL_CMD_EQSTOP_V(1U)
1878 
1879 #define FW_EQ_CTRL_CMD_CMPLIQID_S	20
1880 #define FW_EQ_CTRL_CMD_CMPLIQID_V(x)	((x) << FW_EQ_CTRL_CMD_CMPLIQID_S)
1881 
1882 #define FW_EQ_CTRL_CMD_EQID_S		0
1883 #define FW_EQ_CTRL_CMD_EQID_M		0xfffff
1884 #define FW_EQ_CTRL_CMD_EQID_V(x)	((x) << FW_EQ_CTRL_CMD_EQID_S)
1885 #define FW_EQ_CTRL_CMD_EQID_G(x)	\
1886 	(((x) >> FW_EQ_CTRL_CMD_EQID_S) & FW_EQ_CTRL_CMD_EQID_M)
1887 
1888 #define FW_EQ_CTRL_CMD_PHYSEQID_S	0
1889 #define FW_EQ_CTRL_CMD_PHYSEQID_M	0xfffff
1890 #define FW_EQ_CTRL_CMD_PHYSEQID_G(x)	\
1891 	(((x) >> FW_EQ_CTRL_CMD_PHYSEQID_S) & FW_EQ_CTRL_CMD_PHYSEQID_M)
1892 
1893 #define FW_EQ_CTRL_CMD_FETCHSZM_S	26
1894 #define FW_EQ_CTRL_CMD_FETCHSZM_V(x)	((x) << FW_EQ_CTRL_CMD_FETCHSZM_S)
1895 #define FW_EQ_CTRL_CMD_FETCHSZM_F	FW_EQ_CTRL_CMD_FETCHSZM_V(1U)
1896 
1897 #define FW_EQ_CTRL_CMD_STATUSPGNS_S	25
1898 #define FW_EQ_CTRL_CMD_STATUSPGNS_V(x)	((x) << FW_EQ_CTRL_CMD_STATUSPGNS_S)
1899 #define FW_EQ_CTRL_CMD_STATUSPGNS_F	FW_EQ_CTRL_CMD_STATUSPGNS_V(1U)
1900 
1901 #define FW_EQ_CTRL_CMD_STATUSPGRO_S	24
1902 #define FW_EQ_CTRL_CMD_STATUSPGRO_V(x)	((x) << FW_EQ_CTRL_CMD_STATUSPGRO_S)
1903 #define FW_EQ_CTRL_CMD_STATUSPGRO_F	FW_EQ_CTRL_CMD_STATUSPGRO_V(1U)
1904 
1905 #define FW_EQ_CTRL_CMD_FETCHNS_S	23
1906 #define FW_EQ_CTRL_CMD_FETCHNS_V(x)	((x) << FW_EQ_CTRL_CMD_FETCHNS_S)
1907 #define FW_EQ_CTRL_CMD_FETCHNS_F	FW_EQ_CTRL_CMD_FETCHNS_V(1U)
1908 
1909 #define FW_EQ_CTRL_CMD_FETCHRO_S	22
1910 #define FW_EQ_CTRL_CMD_FETCHRO_V(x)	((x) << FW_EQ_CTRL_CMD_FETCHRO_S)
1911 #define FW_EQ_CTRL_CMD_FETCHRO_F	FW_EQ_CTRL_CMD_FETCHRO_V(1U)
1912 
1913 #define FW_EQ_CTRL_CMD_HOSTFCMODE_S	20
1914 #define FW_EQ_CTRL_CMD_HOSTFCMODE_V(x)	((x) << FW_EQ_CTRL_CMD_HOSTFCMODE_S)
1915 
1916 #define FW_EQ_CTRL_CMD_CPRIO_S		19
1917 #define FW_EQ_CTRL_CMD_CPRIO_V(x)	((x) << FW_EQ_CTRL_CMD_CPRIO_S)
1918 
1919 #define FW_EQ_CTRL_CMD_ONCHIP_S		18
1920 #define FW_EQ_CTRL_CMD_ONCHIP_V(x)	((x) << FW_EQ_CTRL_CMD_ONCHIP_S)
1921 
1922 #define FW_EQ_CTRL_CMD_PCIECHN_S	16
1923 #define FW_EQ_CTRL_CMD_PCIECHN_V(x)	((x) << FW_EQ_CTRL_CMD_PCIECHN_S)
1924 
1925 #define FW_EQ_CTRL_CMD_IQID_S		0
1926 #define FW_EQ_CTRL_CMD_IQID_V(x)	((x) << FW_EQ_CTRL_CMD_IQID_S)
1927 
1928 #define FW_EQ_CTRL_CMD_DCAEN_S		31
1929 #define FW_EQ_CTRL_CMD_DCAEN_V(x)	((x) << FW_EQ_CTRL_CMD_DCAEN_S)
1930 
1931 #define FW_EQ_CTRL_CMD_DCACPU_S		26
1932 #define FW_EQ_CTRL_CMD_DCACPU_V(x)	((x) << FW_EQ_CTRL_CMD_DCACPU_S)
1933 
1934 #define FW_EQ_CTRL_CMD_FBMIN_S		23
1935 #define FW_EQ_CTRL_CMD_FBMIN_V(x)	((x) << FW_EQ_CTRL_CMD_FBMIN_S)
1936 
1937 #define FW_EQ_CTRL_CMD_FBMAX_S		20
1938 #define FW_EQ_CTRL_CMD_FBMAX_V(x)	((x) << FW_EQ_CTRL_CMD_FBMAX_S)
1939 
1940 #define FW_EQ_CTRL_CMD_CIDXFTHRESHO_S		19
1941 #define FW_EQ_CTRL_CMD_CIDXFTHRESHO_V(x)	\
1942 	((x) << FW_EQ_CTRL_CMD_CIDXFTHRESHO_S)
1943 
1944 #define FW_EQ_CTRL_CMD_CIDXFTHRESH_S	16
1945 #define FW_EQ_CTRL_CMD_CIDXFTHRESH_V(x)	((x) << FW_EQ_CTRL_CMD_CIDXFTHRESH_S)
1946 
1947 #define FW_EQ_CTRL_CMD_EQSIZE_S		0
1948 #define FW_EQ_CTRL_CMD_EQSIZE_V(x)	((x) << FW_EQ_CTRL_CMD_EQSIZE_S)
1949 
1950 struct fw_eq_ofld_cmd {
1951 	__be32 op_to_vfn;
1952 	__be32 alloc_to_len16;
1953 	__be32 eqid_pkd;
1954 	__be32 physeqid_pkd;
1955 	__be32 fetchszm_to_iqid;
1956 	__be32 dcaen_to_eqsize;
1957 	__be64 eqaddr;
1958 };
1959 
1960 #define FW_EQ_OFLD_CMD_PFN_S	8
1961 #define FW_EQ_OFLD_CMD_PFN_V(x)	((x) << FW_EQ_OFLD_CMD_PFN_S)
1962 
1963 #define FW_EQ_OFLD_CMD_VFN_S	0
1964 #define FW_EQ_OFLD_CMD_VFN_V(x)	((x) << FW_EQ_OFLD_CMD_VFN_S)
1965 
1966 #define FW_EQ_OFLD_CMD_ALLOC_S		31
1967 #define FW_EQ_OFLD_CMD_ALLOC_V(x)	((x) << FW_EQ_OFLD_CMD_ALLOC_S)
1968 #define FW_EQ_OFLD_CMD_ALLOC_F		FW_EQ_OFLD_CMD_ALLOC_V(1U)
1969 
1970 #define FW_EQ_OFLD_CMD_FREE_S		30
1971 #define FW_EQ_OFLD_CMD_FREE_V(x)	((x) << FW_EQ_OFLD_CMD_FREE_S)
1972 #define FW_EQ_OFLD_CMD_FREE_F		FW_EQ_OFLD_CMD_FREE_V(1U)
1973 
1974 #define FW_EQ_OFLD_CMD_MODIFY_S		29
1975 #define FW_EQ_OFLD_CMD_MODIFY_V(x)	((x) << FW_EQ_OFLD_CMD_MODIFY_S)
1976 #define FW_EQ_OFLD_CMD_MODIFY_F		FW_EQ_OFLD_CMD_MODIFY_V(1U)
1977 
1978 #define FW_EQ_OFLD_CMD_EQSTART_S	28
1979 #define FW_EQ_OFLD_CMD_EQSTART_V(x)	((x) << FW_EQ_OFLD_CMD_EQSTART_S)
1980 #define FW_EQ_OFLD_CMD_EQSTART_F	FW_EQ_OFLD_CMD_EQSTART_V(1U)
1981 
1982 #define FW_EQ_OFLD_CMD_EQSTOP_S		27
1983 #define FW_EQ_OFLD_CMD_EQSTOP_V(x)	((x) << FW_EQ_OFLD_CMD_EQSTOP_S)
1984 #define FW_EQ_OFLD_CMD_EQSTOP_F		FW_EQ_OFLD_CMD_EQSTOP_V(1U)
1985 
1986 #define FW_EQ_OFLD_CMD_EQID_S		0
1987 #define FW_EQ_OFLD_CMD_EQID_M		0xfffff
1988 #define FW_EQ_OFLD_CMD_EQID_V(x)	((x) << FW_EQ_OFLD_CMD_EQID_S)
1989 #define FW_EQ_OFLD_CMD_EQID_G(x)	\
1990 	(((x) >> FW_EQ_OFLD_CMD_EQID_S) & FW_EQ_OFLD_CMD_EQID_M)
1991 
1992 #define FW_EQ_OFLD_CMD_PHYSEQID_S	0
1993 #define FW_EQ_OFLD_CMD_PHYSEQID_M	0xfffff
1994 #define FW_EQ_OFLD_CMD_PHYSEQID_G(x)	\
1995 	(((x) >> FW_EQ_OFLD_CMD_PHYSEQID_S) & FW_EQ_OFLD_CMD_PHYSEQID_M)
1996 
1997 #define FW_EQ_OFLD_CMD_FETCHSZM_S	26
1998 #define FW_EQ_OFLD_CMD_FETCHSZM_V(x)	((x) << FW_EQ_OFLD_CMD_FETCHSZM_S)
1999 
2000 #define FW_EQ_OFLD_CMD_STATUSPGNS_S	25
2001 #define FW_EQ_OFLD_CMD_STATUSPGNS_V(x)	((x) << FW_EQ_OFLD_CMD_STATUSPGNS_S)
2002 
2003 #define FW_EQ_OFLD_CMD_STATUSPGRO_S	24
2004 #define FW_EQ_OFLD_CMD_STATUSPGRO_V(x)	((x) << FW_EQ_OFLD_CMD_STATUSPGRO_S)
2005 
2006 #define FW_EQ_OFLD_CMD_FETCHNS_S	23
2007 #define FW_EQ_OFLD_CMD_FETCHNS_V(x)	((x) << FW_EQ_OFLD_CMD_FETCHNS_S)
2008 
2009 #define FW_EQ_OFLD_CMD_FETCHRO_S	22
2010 #define FW_EQ_OFLD_CMD_FETCHRO_V(x)	((x) << FW_EQ_OFLD_CMD_FETCHRO_S)
2011 #define FW_EQ_OFLD_CMD_FETCHRO_F	FW_EQ_OFLD_CMD_FETCHRO_V(1U)
2012 
2013 #define FW_EQ_OFLD_CMD_HOSTFCMODE_S	20
2014 #define FW_EQ_OFLD_CMD_HOSTFCMODE_V(x)	((x) << FW_EQ_OFLD_CMD_HOSTFCMODE_S)
2015 
2016 #define FW_EQ_OFLD_CMD_CPRIO_S		19
2017 #define FW_EQ_OFLD_CMD_CPRIO_V(x)	((x) << FW_EQ_OFLD_CMD_CPRIO_S)
2018 
2019 #define FW_EQ_OFLD_CMD_ONCHIP_S		18
2020 #define FW_EQ_OFLD_CMD_ONCHIP_V(x)	((x) << FW_EQ_OFLD_CMD_ONCHIP_S)
2021 
2022 #define FW_EQ_OFLD_CMD_PCIECHN_S	16
2023 #define FW_EQ_OFLD_CMD_PCIECHN_V(x)	((x) << FW_EQ_OFLD_CMD_PCIECHN_S)
2024 
2025 #define FW_EQ_OFLD_CMD_IQID_S		0
2026 #define FW_EQ_OFLD_CMD_IQID_V(x)	((x) << FW_EQ_OFLD_CMD_IQID_S)
2027 
2028 #define FW_EQ_OFLD_CMD_DCAEN_S		31
2029 #define FW_EQ_OFLD_CMD_DCAEN_V(x)	((x) << FW_EQ_OFLD_CMD_DCAEN_S)
2030 
2031 #define FW_EQ_OFLD_CMD_DCACPU_S		26
2032 #define FW_EQ_OFLD_CMD_DCACPU_V(x)	((x) << FW_EQ_OFLD_CMD_DCACPU_S)
2033 
2034 #define FW_EQ_OFLD_CMD_FBMIN_S		23
2035 #define FW_EQ_OFLD_CMD_FBMIN_V(x)	((x) << FW_EQ_OFLD_CMD_FBMIN_S)
2036 
2037 #define FW_EQ_OFLD_CMD_FBMAX_S		20
2038 #define FW_EQ_OFLD_CMD_FBMAX_V(x)	((x) << FW_EQ_OFLD_CMD_FBMAX_S)
2039 
2040 #define FW_EQ_OFLD_CMD_CIDXFTHRESHO_S		19
2041 #define FW_EQ_OFLD_CMD_CIDXFTHRESHO_V(x)	\
2042 	((x) << FW_EQ_OFLD_CMD_CIDXFTHRESHO_S)
2043 
2044 #define FW_EQ_OFLD_CMD_CIDXFTHRESH_S	16
2045 #define FW_EQ_OFLD_CMD_CIDXFTHRESH_V(x)	((x) << FW_EQ_OFLD_CMD_CIDXFTHRESH_S)
2046 
2047 #define FW_EQ_OFLD_CMD_EQSIZE_S		0
2048 #define FW_EQ_OFLD_CMD_EQSIZE_V(x)	((x) << FW_EQ_OFLD_CMD_EQSIZE_S)
2049 
2050 /*
2051  * Macros for VIID parsing:
2052  * VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number
2053  */
2054 
2055 #define FW_VIID_PFN_S           8
2056 #define FW_VIID_PFN_M           0x7
2057 #define FW_VIID_PFN_G(x)        (((x) >> FW_VIID_PFN_S) & FW_VIID_PFN_M)
2058 
2059 #define FW_VIID_VIVLD_S		7
2060 #define FW_VIID_VIVLD_M		0x1
2061 #define FW_VIID_VIVLD_G(x)	(((x) >> FW_VIID_VIVLD_S) & FW_VIID_VIVLD_M)
2062 
2063 #define FW_VIID_VIN_S		0
2064 #define FW_VIID_VIN_M		0x7F
2065 #define FW_VIID_VIN_G(x)	(((x) >> FW_VIID_VIN_S) & FW_VIID_VIN_M)
2066 
2067 struct fw_vi_cmd {
2068 	__be32 op_to_vfn;
2069 	__be32 alloc_to_len16;
2070 	__be16 type_viid;
2071 	u8 mac[6];
2072 	u8 portid_pkd;
2073 	u8 nmac;
2074 	u8 nmac0[6];
2075 	__be16 rsssize_pkd;
2076 	u8 nmac1[6];
2077 	__be16 idsiiq_pkd;
2078 	u8 nmac2[6];
2079 	__be16 idseiq_pkd;
2080 	u8 nmac3[6];
2081 	__be64 r9;
2082 	__be64 r10;
2083 };
2084 
2085 #define FW_VI_CMD_PFN_S		8
2086 #define FW_VI_CMD_PFN_V(x)	((x) << FW_VI_CMD_PFN_S)
2087 
2088 #define FW_VI_CMD_VFN_S		0
2089 #define FW_VI_CMD_VFN_V(x)	((x) << FW_VI_CMD_VFN_S)
2090 
2091 #define FW_VI_CMD_ALLOC_S	31
2092 #define FW_VI_CMD_ALLOC_V(x)	((x) << FW_VI_CMD_ALLOC_S)
2093 #define FW_VI_CMD_ALLOC_F	FW_VI_CMD_ALLOC_V(1U)
2094 
2095 #define FW_VI_CMD_FREE_S	30
2096 #define FW_VI_CMD_FREE_V(x)	((x) << FW_VI_CMD_FREE_S)
2097 #define FW_VI_CMD_FREE_F	FW_VI_CMD_FREE_V(1U)
2098 
2099 #define FW_VI_CMD_VIID_S	0
2100 #define FW_VI_CMD_VIID_M	0xfff
2101 #define FW_VI_CMD_VIID_V(x)	((x) << FW_VI_CMD_VIID_S)
2102 #define FW_VI_CMD_VIID_G(x)	(((x) >> FW_VI_CMD_VIID_S) & FW_VI_CMD_VIID_M)
2103 
2104 #define FW_VI_CMD_PORTID_S	4
2105 #define FW_VI_CMD_PORTID_M	0xf
2106 #define FW_VI_CMD_PORTID_V(x)	((x) << FW_VI_CMD_PORTID_S)
2107 #define FW_VI_CMD_PORTID_G(x)	\
2108 	(((x) >> FW_VI_CMD_PORTID_S) & FW_VI_CMD_PORTID_M)
2109 
2110 #define FW_VI_CMD_RSSSIZE_S	0
2111 #define FW_VI_CMD_RSSSIZE_M	0x7ff
2112 #define FW_VI_CMD_RSSSIZE_G(x)	\
2113 	(((x) >> FW_VI_CMD_RSSSIZE_S) & FW_VI_CMD_RSSSIZE_M)
2114 
2115 /* Special VI_MAC command index ids */
2116 #define FW_VI_MAC_ADD_MAC		0x3FF
2117 #define FW_VI_MAC_ADD_PERSIST_MAC	0x3FE
2118 #define FW_VI_MAC_MAC_BASED_FREE	0x3FD
2119 #define FW_VI_MAC_ID_BASED_FREE		0x3FC
2120 #define FW_CLS_TCAM_NUM_ENTRIES		336
2121 
2122 enum fw_vi_mac_smac {
2123 	FW_VI_MAC_MPS_TCAM_ENTRY,
2124 	FW_VI_MAC_MPS_TCAM_ONLY,
2125 	FW_VI_MAC_SMT_ONLY,
2126 	FW_VI_MAC_SMT_AND_MPSTCAM
2127 };
2128 
2129 enum fw_vi_mac_result {
2130 	FW_VI_MAC_R_SUCCESS,
2131 	FW_VI_MAC_R_F_NONEXISTENT_NOMEM,
2132 	FW_VI_MAC_R_SMAC_FAIL,
2133 	FW_VI_MAC_R_F_ACL_CHECK
2134 };
2135 
2136 enum fw_vi_mac_entry_types {
2137 	FW_VI_MAC_TYPE_EXACTMAC,
2138 	FW_VI_MAC_TYPE_HASHVEC,
2139 	FW_VI_MAC_TYPE_RAW,
2140 	FW_VI_MAC_TYPE_EXACTMAC_VNI,
2141 };
2142 
2143 struct fw_vi_mac_cmd {
2144 	__be32 op_to_viid;
2145 	__be32 freemacs_to_len16;
2146 	union fw_vi_mac {
2147 		struct fw_vi_mac_exact {
2148 			__be16 valid_to_idx;
2149 			u8 macaddr[6];
2150 		} exact[7];
2151 		struct fw_vi_mac_hash {
2152 			__be64 hashvec;
2153 		} hash;
2154 		struct fw_vi_mac_raw {
2155 			__be32 raw_idx_pkd;
2156 			__be32 data0_pkd;
2157 			__be32 data1[2];
2158 			__be64 data0m_pkd;
2159 			__be32 data1m[2];
2160 		} raw;
2161 		struct fw_vi_mac_vni {
2162 			__be16 valid_to_idx;
2163 			__u8 macaddr[6];
2164 			__be16 r7;
2165 			__u8 macaddr_mask[6];
2166 			__be32 lookup_type_to_vni;
2167 			__be32 vni_mask_pkd;
2168 		} exact_vni[2];
2169 	} u;
2170 };
2171 
2172 #define FW_VI_MAC_CMD_VIID_S	0
2173 #define FW_VI_MAC_CMD_VIID_V(x)	((x) << FW_VI_MAC_CMD_VIID_S)
2174 
2175 #define FW_VI_MAC_CMD_FREEMACS_S	31
2176 #define FW_VI_MAC_CMD_FREEMACS_V(x)	((x) << FW_VI_MAC_CMD_FREEMACS_S)
2177 
2178 #define FW_VI_MAC_CMD_ENTRY_TYPE_S      23
2179 #define FW_VI_MAC_CMD_ENTRY_TYPE_M      0x7
2180 #define FW_VI_MAC_CMD_ENTRY_TYPE_V(x)   ((x) << FW_VI_MAC_CMD_ENTRY_TYPE_S)
2181 #define FW_VI_MAC_CMD_ENTRY_TYPE_G(x)	\
2182 	(((x) >> FW_VI_MAC_CMD_ENTRY_TYPE_S) & FW_VI_MAC_CMD_ENTRY_TYPE_M)
2183 
2184 #define FW_VI_MAC_CMD_HASHVECEN_S	23
2185 #define FW_VI_MAC_CMD_HASHVECEN_V(x)	((x) << FW_VI_MAC_CMD_HASHVECEN_S)
2186 #define FW_VI_MAC_CMD_HASHVECEN_F	FW_VI_MAC_CMD_HASHVECEN_V(1U)
2187 
2188 #define FW_VI_MAC_CMD_HASHUNIEN_S	22
2189 #define FW_VI_MAC_CMD_HASHUNIEN_V(x)	((x) << FW_VI_MAC_CMD_HASHUNIEN_S)
2190 
2191 #define FW_VI_MAC_CMD_VALID_S		15
2192 #define FW_VI_MAC_CMD_VALID_V(x)	((x) << FW_VI_MAC_CMD_VALID_S)
2193 #define FW_VI_MAC_CMD_VALID_F	FW_VI_MAC_CMD_VALID_V(1U)
2194 
2195 #define FW_VI_MAC_CMD_PRIO_S	12
2196 #define FW_VI_MAC_CMD_PRIO_V(x)	((x) << FW_VI_MAC_CMD_PRIO_S)
2197 
2198 #define FW_VI_MAC_CMD_SMAC_RESULT_S	10
2199 #define FW_VI_MAC_CMD_SMAC_RESULT_M	0x3
2200 #define FW_VI_MAC_CMD_SMAC_RESULT_V(x)	((x) << FW_VI_MAC_CMD_SMAC_RESULT_S)
2201 #define FW_VI_MAC_CMD_SMAC_RESULT_G(x)	\
2202 	(((x) >> FW_VI_MAC_CMD_SMAC_RESULT_S) & FW_VI_MAC_CMD_SMAC_RESULT_M)
2203 
2204 #define FW_VI_MAC_CMD_IDX_S	0
2205 #define FW_VI_MAC_CMD_IDX_M	0x3ff
2206 #define FW_VI_MAC_CMD_IDX_V(x)	((x) << FW_VI_MAC_CMD_IDX_S)
2207 #define FW_VI_MAC_CMD_IDX_G(x)	\
2208 	(((x) >> FW_VI_MAC_CMD_IDX_S) & FW_VI_MAC_CMD_IDX_M)
2209 
2210 #define FW_VI_MAC_CMD_RAW_IDX_S         16
2211 #define FW_VI_MAC_CMD_RAW_IDX_M         0xffff
2212 #define FW_VI_MAC_CMD_RAW_IDX_V(x)      ((x) << FW_VI_MAC_CMD_RAW_IDX_S)
2213 #define FW_VI_MAC_CMD_RAW_IDX_G(x)      \
2214 	(((x) >> FW_VI_MAC_CMD_RAW_IDX_S) & FW_VI_MAC_CMD_RAW_IDX_M)
2215 
2216 #define FW_VI_MAC_CMD_LOOKUP_TYPE_S	31
2217 #define FW_VI_MAC_CMD_LOOKUP_TYPE_M	0x1
2218 #define FW_VI_MAC_CMD_LOOKUP_TYPE_V(x)	((x) << FW_VI_MAC_CMD_LOOKUP_TYPE_S)
2219 #define FW_VI_MAC_CMD_LOOKUP_TYPE_G(x)	\
2220 	(((x) >> FW_VI_MAC_CMD_LOOKUP_TYPE_S) & FW_VI_MAC_CMD_LOOKUP_TYPE_M)
2221 #define FW_VI_MAC_CMD_LOOKUP_TYPE_F	FW_VI_MAC_CMD_LOOKUP_TYPE_V(1U)
2222 
2223 #define FW_VI_MAC_CMD_DIP_HIT_S		30
2224 #define FW_VI_MAC_CMD_DIP_HIT_M		0x1
2225 #define FW_VI_MAC_CMD_DIP_HIT_V(x)	((x) << FW_VI_MAC_CMD_DIP_HIT_S)
2226 #define FW_VI_MAC_CMD_DIP_HIT_G(x)	\
2227 	(((x) >> FW_VI_MAC_CMD_DIP_HIT_S) & FW_VI_MAC_CMD_DIP_HIT_M)
2228 #define FW_VI_MAC_CMD_DIP_HIT_F		FW_VI_MAC_CMD_DIP_HIT_V(1U)
2229 
2230 #define FW_VI_MAC_CMD_VNI_S		0
2231 #define FW_VI_MAC_CMD_VNI_M		0xffffff
2232 #define FW_VI_MAC_CMD_VNI_V(x)		((x) << FW_VI_MAC_CMD_VNI_S)
2233 #define FW_VI_MAC_CMD_VNI_G(x)		\
2234 	(((x) >> FW_VI_MAC_CMD_VNI_S) & FW_VI_MAC_CMD_VNI_M)
2235 
2236 #define FW_VI_MAC_CMD_VNI_MASK_S	0
2237 #define FW_VI_MAC_CMD_VNI_MASK_M	0xffffff
2238 #define FW_VI_MAC_CMD_VNI_MASK_V(x)	((x) << FW_VI_MAC_CMD_VNI_MASK_S)
2239 #define FW_VI_MAC_CMD_VNI_MASK_G(x)	\
2240 	(((x) >> FW_VI_MAC_CMD_VNI_MASK_S) & FW_VI_MAC_CMD_VNI_MASK_M)
2241 
2242 #define FW_RXMODE_MTU_NO_CHG	65535
2243 
2244 struct fw_vi_rxmode_cmd {
2245 	__be32 op_to_viid;
2246 	__be32 retval_len16;
2247 	__be32 mtu_to_vlanexen;
2248 	__be32 r4_lo;
2249 };
2250 
2251 #define FW_VI_RXMODE_CMD_VIID_S		0
2252 #define FW_VI_RXMODE_CMD_VIID_V(x)	((x) << FW_VI_RXMODE_CMD_VIID_S)
2253 
2254 #define FW_VI_RXMODE_CMD_MTU_S		16
2255 #define FW_VI_RXMODE_CMD_MTU_M		0xffff
2256 #define FW_VI_RXMODE_CMD_MTU_V(x)	((x) << FW_VI_RXMODE_CMD_MTU_S)
2257 
2258 #define FW_VI_RXMODE_CMD_PROMISCEN_S	14
2259 #define FW_VI_RXMODE_CMD_PROMISCEN_M	0x3
2260 #define FW_VI_RXMODE_CMD_PROMISCEN_V(x)	((x) << FW_VI_RXMODE_CMD_PROMISCEN_S)
2261 
2262 #define FW_VI_RXMODE_CMD_ALLMULTIEN_S		12
2263 #define FW_VI_RXMODE_CMD_ALLMULTIEN_M		0x3
2264 #define FW_VI_RXMODE_CMD_ALLMULTIEN_V(x)	\
2265 	((x) << FW_VI_RXMODE_CMD_ALLMULTIEN_S)
2266 
2267 #define FW_VI_RXMODE_CMD_BROADCASTEN_S		10
2268 #define FW_VI_RXMODE_CMD_BROADCASTEN_M		0x3
2269 #define FW_VI_RXMODE_CMD_BROADCASTEN_V(x)	\
2270 	((x) << FW_VI_RXMODE_CMD_BROADCASTEN_S)
2271 
2272 #define FW_VI_RXMODE_CMD_VLANEXEN_S	8
2273 #define FW_VI_RXMODE_CMD_VLANEXEN_M	0x3
2274 #define FW_VI_RXMODE_CMD_VLANEXEN_V(x)	((x) << FW_VI_RXMODE_CMD_VLANEXEN_S)
2275 
2276 struct fw_vi_enable_cmd {
2277 	__be32 op_to_viid;
2278 	__be32 ien_to_len16;
2279 	__be16 blinkdur;
2280 	__be16 r3;
2281 	__be32 r4;
2282 };
2283 
2284 #define FW_VI_ENABLE_CMD_VIID_S         0
2285 #define FW_VI_ENABLE_CMD_VIID_V(x)      ((x) << FW_VI_ENABLE_CMD_VIID_S)
2286 
2287 #define FW_VI_ENABLE_CMD_IEN_S		31
2288 #define FW_VI_ENABLE_CMD_IEN_V(x)	((x) << FW_VI_ENABLE_CMD_IEN_S)
2289 
2290 #define FW_VI_ENABLE_CMD_EEN_S		30
2291 #define FW_VI_ENABLE_CMD_EEN_V(x)	((x) << FW_VI_ENABLE_CMD_EEN_S)
2292 
2293 #define FW_VI_ENABLE_CMD_LED_S		29
2294 #define FW_VI_ENABLE_CMD_LED_V(x)	((x) << FW_VI_ENABLE_CMD_LED_S)
2295 #define FW_VI_ENABLE_CMD_LED_F	FW_VI_ENABLE_CMD_LED_V(1U)
2296 
2297 #define FW_VI_ENABLE_CMD_DCB_INFO_S	28
2298 #define FW_VI_ENABLE_CMD_DCB_INFO_V(x)	((x) << FW_VI_ENABLE_CMD_DCB_INFO_S)
2299 
2300 /* VI VF stats offset definitions */
2301 #define VI_VF_NUM_STATS	16
2302 enum fw_vi_stats_vf_index {
2303 	FW_VI_VF_STAT_TX_BCAST_BYTES_IX,
2304 	FW_VI_VF_STAT_TX_BCAST_FRAMES_IX,
2305 	FW_VI_VF_STAT_TX_MCAST_BYTES_IX,
2306 	FW_VI_VF_STAT_TX_MCAST_FRAMES_IX,
2307 	FW_VI_VF_STAT_TX_UCAST_BYTES_IX,
2308 	FW_VI_VF_STAT_TX_UCAST_FRAMES_IX,
2309 	FW_VI_VF_STAT_TX_DROP_FRAMES_IX,
2310 	FW_VI_VF_STAT_TX_OFLD_BYTES_IX,
2311 	FW_VI_VF_STAT_TX_OFLD_FRAMES_IX,
2312 	FW_VI_VF_STAT_RX_BCAST_BYTES_IX,
2313 	FW_VI_VF_STAT_RX_BCAST_FRAMES_IX,
2314 	FW_VI_VF_STAT_RX_MCAST_BYTES_IX,
2315 	FW_VI_VF_STAT_RX_MCAST_FRAMES_IX,
2316 	FW_VI_VF_STAT_RX_UCAST_BYTES_IX,
2317 	FW_VI_VF_STAT_RX_UCAST_FRAMES_IX,
2318 	FW_VI_VF_STAT_RX_ERR_FRAMES_IX
2319 };
2320 
2321 /* VI PF stats offset definitions */
2322 #define VI_PF_NUM_STATS	17
2323 enum fw_vi_stats_pf_index {
2324 	FW_VI_PF_STAT_TX_BCAST_BYTES_IX,
2325 	FW_VI_PF_STAT_TX_BCAST_FRAMES_IX,
2326 	FW_VI_PF_STAT_TX_MCAST_BYTES_IX,
2327 	FW_VI_PF_STAT_TX_MCAST_FRAMES_IX,
2328 	FW_VI_PF_STAT_TX_UCAST_BYTES_IX,
2329 	FW_VI_PF_STAT_TX_UCAST_FRAMES_IX,
2330 	FW_VI_PF_STAT_TX_OFLD_BYTES_IX,
2331 	FW_VI_PF_STAT_TX_OFLD_FRAMES_IX,
2332 	FW_VI_PF_STAT_RX_BYTES_IX,
2333 	FW_VI_PF_STAT_RX_FRAMES_IX,
2334 	FW_VI_PF_STAT_RX_BCAST_BYTES_IX,
2335 	FW_VI_PF_STAT_RX_BCAST_FRAMES_IX,
2336 	FW_VI_PF_STAT_RX_MCAST_BYTES_IX,
2337 	FW_VI_PF_STAT_RX_MCAST_FRAMES_IX,
2338 	FW_VI_PF_STAT_RX_UCAST_BYTES_IX,
2339 	FW_VI_PF_STAT_RX_UCAST_FRAMES_IX,
2340 	FW_VI_PF_STAT_RX_ERR_FRAMES_IX
2341 };
2342 
2343 struct fw_vi_stats_cmd {
2344 	__be32 op_to_viid;
2345 	__be32 retval_len16;
2346 	union fw_vi_stats {
2347 		struct fw_vi_stats_ctl {
2348 			__be16 nstats_ix;
2349 			__be16 r6;
2350 			__be32 r7;
2351 			__be64 stat0;
2352 			__be64 stat1;
2353 			__be64 stat2;
2354 			__be64 stat3;
2355 			__be64 stat4;
2356 			__be64 stat5;
2357 		} ctl;
2358 		struct fw_vi_stats_pf {
2359 			__be64 tx_bcast_bytes;
2360 			__be64 tx_bcast_frames;
2361 			__be64 tx_mcast_bytes;
2362 			__be64 tx_mcast_frames;
2363 			__be64 tx_ucast_bytes;
2364 			__be64 tx_ucast_frames;
2365 			__be64 tx_offload_bytes;
2366 			__be64 tx_offload_frames;
2367 			__be64 rx_pf_bytes;
2368 			__be64 rx_pf_frames;
2369 			__be64 rx_bcast_bytes;
2370 			__be64 rx_bcast_frames;
2371 			__be64 rx_mcast_bytes;
2372 			__be64 rx_mcast_frames;
2373 			__be64 rx_ucast_bytes;
2374 			__be64 rx_ucast_frames;
2375 			__be64 rx_err_frames;
2376 		} pf;
2377 		struct fw_vi_stats_vf {
2378 			__be64 tx_bcast_bytes;
2379 			__be64 tx_bcast_frames;
2380 			__be64 tx_mcast_bytes;
2381 			__be64 tx_mcast_frames;
2382 			__be64 tx_ucast_bytes;
2383 			__be64 tx_ucast_frames;
2384 			__be64 tx_drop_frames;
2385 			__be64 tx_offload_bytes;
2386 			__be64 tx_offload_frames;
2387 			__be64 rx_bcast_bytes;
2388 			__be64 rx_bcast_frames;
2389 			__be64 rx_mcast_bytes;
2390 			__be64 rx_mcast_frames;
2391 			__be64 rx_ucast_bytes;
2392 			__be64 rx_ucast_frames;
2393 			__be64 rx_err_frames;
2394 		} vf;
2395 	} u;
2396 };
2397 
2398 #define FW_VI_STATS_CMD_VIID_S		0
2399 #define FW_VI_STATS_CMD_VIID_V(x)	((x) << FW_VI_STATS_CMD_VIID_S)
2400 
2401 #define FW_VI_STATS_CMD_NSTATS_S	12
2402 #define FW_VI_STATS_CMD_NSTATS_V(x)	((x) << FW_VI_STATS_CMD_NSTATS_S)
2403 
2404 #define FW_VI_STATS_CMD_IX_S	0
2405 #define FW_VI_STATS_CMD_IX_V(x)	((x) << FW_VI_STATS_CMD_IX_S)
2406 
2407 struct fw_acl_mac_cmd {
2408 	__be32 op_to_vfn;
2409 	__be32 en_to_len16;
2410 	u8 nmac;
2411 	u8 r3[7];
2412 	__be16 r4;
2413 	u8 macaddr0[6];
2414 	__be16 r5;
2415 	u8 macaddr1[6];
2416 	__be16 r6;
2417 	u8 macaddr2[6];
2418 	__be16 r7;
2419 	u8 macaddr3[6];
2420 };
2421 
2422 #define FW_ACL_MAC_CMD_PFN_S	8
2423 #define FW_ACL_MAC_CMD_PFN_V(x)	((x) << FW_ACL_MAC_CMD_PFN_S)
2424 
2425 #define FW_ACL_MAC_CMD_VFN_S	0
2426 #define FW_ACL_MAC_CMD_VFN_V(x)	((x) << FW_ACL_MAC_CMD_VFN_S)
2427 
2428 #define FW_ACL_MAC_CMD_EN_S	31
2429 #define FW_ACL_MAC_CMD_EN_V(x)	((x) << FW_ACL_MAC_CMD_EN_S)
2430 
2431 struct fw_acl_vlan_cmd {
2432 	__be32 op_to_vfn;
2433 	__be32 en_to_len16;
2434 	u8 nvlan;
2435 	u8 dropnovlan_fm;
2436 	u8 r3_lo[6];
2437 	__be16 vlanid[16];
2438 };
2439 
2440 #define FW_ACL_VLAN_CMD_PFN_S		8
2441 #define FW_ACL_VLAN_CMD_PFN_V(x)	((x) << FW_ACL_VLAN_CMD_PFN_S)
2442 
2443 #define FW_ACL_VLAN_CMD_VFN_S		0
2444 #define FW_ACL_VLAN_CMD_VFN_V(x)	((x) << FW_ACL_VLAN_CMD_VFN_S)
2445 
2446 #define FW_ACL_VLAN_CMD_EN_S		31
2447 #define FW_ACL_VLAN_CMD_EN_M		0x1
2448 #define FW_ACL_VLAN_CMD_EN_V(x)		((x) << FW_ACL_VLAN_CMD_EN_S)
2449 #define FW_ACL_VLAN_CMD_EN_G(x)         \
2450 	(((x) >> S_FW_ACL_VLAN_CMD_EN_S) & FW_ACL_VLAN_CMD_EN_M)
2451 #define FW_ACL_VLAN_CMD_EN_F            FW_ACL_VLAN_CMD_EN_V(1U)
2452 
2453 #define FW_ACL_VLAN_CMD_DROPNOVLAN_S	7
2454 #define FW_ACL_VLAN_CMD_DROPNOVLAN_V(x)	((x) << FW_ACL_VLAN_CMD_DROPNOVLAN_S)
2455 
2456 #define FW_ACL_VLAN_CMD_FM_S		6
2457 #define FW_ACL_VLAN_CMD_FM_M		0x1
2458 #define FW_ACL_VLAN_CMD_FM_V(x)         ((x) << FW_ACL_VLAN_CMD_FM_S)
2459 #define FW_ACL_VLAN_CMD_FM_G(x)         \
2460 	(((x) >> FW_ACL_VLAN_CMD_FM_S) & FW_ACL_VLAN_CMD_FM_M)
2461 #define FW_ACL_VLAN_CMD_FM_F            FW_ACL_VLAN_CMD_FM_V(1U)
2462 
2463 /* old 16-bit port capabilities bitmap (fw_port_cap16_t) */
2464 enum fw_port_cap {
2465 	FW_PORT_CAP_SPEED_100M		= 0x0001,
2466 	FW_PORT_CAP_SPEED_1G		= 0x0002,
2467 	FW_PORT_CAP_SPEED_25G		= 0x0004,
2468 	FW_PORT_CAP_SPEED_10G		= 0x0008,
2469 	FW_PORT_CAP_SPEED_40G		= 0x0010,
2470 	FW_PORT_CAP_SPEED_100G		= 0x0020,
2471 	FW_PORT_CAP_FC_RX		= 0x0040,
2472 	FW_PORT_CAP_FC_TX		= 0x0080,
2473 	FW_PORT_CAP_ANEG		= 0x0100,
2474 	FW_PORT_CAP_MDIAUTO		= 0x0200,
2475 	FW_PORT_CAP_MDISTRAIGHT		= 0x0400,
2476 	FW_PORT_CAP_FEC_RS		= 0x0800,
2477 	FW_PORT_CAP_FEC_BASER_RS	= 0x1000,
2478 	FW_PORT_CAP_FORCE_PAUSE		= 0x2000,
2479 	FW_PORT_CAP_802_3_PAUSE		= 0x4000,
2480 	FW_PORT_CAP_802_3_ASM_DIR	= 0x8000,
2481 };
2482 
2483 #define FW_PORT_CAP_SPEED_S     0
2484 #define FW_PORT_CAP_SPEED_M     0x3f
2485 #define FW_PORT_CAP_SPEED_V(x)  ((x) << FW_PORT_CAP_SPEED_S)
2486 #define FW_PORT_CAP_SPEED_G(x) \
2487 	(((x) >> FW_PORT_CAP_SPEED_S) & FW_PORT_CAP_SPEED_M)
2488 
2489 enum fw_port_mdi {
2490 	FW_PORT_CAP_MDI_UNCHANGED,
2491 	FW_PORT_CAP_MDI_AUTO,
2492 	FW_PORT_CAP_MDI_F_STRAIGHT,
2493 	FW_PORT_CAP_MDI_F_CROSSOVER
2494 };
2495 
2496 #define FW_PORT_CAP_MDI_S 9
2497 #define FW_PORT_CAP_MDI_V(x) ((x) << FW_PORT_CAP_MDI_S)
2498 
2499 /* new 32-bit port capabilities bitmap (fw_port_cap32_t) */
2500 #define	FW_PORT_CAP32_SPEED_100M	0x00000001UL
2501 #define	FW_PORT_CAP32_SPEED_1G		0x00000002UL
2502 #define	FW_PORT_CAP32_SPEED_10G		0x00000004UL
2503 #define	FW_PORT_CAP32_SPEED_25G		0x00000008UL
2504 #define	FW_PORT_CAP32_SPEED_40G		0x00000010UL
2505 #define	FW_PORT_CAP32_SPEED_50G		0x00000020UL
2506 #define	FW_PORT_CAP32_SPEED_100G	0x00000040UL
2507 #define	FW_PORT_CAP32_SPEED_200G	0x00000080UL
2508 #define	FW_PORT_CAP32_SPEED_400G	0x00000100UL
2509 #define	FW_PORT_CAP32_SPEED_RESERVED1	0x00000200UL
2510 #define	FW_PORT_CAP32_SPEED_RESERVED2	0x00000400UL
2511 #define	FW_PORT_CAP32_SPEED_RESERVED3	0x00000800UL
2512 #define	FW_PORT_CAP32_RESERVED1		0x0000f000UL
2513 #define	FW_PORT_CAP32_FC_RX		0x00010000UL
2514 #define	FW_PORT_CAP32_FC_TX		0x00020000UL
2515 #define	FW_PORT_CAP32_802_3_PAUSE	0x00040000UL
2516 #define	FW_PORT_CAP32_802_3_ASM_DIR	0x00080000UL
2517 #define	FW_PORT_CAP32_ANEG		0x00100000UL
2518 #define	FW_PORT_CAP32_MDIAUTO		0x00200000UL
2519 #define	FW_PORT_CAP32_MDISTRAIGHT	0x00400000UL
2520 #define	FW_PORT_CAP32_FEC_RS		0x00800000UL
2521 #define	FW_PORT_CAP32_FEC_BASER_RS	0x01000000UL
2522 #define	FW_PORT_CAP32_FEC_RESERVED1	0x02000000UL
2523 #define	FW_PORT_CAP32_FEC_RESERVED2	0x04000000UL
2524 #define	FW_PORT_CAP32_FEC_RESERVED3	0x08000000UL
2525 #define FW_PORT_CAP32_FORCE_PAUSE	0x10000000UL
2526 #define FW_PORT_CAP32_RESERVED2		0xe0000000UL
2527 
2528 #define FW_PORT_CAP32_SPEED_S	0
2529 #define FW_PORT_CAP32_SPEED_M	0xfff
2530 #define FW_PORT_CAP32_SPEED_V(x)	((x) << FW_PORT_CAP32_SPEED_S)
2531 #define FW_PORT_CAP32_SPEED_G(x) \
2532 	(((x) >> FW_PORT_CAP32_SPEED_S) & FW_PORT_CAP32_SPEED_M)
2533 
2534 #define FW_PORT_CAP32_FC_S	16
2535 #define FW_PORT_CAP32_FC_M	0x3
2536 #define FW_PORT_CAP32_FC_V(x)	((x) << FW_PORT_CAP32_FC_S)
2537 #define FW_PORT_CAP32_FC_G(x) \
2538 	(((x) >> FW_PORT_CAP32_FC_S) & FW_PORT_CAP32_FC_M)
2539 
2540 #define FW_PORT_CAP32_802_3_S	18
2541 #define FW_PORT_CAP32_802_3_M	0x3
2542 #define FW_PORT_CAP32_802_3_V(x)	((x) << FW_PORT_CAP32_802_3_S)
2543 #define FW_PORT_CAP32_802_3_G(x) \
2544 	(((x) >> FW_PORT_CAP32_802_3_S) & FW_PORT_CAP32_802_3_M)
2545 
2546 #define FW_PORT_CAP32_ANEG_S	20
2547 #define FW_PORT_CAP32_ANEG_M	0x1
2548 #define FW_PORT_CAP32_ANEG_V(x)	((x) << FW_PORT_CAP32_ANEG_S)
2549 #define FW_PORT_CAP32_ANEG_G(x) \
2550 	(((x) >> FW_PORT_CAP32_ANEG_S) & FW_PORT_CAP32_ANEG_M)
2551 
2552 enum fw_port_mdi32 {
2553 	FW_PORT_CAP32_MDI_UNCHANGED,
2554 	FW_PORT_CAP32_MDI_AUTO,
2555 	FW_PORT_CAP32_MDI_F_STRAIGHT,
2556 	FW_PORT_CAP32_MDI_F_CROSSOVER
2557 };
2558 
2559 #define FW_PORT_CAP32_MDI_S 21
2560 #define FW_PORT_CAP32_MDI_M 3
2561 #define FW_PORT_CAP32_MDI_V(x) ((x) << FW_PORT_CAP32_MDI_S)
2562 #define FW_PORT_CAP32_MDI_G(x) \
2563 	(((x) >> FW_PORT_CAP32_MDI_S) & FW_PORT_CAP32_MDI_M)
2564 
2565 #define FW_PORT_CAP32_FEC_S	23
2566 #define FW_PORT_CAP32_FEC_M	0x1f
2567 #define FW_PORT_CAP32_FEC_V(x)	((x) << FW_PORT_CAP32_FEC_S)
2568 #define FW_PORT_CAP32_FEC_G(x) \
2569 	(((x) >> FW_PORT_CAP32_FEC_S) & FW_PORT_CAP32_FEC_M)
2570 
2571 /* macros to isolate various 32-bit Port Capabilities sub-fields */
2572 #define CAP32_SPEED(__cap32) \
2573 	(FW_PORT_CAP32_SPEED_V(FW_PORT_CAP32_SPEED_M) & __cap32)
2574 
2575 #define CAP32_FEC(__cap32) \
2576 	(FW_PORT_CAP32_FEC_V(FW_PORT_CAP32_FEC_M) & __cap32)
2577 
2578 enum fw_port_action {
2579 	FW_PORT_ACTION_L1_CFG		= 0x0001,
2580 	FW_PORT_ACTION_L2_CFG		= 0x0002,
2581 	FW_PORT_ACTION_GET_PORT_INFO	= 0x0003,
2582 	FW_PORT_ACTION_L2_PPP_CFG	= 0x0004,
2583 	FW_PORT_ACTION_L2_DCB_CFG	= 0x0005,
2584 	FW_PORT_ACTION_DCB_READ_TRANS	= 0x0006,
2585 	FW_PORT_ACTION_DCB_READ_RECV	= 0x0007,
2586 	FW_PORT_ACTION_DCB_READ_DET	= 0x0008,
2587 	FW_PORT_ACTION_L1_CFG32		= 0x0009,
2588 	FW_PORT_ACTION_GET_PORT_INFO32	= 0x000a,
2589 	FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010,
2590 	FW_PORT_ACTION_L1_LOW_PWR_EN	= 0x0011,
2591 	FW_PORT_ACTION_L2_WOL_MODE_EN	= 0x0012,
2592 	FW_PORT_ACTION_LPBK_TO_NORMAL	= 0x0020,
2593 	FW_PORT_ACTION_L1_LPBK		= 0x0021,
2594 	FW_PORT_ACTION_L1_PMA_LPBK	= 0x0022,
2595 	FW_PORT_ACTION_L1_PCS_LPBK	= 0x0023,
2596 	FW_PORT_ACTION_L1_PHYXS_CSIDE_LPBK = 0x0024,
2597 	FW_PORT_ACTION_L1_PHYXS_ESIDE_LPBK = 0x0025,
2598 	FW_PORT_ACTION_PHY_RESET	= 0x0040,
2599 	FW_PORT_ACTION_PMA_RESET	= 0x0041,
2600 	FW_PORT_ACTION_PCS_RESET	= 0x0042,
2601 	FW_PORT_ACTION_PHYXS_RESET	= 0x0043,
2602 	FW_PORT_ACTION_DTEXS_REEST	= 0x0044,
2603 	FW_PORT_ACTION_AN_RESET		= 0x0045
2604 };
2605 
2606 enum fw_port_l2cfg_ctlbf {
2607 	FW_PORT_L2_CTLBF_OVLAN0	= 0x01,
2608 	FW_PORT_L2_CTLBF_OVLAN1	= 0x02,
2609 	FW_PORT_L2_CTLBF_OVLAN2	= 0x04,
2610 	FW_PORT_L2_CTLBF_OVLAN3	= 0x08,
2611 	FW_PORT_L2_CTLBF_IVLAN	= 0x10,
2612 	FW_PORT_L2_CTLBF_TXIPG	= 0x20
2613 };
2614 
2615 enum fw_port_dcb_versions {
2616 	FW_PORT_DCB_VER_UNKNOWN,
2617 	FW_PORT_DCB_VER_CEE1D0,
2618 	FW_PORT_DCB_VER_CEE1D01,
2619 	FW_PORT_DCB_VER_IEEE,
2620 	FW_PORT_DCB_VER_AUTO = 7
2621 };
2622 
2623 enum fw_port_dcb_cfg {
2624 	FW_PORT_DCB_CFG_PG	= 0x01,
2625 	FW_PORT_DCB_CFG_PFC	= 0x02,
2626 	FW_PORT_DCB_CFG_APPL	= 0x04
2627 };
2628 
2629 enum fw_port_dcb_cfg_rc {
2630 	FW_PORT_DCB_CFG_SUCCESS	= 0x0,
2631 	FW_PORT_DCB_CFG_ERROR	= 0x1
2632 };
2633 
2634 enum fw_port_dcb_type {
2635 	FW_PORT_DCB_TYPE_PGID		= 0x00,
2636 	FW_PORT_DCB_TYPE_PGRATE		= 0x01,
2637 	FW_PORT_DCB_TYPE_PRIORATE	= 0x02,
2638 	FW_PORT_DCB_TYPE_PFC		= 0x03,
2639 	FW_PORT_DCB_TYPE_APP_ID		= 0x04,
2640 	FW_PORT_DCB_TYPE_CONTROL	= 0x05,
2641 };
2642 
2643 enum fw_port_dcb_feature_state {
2644 	FW_PORT_DCB_FEATURE_STATE_PENDING = 0x0,
2645 	FW_PORT_DCB_FEATURE_STATE_SUCCESS = 0x1,
2646 	FW_PORT_DCB_FEATURE_STATE_ERROR	= 0x2,
2647 	FW_PORT_DCB_FEATURE_STATE_TIMEOUT = 0x3,
2648 };
2649 
2650 struct fw_port_cmd {
2651 	__be32 op_to_portid;
2652 	__be32 action_to_len16;
2653 	union fw_port {
2654 		struct fw_port_l1cfg {
2655 			__be32 rcap;
2656 			__be32 r;
2657 		} l1cfg;
2658 		struct fw_port_l2cfg {
2659 			__u8   ctlbf;
2660 			__u8   ovlan3_to_ivlan0;
2661 			__be16 ivlantype;
2662 			__be16 txipg_force_pinfo;
2663 			__be16 mtu;
2664 			__be16 ovlan0mask;
2665 			__be16 ovlan0type;
2666 			__be16 ovlan1mask;
2667 			__be16 ovlan1type;
2668 			__be16 ovlan2mask;
2669 			__be16 ovlan2type;
2670 			__be16 ovlan3mask;
2671 			__be16 ovlan3type;
2672 		} l2cfg;
2673 		struct fw_port_info {
2674 			__be32 lstatus_to_modtype;
2675 			__be16 pcap;
2676 			__be16 acap;
2677 			__be16 mtu;
2678 			__u8   cbllen;
2679 			__u8   auxlinfo;
2680 			__u8   dcbxdis_pkd;
2681 			__u8   r8_lo;
2682 			__be16 lpacap;
2683 			__be64 r9;
2684 		} info;
2685 		struct fw_port_diags {
2686 			__u8   diagop;
2687 			__u8   r[3];
2688 			__be32 diagval;
2689 		} diags;
2690 		union fw_port_dcb {
2691 			struct fw_port_dcb_pgid {
2692 				__u8   type;
2693 				__u8   apply_pkd;
2694 				__u8   r10_lo[2];
2695 				__be32 pgid;
2696 				__be64 r11;
2697 			} pgid;
2698 			struct fw_port_dcb_pgrate {
2699 				__u8   type;
2700 				__u8   apply_pkd;
2701 				__u8   r10_lo[5];
2702 				__u8   num_tcs_supported;
2703 				__u8   pgrate[8];
2704 				__u8   tsa[8];
2705 			} pgrate;
2706 			struct fw_port_dcb_priorate {
2707 				__u8   type;
2708 				__u8   apply_pkd;
2709 				__u8   r10_lo[6];
2710 				__u8   strict_priorate[8];
2711 			} priorate;
2712 			struct fw_port_dcb_pfc {
2713 				__u8   type;
2714 				__u8   pfcen;
2715 				__u8   r10[5];
2716 				__u8   max_pfc_tcs;
2717 				__be64 r11;
2718 			} pfc;
2719 			struct fw_port_app_priority {
2720 				__u8   type;
2721 				__u8   r10[2];
2722 				__u8   idx;
2723 				__u8   user_prio_map;
2724 				__u8   sel_field;
2725 				__be16 protocolid;
2726 				__be64 r12;
2727 			} app_priority;
2728 			struct fw_port_dcb_control {
2729 				__u8   type;
2730 				__u8   all_syncd_pkd;
2731 				__be16 dcb_version_to_app_state;
2732 				__be32 r11;
2733 				__be64 r12;
2734 			} control;
2735 		} dcb;
2736 		struct fw_port_l1cfg32 {
2737 			__be32 rcap32;
2738 			__be32 r;
2739 		} l1cfg32;
2740 		struct fw_port_info32 {
2741 			__be32 lstatus32_to_cbllen32;
2742 			__be32 auxlinfo32_mtu32;
2743 			__be32 linkattr32;
2744 			__be32 pcaps32;
2745 			__be32 acaps32;
2746 			__be32 lpacaps32;
2747 		} info32;
2748 	} u;
2749 };
2750 
2751 #define FW_PORT_CMD_READ_S	22
2752 #define FW_PORT_CMD_READ_V(x)	((x) << FW_PORT_CMD_READ_S)
2753 #define FW_PORT_CMD_READ_F	FW_PORT_CMD_READ_V(1U)
2754 
2755 #define FW_PORT_CMD_PORTID_S	0
2756 #define FW_PORT_CMD_PORTID_M	0xf
2757 #define FW_PORT_CMD_PORTID_V(x)	((x) << FW_PORT_CMD_PORTID_S)
2758 #define FW_PORT_CMD_PORTID_G(x)	\
2759 	(((x) >> FW_PORT_CMD_PORTID_S) & FW_PORT_CMD_PORTID_M)
2760 
2761 #define FW_PORT_CMD_ACTION_S	16
2762 #define FW_PORT_CMD_ACTION_M	0xffff
2763 #define FW_PORT_CMD_ACTION_V(x)	((x) << FW_PORT_CMD_ACTION_S)
2764 #define FW_PORT_CMD_ACTION_G(x)	\
2765 	(((x) >> FW_PORT_CMD_ACTION_S) & FW_PORT_CMD_ACTION_M)
2766 
2767 #define FW_PORT_CMD_OVLAN3_S	7
2768 #define FW_PORT_CMD_OVLAN3_V(x)	((x) << FW_PORT_CMD_OVLAN3_S)
2769 
2770 #define FW_PORT_CMD_OVLAN2_S	6
2771 #define FW_PORT_CMD_OVLAN2_V(x)	((x) << FW_PORT_CMD_OVLAN2_S)
2772 
2773 #define FW_PORT_CMD_OVLAN1_S	5
2774 #define FW_PORT_CMD_OVLAN1_V(x)	((x) << FW_PORT_CMD_OVLAN1_S)
2775 
2776 #define FW_PORT_CMD_OVLAN0_S	4
2777 #define FW_PORT_CMD_OVLAN0_V(x)	((x) << FW_PORT_CMD_OVLAN0_S)
2778 
2779 #define FW_PORT_CMD_IVLAN0_S	3
2780 #define FW_PORT_CMD_IVLAN0_V(x)	((x) << FW_PORT_CMD_IVLAN0_S)
2781 
2782 #define FW_PORT_CMD_TXIPG_S	3
2783 #define FW_PORT_CMD_TXIPG_V(x)	((x) << FW_PORT_CMD_TXIPG_S)
2784 
2785 #define FW_PORT_CMD_LSTATUS_S           31
2786 #define FW_PORT_CMD_LSTATUS_M           0x1
2787 #define FW_PORT_CMD_LSTATUS_V(x)        ((x) << FW_PORT_CMD_LSTATUS_S)
2788 #define FW_PORT_CMD_LSTATUS_G(x)        \
2789 	(((x) >> FW_PORT_CMD_LSTATUS_S) & FW_PORT_CMD_LSTATUS_M)
2790 #define FW_PORT_CMD_LSTATUS_F   FW_PORT_CMD_LSTATUS_V(1U)
2791 
2792 #define FW_PORT_CMD_LSPEED_S	24
2793 #define FW_PORT_CMD_LSPEED_M	0x3f
2794 #define FW_PORT_CMD_LSPEED_V(x)	((x) << FW_PORT_CMD_LSPEED_S)
2795 #define FW_PORT_CMD_LSPEED_G(x)	\
2796 	(((x) >> FW_PORT_CMD_LSPEED_S) & FW_PORT_CMD_LSPEED_M)
2797 
2798 #define FW_PORT_CMD_TXPAUSE_S		23
2799 #define FW_PORT_CMD_TXPAUSE_V(x)	((x) << FW_PORT_CMD_TXPAUSE_S)
2800 #define FW_PORT_CMD_TXPAUSE_F	FW_PORT_CMD_TXPAUSE_V(1U)
2801 
2802 #define FW_PORT_CMD_RXPAUSE_S		22
2803 #define FW_PORT_CMD_RXPAUSE_V(x)	((x) << FW_PORT_CMD_RXPAUSE_S)
2804 #define FW_PORT_CMD_RXPAUSE_F	FW_PORT_CMD_RXPAUSE_V(1U)
2805 
2806 #define FW_PORT_CMD_MDIOCAP_S		21
2807 #define FW_PORT_CMD_MDIOCAP_V(x)	((x) << FW_PORT_CMD_MDIOCAP_S)
2808 #define FW_PORT_CMD_MDIOCAP_F	FW_PORT_CMD_MDIOCAP_V(1U)
2809 
2810 #define FW_PORT_CMD_MDIOADDR_S		16
2811 #define FW_PORT_CMD_MDIOADDR_M		0x1f
2812 #define FW_PORT_CMD_MDIOADDR_G(x)	\
2813 	(((x) >> FW_PORT_CMD_MDIOADDR_S) & FW_PORT_CMD_MDIOADDR_M)
2814 
2815 #define FW_PORT_CMD_LPTXPAUSE_S		15
2816 #define FW_PORT_CMD_LPTXPAUSE_V(x)	((x) << FW_PORT_CMD_LPTXPAUSE_S)
2817 #define FW_PORT_CMD_LPTXPAUSE_F	FW_PORT_CMD_LPTXPAUSE_V(1U)
2818 
2819 #define FW_PORT_CMD_LPRXPAUSE_S		14
2820 #define FW_PORT_CMD_LPRXPAUSE_V(x)	((x) << FW_PORT_CMD_LPRXPAUSE_S)
2821 #define FW_PORT_CMD_LPRXPAUSE_F	FW_PORT_CMD_LPRXPAUSE_V(1U)
2822 
2823 #define FW_PORT_CMD_PTYPE_S	8
2824 #define FW_PORT_CMD_PTYPE_M	0x1f
2825 #define FW_PORT_CMD_PTYPE_G(x)	\
2826 	(((x) >> FW_PORT_CMD_PTYPE_S) & FW_PORT_CMD_PTYPE_M)
2827 
2828 #define FW_PORT_CMD_LINKDNRC_S		5
2829 #define FW_PORT_CMD_LINKDNRC_M		0x7
2830 #define FW_PORT_CMD_LINKDNRC_G(x)	\
2831 	(((x) >> FW_PORT_CMD_LINKDNRC_S) & FW_PORT_CMD_LINKDNRC_M)
2832 
2833 #define FW_PORT_CMD_MODTYPE_S		0
2834 #define FW_PORT_CMD_MODTYPE_M		0x1f
2835 #define FW_PORT_CMD_MODTYPE_V(x)	((x) << FW_PORT_CMD_MODTYPE_S)
2836 #define FW_PORT_CMD_MODTYPE_G(x)	\
2837 	(((x) >> FW_PORT_CMD_MODTYPE_S) & FW_PORT_CMD_MODTYPE_M)
2838 
2839 #define FW_PORT_CMD_DCBXDIS_S		7
2840 #define FW_PORT_CMD_DCBXDIS_V(x)	((x) << FW_PORT_CMD_DCBXDIS_S)
2841 #define FW_PORT_CMD_DCBXDIS_F	FW_PORT_CMD_DCBXDIS_V(1U)
2842 
2843 #define FW_PORT_CMD_APPLY_S	7
2844 #define FW_PORT_CMD_APPLY_V(x)	((x) << FW_PORT_CMD_APPLY_S)
2845 #define FW_PORT_CMD_APPLY_F	FW_PORT_CMD_APPLY_V(1U)
2846 
2847 #define FW_PORT_CMD_ALL_SYNCD_S		7
2848 #define FW_PORT_CMD_ALL_SYNCD_V(x)	((x) << FW_PORT_CMD_ALL_SYNCD_S)
2849 #define FW_PORT_CMD_ALL_SYNCD_F	FW_PORT_CMD_ALL_SYNCD_V(1U)
2850 
2851 #define FW_PORT_CMD_DCB_VERSION_S	12
2852 #define FW_PORT_CMD_DCB_VERSION_M	0x7
2853 #define FW_PORT_CMD_DCB_VERSION_G(x)	\
2854 	(((x) >> FW_PORT_CMD_DCB_VERSION_S) & FW_PORT_CMD_DCB_VERSION_M)
2855 
2856 #define FW_PORT_CMD_LSTATUS32_S		31
2857 #define FW_PORT_CMD_LSTATUS32_M		0x1
2858 #define FW_PORT_CMD_LSTATUS32_V(x)	((x) << FW_PORT_CMD_LSTATUS32_S)
2859 #define FW_PORT_CMD_LSTATUS32_G(x)	\
2860 	(((x) >> FW_PORT_CMD_LSTATUS32_S) & FW_PORT_CMD_LSTATUS32_M)
2861 #define FW_PORT_CMD_LSTATUS32_F	FW_PORT_CMD_LSTATUS32_V(1U)
2862 
2863 #define FW_PORT_CMD_LINKDNRC32_S	28
2864 #define FW_PORT_CMD_LINKDNRC32_M	0x7
2865 #define FW_PORT_CMD_LINKDNRC32_V(x)	((x) << FW_PORT_CMD_LINKDNRC32_S)
2866 #define FW_PORT_CMD_LINKDNRC32_G(x)	\
2867 	(((x) >> FW_PORT_CMD_LINKDNRC32_S) & FW_PORT_CMD_LINKDNRC32_M)
2868 
2869 #define FW_PORT_CMD_DCBXDIS32_S		27
2870 #define FW_PORT_CMD_DCBXDIS32_M		0x1
2871 #define FW_PORT_CMD_DCBXDIS32_V(x)	((x) << FW_PORT_CMD_DCBXDIS32_S)
2872 #define FW_PORT_CMD_DCBXDIS32_G(x)	\
2873 	(((x) >> FW_PORT_CMD_DCBXDIS32_S) & FW_PORT_CMD_DCBXDIS32_M)
2874 #define FW_PORT_CMD_DCBXDIS32_F	FW_PORT_CMD_DCBXDIS32_V(1U)
2875 
2876 #define FW_PORT_CMD_MDIOCAP32_S		26
2877 #define FW_PORT_CMD_MDIOCAP32_M		0x1
2878 #define FW_PORT_CMD_MDIOCAP32_V(x)	((x) << FW_PORT_CMD_MDIOCAP32_S)
2879 #define FW_PORT_CMD_MDIOCAP32_G(x)	\
2880 	(((x) >> FW_PORT_CMD_MDIOCAP32_S) & FW_PORT_CMD_MDIOCAP32_M)
2881 #define FW_PORT_CMD_MDIOCAP32_F	FW_PORT_CMD_MDIOCAP32_V(1U)
2882 
2883 #define FW_PORT_CMD_MDIOADDR32_S	21
2884 #define FW_PORT_CMD_MDIOADDR32_M	0x1f
2885 #define FW_PORT_CMD_MDIOADDR32_V(x)	((x) << FW_PORT_CMD_MDIOADDR32_S)
2886 #define FW_PORT_CMD_MDIOADDR32_G(x)	\
2887 	(((x) >> FW_PORT_CMD_MDIOADDR32_S) & FW_PORT_CMD_MDIOADDR32_M)
2888 
2889 #define FW_PORT_CMD_PORTTYPE32_S	13
2890 #define FW_PORT_CMD_PORTTYPE32_M	0xff
2891 #define FW_PORT_CMD_PORTTYPE32_V(x)	((x) << FW_PORT_CMD_PORTTYPE32_S)
2892 #define FW_PORT_CMD_PORTTYPE32_G(x)	\
2893 	(((x) >> FW_PORT_CMD_PORTTYPE32_S) & FW_PORT_CMD_PORTTYPE32_M)
2894 
2895 #define FW_PORT_CMD_MODTYPE32_S		8
2896 #define FW_PORT_CMD_MODTYPE32_M		0x1f
2897 #define FW_PORT_CMD_MODTYPE32_V(x)	((x) << FW_PORT_CMD_MODTYPE32_S)
2898 #define FW_PORT_CMD_MODTYPE32_G(x)	\
2899 	(((x) >> FW_PORT_CMD_MODTYPE32_S) & FW_PORT_CMD_MODTYPE32_M)
2900 
2901 #define FW_PORT_CMD_CBLLEN32_S		0
2902 #define FW_PORT_CMD_CBLLEN32_M		0xff
2903 #define FW_PORT_CMD_CBLLEN32_V(x)	((x) << FW_PORT_CMD_CBLLEN32_S)
2904 #define FW_PORT_CMD_CBLLEN32_G(x)	\
2905 	(((x) >> FW_PORT_CMD_CBLLEN32_S) & FW_PORT_CMD_CBLLEN32_M)
2906 
2907 #define FW_PORT_CMD_AUXLINFO32_S	24
2908 #define FW_PORT_CMD_AUXLINFO32_M	0xff
2909 #define FW_PORT_CMD_AUXLINFO32_V(x)	((x) << FW_PORT_CMD_AUXLINFO32_S)
2910 #define FW_PORT_CMD_AUXLINFO32_G(x)	\
2911 	(((x) >> FW_PORT_CMD_AUXLINFO32_S) & FW_PORT_CMD_AUXLINFO32_M)
2912 
2913 #define FW_PORT_AUXLINFO32_KX4_S	2
2914 #define FW_PORT_AUXLINFO32_KX4_M	0x1
2915 #define FW_PORT_AUXLINFO32_KX4_V(x) \
2916 	((x) << FW_PORT_AUXLINFO32_KX4_S)
2917 #define FW_PORT_AUXLINFO32_KX4_G(x) \
2918 	(((x) >> FW_PORT_AUXLINFO32_KX4_S) & FW_PORT_AUXLINFO32_KX4_M)
2919 #define FW_PORT_AUXLINFO32_KX4_F	FW_PORT_AUXLINFO32_KX4_V(1U)
2920 
2921 #define FW_PORT_AUXLINFO32_KR_S	1
2922 #define FW_PORT_AUXLINFO32_KR_M	0x1
2923 #define FW_PORT_AUXLINFO32_KR_V(x) \
2924 	((x) << FW_PORT_AUXLINFO32_KR_S)
2925 #define FW_PORT_AUXLINFO32_KR_G(x) \
2926 	(((x) >> FW_PORT_AUXLINFO32_KR_S) & FW_PORT_AUXLINFO32_KR_M)
2927 #define FW_PORT_AUXLINFO32_KR_F	FW_PORT_AUXLINFO32_KR_V(1U)
2928 
2929 #define FW_PORT_CMD_MTU32_S	0
2930 #define FW_PORT_CMD_MTU32_M	0xffff
2931 #define FW_PORT_CMD_MTU32_V(x)	((x) << FW_PORT_CMD_MTU32_S)
2932 #define FW_PORT_CMD_MTU32_G(x)	\
2933 	(((x) >> FW_PORT_CMD_MTU32_S) & FW_PORT_CMD_MTU32_M)
2934 
2935 enum fw_port_type {
2936 	FW_PORT_TYPE_FIBER_XFI,
2937 	FW_PORT_TYPE_FIBER_XAUI,
2938 	FW_PORT_TYPE_BT_SGMII,
2939 	FW_PORT_TYPE_BT_XFI,
2940 	FW_PORT_TYPE_BT_XAUI,
2941 	FW_PORT_TYPE_KX4,
2942 	FW_PORT_TYPE_CX4,
2943 	FW_PORT_TYPE_KX,
2944 	FW_PORT_TYPE_KR,
2945 	FW_PORT_TYPE_SFP,
2946 	FW_PORT_TYPE_BP_AP,
2947 	FW_PORT_TYPE_BP4_AP,
2948 	FW_PORT_TYPE_QSFP_10G,
2949 	FW_PORT_TYPE_QSA,
2950 	FW_PORT_TYPE_QSFP,
2951 	FW_PORT_TYPE_BP40_BA,
2952 	FW_PORT_TYPE_KR4_100G,
2953 	FW_PORT_TYPE_CR4_QSFP,
2954 	FW_PORT_TYPE_CR_QSFP,
2955 	FW_PORT_TYPE_CR2_QSFP,
2956 	FW_PORT_TYPE_SFP28,
2957 	FW_PORT_TYPE_KR_SFP28,
2958 	FW_PORT_TYPE_KR_XLAUI,
2959 
2960 	FW_PORT_TYPE_NONE = FW_PORT_CMD_PTYPE_M
2961 };
2962 
2963 enum fw_port_module_type {
2964 	FW_PORT_MOD_TYPE_NA,
2965 	FW_PORT_MOD_TYPE_LR,
2966 	FW_PORT_MOD_TYPE_SR,
2967 	FW_PORT_MOD_TYPE_ER,
2968 	FW_PORT_MOD_TYPE_TWINAX_PASSIVE,
2969 	FW_PORT_MOD_TYPE_TWINAX_ACTIVE,
2970 	FW_PORT_MOD_TYPE_LRM,
2971 	FW_PORT_MOD_TYPE_ERROR		= FW_PORT_CMD_MODTYPE_M - 3,
2972 	FW_PORT_MOD_TYPE_UNKNOWN	= FW_PORT_CMD_MODTYPE_M - 2,
2973 	FW_PORT_MOD_TYPE_NOTSUPPORTED	= FW_PORT_CMD_MODTYPE_M - 1,
2974 
2975 	FW_PORT_MOD_TYPE_NONE = FW_PORT_CMD_MODTYPE_M
2976 };
2977 
2978 enum fw_port_mod_sub_type {
2979 	FW_PORT_MOD_SUB_TYPE_NA,
2980 	FW_PORT_MOD_SUB_TYPE_MV88E114X = 0x1,
2981 	FW_PORT_MOD_SUB_TYPE_TN8022 = 0x2,
2982 	FW_PORT_MOD_SUB_TYPE_AQ1202 = 0x3,
2983 	FW_PORT_MOD_SUB_TYPE_88x3120 = 0x4,
2984 	FW_PORT_MOD_SUB_TYPE_BCM84834 = 0x5,
2985 	FW_PORT_MOD_SUB_TYPE_BT_VSC8634 = 0x8,
2986 
2987 	/* The following will never been in the VPD.  They are TWINAX cable
2988 	 * lengths decoded from SFP+ module i2c PROMs.  These should
2989 	 * almost certainly go somewhere else ...
2990 	 */
2991 	FW_PORT_MOD_SUB_TYPE_TWINAX_1 = 0x9,
2992 	FW_PORT_MOD_SUB_TYPE_TWINAX_3 = 0xA,
2993 	FW_PORT_MOD_SUB_TYPE_TWINAX_5 = 0xB,
2994 	FW_PORT_MOD_SUB_TYPE_TWINAX_7 = 0xC,
2995 };
2996 
2997 enum fw_port_stats_tx_index {
2998 	FW_STAT_TX_PORT_BYTES_IX = 0,
2999 	FW_STAT_TX_PORT_FRAMES_IX,
3000 	FW_STAT_TX_PORT_BCAST_IX,
3001 	FW_STAT_TX_PORT_MCAST_IX,
3002 	FW_STAT_TX_PORT_UCAST_IX,
3003 	FW_STAT_TX_PORT_ERROR_IX,
3004 	FW_STAT_TX_PORT_64B_IX,
3005 	FW_STAT_TX_PORT_65B_127B_IX,
3006 	FW_STAT_TX_PORT_128B_255B_IX,
3007 	FW_STAT_TX_PORT_256B_511B_IX,
3008 	FW_STAT_TX_PORT_512B_1023B_IX,
3009 	FW_STAT_TX_PORT_1024B_1518B_IX,
3010 	FW_STAT_TX_PORT_1519B_MAX_IX,
3011 	FW_STAT_TX_PORT_DROP_IX,
3012 	FW_STAT_TX_PORT_PAUSE_IX,
3013 	FW_STAT_TX_PORT_PPP0_IX,
3014 	FW_STAT_TX_PORT_PPP1_IX,
3015 	FW_STAT_TX_PORT_PPP2_IX,
3016 	FW_STAT_TX_PORT_PPP3_IX,
3017 	FW_STAT_TX_PORT_PPP4_IX,
3018 	FW_STAT_TX_PORT_PPP5_IX,
3019 	FW_STAT_TX_PORT_PPP6_IX,
3020 	FW_STAT_TX_PORT_PPP7_IX,
3021 	FW_NUM_PORT_TX_STATS
3022 };
3023 
3024 enum fw_port_stat_rx_index {
3025 	FW_STAT_RX_PORT_BYTES_IX = 0,
3026 	FW_STAT_RX_PORT_FRAMES_IX,
3027 	FW_STAT_RX_PORT_BCAST_IX,
3028 	FW_STAT_RX_PORT_MCAST_IX,
3029 	FW_STAT_RX_PORT_UCAST_IX,
3030 	FW_STAT_RX_PORT_MTU_ERROR_IX,
3031 	FW_STAT_RX_PORT_MTU_CRC_ERROR_IX,
3032 	FW_STAT_RX_PORT_CRC_ERROR_IX,
3033 	FW_STAT_RX_PORT_LEN_ERROR_IX,
3034 	FW_STAT_RX_PORT_SYM_ERROR_IX,
3035 	FW_STAT_RX_PORT_64B_IX,
3036 	FW_STAT_RX_PORT_65B_127B_IX,
3037 	FW_STAT_RX_PORT_128B_255B_IX,
3038 	FW_STAT_RX_PORT_256B_511B_IX,
3039 	FW_STAT_RX_PORT_512B_1023B_IX,
3040 	FW_STAT_RX_PORT_1024B_1518B_IX,
3041 	FW_STAT_RX_PORT_1519B_MAX_IX,
3042 	FW_STAT_RX_PORT_PAUSE_IX,
3043 	FW_STAT_RX_PORT_PPP0_IX,
3044 	FW_STAT_RX_PORT_PPP1_IX,
3045 	FW_STAT_RX_PORT_PPP2_IX,
3046 	FW_STAT_RX_PORT_PPP3_IX,
3047 	FW_STAT_RX_PORT_PPP4_IX,
3048 	FW_STAT_RX_PORT_PPP5_IX,
3049 	FW_STAT_RX_PORT_PPP6_IX,
3050 	FW_STAT_RX_PORT_PPP7_IX,
3051 	FW_STAT_RX_PORT_LESS_64B_IX,
3052 	FW_STAT_RX_PORT_MAC_ERROR_IX,
3053 	FW_NUM_PORT_RX_STATS
3054 };
3055 
3056 /* port stats */
3057 #define FW_NUM_PORT_STATS (FW_NUM_PORT_TX_STATS + FW_NUM_PORT_RX_STATS)
3058 
3059 struct fw_port_stats_cmd {
3060 	__be32 op_to_portid;
3061 	__be32 retval_len16;
3062 	union fw_port_stats {
3063 		struct fw_port_stats_ctl {
3064 			u8 nstats_bg_bm;
3065 			u8 tx_ix;
3066 			__be16 r6;
3067 			__be32 r7;
3068 			__be64 stat0;
3069 			__be64 stat1;
3070 			__be64 stat2;
3071 			__be64 stat3;
3072 			__be64 stat4;
3073 			__be64 stat5;
3074 		} ctl;
3075 		struct fw_port_stats_all {
3076 			__be64 tx_bytes;
3077 			__be64 tx_frames;
3078 			__be64 tx_bcast;
3079 			__be64 tx_mcast;
3080 			__be64 tx_ucast;
3081 			__be64 tx_error;
3082 			__be64 tx_64b;
3083 			__be64 tx_65b_127b;
3084 			__be64 tx_128b_255b;
3085 			__be64 tx_256b_511b;
3086 			__be64 tx_512b_1023b;
3087 			__be64 tx_1024b_1518b;
3088 			__be64 tx_1519b_max;
3089 			__be64 tx_drop;
3090 			__be64 tx_pause;
3091 			__be64 tx_ppp0;
3092 			__be64 tx_ppp1;
3093 			__be64 tx_ppp2;
3094 			__be64 tx_ppp3;
3095 			__be64 tx_ppp4;
3096 			__be64 tx_ppp5;
3097 			__be64 tx_ppp6;
3098 			__be64 tx_ppp7;
3099 			__be64 rx_bytes;
3100 			__be64 rx_frames;
3101 			__be64 rx_bcast;
3102 			__be64 rx_mcast;
3103 			__be64 rx_ucast;
3104 			__be64 rx_mtu_error;
3105 			__be64 rx_mtu_crc_error;
3106 			__be64 rx_crc_error;
3107 			__be64 rx_len_error;
3108 			__be64 rx_sym_error;
3109 			__be64 rx_64b;
3110 			__be64 rx_65b_127b;
3111 			__be64 rx_128b_255b;
3112 			__be64 rx_256b_511b;
3113 			__be64 rx_512b_1023b;
3114 			__be64 rx_1024b_1518b;
3115 			__be64 rx_1519b_max;
3116 			__be64 rx_pause;
3117 			__be64 rx_ppp0;
3118 			__be64 rx_ppp1;
3119 			__be64 rx_ppp2;
3120 			__be64 rx_ppp3;
3121 			__be64 rx_ppp4;
3122 			__be64 rx_ppp5;
3123 			__be64 rx_ppp6;
3124 			__be64 rx_ppp7;
3125 			__be64 rx_less_64b;
3126 			__be64 rx_bg_drop;
3127 			__be64 rx_bg_trunc;
3128 		} all;
3129 	} u;
3130 };
3131 
3132 /* port loopback stats */
3133 #define FW_NUM_LB_STATS 16
3134 enum fw_port_lb_stats_index {
3135 	FW_STAT_LB_PORT_BYTES_IX,
3136 	FW_STAT_LB_PORT_FRAMES_IX,
3137 	FW_STAT_LB_PORT_BCAST_IX,
3138 	FW_STAT_LB_PORT_MCAST_IX,
3139 	FW_STAT_LB_PORT_UCAST_IX,
3140 	FW_STAT_LB_PORT_ERROR_IX,
3141 	FW_STAT_LB_PORT_64B_IX,
3142 	FW_STAT_LB_PORT_65B_127B_IX,
3143 	FW_STAT_LB_PORT_128B_255B_IX,
3144 	FW_STAT_LB_PORT_256B_511B_IX,
3145 	FW_STAT_LB_PORT_512B_1023B_IX,
3146 	FW_STAT_LB_PORT_1024B_1518B_IX,
3147 	FW_STAT_LB_PORT_1519B_MAX_IX,
3148 	FW_STAT_LB_PORT_DROP_FRAMES_IX
3149 };
3150 
3151 struct fw_port_lb_stats_cmd {
3152 	__be32 op_to_lbport;
3153 	__be32 retval_len16;
3154 	union fw_port_lb_stats {
3155 		struct fw_port_lb_stats_ctl {
3156 			u8 nstats_bg_bm;
3157 			u8 ix_pkd;
3158 			__be16 r6;
3159 			__be32 r7;
3160 			__be64 stat0;
3161 			__be64 stat1;
3162 			__be64 stat2;
3163 			__be64 stat3;
3164 			__be64 stat4;
3165 			__be64 stat5;
3166 		} ctl;
3167 		struct fw_port_lb_stats_all {
3168 			__be64 tx_bytes;
3169 			__be64 tx_frames;
3170 			__be64 tx_bcast;
3171 			__be64 tx_mcast;
3172 			__be64 tx_ucast;
3173 			__be64 tx_error;
3174 			__be64 tx_64b;
3175 			__be64 tx_65b_127b;
3176 			__be64 tx_128b_255b;
3177 			__be64 tx_256b_511b;
3178 			__be64 tx_512b_1023b;
3179 			__be64 tx_1024b_1518b;
3180 			__be64 tx_1519b_max;
3181 			__be64 rx_lb_drop;
3182 			__be64 rx_lb_trunc;
3183 		} all;
3184 	} u;
3185 };
3186 
3187 enum fw_ptp_subop {
3188 	/* none */
3189 	FW_PTP_SC_INIT_TIMER            = 0x00,
3190 	FW_PTP_SC_TX_TYPE               = 0x01,
3191 	/* init */
3192 	FW_PTP_SC_RXTIME_STAMP          = 0x08,
3193 	FW_PTP_SC_RDRX_TYPE             = 0x09,
3194 	/* ts */
3195 	FW_PTP_SC_ADJ_FREQ              = 0x10,
3196 	FW_PTP_SC_ADJ_TIME              = 0x11,
3197 	FW_PTP_SC_ADJ_FTIME             = 0x12,
3198 	FW_PTP_SC_WALL_CLOCK            = 0x13,
3199 	FW_PTP_SC_GET_TIME              = 0x14,
3200 	FW_PTP_SC_SET_TIME              = 0x15,
3201 };
3202 
3203 struct fw_ptp_cmd {
3204 	__be32 op_to_portid;
3205 	__be32 retval_len16;
3206 	union fw_ptp {
3207 		struct fw_ptp_sc {
3208 			__u8   sc;
3209 			__u8   r3[7];
3210 		} scmd;
3211 		struct fw_ptp_init {
3212 			__u8   sc;
3213 			__u8   txchan;
3214 			__be16 absid;
3215 			__be16 mode;
3216 			__be16 r3;
3217 		} init;
3218 		struct fw_ptp_ts {
3219 			__u8   sc;
3220 			__u8   sign;
3221 			__be16 r3;
3222 			__be32 ppb;
3223 			__be64 tm;
3224 		} ts;
3225 	} u;
3226 	__be64 r3;
3227 };
3228 
3229 #define FW_PTP_CMD_PORTID_S             0
3230 #define FW_PTP_CMD_PORTID_M             0xf
3231 #define FW_PTP_CMD_PORTID_V(x)          ((x) << FW_PTP_CMD_PORTID_S)
3232 #define FW_PTP_CMD_PORTID_G(x)          \
3233 	(((x) >> FW_PTP_CMD_PORTID_S) & FW_PTP_CMD_PORTID_M)
3234 
3235 struct fw_rss_ind_tbl_cmd {
3236 	__be32 op_to_viid;
3237 	__be32 retval_len16;
3238 	__be16 niqid;
3239 	__be16 startidx;
3240 	__be32 r3;
3241 	__be32 iq0_to_iq2;
3242 	__be32 iq3_to_iq5;
3243 	__be32 iq6_to_iq8;
3244 	__be32 iq9_to_iq11;
3245 	__be32 iq12_to_iq14;
3246 	__be32 iq15_to_iq17;
3247 	__be32 iq18_to_iq20;
3248 	__be32 iq21_to_iq23;
3249 	__be32 iq24_to_iq26;
3250 	__be32 iq27_to_iq29;
3251 	__be32 iq30_iq31;
3252 	__be32 r15_lo;
3253 };
3254 
3255 #define FW_RSS_IND_TBL_CMD_VIID_S	0
3256 #define FW_RSS_IND_TBL_CMD_VIID_V(x)	((x) << FW_RSS_IND_TBL_CMD_VIID_S)
3257 
3258 #define FW_RSS_IND_TBL_CMD_IQ0_S	20
3259 #define FW_RSS_IND_TBL_CMD_IQ0_V(x)	((x) << FW_RSS_IND_TBL_CMD_IQ0_S)
3260 
3261 #define FW_RSS_IND_TBL_CMD_IQ1_S	10
3262 #define FW_RSS_IND_TBL_CMD_IQ1_V(x)	((x) << FW_RSS_IND_TBL_CMD_IQ1_S)
3263 
3264 #define FW_RSS_IND_TBL_CMD_IQ2_S	0
3265 #define FW_RSS_IND_TBL_CMD_IQ2_V(x)	((x) << FW_RSS_IND_TBL_CMD_IQ2_S)
3266 
3267 struct fw_rss_glb_config_cmd {
3268 	__be32 op_to_write;
3269 	__be32 retval_len16;
3270 	union fw_rss_glb_config {
3271 		struct fw_rss_glb_config_manual {
3272 			__be32 mode_pkd;
3273 			__be32 r3;
3274 			__be64 r4;
3275 			__be64 r5;
3276 		} manual;
3277 		struct fw_rss_glb_config_basicvirtual {
3278 			__be32 mode_pkd;
3279 			__be32 synmapen_to_hashtoeplitz;
3280 			__be64 r8;
3281 			__be64 r9;
3282 		} basicvirtual;
3283 	} u;
3284 };
3285 
3286 #define FW_RSS_GLB_CONFIG_CMD_MODE_S	28
3287 #define FW_RSS_GLB_CONFIG_CMD_MODE_M	0xf
3288 #define FW_RSS_GLB_CONFIG_CMD_MODE_V(x)	((x) << FW_RSS_GLB_CONFIG_CMD_MODE_S)
3289 #define FW_RSS_GLB_CONFIG_CMD_MODE_G(x)	\
3290 	(((x) >> FW_RSS_GLB_CONFIG_CMD_MODE_S) & FW_RSS_GLB_CONFIG_CMD_MODE_M)
3291 
3292 #define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL	0
3293 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL	1
3294 
3295 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_S	8
3296 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_V(x)	\
3297 	((x) << FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_S)
3298 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_F	\
3299 	FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_V(1U)
3300 
3301 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_S		7
3302 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_V(x)	\
3303 	((x) << FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_S)
3304 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_F	\
3305 	FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_V(1U)
3306 
3307 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_S		6
3308 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_V(x)	\
3309 	((x) << FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_S)
3310 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_F	\
3311 	FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_V(1U)
3312 
3313 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_S		5
3314 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_V(x)	\
3315 	((x) << FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_S)
3316 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_F	\
3317 	FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_V(1U)
3318 
3319 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_S		4
3320 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_V(x)	\
3321 	((x) << FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_S)
3322 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_F	\
3323 	FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_V(1U)
3324 
3325 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_S	3
3326 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_V(x)	\
3327 	((x) << FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_S)
3328 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_F	\
3329 	FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_V(1U)
3330 
3331 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_S	2
3332 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_V(x)	\
3333 	((x) << FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_S)
3334 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F	\
3335 	FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_V(1U)
3336 
3337 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_S	1
3338 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_V(x)	\
3339 	((x) << FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_S)
3340 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F	\
3341 	FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_V(1U)
3342 
3343 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_S	0
3344 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_V(x)	\
3345 	((x) << FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_S)
3346 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_F	\
3347 	FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_V(1U)
3348 
3349 struct fw_rss_vi_config_cmd {
3350 	__be32 op_to_viid;
3351 #define FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << 0)
3352 	__be32 retval_len16;
3353 	union fw_rss_vi_config {
3354 		struct fw_rss_vi_config_manual {
3355 			__be64 r3;
3356 			__be64 r4;
3357 			__be64 r5;
3358 		} manual;
3359 		struct fw_rss_vi_config_basicvirtual {
3360 			__be32 r6;
3361 			__be32 defaultq_to_udpen;
3362 			__be64 r9;
3363 			__be64 r10;
3364 		} basicvirtual;
3365 	} u;
3366 };
3367 
3368 #define FW_RSS_VI_CONFIG_CMD_VIID_S	0
3369 #define FW_RSS_VI_CONFIG_CMD_VIID_V(x)	((x) << FW_RSS_VI_CONFIG_CMD_VIID_S)
3370 
3371 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S		16
3372 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_M		0x3ff
3373 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_V(x)	\
3374 	((x) << FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S)
3375 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_G(x)	\
3376 	(((x) >> FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S) & \
3377 	 FW_RSS_VI_CONFIG_CMD_DEFAULTQ_M)
3378 
3379 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_S	4
3380 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_V(x)	\
3381 	((x) << FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_S)
3382 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F	\
3383 	FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_V(1U)
3384 
3385 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_S	3
3386 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_V(x)	\
3387 	((x) << FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_S)
3388 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F	\
3389 	FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_V(1U)
3390 
3391 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_S	2
3392 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_V(x)	\
3393 	((x) << FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_S)
3394 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F	\
3395 	FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_V(1U)
3396 
3397 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_S	1
3398 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_V(x)	\
3399 	((x) << FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_S)
3400 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F	\
3401 	FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_V(1U)
3402 
3403 #define FW_RSS_VI_CONFIG_CMD_UDPEN_S	0
3404 #define FW_RSS_VI_CONFIG_CMD_UDPEN_V(x)	((x) << FW_RSS_VI_CONFIG_CMD_UDPEN_S)
3405 #define FW_RSS_VI_CONFIG_CMD_UDPEN_F	FW_RSS_VI_CONFIG_CMD_UDPEN_V(1U)
3406 
3407 enum fw_sched_sc {
3408 	FW_SCHED_SC_PARAMS		= 1,
3409 };
3410 
3411 struct fw_sched_cmd {
3412 	__be32 op_to_write;
3413 	__be32 retval_len16;
3414 	union fw_sched {
3415 		struct fw_sched_config {
3416 			__u8   sc;
3417 			__u8   type;
3418 			__u8   minmaxen;
3419 			__u8   r3[5];
3420 			__u8   nclasses[4];
3421 			__be32 r4;
3422 		} config;
3423 		struct fw_sched_params {
3424 			__u8   sc;
3425 			__u8   type;
3426 			__u8   level;
3427 			__u8   mode;
3428 			__u8   unit;
3429 			__u8   rate;
3430 			__u8   ch;
3431 			__u8   cl;
3432 			__be32 min;
3433 			__be32 max;
3434 			__be16 weight;
3435 			__be16 pktsize;
3436 			__be16 burstsize;
3437 			__be16 r4;
3438 		} params;
3439 	} u;
3440 };
3441 
3442 struct fw_clip_cmd {
3443 	__be32 op_to_write;
3444 	__be32 alloc_to_len16;
3445 	__be64 ip_hi;
3446 	__be64 ip_lo;
3447 	__be32 r4[2];
3448 };
3449 
3450 #define FW_CLIP_CMD_ALLOC_S     31
3451 #define FW_CLIP_CMD_ALLOC_V(x)  ((x) << FW_CLIP_CMD_ALLOC_S)
3452 #define FW_CLIP_CMD_ALLOC_F     FW_CLIP_CMD_ALLOC_V(1U)
3453 
3454 #define FW_CLIP_CMD_FREE_S      30
3455 #define FW_CLIP_CMD_FREE_V(x)   ((x) << FW_CLIP_CMD_FREE_S)
3456 #define FW_CLIP_CMD_FREE_F      FW_CLIP_CMD_FREE_V(1U)
3457 
3458 enum fw_error_type {
3459 	FW_ERROR_TYPE_EXCEPTION		= 0x0,
3460 	FW_ERROR_TYPE_HWMODULE		= 0x1,
3461 	FW_ERROR_TYPE_WR		= 0x2,
3462 	FW_ERROR_TYPE_ACL		= 0x3,
3463 };
3464 
3465 struct fw_error_cmd {
3466 	__be32 op_to_type;
3467 	__be32 len16_pkd;
3468 	union fw_error {
3469 		struct fw_error_exception {
3470 			__be32 info[6];
3471 		} exception;
3472 		struct fw_error_hwmodule {
3473 			__be32 regaddr;
3474 			__be32 regval;
3475 		} hwmodule;
3476 		struct fw_error_wr {
3477 			__be16 cidx;
3478 			__be16 pfn_vfn;
3479 			__be32 eqid;
3480 			u8 wrhdr[16];
3481 		} wr;
3482 		struct fw_error_acl {
3483 			__be16 cidx;
3484 			__be16 pfn_vfn;
3485 			__be32 eqid;
3486 			__be16 mv_pkd;
3487 			u8 val[6];
3488 			__be64 r4;
3489 		} acl;
3490 	} u;
3491 };
3492 
3493 struct fw_debug_cmd {
3494 	__be32 op_type;
3495 	__be32 len16_pkd;
3496 	union fw_debug {
3497 		struct fw_debug_assert {
3498 			__be32 fcid;
3499 			__be32 line;
3500 			__be32 x;
3501 			__be32 y;
3502 			u8 filename_0_7[8];
3503 			u8 filename_8_15[8];
3504 			__be64 r3;
3505 		} assert;
3506 		struct fw_debug_prt {
3507 			__be16 dprtstridx;
3508 			__be16 r3[3];
3509 			__be32 dprtstrparam0;
3510 			__be32 dprtstrparam1;
3511 			__be32 dprtstrparam2;
3512 			__be32 dprtstrparam3;
3513 		} prt;
3514 	} u;
3515 };
3516 
3517 #define FW_DEBUG_CMD_TYPE_S	0
3518 #define FW_DEBUG_CMD_TYPE_M	0xff
3519 #define FW_DEBUG_CMD_TYPE_G(x)	\
3520 	(((x) >> FW_DEBUG_CMD_TYPE_S) & FW_DEBUG_CMD_TYPE_M)
3521 
3522 struct fw_hma_cmd {
3523 	__be32 op_pkd;
3524 	__be32 retval_len16;
3525 	__be32 mode_to_pcie_params;
3526 	__be32 naddr_size;
3527 	__be32 addr_size_pkd;
3528 	__be32 r6;
3529 	__be64 phy_address[5];
3530 };
3531 
3532 #define FW_HMA_CMD_MODE_S	31
3533 #define FW_HMA_CMD_MODE_M	0x1
3534 #define FW_HMA_CMD_MODE_V(x)	((x) << FW_HMA_CMD_MODE_S)
3535 #define FW_HMA_CMD_MODE_G(x)	\
3536 	(((x) >> FW_HMA_CMD_MODE_S) & FW_HMA_CMD_MODE_M)
3537 #define FW_HMA_CMD_MODE_F	FW_HMA_CMD_MODE_V(1U)
3538 
3539 #define FW_HMA_CMD_SOC_S	30
3540 #define FW_HMA_CMD_SOC_M	0x1
3541 #define FW_HMA_CMD_SOC_V(x)	((x) << FW_HMA_CMD_SOC_S)
3542 #define FW_HMA_CMD_SOC_G(x)	(((x) >> FW_HMA_CMD_SOC_S) & FW_HMA_CMD_SOC_M)
3543 #define FW_HMA_CMD_SOC_F	FW_HMA_CMD_SOC_V(1U)
3544 
3545 #define FW_HMA_CMD_EOC_S	29
3546 #define FW_HMA_CMD_EOC_M	0x1
3547 #define FW_HMA_CMD_EOC_V(x)	((x) << FW_HMA_CMD_EOC_S)
3548 #define FW_HMA_CMD_EOC_G(x)	(((x) >> FW_HMA_CMD_EOC_S) & FW_HMA_CMD_EOC_M)
3549 #define FW_HMA_CMD_EOC_F	FW_HMA_CMD_EOC_V(1U)
3550 
3551 #define FW_HMA_CMD_PCIE_PARAMS_S	0
3552 #define FW_HMA_CMD_PCIE_PARAMS_M	0x7ffffff
3553 #define FW_HMA_CMD_PCIE_PARAMS_V(x)	((x) << FW_HMA_CMD_PCIE_PARAMS_S)
3554 #define FW_HMA_CMD_PCIE_PARAMS_G(x)	\
3555 	(((x) >> FW_HMA_CMD_PCIE_PARAMS_S) & FW_HMA_CMD_PCIE_PARAMS_M)
3556 
3557 #define FW_HMA_CMD_NADDR_S	12
3558 #define FW_HMA_CMD_NADDR_M	0x3f
3559 #define FW_HMA_CMD_NADDR_V(x)	((x) << FW_HMA_CMD_NADDR_S)
3560 #define FW_HMA_CMD_NADDR_G(x)	\
3561 	(((x) >> FW_HMA_CMD_NADDR_S) & FW_HMA_CMD_NADDR_M)
3562 
3563 #define FW_HMA_CMD_SIZE_S	0
3564 #define FW_HMA_CMD_SIZE_M	0xfff
3565 #define FW_HMA_CMD_SIZE_V(x)	((x) << FW_HMA_CMD_SIZE_S)
3566 #define FW_HMA_CMD_SIZE_G(x)	\
3567 	(((x) >> FW_HMA_CMD_SIZE_S) & FW_HMA_CMD_SIZE_M)
3568 
3569 #define FW_HMA_CMD_ADDR_SIZE_S		11
3570 #define FW_HMA_CMD_ADDR_SIZE_M		0x1fffff
3571 #define FW_HMA_CMD_ADDR_SIZE_V(x)	((x) << FW_HMA_CMD_ADDR_SIZE_S)
3572 #define FW_HMA_CMD_ADDR_SIZE_G(x)	\
3573 	(((x) >> FW_HMA_CMD_ADDR_SIZE_S) & FW_HMA_CMD_ADDR_SIZE_M)
3574 
3575 enum pcie_fw_eval {
3576 	PCIE_FW_EVAL_CRASH = 0,
3577 };
3578 
3579 #define PCIE_FW_ERR_S		31
3580 #define PCIE_FW_ERR_V(x)	((x) << PCIE_FW_ERR_S)
3581 #define PCIE_FW_ERR_F		PCIE_FW_ERR_V(1U)
3582 
3583 #define PCIE_FW_INIT_S		30
3584 #define PCIE_FW_INIT_V(x)	((x) << PCIE_FW_INIT_S)
3585 #define PCIE_FW_INIT_F		PCIE_FW_INIT_V(1U)
3586 
3587 #define PCIE_FW_HALT_S          29
3588 #define PCIE_FW_HALT_V(x)       ((x) << PCIE_FW_HALT_S)
3589 #define PCIE_FW_HALT_F          PCIE_FW_HALT_V(1U)
3590 
3591 #define PCIE_FW_EVAL_S		24
3592 #define PCIE_FW_EVAL_M		0x7
3593 #define PCIE_FW_EVAL_G(x)	(((x) >> PCIE_FW_EVAL_S) & PCIE_FW_EVAL_M)
3594 
3595 #define PCIE_FW_MASTER_VLD_S	15
3596 #define PCIE_FW_MASTER_VLD_V(x)	((x) << PCIE_FW_MASTER_VLD_S)
3597 #define PCIE_FW_MASTER_VLD_F	PCIE_FW_MASTER_VLD_V(1U)
3598 
3599 #define PCIE_FW_MASTER_S	12
3600 #define PCIE_FW_MASTER_M	0x7
3601 #define PCIE_FW_MASTER_V(x)	((x) << PCIE_FW_MASTER_S)
3602 #define PCIE_FW_MASTER_G(x)	(((x) >> PCIE_FW_MASTER_S) & PCIE_FW_MASTER_M)
3603 
3604 struct fw_hdr {
3605 	u8 ver;
3606 	u8 chip;			/* terminator chip type */
3607 	__be16	len512;			/* bin length in units of 512-bytes */
3608 	__be32	fw_ver;			/* firmware version */
3609 	__be32	tp_microcode_ver;
3610 	u8 intfver_nic;
3611 	u8 intfver_vnic;
3612 	u8 intfver_ofld;
3613 	u8 intfver_ri;
3614 	u8 intfver_iscsipdu;
3615 	u8 intfver_iscsi;
3616 	u8 intfver_fcoepdu;
3617 	u8 intfver_fcoe;
3618 	__u32   reserved2;
3619 	__u32   reserved3;
3620 	__u32   reserved4;
3621 	__be32  flags;
3622 	__be32  reserved6[23];
3623 };
3624 
3625 enum fw_hdr_chip {
3626 	FW_HDR_CHIP_T4,
3627 	FW_HDR_CHIP_T5,
3628 	FW_HDR_CHIP_T6
3629 };
3630 
3631 #define FW_HDR_FW_VER_MAJOR_S	24
3632 #define FW_HDR_FW_VER_MAJOR_M	0xff
3633 #define FW_HDR_FW_VER_MAJOR_V(x) \
3634 	((x) << FW_HDR_FW_VER_MAJOR_S)
3635 #define FW_HDR_FW_VER_MAJOR_G(x) \
3636 	(((x) >> FW_HDR_FW_VER_MAJOR_S) & FW_HDR_FW_VER_MAJOR_M)
3637 
3638 #define FW_HDR_FW_VER_MINOR_S	16
3639 #define FW_HDR_FW_VER_MINOR_M	0xff
3640 #define FW_HDR_FW_VER_MINOR_V(x) \
3641 	((x) << FW_HDR_FW_VER_MINOR_S)
3642 #define FW_HDR_FW_VER_MINOR_G(x) \
3643 	(((x) >> FW_HDR_FW_VER_MINOR_S) & FW_HDR_FW_VER_MINOR_M)
3644 
3645 #define FW_HDR_FW_VER_MICRO_S	8
3646 #define FW_HDR_FW_VER_MICRO_M	0xff
3647 #define FW_HDR_FW_VER_MICRO_V(x) \
3648 	((x) << FW_HDR_FW_VER_MICRO_S)
3649 #define FW_HDR_FW_VER_MICRO_G(x) \
3650 	(((x) >> FW_HDR_FW_VER_MICRO_S) & FW_HDR_FW_VER_MICRO_M)
3651 
3652 #define FW_HDR_FW_VER_BUILD_S	0
3653 #define FW_HDR_FW_VER_BUILD_M	0xff
3654 #define FW_HDR_FW_VER_BUILD_V(x) \
3655 	((x) << FW_HDR_FW_VER_BUILD_S)
3656 #define FW_HDR_FW_VER_BUILD_G(x) \
3657 	(((x) >> FW_HDR_FW_VER_BUILD_S) & FW_HDR_FW_VER_BUILD_M)
3658 
3659 enum fw_hdr_intfver {
3660 	FW_HDR_INTFVER_NIC      = 0x00,
3661 	FW_HDR_INTFVER_VNIC     = 0x00,
3662 	FW_HDR_INTFVER_OFLD     = 0x00,
3663 	FW_HDR_INTFVER_RI       = 0x00,
3664 	FW_HDR_INTFVER_ISCSIPDU = 0x00,
3665 	FW_HDR_INTFVER_ISCSI    = 0x00,
3666 	FW_HDR_INTFVER_FCOEPDU  = 0x00,
3667 	FW_HDR_INTFVER_FCOE     = 0x00,
3668 };
3669 
3670 enum fw_hdr_flags {
3671 	FW_HDR_FLAGS_RESET_HALT = 0x00000001,
3672 };
3673 
3674 /* length of the formatting string  */
3675 #define FW_DEVLOG_FMT_LEN	192
3676 
3677 /* maximum number of the formatting string parameters */
3678 #define FW_DEVLOG_FMT_PARAMS_NUM 8
3679 
3680 /* priority levels */
3681 enum fw_devlog_level {
3682 	FW_DEVLOG_LEVEL_EMERG	= 0x0,
3683 	FW_DEVLOG_LEVEL_CRIT	= 0x1,
3684 	FW_DEVLOG_LEVEL_ERR	= 0x2,
3685 	FW_DEVLOG_LEVEL_NOTICE	= 0x3,
3686 	FW_DEVLOG_LEVEL_INFO	= 0x4,
3687 	FW_DEVLOG_LEVEL_DEBUG	= 0x5,
3688 	FW_DEVLOG_LEVEL_MAX	= 0x5,
3689 };
3690 
3691 /* facilities that may send a log message */
3692 enum fw_devlog_facility {
3693 	FW_DEVLOG_FACILITY_CORE		= 0x00,
3694 	FW_DEVLOG_FACILITY_CF		= 0x01,
3695 	FW_DEVLOG_FACILITY_SCHED	= 0x02,
3696 	FW_DEVLOG_FACILITY_TIMER	= 0x04,
3697 	FW_DEVLOG_FACILITY_RES		= 0x06,
3698 	FW_DEVLOG_FACILITY_HW		= 0x08,
3699 	FW_DEVLOG_FACILITY_FLR		= 0x10,
3700 	FW_DEVLOG_FACILITY_DMAQ		= 0x12,
3701 	FW_DEVLOG_FACILITY_PHY		= 0x14,
3702 	FW_DEVLOG_FACILITY_MAC		= 0x16,
3703 	FW_DEVLOG_FACILITY_PORT		= 0x18,
3704 	FW_DEVLOG_FACILITY_VI		= 0x1A,
3705 	FW_DEVLOG_FACILITY_FILTER	= 0x1C,
3706 	FW_DEVLOG_FACILITY_ACL		= 0x1E,
3707 	FW_DEVLOG_FACILITY_TM		= 0x20,
3708 	FW_DEVLOG_FACILITY_QFC		= 0x22,
3709 	FW_DEVLOG_FACILITY_DCB		= 0x24,
3710 	FW_DEVLOG_FACILITY_ETH		= 0x26,
3711 	FW_DEVLOG_FACILITY_OFLD		= 0x28,
3712 	FW_DEVLOG_FACILITY_RI		= 0x2A,
3713 	FW_DEVLOG_FACILITY_ISCSI	= 0x2C,
3714 	FW_DEVLOG_FACILITY_FCOE		= 0x2E,
3715 	FW_DEVLOG_FACILITY_FOISCSI	= 0x30,
3716 	FW_DEVLOG_FACILITY_FOFCOE	= 0x32,
3717 	FW_DEVLOG_FACILITY_CHNET        = 0x34,
3718 	FW_DEVLOG_FACILITY_MAX          = 0x34,
3719 };
3720 
3721 /* log message format */
3722 struct fw_devlog_e {
3723 	__be64	timestamp;
3724 	__be32	seqno;
3725 	__be16	reserved1;
3726 	__u8	level;
3727 	__u8	facility;
3728 	__u8	fmt[FW_DEVLOG_FMT_LEN];
3729 	__be32	params[FW_DEVLOG_FMT_PARAMS_NUM];
3730 	__be32	reserved3[4];
3731 };
3732 
3733 struct fw_devlog_cmd {
3734 	__be32 op_to_write;
3735 	__be32 retval_len16;
3736 	__u8   level;
3737 	__u8   r2[7];
3738 	__be32 memtype_devlog_memaddr16_devlog;
3739 	__be32 memsize_devlog;
3740 	__be32 r3[2];
3741 };
3742 
3743 #define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_S		28
3744 #define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_M		0xf
3745 #define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(x)	\
3746 	(((x) >> FW_DEVLOG_CMD_MEMTYPE_DEVLOG_S) & \
3747 	 FW_DEVLOG_CMD_MEMTYPE_DEVLOG_M)
3748 
3749 #define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_S	0
3750 #define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_M	0xfffffff
3751 #define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(x)	\
3752 	(((x) >> FW_DEVLOG_CMD_MEMADDR16_DEVLOG_S) & \
3753 	 FW_DEVLOG_CMD_MEMADDR16_DEVLOG_M)
3754 
3755 /* P C I E   F W   P F 7   R E G I S T E R */
3756 
3757 /* PF7 stores the Firmware Device Log parameters which allows Host Drivers to
3758  * access the "devlog" which needing to contact firmware.  The encoding is
3759  * mostly the same as that returned by the DEVLOG command except for the size
3760  * which is encoded as the number of entries in multiples-1 of 128 here rather
3761  * than the memory size as is done in the DEVLOG command.  Thus, 0 means 128
3762  * and 15 means 2048.  This of course in turn constrains the allowed values
3763  * for the devlog size ...
3764  */
3765 #define PCIE_FW_PF_DEVLOG		7
3766 
3767 #define PCIE_FW_PF_DEVLOG_NENTRIES128_S	28
3768 #define PCIE_FW_PF_DEVLOG_NENTRIES128_M	0xf
3769 #define PCIE_FW_PF_DEVLOG_NENTRIES128_V(x) \
3770 	((x) << PCIE_FW_PF_DEVLOG_NENTRIES128_S)
3771 #define PCIE_FW_PF_DEVLOG_NENTRIES128_G(x) \
3772 	(((x) >> PCIE_FW_PF_DEVLOG_NENTRIES128_S) & \
3773 	 PCIE_FW_PF_DEVLOG_NENTRIES128_M)
3774 
3775 #define PCIE_FW_PF_DEVLOG_ADDR16_S	4
3776 #define PCIE_FW_PF_DEVLOG_ADDR16_M	0xffffff
3777 #define PCIE_FW_PF_DEVLOG_ADDR16_V(x)	((x) << PCIE_FW_PF_DEVLOG_ADDR16_S)
3778 #define PCIE_FW_PF_DEVLOG_ADDR16_G(x) \
3779 	(((x) >> PCIE_FW_PF_DEVLOG_ADDR16_S) & PCIE_FW_PF_DEVLOG_ADDR16_M)
3780 
3781 #define PCIE_FW_PF_DEVLOG_MEMTYPE_S	0
3782 #define PCIE_FW_PF_DEVLOG_MEMTYPE_M	0xf
3783 #define PCIE_FW_PF_DEVLOG_MEMTYPE_V(x)	((x) << PCIE_FW_PF_DEVLOG_MEMTYPE_S)
3784 #define PCIE_FW_PF_DEVLOG_MEMTYPE_G(x) \
3785 	(((x) >> PCIE_FW_PF_DEVLOG_MEMTYPE_S) & PCIE_FW_PF_DEVLOG_MEMTYPE_M)
3786 
3787 #define MAX_IMM_OFLD_TX_DATA_WR_LEN (0xff + sizeof(struct fw_ofld_tx_data_wr))
3788 
3789 struct fw_crypto_lookaside_wr {
3790 	__be32 op_to_cctx_size;
3791 	__be32 len16_pkd;
3792 	__be32 session_id;
3793 	__be32 rx_chid_to_rx_q_id;
3794 	__be32 key_addr;
3795 	__be32 pld_size_hash_size;
3796 	__be64 cookie;
3797 };
3798 
3799 #define FW_CRYPTO_LOOKASIDE_WR_OPCODE_S 24
3800 #define FW_CRYPTO_LOOKASIDE_WR_OPCODE_M 0xff
3801 #define FW_CRYPTO_LOOKASIDE_WR_OPCODE_V(x) \
3802 	((x) << FW_CRYPTO_LOOKASIDE_WR_OPCODE_S)
3803 #define FW_CRYPTO_LOOKASIDE_WR_OPCODE_G(x) \
3804 	(((x) >> FW_CRYPTO_LOOKASIDE_WR_OPCODE_S) & \
3805 	 FW_CRYPTO_LOOKASIDE_WR_OPCODE_M)
3806 
3807 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_S 23
3808 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_M 0x1
3809 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_V(x) \
3810 	((x) << FW_CRYPTO_LOOKASIDE_WR_COMPL_S)
3811 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_G(x) \
3812 	(((x) >> FW_CRYPTO_LOOKASIDE_WR_COMPL_S) & \
3813 	 FW_CRYPTO_LOOKASIDE_WR_COMPL_M)
3814 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_F FW_CRYPTO_LOOKASIDE_WR_COMPL_V(1U)
3815 
3816 #define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_S 15
3817 #define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_M 0xff
3818 #define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_V(x) \
3819 	((x) << FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_S)
3820 #define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_G(x) \
3821 	(((x) >> FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_S) & \
3822 	 FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_M)
3823 
3824 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_S 5
3825 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_M 0x3
3826 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_V(x) \
3827 	((x) << FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_S)
3828 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_G(x) \
3829 	(((x) >> FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_S) & \
3830 	 FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_M)
3831 
3832 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_S 0
3833 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_M 0x1f
3834 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_V(x) \
3835 	((x) << FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_S)
3836 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_G(x) \
3837 	(((x) >> FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_S) & \
3838 	 FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_M)
3839 
3840 #define FW_CRYPTO_LOOKASIDE_WR_LEN16_S 0
3841 #define FW_CRYPTO_LOOKASIDE_WR_LEN16_M 0xff
3842 #define FW_CRYPTO_LOOKASIDE_WR_LEN16_V(x) \
3843 	((x) << FW_CRYPTO_LOOKASIDE_WR_LEN16_S)
3844 #define FW_CRYPTO_LOOKASIDE_WR_LEN16_G(x) \
3845 	(((x) >> FW_CRYPTO_LOOKASIDE_WR_LEN16_S) & \
3846 	 FW_CRYPTO_LOOKASIDE_WR_LEN16_M)
3847 
3848 #define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_S 29
3849 #define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_M 0x3
3850 #define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_V(x) \
3851 	((x) << FW_CRYPTO_LOOKASIDE_WR_RX_CHID_S)
3852 #define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_G(x) \
3853 	(((x) >> FW_CRYPTO_LOOKASIDE_WR_RX_CHID_S) & \
3854 	 FW_CRYPTO_LOOKASIDE_WR_RX_CHID_M)
3855 
3856 #define FW_CRYPTO_LOOKASIDE_WR_LCB_S  27
3857 #define FW_CRYPTO_LOOKASIDE_WR_LCB_M  0x3
3858 #define FW_CRYPTO_LOOKASIDE_WR_LCB_V(x) \
3859 	((x) << FW_CRYPTO_LOOKASIDE_WR_LCB_S)
3860 #define FW_CRYPTO_LOOKASIDE_WR_LCB_G(x) \
3861 	(((x) >> FW_CRYPTO_LOOKASIDE_WR_LCB_S) & FW_CRYPTO_LOOKASIDE_WR_LCB_M)
3862 
3863 #define FW_CRYPTO_LOOKASIDE_WR_PHASH_S 25
3864 #define FW_CRYPTO_LOOKASIDE_WR_PHASH_M 0x3
3865 #define FW_CRYPTO_LOOKASIDE_WR_PHASH_V(x) \
3866 	((x) << FW_CRYPTO_LOOKASIDE_WR_PHASH_S)
3867 #define FW_CRYPTO_LOOKASIDE_WR_PHASH_G(x) \
3868 	(((x) >> FW_CRYPTO_LOOKASIDE_WR_PHASH_S) & \
3869 	 FW_CRYPTO_LOOKASIDE_WR_PHASH_M)
3870 
3871 #define FW_CRYPTO_LOOKASIDE_WR_IV_S   23
3872 #define FW_CRYPTO_LOOKASIDE_WR_IV_M   0x3
3873 #define FW_CRYPTO_LOOKASIDE_WR_IV_V(x) \
3874 	((x) << FW_CRYPTO_LOOKASIDE_WR_IV_S)
3875 #define FW_CRYPTO_LOOKASIDE_WR_IV_G(x) \
3876 	(((x) >> FW_CRYPTO_LOOKASIDE_WR_IV_S) & FW_CRYPTO_LOOKASIDE_WR_IV_M)
3877 
3878 #define FW_CRYPTO_LOOKASIDE_WR_FQIDX_S   15
3879 #define FW_CRYPTO_LOOKASIDE_WR_FQIDX_M   0xff
3880 #define FW_CRYPTO_LOOKASIDE_WR_FQIDX_V(x) \
3881 	((x) << FW_CRYPTO_LOOKASIDE_WR_FQIDX_S)
3882 #define FW_CRYPTO_LOOKASIDE_WR_FQIDX_G(x) \
3883 	(((x) >> FW_CRYPTO_LOOKASIDE_WR_FQIDX_S) & \
3884 	 FW_CRYPTO_LOOKASIDE_WR_FQIDX_M)
3885 
3886 #define FW_CRYPTO_LOOKASIDE_WR_TX_CH_S 10
3887 #define FW_CRYPTO_LOOKASIDE_WR_TX_CH_M 0x3
3888 #define FW_CRYPTO_LOOKASIDE_WR_TX_CH_V(x) \
3889 	((x) << FW_CRYPTO_LOOKASIDE_WR_TX_CH_S)
3890 #define FW_CRYPTO_LOOKASIDE_WR_TX_CH_G(x) \
3891 	(((x) >> FW_CRYPTO_LOOKASIDE_WR_TX_CH_S) & \
3892 	 FW_CRYPTO_LOOKASIDE_WR_TX_CH_M)
3893 
3894 #define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_S 0
3895 #define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_M 0x3ff
3896 #define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_V(x) \
3897 	((x) << FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_S)
3898 #define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_G(x) \
3899 	(((x) >> FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_S) & \
3900 	 FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_M)
3901 
3902 #define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_S 24
3903 #define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_M 0xff
3904 #define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_V(x) \
3905 	((x) << FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_S)
3906 #define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_G(x) \
3907 	(((x) >> FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_S) & \
3908 	 FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_M)
3909 
3910 #define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_S 17
3911 #define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_M 0x7f
3912 #define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_V(x) \
3913 	((x) << FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_S)
3914 #define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_G(x) \
3915 	(((x) >> FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_S) & \
3916 	 FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_M)
3917 
3918 struct fw_tlstx_data_wr {
3919 	__be32 op_to_immdlen;
3920 	__be32 flowid_len16;
3921 	__be32 plen;
3922 	__be32 lsodisable_to_flags;
3923 	__be32 r5;
3924 	__be32 ctxloc_to_exp;
3925 	__be16 mfs;
3926 	__be16 adjustedplen_pkd;
3927 	__be16 expinplenmax_pkd;
3928 	u8   pdusinplenmax_pkd;
3929 	u8   r10;
3930 };
3931 
3932 #define FW_TLSTX_DATA_WR_OPCODE_S       24
3933 #define FW_TLSTX_DATA_WR_OPCODE_M       0xff
3934 #define FW_TLSTX_DATA_WR_OPCODE_V(x)    ((x) << FW_TLSTX_DATA_WR_OPCODE_S)
3935 #define FW_TLSTX_DATA_WR_OPCODE_G(x)    \
3936 	(((x) >> FW_TLSTX_DATA_WR_OPCODE_S) & FW_TLSTX_DATA_WR_OPCODE_M)
3937 
3938 #define FW_TLSTX_DATA_WR_COMPL_S        21
3939 #define FW_TLSTX_DATA_WR_COMPL_M        0x1
3940 #define FW_TLSTX_DATA_WR_COMPL_V(x)     ((x) << FW_TLSTX_DATA_WR_COMPL_S)
3941 #define FW_TLSTX_DATA_WR_COMPL_G(x)     \
3942 	(((x) >> FW_TLSTX_DATA_WR_COMPL_S) & FW_TLSTX_DATA_WR_COMPL_M)
3943 #define FW_TLSTX_DATA_WR_COMPL_F        FW_TLSTX_DATA_WR_COMPL_V(1U)
3944 
3945 #define FW_TLSTX_DATA_WR_IMMDLEN_S      0
3946 #define FW_TLSTX_DATA_WR_IMMDLEN_M      0xff
3947 #define FW_TLSTX_DATA_WR_IMMDLEN_V(x)   ((x) << FW_TLSTX_DATA_WR_IMMDLEN_S)
3948 #define FW_TLSTX_DATA_WR_IMMDLEN_G(x)   \
3949 	(((x) >> FW_TLSTX_DATA_WR_IMMDLEN_S) & FW_TLSTX_DATA_WR_IMMDLEN_M)
3950 
3951 #define FW_TLSTX_DATA_WR_FLOWID_S       8
3952 #define FW_TLSTX_DATA_WR_FLOWID_M       0xfffff
3953 #define FW_TLSTX_DATA_WR_FLOWID_V(x)    ((x) << FW_TLSTX_DATA_WR_FLOWID_S)
3954 #define FW_TLSTX_DATA_WR_FLOWID_G(x)    \
3955 	(((x) >> FW_TLSTX_DATA_WR_FLOWID_S) & FW_TLSTX_DATA_WR_FLOWID_M)
3956 
3957 #define FW_TLSTX_DATA_WR_LEN16_S        0
3958 #define FW_TLSTX_DATA_WR_LEN16_M        0xff
3959 #define FW_TLSTX_DATA_WR_LEN16_V(x)     ((x) << FW_TLSTX_DATA_WR_LEN16_S)
3960 #define FW_TLSTX_DATA_WR_LEN16_G(x)     \
3961 	(((x) >> FW_TLSTX_DATA_WR_LEN16_S) & FW_TLSTX_DATA_WR_LEN16_M)
3962 
3963 #define FW_TLSTX_DATA_WR_LSODISABLE_S   31
3964 #define FW_TLSTX_DATA_WR_LSODISABLE_M   0x1
3965 #define FW_TLSTX_DATA_WR_LSODISABLE_V(x) \
3966 	((x) << FW_TLSTX_DATA_WR_LSODISABLE_S)
3967 #define FW_TLSTX_DATA_WR_LSODISABLE_G(x) \
3968 	(((x) >> FW_TLSTX_DATA_WR_LSODISABLE_S) & FW_TLSTX_DATA_WR_LSODISABLE_M)
3969 #define FW_TLSTX_DATA_WR_LSODISABLE_F   FW_TLSTX_DATA_WR_LSODISABLE_V(1U)
3970 
3971 #define FW_TLSTX_DATA_WR_ALIGNPLD_S     30
3972 #define FW_TLSTX_DATA_WR_ALIGNPLD_M     0x1
3973 #define FW_TLSTX_DATA_WR_ALIGNPLD_V(x)  ((x) << FW_TLSTX_DATA_WR_ALIGNPLD_S)
3974 #define FW_TLSTX_DATA_WR_ALIGNPLD_G(x)  \
3975 	(((x) >> FW_TLSTX_DATA_WR_ALIGNPLD_S) & FW_TLSTX_DATA_WR_ALIGNPLD_M)
3976 #define FW_TLSTX_DATA_WR_ALIGNPLD_F     FW_TLSTX_DATA_WR_ALIGNPLD_V(1U)
3977 
3978 #define FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_S 29
3979 #define FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_M 0x1
3980 #define FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_V(x) \
3981 	((x) << FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_S)
3982 #define FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_G(x) \
3983 	(((x) >> FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_S) & \
3984 	FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_M)
3985 #define FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_F FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_V(1U)
3986 
3987 #define FW_TLSTX_DATA_WR_FLAGS_S        0
3988 #define FW_TLSTX_DATA_WR_FLAGS_M        0xfffffff
3989 #define FW_TLSTX_DATA_WR_FLAGS_V(x)     ((x) << FW_TLSTX_DATA_WR_FLAGS_S)
3990 #define FW_TLSTX_DATA_WR_FLAGS_G(x)     \
3991 	(((x) >> FW_TLSTX_DATA_WR_FLAGS_S) & FW_TLSTX_DATA_WR_FLAGS_M)
3992 
3993 #define FW_TLSTX_DATA_WR_CTXLOC_S       30
3994 #define FW_TLSTX_DATA_WR_CTXLOC_M       0x3
3995 #define FW_TLSTX_DATA_WR_CTXLOC_V(x)    ((x) << FW_TLSTX_DATA_WR_CTXLOC_S)
3996 #define FW_TLSTX_DATA_WR_CTXLOC_G(x)    \
3997 	(((x) >> FW_TLSTX_DATA_WR_CTXLOC_S) & FW_TLSTX_DATA_WR_CTXLOC_M)
3998 
3999 #define FW_TLSTX_DATA_WR_IVDSGL_S       29
4000 #define FW_TLSTX_DATA_WR_IVDSGL_M       0x1
4001 #define FW_TLSTX_DATA_WR_IVDSGL_V(x)    ((x) << FW_TLSTX_DATA_WR_IVDSGL_S)
4002 #define FW_TLSTX_DATA_WR_IVDSGL_G(x)    \
4003 	(((x) >> FW_TLSTX_DATA_WR_IVDSGL_S) & FW_TLSTX_DATA_WR_IVDSGL_M)
4004 #define FW_TLSTX_DATA_WR_IVDSGL_F       FW_TLSTX_DATA_WR_IVDSGL_V(1U)
4005 
4006 #define FW_TLSTX_DATA_WR_KEYSIZE_S      24
4007 #define FW_TLSTX_DATA_WR_KEYSIZE_M      0x1f
4008 #define FW_TLSTX_DATA_WR_KEYSIZE_V(x)   ((x) << FW_TLSTX_DATA_WR_KEYSIZE_S)
4009 #define FW_TLSTX_DATA_WR_KEYSIZE_G(x)   \
4010 	(((x) >> FW_TLSTX_DATA_WR_KEYSIZE_S) & FW_TLSTX_DATA_WR_KEYSIZE_M)
4011 
4012 #define FW_TLSTX_DATA_WR_NUMIVS_S       14
4013 #define FW_TLSTX_DATA_WR_NUMIVS_M       0xff
4014 #define FW_TLSTX_DATA_WR_NUMIVS_V(x)    ((x) << FW_TLSTX_DATA_WR_NUMIVS_S)
4015 #define FW_TLSTX_DATA_WR_NUMIVS_G(x)    \
4016 	(((x) >> FW_TLSTX_DATA_WR_NUMIVS_S) & FW_TLSTX_DATA_WR_NUMIVS_M)
4017 
4018 #define FW_TLSTX_DATA_WR_EXP_S          0
4019 #define FW_TLSTX_DATA_WR_EXP_M          0x3fff
4020 #define FW_TLSTX_DATA_WR_EXP_V(x)       ((x) << FW_TLSTX_DATA_WR_EXP_S)
4021 #define FW_TLSTX_DATA_WR_EXP_G(x)       \
4022 	(((x) >> FW_TLSTX_DATA_WR_EXP_S) & FW_TLSTX_DATA_WR_EXP_M)
4023 
4024 #define FW_TLSTX_DATA_WR_ADJUSTEDPLEN_S 1
4025 #define FW_TLSTX_DATA_WR_ADJUSTEDPLEN_V(x) \
4026 	((x) << FW_TLSTX_DATA_WR_ADJUSTEDPLEN_S)
4027 
4028 #define FW_TLSTX_DATA_WR_EXPINPLENMAX_S 4
4029 #define FW_TLSTX_DATA_WR_EXPINPLENMAX_V(x) \
4030 	((x) << FW_TLSTX_DATA_WR_EXPINPLENMAX_S)
4031 
4032 #define FW_TLSTX_DATA_WR_PDUSINPLENMAX_S 2
4033 #define FW_TLSTX_DATA_WR_PDUSINPLENMAX_V(x) \
4034 	((x) << FW_TLSTX_DATA_WR_PDUSINPLENMAX_S)
4035 
4036 #endif /* _T4FW_INTERFACE_H_ */
4037