1 /* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2009-2016 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #ifndef _T4FW_INTERFACE_H_ 36 #define _T4FW_INTERFACE_H_ 37 38 enum fw_retval { 39 FW_SUCCESS = 0, /* completed successfully */ 40 FW_EPERM = 1, /* operation not permitted */ 41 FW_ENOENT = 2, /* no such file or directory */ 42 FW_EIO = 5, /* input/output error; hw bad */ 43 FW_ENOEXEC = 8, /* exec format error; inv microcode */ 44 FW_EAGAIN = 11, /* try again */ 45 FW_ENOMEM = 12, /* out of memory */ 46 FW_EFAULT = 14, /* bad address; fw bad */ 47 FW_EBUSY = 16, /* resource busy */ 48 FW_EEXIST = 17, /* file exists */ 49 FW_ENODEV = 19, /* no such device */ 50 FW_EINVAL = 22, /* invalid argument */ 51 FW_ENOSPC = 28, /* no space left on device */ 52 FW_ENOSYS = 38, /* functionality not implemented */ 53 FW_ENODATA = 61, /* no data available */ 54 FW_EPROTO = 71, /* protocol error */ 55 FW_EADDRINUSE = 98, /* address already in use */ 56 FW_EADDRNOTAVAIL = 99, /* cannot assigned requested address */ 57 FW_ENETDOWN = 100, /* network is down */ 58 FW_ENETUNREACH = 101, /* network is unreachable */ 59 FW_ENOBUFS = 105, /* no buffer space available */ 60 FW_ETIMEDOUT = 110, /* timeout */ 61 FW_EINPROGRESS = 115, /* fw internal */ 62 FW_SCSI_ABORT_REQUESTED = 128, /* */ 63 FW_SCSI_ABORT_TIMEDOUT = 129, /* */ 64 FW_SCSI_ABORTED = 130, /* */ 65 FW_SCSI_CLOSE_REQUESTED = 131, /* */ 66 FW_ERR_LINK_DOWN = 132, /* */ 67 FW_RDEV_NOT_READY = 133, /* */ 68 FW_ERR_RDEV_LOST = 134, /* */ 69 FW_ERR_RDEV_LOGO = 135, /* */ 70 FW_FCOE_NO_XCHG = 136, /* */ 71 FW_SCSI_RSP_ERR = 137, /* */ 72 FW_ERR_RDEV_IMPL_LOGO = 138, /* */ 73 FW_SCSI_UNDER_FLOW_ERR = 139, /* */ 74 FW_SCSI_OVER_FLOW_ERR = 140, /* */ 75 FW_SCSI_DDP_ERR = 141, /* DDP error*/ 76 FW_SCSI_TASK_ERR = 142, /* No SCSI tasks available */ 77 }; 78 79 #define FW_T4VF_SGE_BASE_ADDR 0x0000 80 #define FW_T4VF_MPS_BASE_ADDR 0x0100 81 #define FW_T4VF_PL_BASE_ADDR 0x0200 82 #define FW_T4VF_MBDATA_BASE_ADDR 0x0240 83 #define FW_T4VF_CIM_BASE_ADDR 0x0300 84 85 enum fw_wr_opcodes { 86 FW_FILTER_WR = 0x02, 87 FW_ULPTX_WR = 0x04, 88 FW_TP_WR = 0x05, 89 FW_ETH_TX_PKT_WR = 0x08, 90 FW_ETH_TX_EO_WR = 0x1c, 91 FW_OFLD_CONNECTION_WR = 0x2f, 92 FW_FLOWC_WR = 0x0a, 93 FW_OFLD_TX_DATA_WR = 0x0b, 94 FW_CMD_WR = 0x10, 95 FW_ETH_TX_PKT_VM_WR = 0x11, 96 FW_RI_RES_WR = 0x0c, 97 FW_RI_INIT_WR = 0x0d, 98 FW_RI_RDMA_WRITE_WR = 0x14, 99 FW_RI_SEND_WR = 0x15, 100 FW_RI_RDMA_READ_WR = 0x16, 101 FW_RI_RECV_WR = 0x17, 102 FW_RI_BIND_MW_WR = 0x18, 103 FW_RI_FR_NSMR_WR = 0x19, 104 FW_RI_FR_NSMR_TPTE_WR = 0x20, 105 FW_RI_RDMA_WRITE_CMPL_WR = 0x21, 106 FW_RI_INV_LSTAG_WR = 0x1a, 107 FW_ISCSI_TX_DATA_WR = 0x45, 108 FW_PTP_TX_PKT_WR = 0x46, 109 FW_TLSTX_DATA_WR = 0x68, 110 FW_CRYPTO_LOOKASIDE_WR = 0X6d, 111 FW_LASTC2E_WR = 0x70, 112 FW_FILTER2_WR = 0x77 113 }; 114 115 struct fw_wr_hdr { 116 __be32 hi; 117 __be32 lo; 118 }; 119 120 /* work request opcode (hi) */ 121 #define FW_WR_OP_S 24 122 #define FW_WR_OP_M 0xff 123 #define FW_WR_OP_V(x) ((x) << FW_WR_OP_S) 124 #define FW_WR_OP_G(x) (((x) >> FW_WR_OP_S) & FW_WR_OP_M) 125 126 /* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER */ 127 #define FW_WR_ATOMIC_S 23 128 #define FW_WR_ATOMIC_V(x) ((x) << FW_WR_ATOMIC_S) 129 130 /* flush flag (hi) - firmware flushes flushable work request buffered 131 * in the flow context. 132 */ 133 #define FW_WR_FLUSH_S 22 134 #define FW_WR_FLUSH_V(x) ((x) << FW_WR_FLUSH_S) 135 136 /* completion flag (hi) - firmware generates a cpl_fw6_ack */ 137 #define FW_WR_COMPL_S 21 138 #define FW_WR_COMPL_V(x) ((x) << FW_WR_COMPL_S) 139 #define FW_WR_COMPL_F FW_WR_COMPL_V(1U) 140 141 /* work request immediate data length (hi) */ 142 #define FW_WR_IMMDLEN_S 0 143 #define FW_WR_IMMDLEN_M 0xff 144 #define FW_WR_IMMDLEN_V(x) ((x) << FW_WR_IMMDLEN_S) 145 146 /* egress queue status update to associated ingress queue entry (lo) */ 147 #define FW_WR_EQUIQ_S 31 148 #define FW_WR_EQUIQ_V(x) ((x) << FW_WR_EQUIQ_S) 149 #define FW_WR_EQUIQ_F FW_WR_EQUIQ_V(1U) 150 151 /* egress queue status update to egress queue status entry (lo) */ 152 #define FW_WR_EQUEQ_S 30 153 #define FW_WR_EQUEQ_V(x) ((x) << FW_WR_EQUEQ_S) 154 #define FW_WR_EQUEQ_F FW_WR_EQUEQ_V(1U) 155 156 /* flow context identifier (lo) */ 157 #define FW_WR_FLOWID_S 8 158 #define FW_WR_FLOWID_V(x) ((x) << FW_WR_FLOWID_S) 159 160 /* length in units of 16-bytes (lo) */ 161 #define FW_WR_LEN16_S 0 162 #define FW_WR_LEN16_V(x) ((x) << FW_WR_LEN16_S) 163 164 #define HW_TPL_FR_MT_PR_IV_P_FC 0X32B 165 #define HW_TPL_FR_MT_PR_OV_P_FC 0X327 166 167 /* filter wr reply code in cookie in CPL_SET_TCB_RPL */ 168 enum fw_filter_wr_cookie { 169 FW_FILTER_WR_SUCCESS, 170 FW_FILTER_WR_FLT_ADDED, 171 FW_FILTER_WR_FLT_DELETED, 172 FW_FILTER_WR_SMT_TBL_FULL, 173 FW_FILTER_WR_EINVAL, 174 }; 175 176 struct fw_filter_wr { 177 __be32 op_pkd; 178 __be32 len16_pkd; 179 __be64 r3; 180 __be32 tid_to_iq; 181 __be32 del_filter_to_l2tix; 182 __be16 ethtype; 183 __be16 ethtypem; 184 __u8 frag_to_ovlan_vldm; 185 __u8 smac_sel; 186 __be16 rx_chan_rx_rpl_iq; 187 __be32 maci_to_matchtypem; 188 __u8 ptcl; 189 __u8 ptclm; 190 __u8 ttyp; 191 __u8 ttypm; 192 __be16 ivlan; 193 __be16 ivlanm; 194 __be16 ovlan; 195 __be16 ovlanm; 196 __u8 lip[16]; 197 __u8 lipm[16]; 198 __u8 fip[16]; 199 __u8 fipm[16]; 200 __be16 lp; 201 __be16 lpm; 202 __be16 fp; 203 __be16 fpm; 204 __be16 r7; 205 __u8 sma[6]; 206 }; 207 208 struct fw_filter2_wr { 209 __be32 op_pkd; 210 __be32 len16_pkd; 211 __be64 r3; 212 __be32 tid_to_iq; 213 __be32 del_filter_to_l2tix; 214 __be16 ethtype; 215 __be16 ethtypem; 216 __u8 frag_to_ovlan_vldm; 217 __u8 smac_sel; 218 __be16 rx_chan_rx_rpl_iq; 219 __be32 maci_to_matchtypem; 220 __u8 ptcl; 221 __u8 ptclm; 222 __u8 ttyp; 223 __u8 ttypm; 224 __be16 ivlan; 225 __be16 ivlanm; 226 __be16 ovlan; 227 __be16 ovlanm; 228 __u8 lip[16]; 229 __u8 lipm[16]; 230 __u8 fip[16]; 231 __u8 fipm[16]; 232 __be16 lp; 233 __be16 lpm; 234 __be16 fp; 235 __be16 fpm; 236 __be16 r7; 237 __u8 sma[6]; 238 __be16 r8; 239 __u8 filter_type_swapmac; 240 __u8 natmode_to_ulp_type; 241 __be16 newlport; 242 __be16 newfport; 243 __u8 newlip[16]; 244 __u8 newfip[16]; 245 __be32 natseqcheck; 246 __be32 r9; 247 __be64 r10; 248 __be64 r11; 249 __be64 r12; 250 __be64 r13; 251 }; 252 253 #define FW_FILTER_WR_TID_S 12 254 #define FW_FILTER_WR_TID_M 0xfffff 255 #define FW_FILTER_WR_TID_V(x) ((x) << FW_FILTER_WR_TID_S) 256 #define FW_FILTER_WR_TID_G(x) \ 257 (((x) >> FW_FILTER_WR_TID_S) & FW_FILTER_WR_TID_M) 258 259 #define FW_FILTER_WR_RQTYPE_S 11 260 #define FW_FILTER_WR_RQTYPE_M 0x1 261 #define FW_FILTER_WR_RQTYPE_V(x) ((x) << FW_FILTER_WR_RQTYPE_S) 262 #define FW_FILTER_WR_RQTYPE_G(x) \ 263 (((x) >> FW_FILTER_WR_RQTYPE_S) & FW_FILTER_WR_RQTYPE_M) 264 #define FW_FILTER_WR_RQTYPE_F FW_FILTER_WR_RQTYPE_V(1U) 265 266 #define FW_FILTER_WR_NOREPLY_S 10 267 #define FW_FILTER_WR_NOREPLY_M 0x1 268 #define FW_FILTER_WR_NOREPLY_V(x) ((x) << FW_FILTER_WR_NOREPLY_S) 269 #define FW_FILTER_WR_NOREPLY_G(x) \ 270 (((x) >> FW_FILTER_WR_NOREPLY_S) & FW_FILTER_WR_NOREPLY_M) 271 #define FW_FILTER_WR_NOREPLY_F FW_FILTER_WR_NOREPLY_V(1U) 272 273 #define FW_FILTER_WR_IQ_S 0 274 #define FW_FILTER_WR_IQ_M 0x3ff 275 #define FW_FILTER_WR_IQ_V(x) ((x) << FW_FILTER_WR_IQ_S) 276 #define FW_FILTER_WR_IQ_G(x) \ 277 (((x) >> FW_FILTER_WR_IQ_S) & FW_FILTER_WR_IQ_M) 278 279 #define FW_FILTER_WR_DEL_FILTER_S 31 280 #define FW_FILTER_WR_DEL_FILTER_M 0x1 281 #define FW_FILTER_WR_DEL_FILTER_V(x) ((x) << FW_FILTER_WR_DEL_FILTER_S) 282 #define FW_FILTER_WR_DEL_FILTER_G(x) \ 283 (((x) >> FW_FILTER_WR_DEL_FILTER_S) & FW_FILTER_WR_DEL_FILTER_M) 284 #define FW_FILTER_WR_DEL_FILTER_F FW_FILTER_WR_DEL_FILTER_V(1U) 285 286 #define FW_FILTER_WR_RPTTID_S 25 287 #define FW_FILTER_WR_RPTTID_M 0x1 288 #define FW_FILTER_WR_RPTTID_V(x) ((x) << FW_FILTER_WR_RPTTID_S) 289 #define FW_FILTER_WR_RPTTID_G(x) \ 290 (((x) >> FW_FILTER_WR_RPTTID_S) & FW_FILTER_WR_RPTTID_M) 291 #define FW_FILTER_WR_RPTTID_F FW_FILTER_WR_RPTTID_V(1U) 292 293 #define FW_FILTER_WR_DROP_S 24 294 #define FW_FILTER_WR_DROP_M 0x1 295 #define FW_FILTER_WR_DROP_V(x) ((x) << FW_FILTER_WR_DROP_S) 296 #define FW_FILTER_WR_DROP_G(x) \ 297 (((x) >> FW_FILTER_WR_DROP_S) & FW_FILTER_WR_DROP_M) 298 #define FW_FILTER_WR_DROP_F FW_FILTER_WR_DROP_V(1U) 299 300 #define FW_FILTER_WR_DIRSTEER_S 23 301 #define FW_FILTER_WR_DIRSTEER_M 0x1 302 #define FW_FILTER_WR_DIRSTEER_V(x) ((x) << FW_FILTER_WR_DIRSTEER_S) 303 #define FW_FILTER_WR_DIRSTEER_G(x) \ 304 (((x) >> FW_FILTER_WR_DIRSTEER_S) & FW_FILTER_WR_DIRSTEER_M) 305 #define FW_FILTER_WR_DIRSTEER_F FW_FILTER_WR_DIRSTEER_V(1U) 306 307 #define FW_FILTER_WR_MASKHASH_S 22 308 #define FW_FILTER_WR_MASKHASH_M 0x1 309 #define FW_FILTER_WR_MASKHASH_V(x) ((x) << FW_FILTER_WR_MASKHASH_S) 310 #define FW_FILTER_WR_MASKHASH_G(x) \ 311 (((x) >> FW_FILTER_WR_MASKHASH_S) & FW_FILTER_WR_MASKHASH_M) 312 #define FW_FILTER_WR_MASKHASH_F FW_FILTER_WR_MASKHASH_V(1U) 313 314 #define FW_FILTER_WR_DIRSTEERHASH_S 21 315 #define FW_FILTER_WR_DIRSTEERHASH_M 0x1 316 #define FW_FILTER_WR_DIRSTEERHASH_V(x) ((x) << FW_FILTER_WR_DIRSTEERHASH_S) 317 #define FW_FILTER_WR_DIRSTEERHASH_G(x) \ 318 (((x) >> FW_FILTER_WR_DIRSTEERHASH_S) & FW_FILTER_WR_DIRSTEERHASH_M) 319 #define FW_FILTER_WR_DIRSTEERHASH_F FW_FILTER_WR_DIRSTEERHASH_V(1U) 320 321 #define FW_FILTER_WR_LPBK_S 20 322 #define FW_FILTER_WR_LPBK_M 0x1 323 #define FW_FILTER_WR_LPBK_V(x) ((x) << FW_FILTER_WR_LPBK_S) 324 #define FW_FILTER_WR_LPBK_G(x) \ 325 (((x) >> FW_FILTER_WR_LPBK_S) & FW_FILTER_WR_LPBK_M) 326 #define FW_FILTER_WR_LPBK_F FW_FILTER_WR_LPBK_V(1U) 327 328 #define FW_FILTER_WR_DMAC_S 19 329 #define FW_FILTER_WR_DMAC_M 0x1 330 #define FW_FILTER_WR_DMAC_V(x) ((x) << FW_FILTER_WR_DMAC_S) 331 #define FW_FILTER_WR_DMAC_G(x) \ 332 (((x) >> FW_FILTER_WR_DMAC_S) & FW_FILTER_WR_DMAC_M) 333 #define FW_FILTER_WR_DMAC_F FW_FILTER_WR_DMAC_V(1U) 334 335 #define FW_FILTER_WR_SMAC_S 18 336 #define FW_FILTER_WR_SMAC_M 0x1 337 #define FW_FILTER_WR_SMAC_V(x) ((x) << FW_FILTER_WR_SMAC_S) 338 #define FW_FILTER_WR_SMAC_G(x) \ 339 (((x) >> FW_FILTER_WR_SMAC_S) & FW_FILTER_WR_SMAC_M) 340 #define FW_FILTER_WR_SMAC_F FW_FILTER_WR_SMAC_V(1U) 341 342 #define FW_FILTER_WR_INSVLAN_S 17 343 #define FW_FILTER_WR_INSVLAN_M 0x1 344 #define FW_FILTER_WR_INSVLAN_V(x) ((x) << FW_FILTER_WR_INSVLAN_S) 345 #define FW_FILTER_WR_INSVLAN_G(x) \ 346 (((x) >> FW_FILTER_WR_INSVLAN_S) & FW_FILTER_WR_INSVLAN_M) 347 #define FW_FILTER_WR_INSVLAN_F FW_FILTER_WR_INSVLAN_V(1U) 348 349 #define FW_FILTER_WR_RMVLAN_S 16 350 #define FW_FILTER_WR_RMVLAN_M 0x1 351 #define FW_FILTER_WR_RMVLAN_V(x) ((x) << FW_FILTER_WR_RMVLAN_S) 352 #define FW_FILTER_WR_RMVLAN_G(x) \ 353 (((x) >> FW_FILTER_WR_RMVLAN_S) & FW_FILTER_WR_RMVLAN_M) 354 #define FW_FILTER_WR_RMVLAN_F FW_FILTER_WR_RMVLAN_V(1U) 355 356 #define FW_FILTER_WR_HITCNTS_S 15 357 #define FW_FILTER_WR_HITCNTS_M 0x1 358 #define FW_FILTER_WR_HITCNTS_V(x) ((x) << FW_FILTER_WR_HITCNTS_S) 359 #define FW_FILTER_WR_HITCNTS_G(x) \ 360 (((x) >> FW_FILTER_WR_HITCNTS_S) & FW_FILTER_WR_HITCNTS_M) 361 #define FW_FILTER_WR_HITCNTS_F FW_FILTER_WR_HITCNTS_V(1U) 362 363 #define FW_FILTER_WR_TXCHAN_S 13 364 #define FW_FILTER_WR_TXCHAN_M 0x3 365 #define FW_FILTER_WR_TXCHAN_V(x) ((x) << FW_FILTER_WR_TXCHAN_S) 366 #define FW_FILTER_WR_TXCHAN_G(x) \ 367 (((x) >> FW_FILTER_WR_TXCHAN_S) & FW_FILTER_WR_TXCHAN_M) 368 369 #define FW_FILTER_WR_PRIO_S 12 370 #define FW_FILTER_WR_PRIO_M 0x1 371 #define FW_FILTER_WR_PRIO_V(x) ((x) << FW_FILTER_WR_PRIO_S) 372 #define FW_FILTER_WR_PRIO_G(x) \ 373 (((x) >> FW_FILTER_WR_PRIO_S) & FW_FILTER_WR_PRIO_M) 374 #define FW_FILTER_WR_PRIO_F FW_FILTER_WR_PRIO_V(1U) 375 376 #define FW_FILTER_WR_L2TIX_S 0 377 #define FW_FILTER_WR_L2TIX_M 0xfff 378 #define FW_FILTER_WR_L2TIX_V(x) ((x) << FW_FILTER_WR_L2TIX_S) 379 #define FW_FILTER_WR_L2TIX_G(x) \ 380 (((x) >> FW_FILTER_WR_L2TIX_S) & FW_FILTER_WR_L2TIX_M) 381 382 #define FW_FILTER_WR_FRAG_S 7 383 #define FW_FILTER_WR_FRAG_M 0x1 384 #define FW_FILTER_WR_FRAG_V(x) ((x) << FW_FILTER_WR_FRAG_S) 385 #define FW_FILTER_WR_FRAG_G(x) \ 386 (((x) >> FW_FILTER_WR_FRAG_S) & FW_FILTER_WR_FRAG_M) 387 #define FW_FILTER_WR_FRAG_F FW_FILTER_WR_FRAG_V(1U) 388 389 #define FW_FILTER_WR_FRAGM_S 6 390 #define FW_FILTER_WR_FRAGM_M 0x1 391 #define FW_FILTER_WR_FRAGM_V(x) ((x) << FW_FILTER_WR_FRAGM_S) 392 #define FW_FILTER_WR_FRAGM_G(x) \ 393 (((x) >> FW_FILTER_WR_FRAGM_S) & FW_FILTER_WR_FRAGM_M) 394 #define FW_FILTER_WR_FRAGM_F FW_FILTER_WR_FRAGM_V(1U) 395 396 #define FW_FILTER_WR_IVLAN_VLD_S 5 397 #define FW_FILTER_WR_IVLAN_VLD_M 0x1 398 #define FW_FILTER_WR_IVLAN_VLD_V(x) ((x) << FW_FILTER_WR_IVLAN_VLD_S) 399 #define FW_FILTER_WR_IVLAN_VLD_G(x) \ 400 (((x) >> FW_FILTER_WR_IVLAN_VLD_S) & FW_FILTER_WR_IVLAN_VLD_M) 401 #define FW_FILTER_WR_IVLAN_VLD_F FW_FILTER_WR_IVLAN_VLD_V(1U) 402 403 #define FW_FILTER_WR_OVLAN_VLD_S 4 404 #define FW_FILTER_WR_OVLAN_VLD_M 0x1 405 #define FW_FILTER_WR_OVLAN_VLD_V(x) ((x) << FW_FILTER_WR_OVLAN_VLD_S) 406 #define FW_FILTER_WR_OVLAN_VLD_G(x) \ 407 (((x) >> FW_FILTER_WR_OVLAN_VLD_S) & FW_FILTER_WR_OVLAN_VLD_M) 408 #define FW_FILTER_WR_OVLAN_VLD_F FW_FILTER_WR_OVLAN_VLD_V(1U) 409 410 #define FW_FILTER_WR_IVLAN_VLDM_S 3 411 #define FW_FILTER_WR_IVLAN_VLDM_M 0x1 412 #define FW_FILTER_WR_IVLAN_VLDM_V(x) ((x) << FW_FILTER_WR_IVLAN_VLDM_S) 413 #define FW_FILTER_WR_IVLAN_VLDM_G(x) \ 414 (((x) >> FW_FILTER_WR_IVLAN_VLDM_S) & FW_FILTER_WR_IVLAN_VLDM_M) 415 #define FW_FILTER_WR_IVLAN_VLDM_F FW_FILTER_WR_IVLAN_VLDM_V(1U) 416 417 #define FW_FILTER_WR_OVLAN_VLDM_S 2 418 #define FW_FILTER_WR_OVLAN_VLDM_M 0x1 419 #define FW_FILTER_WR_OVLAN_VLDM_V(x) ((x) << FW_FILTER_WR_OVLAN_VLDM_S) 420 #define FW_FILTER_WR_OVLAN_VLDM_G(x) \ 421 (((x) >> FW_FILTER_WR_OVLAN_VLDM_S) & FW_FILTER_WR_OVLAN_VLDM_M) 422 #define FW_FILTER_WR_OVLAN_VLDM_F FW_FILTER_WR_OVLAN_VLDM_V(1U) 423 424 #define FW_FILTER_WR_RX_CHAN_S 15 425 #define FW_FILTER_WR_RX_CHAN_M 0x1 426 #define FW_FILTER_WR_RX_CHAN_V(x) ((x) << FW_FILTER_WR_RX_CHAN_S) 427 #define FW_FILTER_WR_RX_CHAN_G(x) \ 428 (((x) >> FW_FILTER_WR_RX_CHAN_S) & FW_FILTER_WR_RX_CHAN_M) 429 #define FW_FILTER_WR_RX_CHAN_F FW_FILTER_WR_RX_CHAN_V(1U) 430 431 #define FW_FILTER_WR_RX_RPL_IQ_S 0 432 #define FW_FILTER_WR_RX_RPL_IQ_M 0x3ff 433 #define FW_FILTER_WR_RX_RPL_IQ_V(x) ((x) << FW_FILTER_WR_RX_RPL_IQ_S) 434 #define FW_FILTER_WR_RX_RPL_IQ_G(x) \ 435 (((x) >> FW_FILTER_WR_RX_RPL_IQ_S) & FW_FILTER_WR_RX_RPL_IQ_M) 436 437 #define FW_FILTER2_WR_FILTER_TYPE_S 1 438 #define FW_FILTER2_WR_FILTER_TYPE_M 0x1 439 #define FW_FILTER2_WR_FILTER_TYPE_V(x) ((x) << FW_FILTER2_WR_FILTER_TYPE_S) 440 #define FW_FILTER2_WR_FILTER_TYPE_G(x) \ 441 (((x) >> FW_FILTER2_WR_FILTER_TYPE_S) & FW_FILTER2_WR_FILTER_TYPE_M) 442 #define FW_FILTER2_WR_FILTER_TYPE_F FW_FILTER2_WR_FILTER_TYPE_V(1U) 443 444 #define FW_FILTER2_WR_NATMODE_S 5 445 #define FW_FILTER2_WR_NATMODE_M 0x7 446 #define FW_FILTER2_WR_NATMODE_V(x) ((x) << FW_FILTER2_WR_NATMODE_S) 447 #define FW_FILTER2_WR_NATMODE_G(x) \ 448 (((x) >> FW_FILTER2_WR_NATMODE_S) & FW_FILTER2_WR_NATMODE_M) 449 450 #define FW_FILTER2_WR_NATFLAGCHECK_S 4 451 #define FW_FILTER2_WR_NATFLAGCHECK_M 0x1 452 #define FW_FILTER2_WR_NATFLAGCHECK_V(x) ((x) << FW_FILTER2_WR_NATFLAGCHECK_S) 453 #define FW_FILTER2_WR_NATFLAGCHECK_G(x) \ 454 (((x) >> FW_FILTER2_WR_NATFLAGCHECK_S) & FW_FILTER2_WR_NATFLAGCHECK_M) 455 #define FW_FILTER2_WR_NATFLAGCHECK_F FW_FILTER2_WR_NATFLAGCHECK_V(1U) 456 457 #define FW_FILTER2_WR_ULP_TYPE_S 0 458 #define FW_FILTER2_WR_ULP_TYPE_M 0xf 459 #define FW_FILTER2_WR_ULP_TYPE_V(x) ((x) << FW_FILTER2_WR_ULP_TYPE_S) 460 #define FW_FILTER2_WR_ULP_TYPE_G(x) \ 461 (((x) >> FW_FILTER2_WR_ULP_TYPE_S) & FW_FILTER2_WR_ULP_TYPE_M) 462 463 #define FW_FILTER_WR_MACI_S 23 464 #define FW_FILTER_WR_MACI_M 0x1ff 465 #define FW_FILTER_WR_MACI_V(x) ((x) << FW_FILTER_WR_MACI_S) 466 #define FW_FILTER_WR_MACI_G(x) \ 467 (((x) >> FW_FILTER_WR_MACI_S) & FW_FILTER_WR_MACI_M) 468 469 #define FW_FILTER_WR_MACIM_S 14 470 #define FW_FILTER_WR_MACIM_M 0x1ff 471 #define FW_FILTER_WR_MACIM_V(x) ((x) << FW_FILTER_WR_MACIM_S) 472 #define FW_FILTER_WR_MACIM_G(x) \ 473 (((x) >> FW_FILTER_WR_MACIM_S) & FW_FILTER_WR_MACIM_M) 474 475 #define FW_FILTER_WR_FCOE_S 13 476 #define FW_FILTER_WR_FCOE_M 0x1 477 #define FW_FILTER_WR_FCOE_V(x) ((x) << FW_FILTER_WR_FCOE_S) 478 #define FW_FILTER_WR_FCOE_G(x) \ 479 (((x) >> FW_FILTER_WR_FCOE_S) & FW_FILTER_WR_FCOE_M) 480 #define FW_FILTER_WR_FCOE_F FW_FILTER_WR_FCOE_V(1U) 481 482 #define FW_FILTER_WR_FCOEM_S 12 483 #define FW_FILTER_WR_FCOEM_M 0x1 484 #define FW_FILTER_WR_FCOEM_V(x) ((x) << FW_FILTER_WR_FCOEM_S) 485 #define FW_FILTER_WR_FCOEM_G(x) \ 486 (((x) >> FW_FILTER_WR_FCOEM_S) & FW_FILTER_WR_FCOEM_M) 487 #define FW_FILTER_WR_FCOEM_F FW_FILTER_WR_FCOEM_V(1U) 488 489 #define FW_FILTER_WR_PORT_S 9 490 #define FW_FILTER_WR_PORT_M 0x7 491 #define FW_FILTER_WR_PORT_V(x) ((x) << FW_FILTER_WR_PORT_S) 492 #define FW_FILTER_WR_PORT_G(x) \ 493 (((x) >> FW_FILTER_WR_PORT_S) & FW_FILTER_WR_PORT_M) 494 495 #define FW_FILTER_WR_PORTM_S 6 496 #define FW_FILTER_WR_PORTM_M 0x7 497 #define FW_FILTER_WR_PORTM_V(x) ((x) << FW_FILTER_WR_PORTM_S) 498 #define FW_FILTER_WR_PORTM_G(x) \ 499 (((x) >> FW_FILTER_WR_PORTM_S) & FW_FILTER_WR_PORTM_M) 500 501 #define FW_FILTER_WR_MATCHTYPE_S 3 502 #define FW_FILTER_WR_MATCHTYPE_M 0x7 503 #define FW_FILTER_WR_MATCHTYPE_V(x) ((x) << FW_FILTER_WR_MATCHTYPE_S) 504 #define FW_FILTER_WR_MATCHTYPE_G(x) \ 505 (((x) >> FW_FILTER_WR_MATCHTYPE_S) & FW_FILTER_WR_MATCHTYPE_M) 506 507 #define FW_FILTER_WR_MATCHTYPEM_S 0 508 #define FW_FILTER_WR_MATCHTYPEM_M 0x7 509 #define FW_FILTER_WR_MATCHTYPEM_V(x) ((x) << FW_FILTER_WR_MATCHTYPEM_S) 510 #define FW_FILTER_WR_MATCHTYPEM_G(x) \ 511 (((x) >> FW_FILTER_WR_MATCHTYPEM_S) & FW_FILTER_WR_MATCHTYPEM_M) 512 513 struct fw_ulptx_wr { 514 __be32 op_to_compl; 515 __be32 flowid_len16; 516 u64 cookie; 517 }; 518 519 #define FW_ULPTX_WR_DATA_S 28 520 #define FW_ULPTX_WR_DATA_M 0x1 521 #define FW_ULPTX_WR_DATA_V(x) ((x) << FW_ULPTX_WR_DATA_S) 522 #define FW_ULPTX_WR_DATA_G(x) \ 523 (((x) >> FW_ULPTX_WR_DATA_S) & FW_ULPTX_WR_DATA_M) 524 #define FW_ULPTX_WR_DATA_F FW_ULPTX_WR_DATA_V(1U) 525 526 struct fw_tp_wr { 527 __be32 op_to_immdlen; 528 __be32 flowid_len16; 529 u64 cookie; 530 }; 531 532 struct fw_eth_tx_pkt_wr { 533 __be32 op_immdlen; 534 __be32 equiq_to_len16; 535 __be64 r3; 536 }; 537 538 enum fw_eth_tx_eo_type { 539 FW_ETH_TX_EO_TYPE_TCPSEG = 1, 540 }; 541 542 struct fw_eth_tx_eo_wr { 543 __be32 op_immdlen; 544 __be32 equiq_to_len16; 545 __be64 r3; 546 union fw_eth_tx_eo { 547 struct fw_eth_tx_eo_tcpseg { 548 __u8 type; 549 __u8 ethlen; 550 __be16 iplen; 551 __u8 tcplen; 552 __u8 tsclk_tsoff; 553 __be16 r4; 554 __be16 mss; 555 __be16 r5; 556 __be32 plen; 557 } tcpseg; 558 } u; 559 }; 560 561 #define FW_ETH_TX_EO_WR_IMMDLEN_S 0 562 #define FW_ETH_TX_EO_WR_IMMDLEN_M 0x1ff 563 #define FW_ETH_TX_EO_WR_IMMDLEN_V(x) ((x) << FW_ETH_TX_EO_WR_IMMDLEN_S) 564 #define FW_ETH_TX_EO_WR_IMMDLEN_G(x) \ 565 (((x) >> FW_ETH_TX_EO_WR_IMMDLEN_S) & FW_ETH_TX_EO_WR_IMMDLEN_M) 566 567 struct fw_ofld_connection_wr { 568 __be32 op_compl; 569 __be32 len16_pkd; 570 __u64 cookie; 571 __be64 r2; 572 __be64 r3; 573 struct fw_ofld_connection_le { 574 __be32 version_cpl; 575 __be32 filter; 576 __be32 r1; 577 __be16 lport; 578 __be16 pport; 579 union fw_ofld_connection_leip { 580 struct fw_ofld_connection_le_ipv4 { 581 __be32 pip; 582 __be32 lip; 583 __be64 r0; 584 __be64 r1; 585 __be64 r2; 586 } ipv4; 587 struct fw_ofld_connection_le_ipv6 { 588 __be64 pip_hi; 589 __be64 pip_lo; 590 __be64 lip_hi; 591 __be64 lip_lo; 592 } ipv6; 593 } u; 594 } le; 595 struct fw_ofld_connection_tcb { 596 __be32 t_state_to_astid; 597 __be16 cplrxdataack_cplpassacceptrpl; 598 __be16 rcv_adv; 599 __be32 rcv_nxt; 600 __be32 tx_max; 601 __be64 opt0; 602 __be32 opt2; 603 __be32 r1; 604 __be64 r2; 605 __be64 r3; 606 } tcb; 607 }; 608 609 #define FW_OFLD_CONNECTION_WR_VERSION_S 31 610 #define FW_OFLD_CONNECTION_WR_VERSION_M 0x1 611 #define FW_OFLD_CONNECTION_WR_VERSION_V(x) \ 612 ((x) << FW_OFLD_CONNECTION_WR_VERSION_S) 613 #define FW_OFLD_CONNECTION_WR_VERSION_G(x) \ 614 (((x) >> FW_OFLD_CONNECTION_WR_VERSION_S) & \ 615 FW_OFLD_CONNECTION_WR_VERSION_M) 616 #define FW_OFLD_CONNECTION_WR_VERSION_F \ 617 FW_OFLD_CONNECTION_WR_VERSION_V(1U) 618 619 #define FW_OFLD_CONNECTION_WR_CPL_S 30 620 #define FW_OFLD_CONNECTION_WR_CPL_M 0x1 621 #define FW_OFLD_CONNECTION_WR_CPL_V(x) ((x) << FW_OFLD_CONNECTION_WR_CPL_S) 622 #define FW_OFLD_CONNECTION_WR_CPL_G(x) \ 623 (((x) >> FW_OFLD_CONNECTION_WR_CPL_S) & FW_OFLD_CONNECTION_WR_CPL_M) 624 #define FW_OFLD_CONNECTION_WR_CPL_F FW_OFLD_CONNECTION_WR_CPL_V(1U) 625 626 #define FW_OFLD_CONNECTION_WR_T_STATE_S 28 627 #define FW_OFLD_CONNECTION_WR_T_STATE_M 0xf 628 #define FW_OFLD_CONNECTION_WR_T_STATE_V(x) \ 629 ((x) << FW_OFLD_CONNECTION_WR_T_STATE_S) 630 #define FW_OFLD_CONNECTION_WR_T_STATE_G(x) \ 631 (((x) >> FW_OFLD_CONNECTION_WR_T_STATE_S) & \ 632 FW_OFLD_CONNECTION_WR_T_STATE_M) 633 634 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_S 24 635 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_M 0xf 636 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_V(x) \ 637 ((x) << FW_OFLD_CONNECTION_WR_RCV_SCALE_S) 638 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_G(x) \ 639 (((x) >> FW_OFLD_CONNECTION_WR_RCV_SCALE_S) & \ 640 FW_OFLD_CONNECTION_WR_RCV_SCALE_M) 641 642 #define FW_OFLD_CONNECTION_WR_ASTID_S 0 643 #define FW_OFLD_CONNECTION_WR_ASTID_M 0xffffff 644 #define FW_OFLD_CONNECTION_WR_ASTID_V(x) \ 645 ((x) << FW_OFLD_CONNECTION_WR_ASTID_S) 646 #define FW_OFLD_CONNECTION_WR_ASTID_G(x) \ 647 (((x) >> FW_OFLD_CONNECTION_WR_ASTID_S) & FW_OFLD_CONNECTION_WR_ASTID_M) 648 649 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S 15 650 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_M 0x1 651 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_V(x) \ 652 ((x) << FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S) 653 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_G(x) \ 654 (((x) >> FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S) & \ 655 FW_OFLD_CONNECTION_WR_CPLRXDATAACK_M) 656 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_F \ 657 FW_OFLD_CONNECTION_WR_CPLRXDATAACK_V(1U) 658 659 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S 14 660 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_M 0x1 661 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_V(x) \ 662 ((x) << FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S) 663 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_G(x) \ 664 (((x) >> FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S) & \ 665 FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_M) 666 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_F \ 667 FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_V(1U) 668 669 enum fw_flowc_mnem_tcpstate { 670 FW_FLOWC_MNEM_TCPSTATE_CLOSED = 0, /* illegal */ 671 FW_FLOWC_MNEM_TCPSTATE_LISTEN = 1, /* illegal */ 672 FW_FLOWC_MNEM_TCPSTATE_SYNSENT = 2, /* illegal */ 673 FW_FLOWC_MNEM_TCPSTATE_SYNRECEIVED = 3, /* illegal */ 674 FW_FLOWC_MNEM_TCPSTATE_ESTABLISHED = 4, /* default */ 675 FW_FLOWC_MNEM_TCPSTATE_CLOSEWAIT = 5, /* got peer close already */ 676 FW_FLOWC_MNEM_TCPSTATE_FINWAIT1 = 6, /* haven't gotten ACK for FIN and 677 * will resend FIN - equiv ESTAB 678 */ 679 FW_FLOWC_MNEM_TCPSTATE_CLOSING = 7, /* haven't gotten ACK for FIN and 680 * will resend FIN but have 681 * received FIN 682 */ 683 FW_FLOWC_MNEM_TCPSTATE_LASTACK = 8, /* haven't gotten ACK for FIN and 684 * will resend FIN but have 685 * received FIN 686 */ 687 FW_FLOWC_MNEM_TCPSTATE_FINWAIT2 = 9, /* sent FIN and got FIN + ACK, 688 * waiting for FIN 689 */ 690 FW_FLOWC_MNEM_TCPSTATE_TIMEWAIT = 10, /* not expected */ 691 }; 692 693 enum fw_flowc_mnem_eostate { 694 FW_FLOWC_MNEM_EOSTATE_ESTABLISHED = 1, /* default */ 695 /* graceful close, after sending outstanding payload */ 696 FW_FLOWC_MNEM_EOSTATE_CLOSING = 2, 697 }; 698 699 enum fw_flowc_mnem { 700 FW_FLOWC_MNEM_PFNVFN, /* PFN [15:8] VFN [7:0] */ 701 FW_FLOWC_MNEM_CH, 702 FW_FLOWC_MNEM_PORT, 703 FW_FLOWC_MNEM_IQID, 704 FW_FLOWC_MNEM_SNDNXT, 705 FW_FLOWC_MNEM_RCVNXT, 706 FW_FLOWC_MNEM_SNDBUF, 707 FW_FLOWC_MNEM_MSS, 708 FW_FLOWC_MNEM_TXDATAPLEN_MAX, 709 FW_FLOWC_MNEM_TCPSTATE, 710 FW_FLOWC_MNEM_EOSTATE, 711 FW_FLOWC_MNEM_SCHEDCLASS, 712 FW_FLOWC_MNEM_DCBPRIO, 713 FW_FLOWC_MNEM_SND_SCALE, 714 FW_FLOWC_MNEM_RCV_SCALE, 715 FW_FLOWC_MNEM_ULD_MODE, 716 FW_FLOWC_MNEM_MAX, 717 }; 718 719 struct fw_flowc_mnemval { 720 u8 mnemonic; 721 u8 r4[3]; 722 __be32 val; 723 }; 724 725 struct fw_flowc_wr { 726 __be32 op_to_nparams; 727 __be32 flowid_len16; 728 struct fw_flowc_mnemval mnemval[0]; 729 }; 730 731 #define FW_FLOWC_WR_NPARAMS_S 0 732 #define FW_FLOWC_WR_NPARAMS_V(x) ((x) << FW_FLOWC_WR_NPARAMS_S) 733 734 struct fw_ofld_tx_data_wr { 735 __be32 op_to_immdlen; 736 __be32 flowid_len16; 737 __be32 plen; 738 __be32 tunnel_to_proxy; 739 }; 740 741 #define FW_OFLD_TX_DATA_WR_ALIGNPLD_S 30 742 #define FW_OFLD_TX_DATA_WR_ALIGNPLD_V(x) ((x) << FW_OFLD_TX_DATA_WR_ALIGNPLD_S) 743 #define FW_OFLD_TX_DATA_WR_ALIGNPLD_F FW_OFLD_TX_DATA_WR_ALIGNPLD_V(1U) 744 745 #define FW_OFLD_TX_DATA_WR_SHOVE_S 29 746 #define FW_OFLD_TX_DATA_WR_SHOVE_V(x) ((x) << FW_OFLD_TX_DATA_WR_SHOVE_S) 747 #define FW_OFLD_TX_DATA_WR_SHOVE_F FW_OFLD_TX_DATA_WR_SHOVE_V(1U) 748 749 #define FW_OFLD_TX_DATA_WR_TUNNEL_S 19 750 #define FW_OFLD_TX_DATA_WR_TUNNEL_V(x) ((x) << FW_OFLD_TX_DATA_WR_TUNNEL_S) 751 752 #define FW_OFLD_TX_DATA_WR_SAVE_S 18 753 #define FW_OFLD_TX_DATA_WR_SAVE_V(x) ((x) << FW_OFLD_TX_DATA_WR_SAVE_S) 754 755 #define FW_OFLD_TX_DATA_WR_FLUSH_S 17 756 #define FW_OFLD_TX_DATA_WR_FLUSH_V(x) ((x) << FW_OFLD_TX_DATA_WR_FLUSH_S) 757 #define FW_OFLD_TX_DATA_WR_FLUSH_F FW_OFLD_TX_DATA_WR_FLUSH_V(1U) 758 759 #define FW_OFLD_TX_DATA_WR_URGENT_S 16 760 #define FW_OFLD_TX_DATA_WR_URGENT_V(x) ((x) << FW_OFLD_TX_DATA_WR_URGENT_S) 761 762 #define FW_OFLD_TX_DATA_WR_MORE_S 15 763 #define FW_OFLD_TX_DATA_WR_MORE_V(x) ((x) << FW_OFLD_TX_DATA_WR_MORE_S) 764 765 #define FW_OFLD_TX_DATA_WR_ULPMODE_S 10 766 #define FW_OFLD_TX_DATA_WR_ULPMODE_V(x) ((x) << FW_OFLD_TX_DATA_WR_ULPMODE_S) 767 768 #define FW_OFLD_TX_DATA_WR_ULPSUBMODE_S 6 769 #define FW_OFLD_TX_DATA_WR_ULPSUBMODE_V(x) \ 770 ((x) << FW_OFLD_TX_DATA_WR_ULPSUBMODE_S) 771 772 struct fw_cmd_wr { 773 __be32 op_dma; 774 __be32 len16_pkd; 775 __be64 cookie_daddr; 776 }; 777 778 #define FW_CMD_WR_DMA_S 17 779 #define FW_CMD_WR_DMA_V(x) ((x) << FW_CMD_WR_DMA_S) 780 781 struct fw_eth_tx_pkt_vm_wr { 782 __be32 op_immdlen; 783 __be32 equiq_to_len16; 784 __be32 r3[2]; 785 u8 ethmacdst[6]; 786 u8 ethmacsrc[6]; 787 __be16 ethtype; 788 __be16 vlantci; 789 }; 790 791 #define FW_CMD_MAX_TIMEOUT 10000 792 793 /* 794 * If a host driver does a HELLO and discovers that there's already a MASTER 795 * selected, we may have to wait for that MASTER to finish issuing RESET, 796 * configuration and INITIALIZE commands. Also, there's a possibility that 797 * our own HELLO may get lost if it happens right as the MASTER is issuign a 798 * RESET command, so we need to be willing to make a few retries of our HELLO. 799 */ 800 #define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT) 801 #define FW_CMD_HELLO_RETRIES 3 802 803 804 enum fw_cmd_opcodes { 805 FW_LDST_CMD = 0x01, 806 FW_RESET_CMD = 0x03, 807 FW_HELLO_CMD = 0x04, 808 FW_BYE_CMD = 0x05, 809 FW_INITIALIZE_CMD = 0x06, 810 FW_CAPS_CONFIG_CMD = 0x07, 811 FW_PARAMS_CMD = 0x08, 812 FW_PFVF_CMD = 0x09, 813 FW_IQ_CMD = 0x10, 814 FW_EQ_MNGT_CMD = 0x11, 815 FW_EQ_ETH_CMD = 0x12, 816 FW_EQ_CTRL_CMD = 0x13, 817 FW_EQ_OFLD_CMD = 0x21, 818 FW_VI_CMD = 0x14, 819 FW_VI_MAC_CMD = 0x15, 820 FW_VI_RXMODE_CMD = 0x16, 821 FW_VI_ENABLE_CMD = 0x17, 822 FW_ACL_MAC_CMD = 0x18, 823 FW_ACL_VLAN_CMD = 0x19, 824 FW_VI_STATS_CMD = 0x1a, 825 FW_PORT_CMD = 0x1b, 826 FW_PORT_STATS_CMD = 0x1c, 827 FW_PORT_LB_STATS_CMD = 0x1d, 828 FW_PORT_TRACE_CMD = 0x1e, 829 FW_PORT_TRACE_MMAP_CMD = 0x1f, 830 FW_RSS_IND_TBL_CMD = 0x20, 831 FW_RSS_GLB_CONFIG_CMD = 0x22, 832 FW_RSS_VI_CONFIG_CMD = 0x23, 833 FW_SCHED_CMD = 0x24, 834 FW_DEVLOG_CMD = 0x25, 835 FW_CLIP_CMD = 0x28, 836 FW_PTP_CMD = 0x3e, 837 FW_HMA_CMD = 0x3f, 838 FW_LASTC2E_CMD = 0x40, 839 FW_ERROR_CMD = 0x80, 840 FW_DEBUG_CMD = 0x81, 841 }; 842 843 enum fw_cmd_cap { 844 FW_CMD_CAP_PF = 0x01, 845 FW_CMD_CAP_DMAQ = 0x02, 846 FW_CMD_CAP_PORT = 0x04, 847 FW_CMD_CAP_PORTPROMISC = 0x08, 848 FW_CMD_CAP_PORTSTATS = 0x10, 849 FW_CMD_CAP_VF = 0x80, 850 }; 851 852 /* 853 * Generic command header flit0 854 */ 855 struct fw_cmd_hdr { 856 __be32 hi; 857 __be32 lo; 858 }; 859 860 #define FW_CMD_OP_S 24 861 #define FW_CMD_OP_M 0xff 862 #define FW_CMD_OP_V(x) ((x) << FW_CMD_OP_S) 863 #define FW_CMD_OP_G(x) (((x) >> FW_CMD_OP_S) & FW_CMD_OP_M) 864 865 #define FW_CMD_REQUEST_S 23 866 #define FW_CMD_REQUEST_V(x) ((x) << FW_CMD_REQUEST_S) 867 #define FW_CMD_REQUEST_F FW_CMD_REQUEST_V(1U) 868 869 #define FW_CMD_READ_S 22 870 #define FW_CMD_READ_V(x) ((x) << FW_CMD_READ_S) 871 #define FW_CMD_READ_F FW_CMD_READ_V(1U) 872 873 #define FW_CMD_WRITE_S 21 874 #define FW_CMD_WRITE_V(x) ((x) << FW_CMD_WRITE_S) 875 #define FW_CMD_WRITE_F FW_CMD_WRITE_V(1U) 876 877 #define FW_CMD_EXEC_S 20 878 #define FW_CMD_EXEC_V(x) ((x) << FW_CMD_EXEC_S) 879 #define FW_CMD_EXEC_F FW_CMD_EXEC_V(1U) 880 881 #define FW_CMD_RAMASK_S 20 882 #define FW_CMD_RAMASK_V(x) ((x) << FW_CMD_RAMASK_S) 883 884 #define FW_CMD_RETVAL_S 8 885 #define FW_CMD_RETVAL_M 0xff 886 #define FW_CMD_RETVAL_V(x) ((x) << FW_CMD_RETVAL_S) 887 #define FW_CMD_RETVAL_G(x) (((x) >> FW_CMD_RETVAL_S) & FW_CMD_RETVAL_M) 888 889 #define FW_CMD_LEN16_S 0 890 #define FW_CMD_LEN16_V(x) ((x) << FW_CMD_LEN16_S) 891 892 #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16) 893 894 enum fw_ldst_addrspc { 895 FW_LDST_ADDRSPC_FIRMWARE = 0x0001, 896 FW_LDST_ADDRSPC_SGE_EGRC = 0x0008, 897 FW_LDST_ADDRSPC_SGE_INGC = 0x0009, 898 FW_LDST_ADDRSPC_SGE_FLMC = 0x000a, 899 FW_LDST_ADDRSPC_SGE_CONMC = 0x000b, 900 FW_LDST_ADDRSPC_TP_PIO = 0x0010, 901 FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011, 902 FW_LDST_ADDRSPC_TP_MIB = 0x0012, 903 FW_LDST_ADDRSPC_MDIO = 0x0018, 904 FW_LDST_ADDRSPC_MPS = 0x0020, 905 FW_LDST_ADDRSPC_FUNC = 0x0028, 906 FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029, 907 FW_LDST_ADDRSPC_I2C = 0x0038, 908 }; 909 910 enum fw_ldst_mps_fid { 911 FW_LDST_MPS_ATRB, 912 FW_LDST_MPS_RPLC 913 }; 914 915 enum fw_ldst_func_access_ctl { 916 FW_LDST_FUNC_ACC_CTL_VIID, 917 FW_LDST_FUNC_ACC_CTL_FID 918 }; 919 920 enum fw_ldst_func_mod_index { 921 FW_LDST_FUNC_MPS 922 }; 923 924 struct fw_ldst_cmd { 925 __be32 op_to_addrspace; 926 __be32 cycles_to_len16; 927 union fw_ldst { 928 struct fw_ldst_addrval { 929 __be32 addr; 930 __be32 val; 931 } addrval; 932 struct fw_ldst_idctxt { 933 __be32 physid; 934 __be32 msg_ctxtflush; 935 __be32 ctxt_data7; 936 __be32 ctxt_data6; 937 __be32 ctxt_data5; 938 __be32 ctxt_data4; 939 __be32 ctxt_data3; 940 __be32 ctxt_data2; 941 __be32 ctxt_data1; 942 __be32 ctxt_data0; 943 } idctxt; 944 struct fw_ldst_mdio { 945 __be16 paddr_mmd; 946 __be16 raddr; 947 __be16 vctl; 948 __be16 rval; 949 } mdio; 950 struct fw_ldst_cim_rq { 951 u8 req_first64[8]; 952 u8 req_second64[8]; 953 u8 resp_first64[8]; 954 u8 resp_second64[8]; 955 __be32 r3[2]; 956 } cim_rq; 957 union fw_ldst_mps { 958 struct fw_ldst_mps_rplc { 959 __be16 fid_idx; 960 __be16 rplcpf_pkd; 961 __be32 rplc255_224; 962 __be32 rplc223_192; 963 __be32 rplc191_160; 964 __be32 rplc159_128; 965 __be32 rplc127_96; 966 __be32 rplc95_64; 967 __be32 rplc63_32; 968 __be32 rplc31_0; 969 } rplc; 970 struct fw_ldst_mps_atrb { 971 __be16 fid_mpsid; 972 __be16 r2[3]; 973 __be32 r3[2]; 974 __be32 r4; 975 __be32 atrb; 976 __be16 vlan[16]; 977 } atrb; 978 } mps; 979 struct fw_ldst_func { 980 u8 access_ctl; 981 u8 mod_index; 982 __be16 ctl_id; 983 __be32 offset; 984 __be64 data0; 985 __be64 data1; 986 } func; 987 struct fw_ldst_pcie { 988 u8 ctrl_to_fn; 989 u8 bnum; 990 u8 r; 991 u8 ext_r; 992 u8 select_naccess; 993 u8 pcie_fn; 994 __be16 nset_pkd; 995 __be32 data[12]; 996 } pcie; 997 struct fw_ldst_i2c_deprecated { 998 u8 pid_pkd; 999 u8 base; 1000 u8 boffset; 1001 u8 data; 1002 __be32 r9; 1003 } i2c_deprecated; 1004 struct fw_ldst_i2c { 1005 u8 pid; 1006 u8 did; 1007 u8 boffset; 1008 u8 blen; 1009 __be32 r9; 1010 __u8 data[48]; 1011 } i2c; 1012 struct fw_ldst_le { 1013 __be32 index; 1014 __be32 r9; 1015 u8 val[33]; 1016 u8 r11[7]; 1017 } le; 1018 } u; 1019 }; 1020 1021 #define FW_LDST_CMD_ADDRSPACE_S 0 1022 #define FW_LDST_CMD_ADDRSPACE_V(x) ((x) << FW_LDST_CMD_ADDRSPACE_S) 1023 1024 #define FW_LDST_CMD_MSG_S 31 1025 #define FW_LDST_CMD_MSG_V(x) ((x) << FW_LDST_CMD_MSG_S) 1026 1027 #define FW_LDST_CMD_CTXTFLUSH_S 30 1028 #define FW_LDST_CMD_CTXTFLUSH_V(x) ((x) << FW_LDST_CMD_CTXTFLUSH_S) 1029 #define FW_LDST_CMD_CTXTFLUSH_F FW_LDST_CMD_CTXTFLUSH_V(1U) 1030 1031 #define FW_LDST_CMD_PADDR_S 8 1032 #define FW_LDST_CMD_PADDR_V(x) ((x) << FW_LDST_CMD_PADDR_S) 1033 1034 #define FW_LDST_CMD_MMD_S 0 1035 #define FW_LDST_CMD_MMD_V(x) ((x) << FW_LDST_CMD_MMD_S) 1036 1037 #define FW_LDST_CMD_FID_S 15 1038 #define FW_LDST_CMD_FID_V(x) ((x) << FW_LDST_CMD_FID_S) 1039 1040 #define FW_LDST_CMD_IDX_S 0 1041 #define FW_LDST_CMD_IDX_V(x) ((x) << FW_LDST_CMD_IDX_S) 1042 1043 #define FW_LDST_CMD_RPLCPF_S 0 1044 #define FW_LDST_CMD_RPLCPF_V(x) ((x) << FW_LDST_CMD_RPLCPF_S) 1045 1046 #define FW_LDST_CMD_LC_S 4 1047 #define FW_LDST_CMD_LC_V(x) ((x) << FW_LDST_CMD_LC_S) 1048 #define FW_LDST_CMD_LC_F FW_LDST_CMD_LC_V(1U) 1049 1050 #define FW_LDST_CMD_FN_S 0 1051 #define FW_LDST_CMD_FN_V(x) ((x) << FW_LDST_CMD_FN_S) 1052 1053 #define FW_LDST_CMD_NACCESS_S 0 1054 #define FW_LDST_CMD_NACCESS_V(x) ((x) << FW_LDST_CMD_NACCESS_S) 1055 1056 struct fw_reset_cmd { 1057 __be32 op_to_write; 1058 __be32 retval_len16; 1059 __be32 val; 1060 __be32 halt_pkd; 1061 }; 1062 1063 #define FW_RESET_CMD_HALT_S 31 1064 #define FW_RESET_CMD_HALT_M 0x1 1065 #define FW_RESET_CMD_HALT_V(x) ((x) << FW_RESET_CMD_HALT_S) 1066 #define FW_RESET_CMD_HALT_G(x) \ 1067 (((x) >> FW_RESET_CMD_HALT_S) & FW_RESET_CMD_HALT_M) 1068 #define FW_RESET_CMD_HALT_F FW_RESET_CMD_HALT_V(1U) 1069 1070 enum fw_hellow_cmd { 1071 fw_hello_cmd_stage_os = 0x0 1072 }; 1073 1074 struct fw_hello_cmd { 1075 __be32 op_to_write; 1076 __be32 retval_len16; 1077 __be32 err_to_clearinit; 1078 __be32 fwrev; 1079 }; 1080 1081 #define FW_HELLO_CMD_ERR_S 31 1082 #define FW_HELLO_CMD_ERR_V(x) ((x) << FW_HELLO_CMD_ERR_S) 1083 #define FW_HELLO_CMD_ERR_F FW_HELLO_CMD_ERR_V(1U) 1084 1085 #define FW_HELLO_CMD_INIT_S 30 1086 #define FW_HELLO_CMD_INIT_V(x) ((x) << FW_HELLO_CMD_INIT_S) 1087 #define FW_HELLO_CMD_INIT_F FW_HELLO_CMD_INIT_V(1U) 1088 1089 #define FW_HELLO_CMD_MASTERDIS_S 29 1090 #define FW_HELLO_CMD_MASTERDIS_V(x) ((x) << FW_HELLO_CMD_MASTERDIS_S) 1091 1092 #define FW_HELLO_CMD_MASTERFORCE_S 28 1093 #define FW_HELLO_CMD_MASTERFORCE_V(x) ((x) << FW_HELLO_CMD_MASTERFORCE_S) 1094 1095 #define FW_HELLO_CMD_MBMASTER_S 24 1096 #define FW_HELLO_CMD_MBMASTER_M 0xfU 1097 #define FW_HELLO_CMD_MBMASTER_V(x) ((x) << FW_HELLO_CMD_MBMASTER_S) 1098 #define FW_HELLO_CMD_MBMASTER_G(x) \ 1099 (((x) >> FW_HELLO_CMD_MBMASTER_S) & FW_HELLO_CMD_MBMASTER_M) 1100 1101 #define FW_HELLO_CMD_MBASYNCNOTINT_S 23 1102 #define FW_HELLO_CMD_MBASYNCNOTINT_V(x) ((x) << FW_HELLO_CMD_MBASYNCNOTINT_S) 1103 1104 #define FW_HELLO_CMD_MBASYNCNOT_S 20 1105 #define FW_HELLO_CMD_MBASYNCNOT_V(x) ((x) << FW_HELLO_CMD_MBASYNCNOT_S) 1106 1107 #define FW_HELLO_CMD_STAGE_S 17 1108 #define FW_HELLO_CMD_STAGE_V(x) ((x) << FW_HELLO_CMD_STAGE_S) 1109 1110 #define FW_HELLO_CMD_CLEARINIT_S 16 1111 #define FW_HELLO_CMD_CLEARINIT_V(x) ((x) << FW_HELLO_CMD_CLEARINIT_S) 1112 #define FW_HELLO_CMD_CLEARINIT_F FW_HELLO_CMD_CLEARINIT_V(1U) 1113 1114 struct fw_bye_cmd { 1115 __be32 op_to_write; 1116 __be32 retval_len16; 1117 __be64 r3; 1118 }; 1119 1120 struct fw_initialize_cmd { 1121 __be32 op_to_write; 1122 __be32 retval_len16; 1123 __be64 r3; 1124 }; 1125 1126 enum fw_caps_config_hm { 1127 FW_CAPS_CONFIG_HM_PCIE = 0x00000001, 1128 FW_CAPS_CONFIG_HM_PL = 0x00000002, 1129 FW_CAPS_CONFIG_HM_SGE = 0x00000004, 1130 FW_CAPS_CONFIG_HM_CIM = 0x00000008, 1131 FW_CAPS_CONFIG_HM_ULPTX = 0x00000010, 1132 FW_CAPS_CONFIG_HM_TP = 0x00000020, 1133 FW_CAPS_CONFIG_HM_ULPRX = 0x00000040, 1134 FW_CAPS_CONFIG_HM_PMRX = 0x00000080, 1135 FW_CAPS_CONFIG_HM_PMTX = 0x00000100, 1136 FW_CAPS_CONFIG_HM_MC = 0x00000200, 1137 FW_CAPS_CONFIG_HM_LE = 0x00000400, 1138 FW_CAPS_CONFIG_HM_MPS = 0x00000800, 1139 FW_CAPS_CONFIG_HM_XGMAC = 0x00001000, 1140 FW_CAPS_CONFIG_HM_CPLSWITCH = 0x00002000, 1141 FW_CAPS_CONFIG_HM_T4DBG = 0x00004000, 1142 FW_CAPS_CONFIG_HM_MI = 0x00008000, 1143 FW_CAPS_CONFIG_HM_I2CM = 0x00010000, 1144 FW_CAPS_CONFIG_HM_NCSI = 0x00020000, 1145 FW_CAPS_CONFIG_HM_SMB = 0x00040000, 1146 FW_CAPS_CONFIG_HM_MA = 0x00080000, 1147 FW_CAPS_CONFIG_HM_EDRAM = 0x00100000, 1148 FW_CAPS_CONFIG_HM_PMU = 0x00200000, 1149 FW_CAPS_CONFIG_HM_UART = 0x00400000, 1150 FW_CAPS_CONFIG_HM_SF = 0x00800000, 1151 }; 1152 1153 enum fw_caps_config_nbm { 1154 FW_CAPS_CONFIG_NBM_IPMI = 0x00000001, 1155 FW_CAPS_CONFIG_NBM_NCSI = 0x00000002, 1156 }; 1157 1158 enum fw_caps_config_link { 1159 FW_CAPS_CONFIG_LINK_PPP = 0x00000001, 1160 FW_CAPS_CONFIG_LINK_QFC = 0x00000002, 1161 FW_CAPS_CONFIG_LINK_DCBX = 0x00000004, 1162 }; 1163 1164 enum fw_caps_config_switch { 1165 FW_CAPS_CONFIG_SWITCH_INGRESS = 0x00000001, 1166 FW_CAPS_CONFIG_SWITCH_EGRESS = 0x00000002, 1167 }; 1168 1169 enum fw_caps_config_nic { 1170 FW_CAPS_CONFIG_NIC = 0x00000001, 1171 FW_CAPS_CONFIG_NIC_VM = 0x00000002, 1172 FW_CAPS_CONFIG_NIC_HASHFILTER = 0x00000020, 1173 FW_CAPS_CONFIG_NIC_ETHOFLD = 0x00000040, 1174 }; 1175 1176 enum fw_caps_config_ofld { 1177 FW_CAPS_CONFIG_OFLD = 0x00000001, 1178 }; 1179 1180 enum fw_caps_config_rdma { 1181 FW_CAPS_CONFIG_RDMA_RDDP = 0x00000001, 1182 FW_CAPS_CONFIG_RDMA_RDMAC = 0x00000002, 1183 }; 1184 1185 enum fw_caps_config_iscsi { 1186 FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU = 0x00000001, 1187 FW_CAPS_CONFIG_ISCSI_TARGET_PDU = 0x00000002, 1188 FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD = 0x00000004, 1189 FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008, 1190 }; 1191 1192 enum fw_caps_config_crypto { 1193 FW_CAPS_CONFIG_CRYPTO_LOOKASIDE = 0x00000001, 1194 FW_CAPS_CONFIG_TLS_INLINE = 0x00000002, 1195 FW_CAPS_CONFIG_IPSEC_INLINE = 0x00000004, 1196 }; 1197 1198 enum fw_caps_config_fcoe { 1199 FW_CAPS_CONFIG_FCOE_INITIATOR = 0x00000001, 1200 FW_CAPS_CONFIG_FCOE_TARGET = 0x00000002, 1201 FW_CAPS_CONFIG_FCOE_CTRL_OFLD = 0x00000004, 1202 }; 1203 1204 enum fw_memtype_cf { 1205 FW_MEMTYPE_CF_EDC0 = 0x0, 1206 FW_MEMTYPE_CF_EDC1 = 0x1, 1207 FW_MEMTYPE_CF_EXTMEM = 0x2, 1208 FW_MEMTYPE_CF_FLASH = 0x4, 1209 FW_MEMTYPE_CF_INTERNAL = 0x5, 1210 FW_MEMTYPE_CF_EXTMEM1 = 0x6, 1211 FW_MEMTYPE_CF_HMA = 0x7, 1212 }; 1213 1214 struct fw_caps_config_cmd { 1215 __be32 op_to_write; 1216 __be32 cfvalid_to_len16; 1217 __be32 r2; 1218 __be32 hwmbitmap; 1219 __be16 nbmcaps; 1220 __be16 linkcaps; 1221 __be16 switchcaps; 1222 __be16 r3; 1223 __be16 niccaps; 1224 __be16 ofldcaps; 1225 __be16 rdmacaps; 1226 __be16 cryptocaps; 1227 __be16 iscsicaps; 1228 __be16 fcoecaps; 1229 __be32 cfcsum; 1230 __be32 finiver; 1231 __be32 finicsum; 1232 }; 1233 1234 #define FW_CAPS_CONFIG_CMD_CFVALID_S 27 1235 #define FW_CAPS_CONFIG_CMD_CFVALID_V(x) ((x) << FW_CAPS_CONFIG_CMD_CFVALID_S) 1236 #define FW_CAPS_CONFIG_CMD_CFVALID_F FW_CAPS_CONFIG_CMD_CFVALID_V(1U) 1237 1238 #define FW_CAPS_CONFIG_CMD_MEMTYPE_CF_S 24 1239 #define FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(x) \ 1240 ((x) << FW_CAPS_CONFIG_CMD_MEMTYPE_CF_S) 1241 1242 #define FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_S 16 1243 #define FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(x) \ 1244 ((x) << FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_S) 1245 1246 /* 1247 * params command mnemonics 1248 */ 1249 enum fw_params_mnem { 1250 FW_PARAMS_MNEM_DEV = 1, /* device params */ 1251 FW_PARAMS_MNEM_PFVF = 2, /* function params */ 1252 FW_PARAMS_MNEM_REG = 3, /* limited register access */ 1253 FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */ 1254 FW_PARAMS_MNEM_CHNET = 5, /* chnet params */ 1255 FW_PARAMS_MNEM_LAST 1256 }; 1257 1258 /* 1259 * device parameters 1260 */ 1261 1262 #define FW_PARAMS_PARAM_FILTER_MODE_S 16 1263 #define FW_PARAMS_PARAM_FILTER_MODE_M 0xffff 1264 #define FW_PARAMS_PARAM_FILTER_MODE_V(x) \ 1265 ((x) << FW_PARAMS_PARAM_FILTER_MODE_S) 1266 #define FW_PARAMS_PARAM_FILTER_MODE_G(x) \ 1267 (((x) >> FW_PARAMS_PARAM_FILTER_MODE_S) & \ 1268 FW_PARAMS_PARAM_FILTER_MODE_M) 1269 1270 #define FW_PARAMS_PARAM_FILTER_MASK_S 0 1271 #define FW_PARAMS_PARAM_FILTER_MASK_M 0xffff 1272 #define FW_PARAMS_PARAM_FILTER_MASK_V(x) \ 1273 ((x) << FW_PARAMS_PARAM_FILTER_MASK_S) 1274 #define FW_PARAMS_PARAM_FILTER_MASK_G(x) \ 1275 (((x) >> FW_PARAMS_PARAM_FILTER_MASK_S) & \ 1276 FW_PARAMS_PARAM_FILTER_MASK_M) 1277 1278 enum fw_params_param_dev { 1279 FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */ 1280 FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */ 1281 FW_PARAMS_PARAM_DEV_NTID = 0x02, /* reads the number of TIDs 1282 * allocated by the device's 1283 * Lookup Engine 1284 */ 1285 FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03, 1286 FW_PARAMS_PARAM_DEV_INTVER_NIC = 0x04, 1287 FW_PARAMS_PARAM_DEV_INTVER_VNIC = 0x05, 1288 FW_PARAMS_PARAM_DEV_INTVER_OFLD = 0x06, 1289 FW_PARAMS_PARAM_DEV_INTVER_RI = 0x07, 1290 FW_PARAMS_PARAM_DEV_INTVER_ISCSIPDU = 0x08, 1291 FW_PARAMS_PARAM_DEV_INTVER_ISCSI = 0x09, 1292 FW_PARAMS_PARAM_DEV_INTVER_FCOE = 0x0A, 1293 FW_PARAMS_PARAM_DEV_FWREV = 0x0B, 1294 FW_PARAMS_PARAM_DEV_TPREV = 0x0C, 1295 FW_PARAMS_PARAM_DEV_CF = 0x0D, 1296 FW_PARAMS_PARAM_DEV_PHYFW = 0x0F, 1297 FW_PARAMS_PARAM_DEV_DIAG = 0x11, 1298 FW_PARAMS_PARAM_DEV_MAXORDIRD_QP = 0x13, /* max supported QP IRD/ORD */ 1299 FW_PARAMS_PARAM_DEV_MAXIRD_ADAPTER = 0x14, /* max supported adap IRD */ 1300 FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17, 1301 FW_PARAMS_PARAM_DEV_FWCACHE = 0x18, 1302 FW_PARAMS_PARAM_DEV_SCFGREV = 0x1A, 1303 FW_PARAMS_PARAM_DEV_VPDREV = 0x1B, 1304 FW_PARAMS_PARAM_DEV_RI_FR_NSMR_TPTE_WR = 0x1C, 1305 FW_PARAMS_PARAM_DEV_FILTER2_WR = 0x1D, 1306 FW_PARAMS_PARAM_DEV_MPSBGMAP = 0x1E, 1307 FW_PARAMS_PARAM_DEV_TPCHMAP = 0x1F, 1308 FW_PARAMS_PARAM_DEV_HMA_SIZE = 0x20, 1309 FW_PARAMS_PARAM_DEV_RDMA_WRITE_WITH_IMM = 0x21, 1310 FW_PARAMS_PARAM_DEV_PPOD_EDRAM = 0x23, 1311 FW_PARAMS_PARAM_DEV_RI_WRITE_CMPL_WR = 0x24, 1312 FW_PARAMS_PARAM_DEV_OPAQUE_VIID_SMT_EXTN = 0x27, 1313 FW_PARAMS_PARAM_DEV_HASHFILTER_WITH_OFLD = 0x28, 1314 FW_PARAMS_PARAM_DEV_DBQ_TIMER = 0x29, 1315 FW_PARAMS_PARAM_DEV_DBQ_TIMERTICK = 0x2A, 1316 FW_PARAMS_PARAM_DEV_NUM_TM_CLASS = 0x2B, 1317 FW_PARAMS_PARAM_DEV_FILTER = 0x2E, 1318 }; 1319 1320 /* 1321 * physical and virtual function parameters 1322 */ 1323 enum fw_params_param_pfvf { 1324 FW_PARAMS_PARAM_PFVF_RWXCAPS = 0x00, 1325 FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01, 1326 FW_PARAMS_PARAM_PFVF_ROUTE_END = 0x02, 1327 FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03, 1328 FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04, 1329 FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05, 1330 FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06, 1331 FW_PARAMS_PARAM_PFVF_SERVER_START = 0x07, 1332 FW_PARAMS_PARAM_PFVF_SERVER_END = 0x08, 1333 FW_PARAMS_PARAM_PFVF_TDDP_START = 0x09, 1334 FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A, 1335 FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B, 1336 FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C, 1337 FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D, 1338 FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E, 1339 FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F, 1340 FW_PARAMS_PARAM_PFVF_RQ_END = 0x10, 1341 FW_PARAMS_PARAM_PFVF_PBL_START = 0x11, 1342 FW_PARAMS_PARAM_PFVF_PBL_END = 0x12, 1343 FW_PARAMS_PARAM_PFVF_L2T_START = 0x13, 1344 FW_PARAMS_PARAM_PFVF_L2T_END = 0x14, 1345 FW_PARAMS_PARAM_PFVF_SQRQ_START = 0x15, 1346 FW_PARAMS_PARAM_PFVF_SQRQ_END = 0x16, 1347 FW_PARAMS_PARAM_PFVF_CQ_START = 0x17, 1348 FW_PARAMS_PARAM_PFVF_CQ_END = 0x18, 1349 FW_PARAMS_PARAM_PFVF_SRQ_START = 0x19, 1350 FW_PARAMS_PARAM_PFVF_SRQ_END = 0x1A, 1351 FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20, 1352 FW_PARAMS_PARAM_PFVF_VIID = 0x24, 1353 FW_PARAMS_PARAM_PFVF_CPMASK = 0x25, 1354 FW_PARAMS_PARAM_PFVF_OCQ_START = 0x26, 1355 FW_PARAMS_PARAM_PFVF_OCQ_END = 0x27, 1356 FW_PARAMS_PARAM_PFVF_CONM_MAP = 0x28, 1357 FW_PARAMS_PARAM_PFVF_IQFLINT_START = 0x29, 1358 FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A, 1359 FW_PARAMS_PARAM_PFVF_EQ_START = 0x2B, 1360 FW_PARAMS_PARAM_PFVF_EQ_END = 0x2C, 1361 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D, 1362 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E, 1363 FW_PARAMS_PARAM_PFVF_ETHOFLD_START = 0x2F, 1364 FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30, 1365 FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31, 1366 FW_PARAMS_PARAM_PFVF_HPFILTER_START = 0x32, 1367 FW_PARAMS_PARAM_PFVF_HPFILTER_END = 0x33, 1368 FW_PARAMS_PARAM_PFVF_TLS_START = 0x34, 1369 FW_PARAMS_PARAM_PFVF_TLS_END = 0x35, 1370 FW_PARAMS_PARAM_PFVF_RAWF_START = 0x36, 1371 FW_PARAMS_PARAM_PFVF_RAWF_END = 0x37, 1372 FW_PARAMS_PARAM_PFVF_NCRYPTO_LOOKASIDE = 0x39, 1373 FW_PARAMS_PARAM_PFVF_PORT_CAPS32 = 0x3A, 1374 FW_PARAMS_PARAM_PFVF_PPOD_EDRAM_START = 0x3B, 1375 FW_PARAMS_PARAM_PFVF_PPOD_EDRAM_END = 0x3C, 1376 FW_PARAMS_PARAM_PFVF_LINK_STATE = 0x40, 1377 }; 1378 1379 /* Virtual link state as seen by the specified VF */ 1380 enum vf_link_states { 1381 FW_VF_LINK_STATE_AUTO = 0x00, 1382 FW_VF_LINK_STATE_ENABLE = 0x01, 1383 FW_VF_LINK_STATE_DISABLE = 0x02, 1384 }; 1385 1386 /* 1387 * dma queue parameters 1388 */ 1389 enum fw_params_param_dmaq { 1390 FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00, 1391 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01, 1392 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10, 1393 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11, 1394 FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12, 1395 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13, 1396 FW_PARAMS_PARAM_DMAQ_EQ_TIMERIX = 0x15, 1397 FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20, 1398 }; 1399 1400 enum fw_params_param_dev_phyfw { 1401 FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD = 0x00, 1402 FW_PARAMS_PARAM_DEV_PHYFW_VERSION = 0x01, 1403 }; 1404 1405 enum fw_params_param_dev_diag { 1406 FW_PARAM_DEV_DIAG_TMP = 0x00, 1407 FW_PARAM_DEV_DIAG_VDD = 0x01, 1408 FW_PARAM_DEV_DIAG_MAXTMPTHRESH = 0x02, 1409 }; 1410 1411 enum fw_params_param_dev_filter { 1412 FW_PARAM_DEV_FILTER_VNIC_MODE = 0x00, 1413 FW_PARAM_DEV_FILTER_MODE_MASK = 0x01, 1414 }; 1415 1416 enum fw_params_param_dev_fwcache { 1417 FW_PARAM_DEV_FWCACHE_FLUSH = 0x00, 1418 FW_PARAM_DEV_FWCACHE_FLUSHINV = 0x01, 1419 }; 1420 1421 #define FW_PARAMS_MNEM_S 24 1422 #define FW_PARAMS_MNEM_V(x) ((x) << FW_PARAMS_MNEM_S) 1423 1424 #define FW_PARAMS_PARAM_X_S 16 1425 #define FW_PARAMS_PARAM_X_V(x) ((x) << FW_PARAMS_PARAM_X_S) 1426 1427 #define FW_PARAMS_PARAM_Y_S 8 1428 #define FW_PARAMS_PARAM_Y_M 0xffU 1429 #define FW_PARAMS_PARAM_Y_V(x) ((x) << FW_PARAMS_PARAM_Y_S) 1430 #define FW_PARAMS_PARAM_Y_G(x) (((x) >> FW_PARAMS_PARAM_Y_S) &\ 1431 FW_PARAMS_PARAM_Y_M) 1432 1433 #define FW_PARAMS_PARAM_Z_S 0 1434 #define FW_PARAMS_PARAM_Z_M 0xffu 1435 #define FW_PARAMS_PARAM_Z_V(x) ((x) << FW_PARAMS_PARAM_Z_S) 1436 #define FW_PARAMS_PARAM_Z_G(x) (((x) >> FW_PARAMS_PARAM_Z_S) &\ 1437 FW_PARAMS_PARAM_Z_M) 1438 1439 #define FW_PARAMS_PARAM_XYZ_S 0 1440 #define FW_PARAMS_PARAM_XYZ_V(x) ((x) << FW_PARAMS_PARAM_XYZ_S) 1441 1442 #define FW_PARAMS_PARAM_YZ_S 0 1443 #define FW_PARAMS_PARAM_YZ_V(x) ((x) << FW_PARAMS_PARAM_YZ_S) 1444 1445 struct fw_params_cmd { 1446 __be32 op_to_vfn; 1447 __be32 retval_len16; 1448 struct fw_params_param { 1449 __be32 mnem; 1450 __be32 val; 1451 } param[7]; 1452 }; 1453 1454 #define FW_PARAMS_CMD_PFN_S 8 1455 #define FW_PARAMS_CMD_PFN_V(x) ((x) << FW_PARAMS_CMD_PFN_S) 1456 1457 #define FW_PARAMS_CMD_VFN_S 0 1458 #define FW_PARAMS_CMD_VFN_V(x) ((x) << FW_PARAMS_CMD_VFN_S) 1459 1460 struct fw_pfvf_cmd { 1461 __be32 op_to_vfn; 1462 __be32 retval_len16; 1463 __be32 niqflint_niq; 1464 __be32 type_to_neq; 1465 __be32 tc_to_nexactf; 1466 __be32 r_caps_to_nethctrl; 1467 __be16 nricq; 1468 __be16 nriqp; 1469 __be32 r4; 1470 }; 1471 1472 #define FW_PFVF_CMD_PFN_S 8 1473 #define FW_PFVF_CMD_PFN_V(x) ((x) << FW_PFVF_CMD_PFN_S) 1474 1475 #define FW_PFVF_CMD_VFN_S 0 1476 #define FW_PFVF_CMD_VFN_V(x) ((x) << FW_PFVF_CMD_VFN_S) 1477 1478 #define FW_PFVF_CMD_NIQFLINT_S 20 1479 #define FW_PFVF_CMD_NIQFLINT_M 0xfff 1480 #define FW_PFVF_CMD_NIQFLINT_V(x) ((x) << FW_PFVF_CMD_NIQFLINT_S) 1481 #define FW_PFVF_CMD_NIQFLINT_G(x) \ 1482 (((x) >> FW_PFVF_CMD_NIQFLINT_S) & FW_PFVF_CMD_NIQFLINT_M) 1483 1484 #define FW_PFVF_CMD_NIQ_S 0 1485 #define FW_PFVF_CMD_NIQ_M 0xfffff 1486 #define FW_PFVF_CMD_NIQ_V(x) ((x) << FW_PFVF_CMD_NIQ_S) 1487 #define FW_PFVF_CMD_NIQ_G(x) \ 1488 (((x) >> FW_PFVF_CMD_NIQ_S) & FW_PFVF_CMD_NIQ_M) 1489 1490 #define FW_PFVF_CMD_TYPE_S 31 1491 #define FW_PFVF_CMD_TYPE_M 0x1 1492 #define FW_PFVF_CMD_TYPE_V(x) ((x) << FW_PFVF_CMD_TYPE_S) 1493 #define FW_PFVF_CMD_TYPE_G(x) \ 1494 (((x) >> FW_PFVF_CMD_TYPE_S) & FW_PFVF_CMD_TYPE_M) 1495 #define FW_PFVF_CMD_TYPE_F FW_PFVF_CMD_TYPE_V(1U) 1496 1497 #define FW_PFVF_CMD_CMASK_S 24 1498 #define FW_PFVF_CMD_CMASK_M 0xf 1499 #define FW_PFVF_CMD_CMASK_V(x) ((x) << FW_PFVF_CMD_CMASK_S) 1500 #define FW_PFVF_CMD_CMASK_G(x) \ 1501 (((x) >> FW_PFVF_CMD_CMASK_S) & FW_PFVF_CMD_CMASK_M) 1502 1503 #define FW_PFVF_CMD_PMASK_S 20 1504 #define FW_PFVF_CMD_PMASK_M 0xf 1505 #define FW_PFVF_CMD_PMASK_V(x) ((x) << FW_PFVF_CMD_PMASK_S) 1506 #define FW_PFVF_CMD_PMASK_G(x) \ 1507 (((x) >> FW_PFVF_CMD_PMASK_S) & FW_PFVF_CMD_PMASK_M) 1508 1509 #define FW_PFVF_CMD_NEQ_S 0 1510 #define FW_PFVF_CMD_NEQ_M 0xfffff 1511 #define FW_PFVF_CMD_NEQ_V(x) ((x) << FW_PFVF_CMD_NEQ_S) 1512 #define FW_PFVF_CMD_NEQ_G(x) \ 1513 (((x) >> FW_PFVF_CMD_NEQ_S) & FW_PFVF_CMD_NEQ_M) 1514 1515 #define FW_PFVF_CMD_TC_S 24 1516 #define FW_PFVF_CMD_TC_M 0xff 1517 #define FW_PFVF_CMD_TC_V(x) ((x) << FW_PFVF_CMD_TC_S) 1518 #define FW_PFVF_CMD_TC_G(x) (((x) >> FW_PFVF_CMD_TC_S) & FW_PFVF_CMD_TC_M) 1519 1520 #define FW_PFVF_CMD_NVI_S 16 1521 #define FW_PFVF_CMD_NVI_M 0xff 1522 #define FW_PFVF_CMD_NVI_V(x) ((x) << FW_PFVF_CMD_NVI_S) 1523 #define FW_PFVF_CMD_NVI_G(x) (((x) >> FW_PFVF_CMD_NVI_S) & FW_PFVF_CMD_NVI_M) 1524 1525 #define FW_PFVF_CMD_NEXACTF_S 0 1526 #define FW_PFVF_CMD_NEXACTF_M 0xffff 1527 #define FW_PFVF_CMD_NEXACTF_V(x) ((x) << FW_PFVF_CMD_NEXACTF_S) 1528 #define FW_PFVF_CMD_NEXACTF_G(x) \ 1529 (((x) >> FW_PFVF_CMD_NEXACTF_S) & FW_PFVF_CMD_NEXACTF_M) 1530 1531 #define FW_PFVF_CMD_R_CAPS_S 24 1532 #define FW_PFVF_CMD_R_CAPS_M 0xff 1533 #define FW_PFVF_CMD_R_CAPS_V(x) ((x) << FW_PFVF_CMD_R_CAPS_S) 1534 #define FW_PFVF_CMD_R_CAPS_G(x) \ 1535 (((x) >> FW_PFVF_CMD_R_CAPS_S) & FW_PFVF_CMD_R_CAPS_M) 1536 1537 #define FW_PFVF_CMD_WX_CAPS_S 16 1538 #define FW_PFVF_CMD_WX_CAPS_M 0xff 1539 #define FW_PFVF_CMD_WX_CAPS_V(x) ((x) << FW_PFVF_CMD_WX_CAPS_S) 1540 #define FW_PFVF_CMD_WX_CAPS_G(x) \ 1541 (((x) >> FW_PFVF_CMD_WX_CAPS_S) & FW_PFVF_CMD_WX_CAPS_M) 1542 1543 #define FW_PFVF_CMD_NETHCTRL_S 0 1544 #define FW_PFVF_CMD_NETHCTRL_M 0xffff 1545 #define FW_PFVF_CMD_NETHCTRL_V(x) ((x) << FW_PFVF_CMD_NETHCTRL_S) 1546 #define FW_PFVF_CMD_NETHCTRL_G(x) \ 1547 (((x) >> FW_PFVF_CMD_NETHCTRL_S) & FW_PFVF_CMD_NETHCTRL_M) 1548 1549 enum fw_iq_type { 1550 FW_IQ_TYPE_FL_INT_CAP, 1551 FW_IQ_TYPE_NO_FL_INT_CAP 1552 }; 1553 1554 enum fw_iq_iqtype { 1555 FW_IQ_IQTYPE_OTHER, 1556 FW_IQ_IQTYPE_NIC, 1557 FW_IQ_IQTYPE_OFLD, 1558 }; 1559 1560 struct fw_iq_cmd { 1561 __be32 op_to_vfn; 1562 __be32 alloc_to_len16; 1563 __be16 physiqid; 1564 __be16 iqid; 1565 __be16 fl0id; 1566 __be16 fl1id; 1567 __be32 type_to_iqandstindex; 1568 __be16 iqdroprss_to_iqesize; 1569 __be16 iqsize; 1570 __be64 iqaddr; 1571 __be32 iqns_to_fl0congen; 1572 __be16 fl0dcaen_to_fl0cidxfthresh; 1573 __be16 fl0size; 1574 __be64 fl0addr; 1575 __be32 fl1cngchmap_to_fl1congen; 1576 __be16 fl1dcaen_to_fl1cidxfthresh; 1577 __be16 fl1size; 1578 __be64 fl1addr; 1579 }; 1580 1581 #define FW_IQ_CMD_PFN_S 8 1582 #define FW_IQ_CMD_PFN_V(x) ((x) << FW_IQ_CMD_PFN_S) 1583 1584 #define FW_IQ_CMD_VFN_S 0 1585 #define FW_IQ_CMD_VFN_V(x) ((x) << FW_IQ_CMD_VFN_S) 1586 1587 #define FW_IQ_CMD_ALLOC_S 31 1588 #define FW_IQ_CMD_ALLOC_V(x) ((x) << FW_IQ_CMD_ALLOC_S) 1589 #define FW_IQ_CMD_ALLOC_F FW_IQ_CMD_ALLOC_V(1U) 1590 1591 #define FW_IQ_CMD_FREE_S 30 1592 #define FW_IQ_CMD_FREE_V(x) ((x) << FW_IQ_CMD_FREE_S) 1593 #define FW_IQ_CMD_FREE_F FW_IQ_CMD_FREE_V(1U) 1594 1595 #define FW_IQ_CMD_MODIFY_S 29 1596 #define FW_IQ_CMD_MODIFY_V(x) ((x) << FW_IQ_CMD_MODIFY_S) 1597 #define FW_IQ_CMD_MODIFY_F FW_IQ_CMD_MODIFY_V(1U) 1598 1599 #define FW_IQ_CMD_IQSTART_S 28 1600 #define FW_IQ_CMD_IQSTART_V(x) ((x) << FW_IQ_CMD_IQSTART_S) 1601 #define FW_IQ_CMD_IQSTART_F FW_IQ_CMD_IQSTART_V(1U) 1602 1603 #define FW_IQ_CMD_IQSTOP_S 27 1604 #define FW_IQ_CMD_IQSTOP_V(x) ((x) << FW_IQ_CMD_IQSTOP_S) 1605 #define FW_IQ_CMD_IQSTOP_F FW_IQ_CMD_IQSTOP_V(1U) 1606 1607 #define FW_IQ_CMD_TYPE_S 29 1608 #define FW_IQ_CMD_TYPE_V(x) ((x) << FW_IQ_CMD_TYPE_S) 1609 1610 #define FW_IQ_CMD_IQASYNCH_S 28 1611 #define FW_IQ_CMD_IQASYNCH_V(x) ((x) << FW_IQ_CMD_IQASYNCH_S) 1612 1613 #define FW_IQ_CMD_VIID_S 16 1614 #define FW_IQ_CMD_VIID_V(x) ((x) << FW_IQ_CMD_VIID_S) 1615 1616 #define FW_IQ_CMD_IQANDST_S 15 1617 #define FW_IQ_CMD_IQANDST_V(x) ((x) << FW_IQ_CMD_IQANDST_S) 1618 1619 #define FW_IQ_CMD_IQANUS_S 14 1620 #define FW_IQ_CMD_IQANUS_V(x) ((x) << FW_IQ_CMD_IQANUS_S) 1621 1622 #define FW_IQ_CMD_IQANUD_S 12 1623 #define FW_IQ_CMD_IQANUD_V(x) ((x) << FW_IQ_CMD_IQANUD_S) 1624 1625 #define FW_IQ_CMD_IQANDSTINDEX_S 0 1626 #define FW_IQ_CMD_IQANDSTINDEX_V(x) ((x) << FW_IQ_CMD_IQANDSTINDEX_S) 1627 1628 #define FW_IQ_CMD_IQDROPRSS_S 15 1629 #define FW_IQ_CMD_IQDROPRSS_V(x) ((x) << FW_IQ_CMD_IQDROPRSS_S) 1630 #define FW_IQ_CMD_IQDROPRSS_F FW_IQ_CMD_IQDROPRSS_V(1U) 1631 1632 #define FW_IQ_CMD_IQGTSMODE_S 14 1633 #define FW_IQ_CMD_IQGTSMODE_V(x) ((x) << FW_IQ_CMD_IQGTSMODE_S) 1634 #define FW_IQ_CMD_IQGTSMODE_F FW_IQ_CMD_IQGTSMODE_V(1U) 1635 1636 #define FW_IQ_CMD_IQPCIECH_S 12 1637 #define FW_IQ_CMD_IQPCIECH_V(x) ((x) << FW_IQ_CMD_IQPCIECH_S) 1638 1639 #define FW_IQ_CMD_IQDCAEN_S 11 1640 #define FW_IQ_CMD_IQDCAEN_V(x) ((x) << FW_IQ_CMD_IQDCAEN_S) 1641 1642 #define FW_IQ_CMD_IQDCACPU_S 6 1643 #define FW_IQ_CMD_IQDCACPU_V(x) ((x) << FW_IQ_CMD_IQDCACPU_S) 1644 1645 #define FW_IQ_CMD_IQINTCNTTHRESH_S 4 1646 #define FW_IQ_CMD_IQINTCNTTHRESH_V(x) ((x) << FW_IQ_CMD_IQINTCNTTHRESH_S) 1647 1648 #define FW_IQ_CMD_IQO_S 3 1649 #define FW_IQ_CMD_IQO_V(x) ((x) << FW_IQ_CMD_IQO_S) 1650 #define FW_IQ_CMD_IQO_F FW_IQ_CMD_IQO_V(1U) 1651 1652 #define FW_IQ_CMD_IQCPRIO_S 2 1653 #define FW_IQ_CMD_IQCPRIO_V(x) ((x) << FW_IQ_CMD_IQCPRIO_S) 1654 1655 #define FW_IQ_CMD_IQESIZE_S 0 1656 #define FW_IQ_CMD_IQESIZE_V(x) ((x) << FW_IQ_CMD_IQESIZE_S) 1657 1658 #define FW_IQ_CMD_IQNS_S 31 1659 #define FW_IQ_CMD_IQNS_V(x) ((x) << FW_IQ_CMD_IQNS_S) 1660 1661 #define FW_IQ_CMD_IQRO_S 30 1662 #define FW_IQ_CMD_IQRO_V(x) ((x) << FW_IQ_CMD_IQRO_S) 1663 1664 #define FW_IQ_CMD_IQFLINTIQHSEN_S 28 1665 #define FW_IQ_CMD_IQFLINTIQHSEN_V(x) ((x) << FW_IQ_CMD_IQFLINTIQHSEN_S) 1666 1667 #define FW_IQ_CMD_IQFLINTCONGEN_S 27 1668 #define FW_IQ_CMD_IQFLINTCONGEN_V(x) ((x) << FW_IQ_CMD_IQFLINTCONGEN_S) 1669 #define FW_IQ_CMD_IQFLINTCONGEN_F FW_IQ_CMD_IQFLINTCONGEN_V(1U) 1670 1671 #define FW_IQ_CMD_IQFLINTISCSIC_S 26 1672 #define FW_IQ_CMD_IQFLINTISCSIC_V(x) ((x) << FW_IQ_CMD_IQFLINTISCSIC_S) 1673 1674 #define FW_IQ_CMD_IQTYPE_S 24 1675 #define FW_IQ_CMD_IQTYPE_M 0x3 1676 #define FW_IQ_CMD_IQTYPE_V(x) ((x) << FW_IQ_CMD_IQTYPE_S) 1677 #define FW_IQ_CMD_IQTYPE_G(x) \ 1678 (((x) >> FW_IQ_CMD_IQTYPE_S) & FW_IQ_CMD_IQTYPE_M) 1679 1680 #define FW_IQ_CMD_FL0CNGCHMAP_S 20 1681 #define FW_IQ_CMD_FL0CNGCHMAP_V(x) ((x) << FW_IQ_CMD_FL0CNGCHMAP_S) 1682 1683 #define FW_IQ_CMD_FL0CACHELOCK_S 15 1684 #define FW_IQ_CMD_FL0CACHELOCK_V(x) ((x) << FW_IQ_CMD_FL0CACHELOCK_S) 1685 1686 #define FW_IQ_CMD_FL0DBP_S 14 1687 #define FW_IQ_CMD_FL0DBP_V(x) ((x) << FW_IQ_CMD_FL0DBP_S) 1688 1689 #define FW_IQ_CMD_FL0DATANS_S 13 1690 #define FW_IQ_CMD_FL0DATANS_V(x) ((x) << FW_IQ_CMD_FL0DATANS_S) 1691 1692 #define FW_IQ_CMD_FL0DATARO_S 12 1693 #define FW_IQ_CMD_FL0DATARO_V(x) ((x) << FW_IQ_CMD_FL0DATARO_S) 1694 #define FW_IQ_CMD_FL0DATARO_F FW_IQ_CMD_FL0DATARO_V(1U) 1695 1696 #define FW_IQ_CMD_FL0CONGCIF_S 11 1697 #define FW_IQ_CMD_FL0CONGCIF_V(x) ((x) << FW_IQ_CMD_FL0CONGCIF_S) 1698 #define FW_IQ_CMD_FL0CONGCIF_F FW_IQ_CMD_FL0CONGCIF_V(1U) 1699 1700 #define FW_IQ_CMD_FL0ONCHIP_S 10 1701 #define FW_IQ_CMD_FL0ONCHIP_V(x) ((x) << FW_IQ_CMD_FL0ONCHIP_S) 1702 1703 #define FW_IQ_CMD_FL0STATUSPGNS_S 9 1704 #define FW_IQ_CMD_FL0STATUSPGNS_V(x) ((x) << FW_IQ_CMD_FL0STATUSPGNS_S) 1705 1706 #define FW_IQ_CMD_FL0STATUSPGRO_S 8 1707 #define FW_IQ_CMD_FL0STATUSPGRO_V(x) ((x) << FW_IQ_CMD_FL0STATUSPGRO_S) 1708 1709 #define FW_IQ_CMD_FL0FETCHNS_S 7 1710 #define FW_IQ_CMD_FL0FETCHNS_V(x) ((x) << FW_IQ_CMD_FL0FETCHNS_S) 1711 1712 #define FW_IQ_CMD_FL0FETCHRO_S 6 1713 #define FW_IQ_CMD_FL0FETCHRO_V(x) ((x) << FW_IQ_CMD_FL0FETCHRO_S) 1714 #define FW_IQ_CMD_FL0FETCHRO_F FW_IQ_CMD_FL0FETCHRO_V(1U) 1715 1716 #define FW_IQ_CMD_FL0HOSTFCMODE_S 4 1717 #define FW_IQ_CMD_FL0HOSTFCMODE_V(x) ((x) << FW_IQ_CMD_FL0HOSTFCMODE_S) 1718 1719 #define FW_IQ_CMD_FL0CPRIO_S 3 1720 #define FW_IQ_CMD_FL0CPRIO_V(x) ((x) << FW_IQ_CMD_FL0CPRIO_S) 1721 1722 #define FW_IQ_CMD_FL0PADEN_S 2 1723 #define FW_IQ_CMD_FL0PADEN_V(x) ((x) << FW_IQ_CMD_FL0PADEN_S) 1724 #define FW_IQ_CMD_FL0PADEN_F FW_IQ_CMD_FL0PADEN_V(1U) 1725 1726 #define FW_IQ_CMD_FL0PACKEN_S 1 1727 #define FW_IQ_CMD_FL0PACKEN_V(x) ((x) << FW_IQ_CMD_FL0PACKEN_S) 1728 #define FW_IQ_CMD_FL0PACKEN_F FW_IQ_CMD_FL0PACKEN_V(1U) 1729 1730 #define FW_IQ_CMD_FL0CONGEN_S 0 1731 #define FW_IQ_CMD_FL0CONGEN_V(x) ((x) << FW_IQ_CMD_FL0CONGEN_S) 1732 #define FW_IQ_CMD_FL0CONGEN_F FW_IQ_CMD_FL0CONGEN_V(1U) 1733 1734 #define FW_IQ_CMD_FL0DCAEN_S 15 1735 #define FW_IQ_CMD_FL0DCAEN_V(x) ((x) << FW_IQ_CMD_FL0DCAEN_S) 1736 1737 #define FW_IQ_CMD_FL0DCACPU_S 10 1738 #define FW_IQ_CMD_FL0DCACPU_V(x) ((x) << FW_IQ_CMD_FL0DCACPU_S) 1739 1740 #define FW_IQ_CMD_FL0FBMIN_S 7 1741 #define FW_IQ_CMD_FL0FBMIN_V(x) ((x) << FW_IQ_CMD_FL0FBMIN_S) 1742 1743 #define FW_IQ_CMD_FL0FBMAX_S 4 1744 #define FW_IQ_CMD_FL0FBMAX_V(x) ((x) << FW_IQ_CMD_FL0FBMAX_S) 1745 1746 #define FW_IQ_CMD_FL0CIDXFTHRESHO_S 3 1747 #define FW_IQ_CMD_FL0CIDXFTHRESHO_V(x) ((x) << FW_IQ_CMD_FL0CIDXFTHRESHO_S) 1748 #define FW_IQ_CMD_FL0CIDXFTHRESHO_F FW_IQ_CMD_FL0CIDXFTHRESHO_V(1U) 1749 1750 #define FW_IQ_CMD_FL0CIDXFTHRESH_S 0 1751 #define FW_IQ_CMD_FL0CIDXFTHRESH_V(x) ((x) << FW_IQ_CMD_FL0CIDXFTHRESH_S) 1752 1753 #define FW_IQ_CMD_FL1CNGCHMAP_S 20 1754 #define FW_IQ_CMD_FL1CNGCHMAP_V(x) ((x) << FW_IQ_CMD_FL1CNGCHMAP_S) 1755 1756 #define FW_IQ_CMD_FL1CACHELOCK_S 15 1757 #define FW_IQ_CMD_FL1CACHELOCK_V(x) ((x) << FW_IQ_CMD_FL1CACHELOCK_S) 1758 1759 #define FW_IQ_CMD_FL1DBP_S 14 1760 #define FW_IQ_CMD_FL1DBP_V(x) ((x) << FW_IQ_CMD_FL1DBP_S) 1761 1762 #define FW_IQ_CMD_FL1DATANS_S 13 1763 #define FW_IQ_CMD_FL1DATANS_V(x) ((x) << FW_IQ_CMD_FL1DATANS_S) 1764 1765 #define FW_IQ_CMD_FL1DATARO_S 12 1766 #define FW_IQ_CMD_FL1DATARO_V(x) ((x) << FW_IQ_CMD_FL1DATARO_S) 1767 1768 #define FW_IQ_CMD_FL1CONGCIF_S 11 1769 #define FW_IQ_CMD_FL1CONGCIF_V(x) ((x) << FW_IQ_CMD_FL1CONGCIF_S) 1770 1771 #define FW_IQ_CMD_FL1ONCHIP_S 10 1772 #define FW_IQ_CMD_FL1ONCHIP_V(x) ((x) << FW_IQ_CMD_FL1ONCHIP_S) 1773 1774 #define FW_IQ_CMD_FL1STATUSPGNS_S 9 1775 #define FW_IQ_CMD_FL1STATUSPGNS_V(x) ((x) << FW_IQ_CMD_FL1STATUSPGNS_S) 1776 1777 #define FW_IQ_CMD_FL1STATUSPGRO_S 8 1778 #define FW_IQ_CMD_FL1STATUSPGRO_V(x) ((x) << FW_IQ_CMD_FL1STATUSPGRO_S) 1779 1780 #define FW_IQ_CMD_FL1FETCHNS_S 7 1781 #define FW_IQ_CMD_FL1FETCHNS_V(x) ((x) << FW_IQ_CMD_FL1FETCHNS_S) 1782 1783 #define FW_IQ_CMD_FL1FETCHRO_S 6 1784 #define FW_IQ_CMD_FL1FETCHRO_V(x) ((x) << FW_IQ_CMD_FL1FETCHRO_S) 1785 1786 #define FW_IQ_CMD_FL1HOSTFCMODE_S 4 1787 #define FW_IQ_CMD_FL1HOSTFCMODE_V(x) ((x) << FW_IQ_CMD_FL1HOSTFCMODE_S) 1788 1789 #define FW_IQ_CMD_FL1CPRIO_S 3 1790 #define FW_IQ_CMD_FL1CPRIO_V(x) ((x) << FW_IQ_CMD_FL1CPRIO_S) 1791 1792 #define FW_IQ_CMD_FL1PADEN_S 2 1793 #define FW_IQ_CMD_FL1PADEN_V(x) ((x) << FW_IQ_CMD_FL1PADEN_S) 1794 #define FW_IQ_CMD_FL1PADEN_F FW_IQ_CMD_FL1PADEN_V(1U) 1795 1796 #define FW_IQ_CMD_FL1PACKEN_S 1 1797 #define FW_IQ_CMD_FL1PACKEN_V(x) ((x) << FW_IQ_CMD_FL1PACKEN_S) 1798 #define FW_IQ_CMD_FL1PACKEN_F FW_IQ_CMD_FL1PACKEN_V(1U) 1799 1800 #define FW_IQ_CMD_FL1CONGEN_S 0 1801 #define FW_IQ_CMD_FL1CONGEN_V(x) ((x) << FW_IQ_CMD_FL1CONGEN_S) 1802 #define FW_IQ_CMD_FL1CONGEN_F FW_IQ_CMD_FL1CONGEN_V(1U) 1803 1804 #define FW_IQ_CMD_FL1DCAEN_S 15 1805 #define FW_IQ_CMD_FL1DCAEN_V(x) ((x) << FW_IQ_CMD_FL1DCAEN_S) 1806 1807 #define FW_IQ_CMD_FL1DCACPU_S 10 1808 #define FW_IQ_CMD_FL1DCACPU_V(x) ((x) << FW_IQ_CMD_FL1DCACPU_S) 1809 1810 #define FW_IQ_CMD_FL1FBMIN_S 7 1811 #define FW_IQ_CMD_FL1FBMIN_V(x) ((x) << FW_IQ_CMD_FL1FBMIN_S) 1812 1813 #define FW_IQ_CMD_FL1FBMAX_S 4 1814 #define FW_IQ_CMD_FL1FBMAX_V(x) ((x) << FW_IQ_CMD_FL1FBMAX_S) 1815 1816 #define FW_IQ_CMD_FL1CIDXFTHRESHO_S 3 1817 #define FW_IQ_CMD_FL1CIDXFTHRESHO_V(x) ((x) << FW_IQ_CMD_FL1CIDXFTHRESHO_S) 1818 #define FW_IQ_CMD_FL1CIDXFTHRESHO_F FW_IQ_CMD_FL1CIDXFTHRESHO_V(1U) 1819 1820 #define FW_IQ_CMD_FL1CIDXFTHRESH_S 0 1821 #define FW_IQ_CMD_FL1CIDXFTHRESH_V(x) ((x) << FW_IQ_CMD_FL1CIDXFTHRESH_S) 1822 1823 struct fw_eq_eth_cmd { 1824 __be32 op_to_vfn; 1825 __be32 alloc_to_len16; 1826 __be32 eqid_pkd; 1827 __be32 physeqid_pkd; 1828 __be32 fetchszm_to_iqid; 1829 __be32 dcaen_to_eqsize; 1830 __be64 eqaddr; 1831 __be32 autoequiqe_to_viid; 1832 __be32 timeren_timerix; 1833 __be64 r9; 1834 }; 1835 1836 #define FW_EQ_ETH_CMD_PFN_S 8 1837 #define FW_EQ_ETH_CMD_PFN_V(x) ((x) << FW_EQ_ETH_CMD_PFN_S) 1838 1839 #define FW_EQ_ETH_CMD_VFN_S 0 1840 #define FW_EQ_ETH_CMD_VFN_V(x) ((x) << FW_EQ_ETH_CMD_VFN_S) 1841 1842 #define FW_EQ_ETH_CMD_ALLOC_S 31 1843 #define FW_EQ_ETH_CMD_ALLOC_V(x) ((x) << FW_EQ_ETH_CMD_ALLOC_S) 1844 #define FW_EQ_ETH_CMD_ALLOC_F FW_EQ_ETH_CMD_ALLOC_V(1U) 1845 1846 #define FW_EQ_ETH_CMD_FREE_S 30 1847 #define FW_EQ_ETH_CMD_FREE_V(x) ((x) << FW_EQ_ETH_CMD_FREE_S) 1848 #define FW_EQ_ETH_CMD_FREE_F FW_EQ_ETH_CMD_FREE_V(1U) 1849 1850 #define FW_EQ_ETH_CMD_MODIFY_S 29 1851 #define FW_EQ_ETH_CMD_MODIFY_V(x) ((x) << FW_EQ_ETH_CMD_MODIFY_S) 1852 #define FW_EQ_ETH_CMD_MODIFY_F FW_EQ_ETH_CMD_MODIFY_V(1U) 1853 1854 #define FW_EQ_ETH_CMD_EQSTART_S 28 1855 #define FW_EQ_ETH_CMD_EQSTART_V(x) ((x) << FW_EQ_ETH_CMD_EQSTART_S) 1856 #define FW_EQ_ETH_CMD_EQSTART_F FW_EQ_ETH_CMD_EQSTART_V(1U) 1857 1858 #define FW_EQ_ETH_CMD_EQSTOP_S 27 1859 #define FW_EQ_ETH_CMD_EQSTOP_V(x) ((x) << FW_EQ_ETH_CMD_EQSTOP_S) 1860 #define FW_EQ_ETH_CMD_EQSTOP_F FW_EQ_ETH_CMD_EQSTOP_V(1U) 1861 1862 #define FW_EQ_ETH_CMD_EQID_S 0 1863 #define FW_EQ_ETH_CMD_EQID_M 0xfffff 1864 #define FW_EQ_ETH_CMD_EQID_V(x) ((x) << FW_EQ_ETH_CMD_EQID_S) 1865 #define FW_EQ_ETH_CMD_EQID_G(x) \ 1866 (((x) >> FW_EQ_ETH_CMD_EQID_S) & FW_EQ_ETH_CMD_EQID_M) 1867 1868 #define FW_EQ_ETH_CMD_PHYSEQID_S 0 1869 #define FW_EQ_ETH_CMD_PHYSEQID_M 0xfffff 1870 #define FW_EQ_ETH_CMD_PHYSEQID_V(x) ((x) << FW_EQ_ETH_CMD_PHYSEQID_S) 1871 #define FW_EQ_ETH_CMD_PHYSEQID_G(x) \ 1872 (((x) >> FW_EQ_ETH_CMD_PHYSEQID_S) & FW_EQ_ETH_CMD_PHYSEQID_M) 1873 1874 #define FW_EQ_ETH_CMD_FETCHSZM_S 26 1875 #define FW_EQ_ETH_CMD_FETCHSZM_V(x) ((x) << FW_EQ_ETH_CMD_FETCHSZM_S) 1876 #define FW_EQ_ETH_CMD_FETCHSZM_F FW_EQ_ETH_CMD_FETCHSZM_V(1U) 1877 1878 #define FW_EQ_ETH_CMD_STATUSPGNS_S 25 1879 #define FW_EQ_ETH_CMD_STATUSPGNS_V(x) ((x) << FW_EQ_ETH_CMD_STATUSPGNS_S) 1880 1881 #define FW_EQ_ETH_CMD_STATUSPGRO_S 24 1882 #define FW_EQ_ETH_CMD_STATUSPGRO_V(x) ((x) << FW_EQ_ETH_CMD_STATUSPGRO_S) 1883 1884 #define FW_EQ_ETH_CMD_FETCHNS_S 23 1885 #define FW_EQ_ETH_CMD_FETCHNS_V(x) ((x) << FW_EQ_ETH_CMD_FETCHNS_S) 1886 1887 #define FW_EQ_ETH_CMD_FETCHRO_S 22 1888 #define FW_EQ_ETH_CMD_FETCHRO_V(x) ((x) << FW_EQ_ETH_CMD_FETCHRO_S) 1889 #define FW_EQ_ETH_CMD_FETCHRO_F FW_EQ_ETH_CMD_FETCHRO_V(1U) 1890 1891 #define FW_EQ_ETH_CMD_HOSTFCMODE_S 20 1892 #define FW_EQ_ETH_CMD_HOSTFCMODE_V(x) ((x) << FW_EQ_ETH_CMD_HOSTFCMODE_S) 1893 1894 #define FW_EQ_ETH_CMD_CPRIO_S 19 1895 #define FW_EQ_ETH_CMD_CPRIO_V(x) ((x) << FW_EQ_ETH_CMD_CPRIO_S) 1896 1897 #define FW_EQ_ETH_CMD_ONCHIP_S 18 1898 #define FW_EQ_ETH_CMD_ONCHIP_V(x) ((x) << FW_EQ_ETH_CMD_ONCHIP_S) 1899 1900 #define FW_EQ_ETH_CMD_PCIECHN_S 16 1901 #define FW_EQ_ETH_CMD_PCIECHN_V(x) ((x) << FW_EQ_ETH_CMD_PCIECHN_S) 1902 1903 #define FW_EQ_ETH_CMD_IQID_S 0 1904 #define FW_EQ_ETH_CMD_IQID_V(x) ((x) << FW_EQ_ETH_CMD_IQID_S) 1905 1906 #define FW_EQ_ETH_CMD_DCAEN_S 31 1907 #define FW_EQ_ETH_CMD_DCAEN_V(x) ((x) << FW_EQ_ETH_CMD_DCAEN_S) 1908 1909 #define FW_EQ_ETH_CMD_DCACPU_S 26 1910 #define FW_EQ_ETH_CMD_DCACPU_V(x) ((x) << FW_EQ_ETH_CMD_DCACPU_S) 1911 1912 #define FW_EQ_ETH_CMD_FBMIN_S 23 1913 #define FW_EQ_ETH_CMD_FBMIN_V(x) ((x) << FW_EQ_ETH_CMD_FBMIN_S) 1914 1915 #define FW_EQ_ETH_CMD_FBMAX_S 20 1916 #define FW_EQ_ETH_CMD_FBMAX_V(x) ((x) << FW_EQ_ETH_CMD_FBMAX_S) 1917 1918 #define FW_EQ_ETH_CMD_CIDXFTHRESHO_S 19 1919 #define FW_EQ_ETH_CMD_CIDXFTHRESHO_V(x) ((x) << FW_EQ_ETH_CMD_CIDXFTHRESHO_S) 1920 1921 #define FW_EQ_ETH_CMD_CIDXFTHRESH_S 16 1922 #define FW_EQ_ETH_CMD_CIDXFTHRESH_V(x) ((x) << FW_EQ_ETH_CMD_CIDXFTHRESH_S) 1923 1924 #define FW_EQ_ETH_CMD_EQSIZE_S 0 1925 #define FW_EQ_ETH_CMD_EQSIZE_V(x) ((x) << FW_EQ_ETH_CMD_EQSIZE_S) 1926 1927 #define FW_EQ_ETH_CMD_AUTOEQUIQE_S 31 1928 #define FW_EQ_ETH_CMD_AUTOEQUIQE_V(x) ((x) << FW_EQ_ETH_CMD_AUTOEQUIQE_S) 1929 #define FW_EQ_ETH_CMD_AUTOEQUIQE_F FW_EQ_ETH_CMD_AUTOEQUIQE_V(1U) 1930 1931 #define FW_EQ_ETH_CMD_AUTOEQUEQE_S 30 1932 #define FW_EQ_ETH_CMD_AUTOEQUEQE_V(x) ((x) << FW_EQ_ETH_CMD_AUTOEQUEQE_S) 1933 #define FW_EQ_ETH_CMD_AUTOEQUEQE_F FW_EQ_ETH_CMD_AUTOEQUEQE_V(1U) 1934 1935 #define FW_EQ_ETH_CMD_VIID_S 16 1936 #define FW_EQ_ETH_CMD_VIID_V(x) ((x) << FW_EQ_ETH_CMD_VIID_S) 1937 1938 #define FW_EQ_ETH_CMD_TIMEREN_S 3 1939 #define FW_EQ_ETH_CMD_TIMEREN_M 0x1 1940 #define FW_EQ_ETH_CMD_TIMEREN_V(x) ((x) << FW_EQ_ETH_CMD_TIMEREN_S) 1941 #define FW_EQ_ETH_CMD_TIMEREN_G(x) \ 1942 (((x) >> FW_EQ_ETH_CMD_TIMEREN_S) & FW_EQ_ETH_CMD_TIMEREN_M) 1943 #define FW_EQ_ETH_CMD_TIMEREN_F FW_EQ_ETH_CMD_TIMEREN_V(1U) 1944 1945 #define FW_EQ_ETH_CMD_TIMERIX_S 0 1946 #define FW_EQ_ETH_CMD_TIMERIX_M 0x7 1947 #define FW_EQ_ETH_CMD_TIMERIX_V(x) ((x) << FW_EQ_ETH_CMD_TIMERIX_S) 1948 #define FW_EQ_ETH_CMD_TIMERIX_G(x) \ 1949 (((x) >> FW_EQ_ETH_CMD_TIMERIX_S) & FW_EQ_ETH_CMD_TIMERIX_M) 1950 1951 struct fw_eq_ctrl_cmd { 1952 __be32 op_to_vfn; 1953 __be32 alloc_to_len16; 1954 __be32 cmpliqid_eqid; 1955 __be32 physeqid_pkd; 1956 __be32 fetchszm_to_iqid; 1957 __be32 dcaen_to_eqsize; 1958 __be64 eqaddr; 1959 }; 1960 1961 #define FW_EQ_CTRL_CMD_PFN_S 8 1962 #define FW_EQ_CTRL_CMD_PFN_V(x) ((x) << FW_EQ_CTRL_CMD_PFN_S) 1963 1964 #define FW_EQ_CTRL_CMD_VFN_S 0 1965 #define FW_EQ_CTRL_CMD_VFN_V(x) ((x) << FW_EQ_CTRL_CMD_VFN_S) 1966 1967 #define FW_EQ_CTRL_CMD_ALLOC_S 31 1968 #define FW_EQ_CTRL_CMD_ALLOC_V(x) ((x) << FW_EQ_CTRL_CMD_ALLOC_S) 1969 #define FW_EQ_CTRL_CMD_ALLOC_F FW_EQ_CTRL_CMD_ALLOC_V(1U) 1970 1971 #define FW_EQ_CTRL_CMD_FREE_S 30 1972 #define FW_EQ_CTRL_CMD_FREE_V(x) ((x) << FW_EQ_CTRL_CMD_FREE_S) 1973 #define FW_EQ_CTRL_CMD_FREE_F FW_EQ_CTRL_CMD_FREE_V(1U) 1974 1975 #define FW_EQ_CTRL_CMD_MODIFY_S 29 1976 #define FW_EQ_CTRL_CMD_MODIFY_V(x) ((x) << FW_EQ_CTRL_CMD_MODIFY_S) 1977 #define FW_EQ_CTRL_CMD_MODIFY_F FW_EQ_CTRL_CMD_MODIFY_V(1U) 1978 1979 #define FW_EQ_CTRL_CMD_EQSTART_S 28 1980 #define FW_EQ_CTRL_CMD_EQSTART_V(x) ((x) << FW_EQ_CTRL_CMD_EQSTART_S) 1981 #define FW_EQ_CTRL_CMD_EQSTART_F FW_EQ_CTRL_CMD_EQSTART_V(1U) 1982 1983 #define FW_EQ_CTRL_CMD_EQSTOP_S 27 1984 #define FW_EQ_CTRL_CMD_EQSTOP_V(x) ((x) << FW_EQ_CTRL_CMD_EQSTOP_S) 1985 #define FW_EQ_CTRL_CMD_EQSTOP_F FW_EQ_CTRL_CMD_EQSTOP_V(1U) 1986 1987 #define FW_EQ_CTRL_CMD_CMPLIQID_S 20 1988 #define FW_EQ_CTRL_CMD_CMPLIQID_V(x) ((x) << FW_EQ_CTRL_CMD_CMPLIQID_S) 1989 1990 #define FW_EQ_CTRL_CMD_EQID_S 0 1991 #define FW_EQ_CTRL_CMD_EQID_M 0xfffff 1992 #define FW_EQ_CTRL_CMD_EQID_V(x) ((x) << FW_EQ_CTRL_CMD_EQID_S) 1993 #define FW_EQ_CTRL_CMD_EQID_G(x) \ 1994 (((x) >> FW_EQ_CTRL_CMD_EQID_S) & FW_EQ_CTRL_CMD_EQID_M) 1995 1996 #define FW_EQ_CTRL_CMD_PHYSEQID_S 0 1997 #define FW_EQ_CTRL_CMD_PHYSEQID_M 0xfffff 1998 #define FW_EQ_CTRL_CMD_PHYSEQID_G(x) \ 1999 (((x) >> FW_EQ_CTRL_CMD_PHYSEQID_S) & FW_EQ_CTRL_CMD_PHYSEQID_M) 2000 2001 #define FW_EQ_CTRL_CMD_FETCHSZM_S 26 2002 #define FW_EQ_CTRL_CMD_FETCHSZM_V(x) ((x) << FW_EQ_CTRL_CMD_FETCHSZM_S) 2003 #define FW_EQ_CTRL_CMD_FETCHSZM_F FW_EQ_CTRL_CMD_FETCHSZM_V(1U) 2004 2005 #define FW_EQ_CTRL_CMD_STATUSPGNS_S 25 2006 #define FW_EQ_CTRL_CMD_STATUSPGNS_V(x) ((x) << FW_EQ_CTRL_CMD_STATUSPGNS_S) 2007 #define FW_EQ_CTRL_CMD_STATUSPGNS_F FW_EQ_CTRL_CMD_STATUSPGNS_V(1U) 2008 2009 #define FW_EQ_CTRL_CMD_STATUSPGRO_S 24 2010 #define FW_EQ_CTRL_CMD_STATUSPGRO_V(x) ((x) << FW_EQ_CTRL_CMD_STATUSPGRO_S) 2011 #define FW_EQ_CTRL_CMD_STATUSPGRO_F FW_EQ_CTRL_CMD_STATUSPGRO_V(1U) 2012 2013 #define FW_EQ_CTRL_CMD_FETCHNS_S 23 2014 #define FW_EQ_CTRL_CMD_FETCHNS_V(x) ((x) << FW_EQ_CTRL_CMD_FETCHNS_S) 2015 #define FW_EQ_CTRL_CMD_FETCHNS_F FW_EQ_CTRL_CMD_FETCHNS_V(1U) 2016 2017 #define FW_EQ_CTRL_CMD_FETCHRO_S 22 2018 #define FW_EQ_CTRL_CMD_FETCHRO_V(x) ((x) << FW_EQ_CTRL_CMD_FETCHRO_S) 2019 #define FW_EQ_CTRL_CMD_FETCHRO_F FW_EQ_CTRL_CMD_FETCHRO_V(1U) 2020 2021 #define FW_EQ_CTRL_CMD_HOSTFCMODE_S 20 2022 #define FW_EQ_CTRL_CMD_HOSTFCMODE_V(x) ((x) << FW_EQ_CTRL_CMD_HOSTFCMODE_S) 2023 2024 #define FW_EQ_CTRL_CMD_CPRIO_S 19 2025 #define FW_EQ_CTRL_CMD_CPRIO_V(x) ((x) << FW_EQ_CTRL_CMD_CPRIO_S) 2026 2027 #define FW_EQ_CTRL_CMD_ONCHIP_S 18 2028 #define FW_EQ_CTRL_CMD_ONCHIP_V(x) ((x) << FW_EQ_CTRL_CMD_ONCHIP_S) 2029 2030 #define FW_EQ_CTRL_CMD_PCIECHN_S 16 2031 #define FW_EQ_CTRL_CMD_PCIECHN_V(x) ((x) << FW_EQ_CTRL_CMD_PCIECHN_S) 2032 2033 #define FW_EQ_CTRL_CMD_IQID_S 0 2034 #define FW_EQ_CTRL_CMD_IQID_V(x) ((x) << FW_EQ_CTRL_CMD_IQID_S) 2035 2036 #define FW_EQ_CTRL_CMD_DCAEN_S 31 2037 #define FW_EQ_CTRL_CMD_DCAEN_V(x) ((x) << FW_EQ_CTRL_CMD_DCAEN_S) 2038 2039 #define FW_EQ_CTRL_CMD_DCACPU_S 26 2040 #define FW_EQ_CTRL_CMD_DCACPU_V(x) ((x) << FW_EQ_CTRL_CMD_DCACPU_S) 2041 2042 #define FW_EQ_CTRL_CMD_FBMIN_S 23 2043 #define FW_EQ_CTRL_CMD_FBMIN_V(x) ((x) << FW_EQ_CTRL_CMD_FBMIN_S) 2044 2045 #define FW_EQ_CTRL_CMD_FBMAX_S 20 2046 #define FW_EQ_CTRL_CMD_FBMAX_V(x) ((x) << FW_EQ_CTRL_CMD_FBMAX_S) 2047 2048 #define FW_EQ_CTRL_CMD_CIDXFTHRESHO_S 19 2049 #define FW_EQ_CTRL_CMD_CIDXFTHRESHO_V(x) \ 2050 ((x) << FW_EQ_CTRL_CMD_CIDXFTHRESHO_S) 2051 2052 #define FW_EQ_CTRL_CMD_CIDXFTHRESH_S 16 2053 #define FW_EQ_CTRL_CMD_CIDXFTHRESH_V(x) ((x) << FW_EQ_CTRL_CMD_CIDXFTHRESH_S) 2054 2055 #define FW_EQ_CTRL_CMD_EQSIZE_S 0 2056 #define FW_EQ_CTRL_CMD_EQSIZE_V(x) ((x) << FW_EQ_CTRL_CMD_EQSIZE_S) 2057 2058 struct fw_eq_ofld_cmd { 2059 __be32 op_to_vfn; 2060 __be32 alloc_to_len16; 2061 __be32 eqid_pkd; 2062 __be32 physeqid_pkd; 2063 __be32 fetchszm_to_iqid; 2064 __be32 dcaen_to_eqsize; 2065 __be64 eqaddr; 2066 }; 2067 2068 #define FW_EQ_OFLD_CMD_PFN_S 8 2069 #define FW_EQ_OFLD_CMD_PFN_V(x) ((x) << FW_EQ_OFLD_CMD_PFN_S) 2070 2071 #define FW_EQ_OFLD_CMD_VFN_S 0 2072 #define FW_EQ_OFLD_CMD_VFN_V(x) ((x) << FW_EQ_OFLD_CMD_VFN_S) 2073 2074 #define FW_EQ_OFLD_CMD_ALLOC_S 31 2075 #define FW_EQ_OFLD_CMD_ALLOC_V(x) ((x) << FW_EQ_OFLD_CMD_ALLOC_S) 2076 #define FW_EQ_OFLD_CMD_ALLOC_F FW_EQ_OFLD_CMD_ALLOC_V(1U) 2077 2078 #define FW_EQ_OFLD_CMD_FREE_S 30 2079 #define FW_EQ_OFLD_CMD_FREE_V(x) ((x) << FW_EQ_OFLD_CMD_FREE_S) 2080 #define FW_EQ_OFLD_CMD_FREE_F FW_EQ_OFLD_CMD_FREE_V(1U) 2081 2082 #define FW_EQ_OFLD_CMD_MODIFY_S 29 2083 #define FW_EQ_OFLD_CMD_MODIFY_V(x) ((x) << FW_EQ_OFLD_CMD_MODIFY_S) 2084 #define FW_EQ_OFLD_CMD_MODIFY_F FW_EQ_OFLD_CMD_MODIFY_V(1U) 2085 2086 #define FW_EQ_OFLD_CMD_EQSTART_S 28 2087 #define FW_EQ_OFLD_CMD_EQSTART_V(x) ((x) << FW_EQ_OFLD_CMD_EQSTART_S) 2088 #define FW_EQ_OFLD_CMD_EQSTART_F FW_EQ_OFLD_CMD_EQSTART_V(1U) 2089 2090 #define FW_EQ_OFLD_CMD_EQSTOP_S 27 2091 #define FW_EQ_OFLD_CMD_EQSTOP_V(x) ((x) << FW_EQ_OFLD_CMD_EQSTOP_S) 2092 #define FW_EQ_OFLD_CMD_EQSTOP_F FW_EQ_OFLD_CMD_EQSTOP_V(1U) 2093 2094 #define FW_EQ_OFLD_CMD_EQID_S 0 2095 #define FW_EQ_OFLD_CMD_EQID_M 0xfffff 2096 #define FW_EQ_OFLD_CMD_EQID_V(x) ((x) << FW_EQ_OFLD_CMD_EQID_S) 2097 #define FW_EQ_OFLD_CMD_EQID_G(x) \ 2098 (((x) >> FW_EQ_OFLD_CMD_EQID_S) & FW_EQ_OFLD_CMD_EQID_M) 2099 2100 #define FW_EQ_OFLD_CMD_PHYSEQID_S 0 2101 #define FW_EQ_OFLD_CMD_PHYSEQID_M 0xfffff 2102 #define FW_EQ_OFLD_CMD_PHYSEQID_G(x) \ 2103 (((x) >> FW_EQ_OFLD_CMD_PHYSEQID_S) & FW_EQ_OFLD_CMD_PHYSEQID_M) 2104 2105 #define FW_EQ_OFLD_CMD_FETCHSZM_S 26 2106 #define FW_EQ_OFLD_CMD_FETCHSZM_V(x) ((x) << FW_EQ_OFLD_CMD_FETCHSZM_S) 2107 2108 #define FW_EQ_OFLD_CMD_STATUSPGNS_S 25 2109 #define FW_EQ_OFLD_CMD_STATUSPGNS_V(x) ((x) << FW_EQ_OFLD_CMD_STATUSPGNS_S) 2110 2111 #define FW_EQ_OFLD_CMD_STATUSPGRO_S 24 2112 #define FW_EQ_OFLD_CMD_STATUSPGRO_V(x) ((x) << FW_EQ_OFLD_CMD_STATUSPGRO_S) 2113 2114 #define FW_EQ_OFLD_CMD_FETCHNS_S 23 2115 #define FW_EQ_OFLD_CMD_FETCHNS_V(x) ((x) << FW_EQ_OFLD_CMD_FETCHNS_S) 2116 2117 #define FW_EQ_OFLD_CMD_FETCHRO_S 22 2118 #define FW_EQ_OFLD_CMD_FETCHRO_V(x) ((x) << FW_EQ_OFLD_CMD_FETCHRO_S) 2119 #define FW_EQ_OFLD_CMD_FETCHRO_F FW_EQ_OFLD_CMD_FETCHRO_V(1U) 2120 2121 #define FW_EQ_OFLD_CMD_HOSTFCMODE_S 20 2122 #define FW_EQ_OFLD_CMD_HOSTFCMODE_V(x) ((x) << FW_EQ_OFLD_CMD_HOSTFCMODE_S) 2123 2124 #define FW_EQ_OFLD_CMD_CPRIO_S 19 2125 #define FW_EQ_OFLD_CMD_CPRIO_V(x) ((x) << FW_EQ_OFLD_CMD_CPRIO_S) 2126 2127 #define FW_EQ_OFLD_CMD_ONCHIP_S 18 2128 #define FW_EQ_OFLD_CMD_ONCHIP_V(x) ((x) << FW_EQ_OFLD_CMD_ONCHIP_S) 2129 2130 #define FW_EQ_OFLD_CMD_PCIECHN_S 16 2131 #define FW_EQ_OFLD_CMD_PCIECHN_V(x) ((x) << FW_EQ_OFLD_CMD_PCIECHN_S) 2132 2133 #define FW_EQ_OFLD_CMD_IQID_S 0 2134 #define FW_EQ_OFLD_CMD_IQID_V(x) ((x) << FW_EQ_OFLD_CMD_IQID_S) 2135 2136 #define FW_EQ_OFLD_CMD_DCAEN_S 31 2137 #define FW_EQ_OFLD_CMD_DCAEN_V(x) ((x) << FW_EQ_OFLD_CMD_DCAEN_S) 2138 2139 #define FW_EQ_OFLD_CMD_DCACPU_S 26 2140 #define FW_EQ_OFLD_CMD_DCACPU_V(x) ((x) << FW_EQ_OFLD_CMD_DCACPU_S) 2141 2142 #define FW_EQ_OFLD_CMD_FBMIN_S 23 2143 #define FW_EQ_OFLD_CMD_FBMIN_V(x) ((x) << FW_EQ_OFLD_CMD_FBMIN_S) 2144 2145 #define FW_EQ_OFLD_CMD_FBMAX_S 20 2146 #define FW_EQ_OFLD_CMD_FBMAX_V(x) ((x) << FW_EQ_OFLD_CMD_FBMAX_S) 2147 2148 #define FW_EQ_OFLD_CMD_CIDXFTHRESHO_S 19 2149 #define FW_EQ_OFLD_CMD_CIDXFTHRESHO_V(x) \ 2150 ((x) << FW_EQ_OFLD_CMD_CIDXFTHRESHO_S) 2151 2152 #define FW_EQ_OFLD_CMD_CIDXFTHRESH_S 16 2153 #define FW_EQ_OFLD_CMD_CIDXFTHRESH_V(x) ((x) << FW_EQ_OFLD_CMD_CIDXFTHRESH_S) 2154 2155 #define FW_EQ_OFLD_CMD_EQSIZE_S 0 2156 #define FW_EQ_OFLD_CMD_EQSIZE_V(x) ((x) << FW_EQ_OFLD_CMD_EQSIZE_S) 2157 2158 /* 2159 * Macros for VIID parsing: 2160 * VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number 2161 */ 2162 2163 #define FW_VIID_PFN_S 8 2164 #define FW_VIID_PFN_M 0x7 2165 #define FW_VIID_PFN_G(x) (((x) >> FW_VIID_PFN_S) & FW_VIID_PFN_M) 2166 2167 #define FW_VIID_VIVLD_S 7 2168 #define FW_VIID_VIVLD_M 0x1 2169 #define FW_VIID_VIVLD_G(x) (((x) >> FW_VIID_VIVLD_S) & FW_VIID_VIVLD_M) 2170 2171 #define FW_VIID_VIN_S 0 2172 #define FW_VIID_VIN_M 0x7F 2173 #define FW_VIID_VIN_G(x) (((x) >> FW_VIID_VIN_S) & FW_VIID_VIN_M) 2174 2175 struct fw_vi_cmd { 2176 __be32 op_to_vfn; 2177 __be32 alloc_to_len16; 2178 __be16 type_viid; 2179 u8 mac[6]; 2180 u8 portid_pkd; 2181 u8 nmac; 2182 u8 nmac0[6]; 2183 __be16 rsssize_pkd; 2184 u8 nmac1[6]; 2185 __be16 idsiiq_pkd; 2186 u8 nmac2[6]; 2187 __be16 idseiq_pkd; 2188 u8 nmac3[6]; 2189 __be64 r9; 2190 __be64 r10; 2191 }; 2192 2193 #define FW_VI_CMD_PFN_S 8 2194 #define FW_VI_CMD_PFN_V(x) ((x) << FW_VI_CMD_PFN_S) 2195 2196 #define FW_VI_CMD_VFN_S 0 2197 #define FW_VI_CMD_VFN_V(x) ((x) << FW_VI_CMD_VFN_S) 2198 2199 #define FW_VI_CMD_ALLOC_S 31 2200 #define FW_VI_CMD_ALLOC_V(x) ((x) << FW_VI_CMD_ALLOC_S) 2201 #define FW_VI_CMD_ALLOC_F FW_VI_CMD_ALLOC_V(1U) 2202 2203 #define FW_VI_CMD_FREE_S 30 2204 #define FW_VI_CMD_FREE_V(x) ((x) << FW_VI_CMD_FREE_S) 2205 #define FW_VI_CMD_FREE_F FW_VI_CMD_FREE_V(1U) 2206 2207 #define FW_VI_CMD_VFVLD_S 24 2208 #define FW_VI_CMD_VFVLD_M 0x1 2209 #define FW_VI_CMD_VFVLD_V(x) ((x) << FW_VI_CMD_VFVLD_S) 2210 #define FW_VI_CMD_VFVLD_G(x) \ 2211 (((x) >> FW_VI_CMD_VFVLD_S) & FW_VI_CMD_VFVLD_M) 2212 #define FW_VI_CMD_VFVLD_F FW_VI_CMD_VFVLD_V(1U) 2213 2214 #define FW_VI_CMD_VIN_S 16 2215 #define FW_VI_CMD_VIN_M 0xff 2216 #define FW_VI_CMD_VIN_V(x) ((x) << FW_VI_CMD_VIN_S) 2217 #define FW_VI_CMD_VIN_G(x) \ 2218 (((x) >> FW_VI_CMD_VIN_S) & FW_VI_CMD_VIN_M) 2219 2220 #define FW_VI_CMD_VIID_S 0 2221 #define FW_VI_CMD_VIID_M 0xfff 2222 #define FW_VI_CMD_VIID_V(x) ((x) << FW_VI_CMD_VIID_S) 2223 #define FW_VI_CMD_VIID_G(x) (((x) >> FW_VI_CMD_VIID_S) & FW_VI_CMD_VIID_M) 2224 2225 #define FW_VI_CMD_PORTID_S 4 2226 #define FW_VI_CMD_PORTID_M 0xf 2227 #define FW_VI_CMD_PORTID_V(x) ((x) << FW_VI_CMD_PORTID_S) 2228 #define FW_VI_CMD_PORTID_G(x) \ 2229 (((x) >> FW_VI_CMD_PORTID_S) & FW_VI_CMD_PORTID_M) 2230 2231 #define FW_VI_CMD_RSSSIZE_S 0 2232 #define FW_VI_CMD_RSSSIZE_M 0x7ff 2233 #define FW_VI_CMD_RSSSIZE_G(x) \ 2234 (((x) >> FW_VI_CMD_RSSSIZE_S) & FW_VI_CMD_RSSSIZE_M) 2235 2236 /* Special VI_MAC command index ids */ 2237 #define FW_VI_MAC_ADD_MAC 0x3FF 2238 #define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE 2239 #define FW_VI_MAC_MAC_BASED_FREE 0x3FD 2240 #define FW_VI_MAC_ID_BASED_FREE 0x3FC 2241 #define FW_CLS_TCAM_NUM_ENTRIES 336 2242 2243 enum fw_vi_mac_smac { 2244 FW_VI_MAC_MPS_TCAM_ENTRY, 2245 FW_VI_MAC_MPS_TCAM_ONLY, 2246 FW_VI_MAC_SMT_ONLY, 2247 FW_VI_MAC_SMT_AND_MPSTCAM 2248 }; 2249 2250 enum fw_vi_mac_result { 2251 FW_VI_MAC_R_SUCCESS, 2252 FW_VI_MAC_R_F_NONEXISTENT_NOMEM, 2253 FW_VI_MAC_R_SMAC_FAIL, 2254 FW_VI_MAC_R_F_ACL_CHECK 2255 }; 2256 2257 enum fw_vi_mac_entry_types { 2258 FW_VI_MAC_TYPE_EXACTMAC, 2259 FW_VI_MAC_TYPE_HASHVEC, 2260 FW_VI_MAC_TYPE_RAW, 2261 FW_VI_MAC_TYPE_EXACTMAC_VNI, 2262 }; 2263 2264 struct fw_vi_mac_cmd { 2265 __be32 op_to_viid; 2266 __be32 freemacs_to_len16; 2267 union fw_vi_mac { 2268 struct fw_vi_mac_exact { 2269 __be16 valid_to_idx; 2270 u8 macaddr[6]; 2271 } exact[7]; 2272 struct fw_vi_mac_hash { 2273 __be64 hashvec; 2274 } hash; 2275 struct fw_vi_mac_raw { 2276 __be32 raw_idx_pkd; 2277 __be32 data0_pkd; 2278 __be32 data1[2]; 2279 __be64 data0m_pkd; 2280 __be32 data1m[2]; 2281 } raw; 2282 struct fw_vi_mac_vni { 2283 __be16 valid_to_idx; 2284 __u8 macaddr[6]; 2285 __be16 r7; 2286 __u8 macaddr_mask[6]; 2287 __be32 lookup_type_to_vni; 2288 __be32 vni_mask_pkd; 2289 } exact_vni[2]; 2290 } u; 2291 }; 2292 2293 #define FW_VI_MAC_CMD_SMTID_S 12 2294 #define FW_VI_MAC_CMD_SMTID_M 0xff 2295 #define FW_VI_MAC_CMD_SMTID_V(x) ((x) << FW_VI_MAC_CMD_SMTID_S) 2296 #define FW_VI_MAC_CMD_SMTID_G(x) \ 2297 (((x) >> FW_VI_MAC_CMD_SMTID_S) & FW_VI_MAC_CMD_SMTID_M) 2298 2299 #define FW_VI_MAC_CMD_VIID_S 0 2300 #define FW_VI_MAC_CMD_VIID_V(x) ((x) << FW_VI_MAC_CMD_VIID_S) 2301 2302 #define FW_VI_MAC_CMD_FREEMACS_S 31 2303 #define FW_VI_MAC_CMD_FREEMACS_V(x) ((x) << FW_VI_MAC_CMD_FREEMACS_S) 2304 2305 #define FW_VI_MAC_CMD_ENTRY_TYPE_S 23 2306 #define FW_VI_MAC_CMD_ENTRY_TYPE_M 0x7 2307 #define FW_VI_MAC_CMD_ENTRY_TYPE_V(x) ((x) << FW_VI_MAC_CMD_ENTRY_TYPE_S) 2308 #define FW_VI_MAC_CMD_ENTRY_TYPE_G(x) \ 2309 (((x) >> FW_VI_MAC_CMD_ENTRY_TYPE_S) & FW_VI_MAC_CMD_ENTRY_TYPE_M) 2310 2311 #define FW_VI_MAC_CMD_HASHVECEN_S 23 2312 #define FW_VI_MAC_CMD_HASHVECEN_V(x) ((x) << FW_VI_MAC_CMD_HASHVECEN_S) 2313 #define FW_VI_MAC_CMD_HASHVECEN_F FW_VI_MAC_CMD_HASHVECEN_V(1U) 2314 2315 #define FW_VI_MAC_CMD_HASHUNIEN_S 22 2316 #define FW_VI_MAC_CMD_HASHUNIEN_V(x) ((x) << FW_VI_MAC_CMD_HASHUNIEN_S) 2317 2318 #define FW_VI_MAC_CMD_VALID_S 15 2319 #define FW_VI_MAC_CMD_VALID_V(x) ((x) << FW_VI_MAC_CMD_VALID_S) 2320 #define FW_VI_MAC_CMD_VALID_F FW_VI_MAC_CMD_VALID_V(1U) 2321 2322 #define FW_VI_MAC_CMD_PRIO_S 12 2323 #define FW_VI_MAC_CMD_PRIO_V(x) ((x) << FW_VI_MAC_CMD_PRIO_S) 2324 2325 #define FW_VI_MAC_CMD_SMAC_RESULT_S 10 2326 #define FW_VI_MAC_CMD_SMAC_RESULT_M 0x3 2327 #define FW_VI_MAC_CMD_SMAC_RESULT_V(x) ((x) << FW_VI_MAC_CMD_SMAC_RESULT_S) 2328 #define FW_VI_MAC_CMD_SMAC_RESULT_G(x) \ 2329 (((x) >> FW_VI_MAC_CMD_SMAC_RESULT_S) & FW_VI_MAC_CMD_SMAC_RESULT_M) 2330 2331 #define FW_VI_MAC_CMD_IDX_S 0 2332 #define FW_VI_MAC_CMD_IDX_M 0x3ff 2333 #define FW_VI_MAC_CMD_IDX_V(x) ((x) << FW_VI_MAC_CMD_IDX_S) 2334 #define FW_VI_MAC_CMD_IDX_G(x) \ 2335 (((x) >> FW_VI_MAC_CMD_IDX_S) & FW_VI_MAC_CMD_IDX_M) 2336 2337 #define FW_VI_MAC_CMD_RAW_IDX_S 16 2338 #define FW_VI_MAC_CMD_RAW_IDX_M 0xffff 2339 #define FW_VI_MAC_CMD_RAW_IDX_V(x) ((x) << FW_VI_MAC_CMD_RAW_IDX_S) 2340 #define FW_VI_MAC_CMD_RAW_IDX_G(x) \ 2341 (((x) >> FW_VI_MAC_CMD_RAW_IDX_S) & FW_VI_MAC_CMD_RAW_IDX_M) 2342 2343 #define FW_VI_MAC_CMD_LOOKUP_TYPE_S 31 2344 #define FW_VI_MAC_CMD_LOOKUP_TYPE_M 0x1 2345 #define FW_VI_MAC_CMD_LOOKUP_TYPE_V(x) ((x) << FW_VI_MAC_CMD_LOOKUP_TYPE_S) 2346 #define FW_VI_MAC_CMD_LOOKUP_TYPE_G(x) \ 2347 (((x) >> FW_VI_MAC_CMD_LOOKUP_TYPE_S) & FW_VI_MAC_CMD_LOOKUP_TYPE_M) 2348 #define FW_VI_MAC_CMD_LOOKUP_TYPE_F FW_VI_MAC_CMD_LOOKUP_TYPE_V(1U) 2349 2350 #define FW_VI_MAC_CMD_DIP_HIT_S 30 2351 #define FW_VI_MAC_CMD_DIP_HIT_M 0x1 2352 #define FW_VI_MAC_CMD_DIP_HIT_V(x) ((x) << FW_VI_MAC_CMD_DIP_HIT_S) 2353 #define FW_VI_MAC_CMD_DIP_HIT_G(x) \ 2354 (((x) >> FW_VI_MAC_CMD_DIP_HIT_S) & FW_VI_MAC_CMD_DIP_HIT_M) 2355 #define FW_VI_MAC_CMD_DIP_HIT_F FW_VI_MAC_CMD_DIP_HIT_V(1U) 2356 2357 #define FW_VI_MAC_CMD_VNI_S 0 2358 #define FW_VI_MAC_CMD_VNI_M 0xffffff 2359 #define FW_VI_MAC_CMD_VNI_V(x) ((x) << FW_VI_MAC_CMD_VNI_S) 2360 #define FW_VI_MAC_CMD_VNI_G(x) \ 2361 (((x) >> FW_VI_MAC_CMD_VNI_S) & FW_VI_MAC_CMD_VNI_M) 2362 2363 #define FW_VI_MAC_CMD_VNI_MASK_S 0 2364 #define FW_VI_MAC_CMD_VNI_MASK_M 0xffffff 2365 #define FW_VI_MAC_CMD_VNI_MASK_V(x) ((x) << FW_VI_MAC_CMD_VNI_MASK_S) 2366 #define FW_VI_MAC_CMD_VNI_MASK_G(x) \ 2367 (((x) >> FW_VI_MAC_CMD_VNI_MASK_S) & FW_VI_MAC_CMD_VNI_MASK_M) 2368 2369 #define FW_RXMODE_MTU_NO_CHG 65535 2370 2371 struct fw_vi_rxmode_cmd { 2372 __be32 op_to_viid; 2373 __be32 retval_len16; 2374 __be32 mtu_to_vlanexen; 2375 __be32 r4_lo; 2376 }; 2377 2378 #define FW_VI_RXMODE_CMD_VIID_S 0 2379 #define FW_VI_RXMODE_CMD_VIID_V(x) ((x) << FW_VI_RXMODE_CMD_VIID_S) 2380 2381 #define FW_VI_RXMODE_CMD_MTU_S 16 2382 #define FW_VI_RXMODE_CMD_MTU_M 0xffff 2383 #define FW_VI_RXMODE_CMD_MTU_V(x) ((x) << FW_VI_RXMODE_CMD_MTU_S) 2384 2385 #define FW_VI_RXMODE_CMD_PROMISCEN_S 14 2386 #define FW_VI_RXMODE_CMD_PROMISCEN_M 0x3 2387 #define FW_VI_RXMODE_CMD_PROMISCEN_V(x) ((x) << FW_VI_RXMODE_CMD_PROMISCEN_S) 2388 2389 #define FW_VI_RXMODE_CMD_ALLMULTIEN_S 12 2390 #define FW_VI_RXMODE_CMD_ALLMULTIEN_M 0x3 2391 #define FW_VI_RXMODE_CMD_ALLMULTIEN_V(x) \ 2392 ((x) << FW_VI_RXMODE_CMD_ALLMULTIEN_S) 2393 2394 #define FW_VI_RXMODE_CMD_BROADCASTEN_S 10 2395 #define FW_VI_RXMODE_CMD_BROADCASTEN_M 0x3 2396 #define FW_VI_RXMODE_CMD_BROADCASTEN_V(x) \ 2397 ((x) << FW_VI_RXMODE_CMD_BROADCASTEN_S) 2398 2399 #define FW_VI_RXMODE_CMD_VLANEXEN_S 8 2400 #define FW_VI_RXMODE_CMD_VLANEXEN_M 0x3 2401 #define FW_VI_RXMODE_CMD_VLANEXEN_V(x) ((x) << FW_VI_RXMODE_CMD_VLANEXEN_S) 2402 2403 struct fw_vi_enable_cmd { 2404 __be32 op_to_viid; 2405 __be32 ien_to_len16; 2406 __be16 blinkdur; 2407 __be16 r3; 2408 __be32 r4; 2409 }; 2410 2411 #define FW_VI_ENABLE_CMD_VIID_S 0 2412 #define FW_VI_ENABLE_CMD_VIID_V(x) ((x) << FW_VI_ENABLE_CMD_VIID_S) 2413 2414 #define FW_VI_ENABLE_CMD_IEN_S 31 2415 #define FW_VI_ENABLE_CMD_IEN_V(x) ((x) << FW_VI_ENABLE_CMD_IEN_S) 2416 2417 #define FW_VI_ENABLE_CMD_EEN_S 30 2418 #define FW_VI_ENABLE_CMD_EEN_V(x) ((x) << FW_VI_ENABLE_CMD_EEN_S) 2419 2420 #define FW_VI_ENABLE_CMD_LED_S 29 2421 #define FW_VI_ENABLE_CMD_LED_V(x) ((x) << FW_VI_ENABLE_CMD_LED_S) 2422 #define FW_VI_ENABLE_CMD_LED_F FW_VI_ENABLE_CMD_LED_V(1U) 2423 2424 #define FW_VI_ENABLE_CMD_DCB_INFO_S 28 2425 #define FW_VI_ENABLE_CMD_DCB_INFO_V(x) ((x) << FW_VI_ENABLE_CMD_DCB_INFO_S) 2426 2427 /* VI VF stats offset definitions */ 2428 #define VI_VF_NUM_STATS 16 2429 enum fw_vi_stats_vf_index { 2430 FW_VI_VF_STAT_TX_BCAST_BYTES_IX, 2431 FW_VI_VF_STAT_TX_BCAST_FRAMES_IX, 2432 FW_VI_VF_STAT_TX_MCAST_BYTES_IX, 2433 FW_VI_VF_STAT_TX_MCAST_FRAMES_IX, 2434 FW_VI_VF_STAT_TX_UCAST_BYTES_IX, 2435 FW_VI_VF_STAT_TX_UCAST_FRAMES_IX, 2436 FW_VI_VF_STAT_TX_DROP_FRAMES_IX, 2437 FW_VI_VF_STAT_TX_OFLD_BYTES_IX, 2438 FW_VI_VF_STAT_TX_OFLD_FRAMES_IX, 2439 FW_VI_VF_STAT_RX_BCAST_BYTES_IX, 2440 FW_VI_VF_STAT_RX_BCAST_FRAMES_IX, 2441 FW_VI_VF_STAT_RX_MCAST_BYTES_IX, 2442 FW_VI_VF_STAT_RX_MCAST_FRAMES_IX, 2443 FW_VI_VF_STAT_RX_UCAST_BYTES_IX, 2444 FW_VI_VF_STAT_RX_UCAST_FRAMES_IX, 2445 FW_VI_VF_STAT_RX_ERR_FRAMES_IX 2446 }; 2447 2448 /* VI PF stats offset definitions */ 2449 #define VI_PF_NUM_STATS 17 2450 enum fw_vi_stats_pf_index { 2451 FW_VI_PF_STAT_TX_BCAST_BYTES_IX, 2452 FW_VI_PF_STAT_TX_BCAST_FRAMES_IX, 2453 FW_VI_PF_STAT_TX_MCAST_BYTES_IX, 2454 FW_VI_PF_STAT_TX_MCAST_FRAMES_IX, 2455 FW_VI_PF_STAT_TX_UCAST_BYTES_IX, 2456 FW_VI_PF_STAT_TX_UCAST_FRAMES_IX, 2457 FW_VI_PF_STAT_TX_OFLD_BYTES_IX, 2458 FW_VI_PF_STAT_TX_OFLD_FRAMES_IX, 2459 FW_VI_PF_STAT_RX_BYTES_IX, 2460 FW_VI_PF_STAT_RX_FRAMES_IX, 2461 FW_VI_PF_STAT_RX_BCAST_BYTES_IX, 2462 FW_VI_PF_STAT_RX_BCAST_FRAMES_IX, 2463 FW_VI_PF_STAT_RX_MCAST_BYTES_IX, 2464 FW_VI_PF_STAT_RX_MCAST_FRAMES_IX, 2465 FW_VI_PF_STAT_RX_UCAST_BYTES_IX, 2466 FW_VI_PF_STAT_RX_UCAST_FRAMES_IX, 2467 FW_VI_PF_STAT_RX_ERR_FRAMES_IX 2468 }; 2469 2470 struct fw_vi_stats_cmd { 2471 __be32 op_to_viid; 2472 __be32 retval_len16; 2473 union fw_vi_stats { 2474 struct fw_vi_stats_ctl { 2475 __be16 nstats_ix; 2476 __be16 r6; 2477 __be32 r7; 2478 __be64 stat0; 2479 __be64 stat1; 2480 __be64 stat2; 2481 __be64 stat3; 2482 __be64 stat4; 2483 __be64 stat5; 2484 } ctl; 2485 struct fw_vi_stats_pf { 2486 __be64 tx_bcast_bytes; 2487 __be64 tx_bcast_frames; 2488 __be64 tx_mcast_bytes; 2489 __be64 tx_mcast_frames; 2490 __be64 tx_ucast_bytes; 2491 __be64 tx_ucast_frames; 2492 __be64 tx_offload_bytes; 2493 __be64 tx_offload_frames; 2494 __be64 rx_pf_bytes; 2495 __be64 rx_pf_frames; 2496 __be64 rx_bcast_bytes; 2497 __be64 rx_bcast_frames; 2498 __be64 rx_mcast_bytes; 2499 __be64 rx_mcast_frames; 2500 __be64 rx_ucast_bytes; 2501 __be64 rx_ucast_frames; 2502 __be64 rx_err_frames; 2503 } pf; 2504 struct fw_vi_stats_vf { 2505 __be64 tx_bcast_bytes; 2506 __be64 tx_bcast_frames; 2507 __be64 tx_mcast_bytes; 2508 __be64 tx_mcast_frames; 2509 __be64 tx_ucast_bytes; 2510 __be64 tx_ucast_frames; 2511 __be64 tx_drop_frames; 2512 __be64 tx_offload_bytes; 2513 __be64 tx_offload_frames; 2514 __be64 rx_bcast_bytes; 2515 __be64 rx_bcast_frames; 2516 __be64 rx_mcast_bytes; 2517 __be64 rx_mcast_frames; 2518 __be64 rx_ucast_bytes; 2519 __be64 rx_ucast_frames; 2520 __be64 rx_err_frames; 2521 } vf; 2522 } u; 2523 }; 2524 2525 #define FW_VI_STATS_CMD_VIID_S 0 2526 #define FW_VI_STATS_CMD_VIID_V(x) ((x) << FW_VI_STATS_CMD_VIID_S) 2527 2528 #define FW_VI_STATS_CMD_NSTATS_S 12 2529 #define FW_VI_STATS_CMD_NSTATS_V(x) ((x) << FW_VI_STATS_CMD_NSTATS_S) 2530 2531 #define FW_VI_STATS_CMD_IX_S 0 2532 #define FW_VI_STATS_CMD_IX_V(x) ((x) << FW_VI_STATS_CMD_IX_S) 2533 2534 struct fw_acl_mac_cmd { 2535 __be32 op_to_vfn; 2536 __be32 en_to_len16; 2537 u8 nmac; 2538 u8 r3[7]; 2539 __be16 r4; 2540 u8 macaddr0[6]; 2541 __be16 r5; 2542 u8 macaddr1[6]; 2543 __be16 r6; 2544 u8 macaddr2[6]; 2545 __be16 r7; 2546 u8 macaddr3[6]; 2547 }; 2548 2549 #define FW_ACL_MAC_CMD_PFN_S 8 2550 #define FW_ACL_MAC_CMD_PFN_V(x) ((x) << FW_ACL_MAC_CMD_PFN_S) 2551 2552 #define FW_ACL_MAC_CMD_VFN_S 0 2553 #define FW_ACL_MAC_CMD_VFN_V(x) ((x) << FW_ACL_MAC_CMD_VFN_S) 2554 2555 #define FW_ACL_MAC_CMD_EN_S 31 2556 #define FW_ACL_MAC_CMD_EN_V(x) ((x) << FW_ACL_MAC_CMD_EN_S) 2557 2558 struct fw_acl_vlan_cmd { 2559 __be32 op_to_vfn; 2560 __be32 en_to_len16; 2561 u8 nvlan; 2562 u8 dropnovlan_fm; 2563 u8 r3_lo[6]; 2564 __be16 vlanid[16]; 2565 }; 2566 2567 #define FW_ACL_VLAN_CMD_PFN_S 8 2568 #define FW_ACL_VLAN_CMD_PFN_V(x) ((x) << FW_ACL_VLAN_CMD_PFN_S) 2569 2570 #define FW_ACL_VLAN_CMD_VFN_S 0 2571 #define FW_ACL_VLAN_CMD_VFN_V(x) ((x) << FW_ACL_VLAN_CMD_VFN_S) 2572 2573 #define FW_ACL_VLAN_CMD_EN_S 31 2574 #define FW_ACL_VLAN_CMD_EN_M 0x1 2575 #define FW_ACL_VLAN_CMD_EN_V(x) ((x) << FW_ACL_VLAN_CMD_EN_S) 2576 #define FW_ACL_VLAN_CMD_EN_G(x) \ 2577 (((x) >> S_FW_ACL_VLAN_CMD_EN_S) & FW_ACL_VLAN_CMD_EN_M) 2578 #define FW_ACL_VLAN_CMD_EN_F FW_ACL_VLAN_CMD_EN_V(1U) 2579 2580 #define FW_ACL_VLAN_CMD_DROPNOVLAN_S 7 2581 #define FW_ACL_VLAN_CMD_DROPNOVLAN_V(x) ((x) << FW_ACL_VLAN_CMD_DROPNOVLAN_S) 2582 #define FW_ACL_VLAN_CMD_DROPNOVLAN_F FW_ACL_VLAN_CMD_DROPNOVLAN_V(1U) 2583 2584 #define FW_ACL_VLAN_CMD_FM_S 6 2585 #define FW_ACL_VLAN_CMD_FM_M 0x1 2586 #define FW_ACL_VLAN_CMD_FM_V(x) ((x) << FW_ACL_VLAN_CMD_FM_S) 2587 #define FW_ACL_VLAN_CMD_FM_G(x) \ 2588 (((x) >> FW_ACL_VLAN_CMD_FM_S) & FW_ACL_VLAN_CMD_FM_M) 2589 #define FW_ACL_VLAN_CMD_FM_F FW_ACL_VLAN_CMD_FM_V(1U) 2590 2591 /* old 16-bit port capabilities bitmap (fw_port_cap16_t) */ 2592 enum fw_port_cap { 2593 FW_PORT_CAP_SPEED_100M = 0x0001, 2594 FW_PORT_CAP_SPEED_1G = 0x0002, 2595 FW_PORT_CAP_SPEED_25G = 0x0004, 2596 FW_PORT_CAP_SPEED_10G = 0x0008, 2597 FW_PORT_CAP_SPEED_40G = 0x0010, 2598 FW_PORT_CAP_SPEED_100G = 0x0020, 2599 FW_PORT_CAP_FC_RX = 0x0040, 2600 FW_PORT_CAP_FC_TX = 0x0080, 2601 FW_PORT_CAP_ANEG = 0x0100, 2602 FW_PORT_CAP_MDIAUTO = 0x0200, 2603 FW_PORT_CAP_MDISTRAIGHT = 0x0400, 2604 FW_PORT_CAP_FEC_RS = 0x0800, 2605 FW_PORT_CAP_FEC_BASER_RS = 0x1000, 2606 FW_PORT_CAP_FORCE_PAUSE = 0x2000, 2607 FW_PORT_CAP_802_3_PAUSE = 0x4000, 2608 FW_PORT_CAP_802_3_ASM_DIR = 0x8000, 2609 }; 2610 2611 #define FW_PORT_CAP_SPEED_S 0 2612 #define FW_PORT_CAP_SPEED_M 0x3f 2613 #define FW_PORT_CAP_SPEED_V(x) ((x) << FW_PORT_CAP_SPEED_S) 2614 #define FW_PORT_CAP_SPEED_G(x) \ 2615 (((x) >> FW_PORT_CAP_SPEED_S) & FW_PORT_CAP_SPEED_M) 2616 2617 enum fw_port_mdi { 2618 FW_PORT_CAP_MDI_UNCHANGED, 2619 FW_PORT_CAP_MDI_AUTO, 2620 FW_PORT_CAP_MDI_F_STRAIGHT, 2621 FW_PORT_CAP_MDI_F_CROSSOVER 2622 }; 2623 2624 #define FW_PORT_CAP_MDI_S 9 2625 #define FW_PORT_CAP_MDI_V(x) ((x) << FW_PORT_CAP_MDI_S) 2626 2627 /* new 32-bit port capabilities bitmap (fw_port_cap32_t) */ 2628 #define FW_PORT_CAP32_SPEED_100M 0x00000001UL 2629 #define FW_PORT_CAP32_SPEED_1G 0x00000002UL 2630 #define FW_PORT_CAP32_SPEED_10G 0x00000004UL 2631 #define FW_PORT_CAP32_SPEED_25G 0x00000008UL 2632 #define FW_PORT_CAP32_SPEED_40G 0x00000010UL 2633 #define FW_PORT_CAP32_SPEED_50G 0x00000020UL 2634 #define FW_PORT_CAP32_SPEED_100G 0x00000040UL 2635 #define FW_PORT_CAP32_SPEED_200G 0x00000080UL 2636 #define FW_PORT_CAP32_SPEED_400G 0x00000100UL 2637 #define FW_PORT_CAP32_SPEED_RESERVED1 0x00000200UL 2638 #define FW_PORT_CAP32_SPEED_RESERVED2 0x00000400UL 2639 #define FW_PORT_CAP32_SPEED_RESERVED3 0x00000800UL 2640 #define FW_PORT_CAP32_RESERVED1 0x0000f000UL 2641 #define FW_PORT_CAP32_FC_RX 0x00010000UL 2642 #define FW_PORT_CAP32_FC_TX 0x00020000UL 2643 #define FW_PORT_CAP32_802_3_PAUSE 0x00040000UL 2644 #define FW_PORT_CAP32_802_3_ASM_DIR 0x00080000UL 2645 #define FW_PORT_CAP32_ANEG 0x00100000UL 2646 #define FW_PORT_CAP32_MDIAUTO 0x00200000UL 2647 #define FW_PORT_CAP32_MDISTRAIGHT 0x00400000UL 2648 #define FW_PORT_CAP32_FEC_RS 0x00800000UL 2649 #define FW_PORT_CAP32_FEC_BASER_RS 0x01000000UL 2650 #define FW_PORT_CAP32_FEC_RESERVED1 0x02000000UL 2651 #define FW_PORT_CAP32_FEC_RESERVED2 0x04000000UL 2652 #define FW_PORT_CAP32_FEC_RESERVED3 0x08000000UL 2653 #define FW_PORT_CAP32_FORCE_PAUSE 0x10000000UL 2654 #define FW_PORT_CAP32_RESERVED2 0xe0000000UL 2655 2656 #define FW_PORT_CAP32_SPEED_S 0 2657 #define FW_PORT_CAP32_SPEED_M 0xfff 2658 #define FW_PORT_CAP32_SPEED_V(x) ((x) << FW_PORT_CAP32_SPEED_S) 2659 #define FW_PORT_CAP32_SPEED_G(x) \ 2660 (((x) >> FW_PORT_CAP32_SPEED_S) & FW_PORT_CAP32_SPEED_M) 2661 2662 #define FW_PORT_CAP32_FC_S 16 2663 #define FW_PORT_CAP32_FC_M 0x3 2664 #define FW_PORT_CAP32_FC_V(x) ((x) << FW_PORT_CAP32_FC_S) 2665 #define FW_PORT_CAP32_FC_G(x) \ 2666 (((x) >> FW_PORT_CAP32_FC_S) & FW_PORT_CAP32_FC_M) 2667 2668 #define FW_PORT_CAP32_802_3_S 18 2669 #define FW_PORT_CAP32_802_3_M 0x3 2670 #define FW_PORT_CAP32_802_3_V(x) ((x) << FW_PORT_CAP32_802_3_S) 2671 #define FW_PORT_CAP32_802_3_G(x) \ 2672 (((x) >> FW_PORT_CAP32_802_3_S) & FW_PORT_CAP32_802_3_M) 2673 2674 #define FW_PORT_CAP32_ANEG_S 20 2675 #define FW_PORT_CAP32_ANEG_M 0x1 2676 #define FW_PORT_CAP32_ANEG_V(x) ((x) << FW_PORT_CAP32_ANEG_S) 2677 #define FW_PORT_CAP32_ANEG_G(x) \ 2678 (((x) >> FW_PORT_CAP32_ANEG_S) & FW_PORT_CAP32_ANEG_M) 2679 2680 enum fw_port_mdi32 { 2681 FW_PORT_CAP32_MDI_UNCHANGED, 2682 FW_PORT_CAP32_MDI_AUTO, 2683 FW_PORT_CAP32_MDI_F_STRAIGHT, 2684 FW_PORT_CAP32_MDI_F_CROSSOVER 2685 }; 2686 2687 #define FW_PORT_CAP32_MDI_S 21 2688 #define FW_PORT_CAP32_MDI_M 3 2689 #define FW_PORT_CAP32_MDI_V(x) ((x) << FW_PORT_CAP32_MDI_S) 2690 #define FW_PORT_CAP32_MDI_G(x) \ 2691 (((x) >> FW_PORT_CAP32_MDI_S) & FW_PORT_CAP32_MDI_M) 2692 2693 #define FW_PORT_CAP32_FEC_S 23 2694 #define FW_PORT_CAP32_FEC_M 0x1f 2695 #define FW_PORT_CAP32_FEC_V(x) ((x) << FW_PORT_CAP32_FEC_S) 2696 #define FW_PORT_CAP32_FEC_G(x) \ 2697 (((x) >> FW_PORT_CAP32_FEC_S) & FW_PORT_CAP32_FEC_M) 2698 2699 /* macros to isolate various 32-bit Port Capabilities sub-fields */ 2700 #define CAP32_SPEED(__cap32) \ 2701 (FW_PORT_CAP32_SPEED_V(FW_PORT_CAP32_SPEED_M) & __cap32) 2702 2703 #define CAP32_FEC(__cap32) \ 2704 (FW_PORT_CAP32_FEC_V(FW_PORT_CAP32_FEC_M) & __cap32) 2705 2706 enum fw_port_action { 2707 FW_PORT_ACTION_L1_CFG = 0x0001, 2708 FW_PORT_ACTION_L2_CFG = 0x0002, 2709 FW_PORT_ACTION_GET_PORT_INFO = 0x0003, 2710 FW_PORT_ACTION_L2_PPP_CFG = 0x0004, 2711 FW_PORT_ACTION_L2_DCB_CFG = 0x0005, 2712 FW_PORT_ACTION_DCB_READ_TRANS = 0x0006, 2713 FW_PORT_ACTION_DCB_READ_RECV = 0x0007, 2714 FW_PORT_ACTION_DCB_READ_DET = 0x0008, 2715 FW_PORT_ACTION_L1_CFG32 = 0x0009, 2716 FW_PORT_ACTION_GET_PORT_INFO32 = 0x000a, 2717 FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010, 2718 FW_PORT_ACTION_L1_LOW_PWR_EN = 0x0011, 2719 FW_PORT_ACTION_L2_WOL_MODE_EN = 0x0012, 2720 FW_PORT_ACTION_LPBK_TO_NORMAL = 0x0020, 2721 FW_PORT_ACTION_L1_LPBK = 0x0021, 2722 FW_PORT_ACTION_L1_PMA_LPBK = 0x0022, 2723 FW_PORT_ACTION_L1_PCS_LPBK = 0x0023, 2724 FW_PORT_ACTION_L1_PHYXS_CSIDE_LPBK = 0x0024, 2725 FW_PORT_ACTION_L1_PHYXS_ESIDE_LPBK = 0x0025, 2726 FW_PORT_ACTION_PHY_RESET = 0x0040, 2727 FW_PORT_ACTION_PMA_RESET = 0x0041, 2728 FW_PORT_ACTION_PCS_RESET = 0x0042, 2729 FW_PORT_ACTION_PHYXS_RESET = 0x0043, 2730 FW_PORT_ACTION_DTEXS_REEST = 0x0044, 2731 FW_PORT_ACTION_AN_RESET = 0x0045 2732 }; 2733 2734 enum fw_port_l2cfg_ctlbf { 2735 FW_PORT_L2_CTLBF_OVLAN0 = 0x01, 2736 FW_PORT_L2_CTLBF_OVLAN1 = 0x02, 2737 FW_PORT_L2_CTLBF_OVLAN2 = 0x04, 2738 FW_PORT_L2_CTLBF_OVLAN3 = 0x08, 2739 FW_PORT_L2_CTLBF_IVLAN = 0x10, 2740 FW_PORT_L2_CTLBF_TXIPG = 0x20 2741 }; 2742 2743 enum fw_port_dcb_versions { 2744 FW_PORT_DCB_VER_UNKNOWN, 2745 FW_PORT_DCB_VER_CEE1D0, 2746 FW_PORT_DCB_VER_CEE1D01, 2747 FW_PORT_DCB_VER_IEEE, 2748 FW_PORT_DCB_VER_AUTO = 7 2749 }; 2750 2751 enum fw_port_dcb_cfg { 2752 FW_PORT_DCB_CFG_PG = 0x01, 2753 FW_PORT_DCB_CFG_PFC = 0x02, 2754 FW_PORT_DCB_CFG_APPL = 0x04 2755 }; 2756 2757 enum fw_port_dcb_cfg_rc { 2758 FW_PORT_DCB_CFG_SUCCESS = 0x0, 2759 FW_PORT_DCB_CFG_ERROR = 0x1 2760 }; 2761 2762 enum fw_port_dcb_type { 2763 FW_PORT_DCB_TYPE_PGID = 0x00, 2764 FW_PORT_DCB_TYPE_PGRATE = 0x01, 2765 FW_PORT_DCB_TYPE_PRIORATE = 0x02, 2766 FW_PORT_DCB_TYPE_PFC = 0x03, 2767 FW_PORT_DCB_TYPE_APP_ID = 0x04, 2768 FW_PORT_DCB_TYPE_CONTROL = 0x05, 2769 }; 2770 2771 enum fw_port_dcb_feature_state { 2772 FW_PORT_DCB_FEATURE_STATE_PENDING = 0x0, 2773 FW_PORT_DCB_FEATURE_STATE_SUCCESS = 0x1, 2774 FW_PORT_DCB_FEATURE_STATE_ERROR = 0x2, 2775 FW_PORT_DCB_FEATURE_STATE_TIMEOUT = 0x3, 2776 }; 2777 2778 struct fw_port_cmd { 2779 __be32 op_to_portid; 2780 __be32 action_to_len16; 2781 union fw_port { 2782 struct fw_port_l1cfg { 2783 __be32 rcap; 2784 __be32 r; 2785 } l1cfg; 2786 struct fw_port_l2cfg { 2787 __u8 ctlbf; 2788 __u8 ovlan3_to_ivlan0; 2789 __be16 ivlantype; 2790 __be16 txipg_force_pinfo; 2791 __be16 mtu; 2792 __be16 ovlan0mask; 2793 __be16 ovlan0type; 2794 __be16 ovlan1mask; 2795 __be16 ovlan1type; 2796 __be16 ovlan2mask; 2797 __be16 ovlan2type; 2798 __be16 ovlan3mask; 2799 __be16 ovlan3type; 2800 } l2cfg; 2801 struct fw_port_info { 2802 __be32 lstatus_to_modtype; 2803 __be16 pcap; 2804 __be16 acap; 2805 __be16 mtu; 2806 __u8 cbllen; 2807 __u8 auxlinfo; 2808 __u8 dcbxdis_pkd; 2809 __u8 r8_lo; 2810 __be16 lpacap; 2811 __be64 r9; 2812 } info; 2813 struct fw_port_diags { 2814 __u8 diagop; 2815 __u8 r[3]; 2816 __be32 diagval; 2817 } diags; 2818 union fw_port_dcb { 2819 struct fw_port_dcb_pgid { 2820 __u8 type; 2821 __u8 apply_pkd; 2822 __u8 r10_lo[2]; 2823 __be32 pgid; 2824 __be64 r11; 2825 } pgid; 2826 struct fw_port_dcb_pgrate { 2827 __u8 type; 2828 __u8 apply_pkd; 2829 __u8 r10_lo[5]; 2830 __u8 num_tcs_supported; 2831 __u8 pgrate[8]; 2832 __u8 tsa[8]; 2833 } pgrate; 2834 struct fw_port_dcb_priorate { 2835 __u8 type; 2836 __u8 apply_pkd; 2837 __u8 r10_lo[6]; 2838 __u8 strict_priorate[8]; 2839 } priorate; 2840 struct fw_port_dcb_pfc { 2841 __u8 type; 2842 __u8 pfcen; 2843 __u8 r10[5]; 2844 __u8 max_pfc_tcs; 2845 __be64 r11; 2846 } pfc; 2847 struct fw_port_app_priority { 2848 __u8 type; 2849 __u8 r10[2]; 2850 __u8 idx; 2851 __u8 user_prio_map; 2852 __u8 sel_field; 2853 __be16 protocolid; 2854 __be64 r12; 2855 } app_priority; 2856 struct fw_port_dcb_control { 2857 __u8 type; 2858 __u8 all_syncd_pkd; 2859 __be16 dcb_version_to_app_state; 2860 __be32 r11; 2861 __be64 r12; 2862 } control; 2863 } dcb; 2864 struct fw_port_l1cfg32 { 2865 __be32 rcap32; 2866 __be32 r; 2867 } l1cfg32; 2868 struct fw_port_info32 { 2869 __be32 lstatus32_to_cbllen32; 2870 __be32 auxlinfo32_mtu32; 2871 __be32 linkattr32; 2872 __be32 pcaps32; 2873 __be32 acaps32; 2874 __be32 lpacaps32; 2875 } info32; 2876 } u; 2877 }; 2878 2879 #define FW_PORT_CMD_READ_S 22 2880 #define FW_PORT_CMD_READ_V(x) ((x) << FW_PORT_CMD_READ_S) 2881 #define FW_PORT_CMD_READ_F FW_PORT_CMD_READ_V(1U) 2882 2883 #define FW_PORT_CMD_PORTID_S 0 2884 #define FW_PORT_CMD_PORTID_M 0xf 2885 #define FW_PORT_CMD_PORTID_V(x) ((x) << FW_PORT_CMD_PORTID_S) 2886 #define FW_PORT_CMD_PORTID_G(x) \ 2887 (((x) >> FW_PORT_CMD_PORTID_S) & FW_PORT_CMD_PORTID_M) 2888 2889 #define FW_PORT_CMD_ACTION_S 16 2890 #define FW_PORT_CMD_ACTION_M 0xffff 2891 #define FW_PORT_CMD_ACTION_V(x) ((x) << FW_PORT_CMD_ACTION_S) 2892 #define FW_PORT_CMD_ACTION_G(x) \ 2893 (((x) >> FW_PORT_CMD_ACTION_S) & FW_PORT_CMD_ACTION_M) 2894 2895 #define FW_PORT_CMD_OVLAN3_S 7 2896 #define FW_PORT_CMD_OVLAN3_V(x) ((x) << FW_PORT_CMD_OVLAN3_S) 2897 2898 #define FW_PORT_CMD_OVLAN2_S 6 2899 #define FW_PORT_CMD_OVLAN2_V(x) ((x) << FW_PORT_CMD_OVLAN2_S) 2900 2901 #define FW_PORT_CMD_OVLAN1_S 5 2902 #define FW_PORT_CMD_OVLAN1_V(x) ((x) << FW_PORT_CMD_OVLAN1_S) 2903 2904 #define FW_PORT_CMD_OVLAN0_S 4 2905 #define FW_PORT_CMD_OVLAN0_V(x) ((x) << FW_PORT_CMD_OVLAN0_S) 2906 2907 #define FW_PORT_CMD_IVLAN0_S 3 2908 #define FW_PORT_CMD_IVLAN0_V(x) ((x) << FW_PORT_CMD_IVLAN0_S) 2909 2910 #define FW_PORT_CMD_TXIPG_S 3 2911 #define FW_PORT_CMD_TXIPG_V(x) ((x) << FW_PORT_CMD_TXIPG_S) 2912 2913 #define FW_PORT_CMD_LSTATUS_S 31 2914 #define FW_PORT_CMD_LSTATUS_M 0x1 2915 #define FW_PORT_CMD_LSTATUS_V(x) ((x) << FW_PORT_CMD_LSTATUS_S) 2916 #define FW_PORT_CMD_LSTATUS_G(x) \ 2917 (((x) >> FW_PORT_CMD_LSTATUS_S) & FW_PORT_CMD_LSTATUS_M) 2918 #define FW_PORT_CMD_LSTATUS_F FW_PORT_CMD_LSTATUS_V(1U) 2919 2920 #define FW_PORT_CMD_LSPEED_S 24 2921 #define FW_PORT_CMD_LSPEED_M 0x3f 2922 #define FW_PORT_CMD_LSPEED_V(x) ((x) << FW_PORT_CMD_LSPEED_S) 2923 #define FW_PORT_CMD_LSPEED_G(x) \ 2924 (((x) >> FW_PORT_CMD_LSPEED_S) & FW_PORT_CMD_LSPEED_M) 2925 2926 #define FW_PORT_CMD_TXPAUSE_S 23 2927 #define FW_PORT_CMD_TXPAUSE_V(x) ((x) << FW_PORT_CMD_TXPAUSE_S) 2928 #define FW_PORT_CMD_TXPAUSE_F FW_PORT_CMD_TXPAUSE_V(1U) 2929 2930 #define FW_PORT_CMD_RXPAUSE_S 22 2931 #define FW_PORT_CMD_RXPAUSE_V(x) ((x) << FW_PORT_CMD_RXPAUSE_S) 2932 #define FW_PORT_CMD_RXPAUSE_F FW_PORT_CMD_RXPAUSE_V(1U) 2933 2934 #define FW_PORT_CMD_MDIOCAP_S 21 2935 #define FW_PORT_CMD_MDIOCAP_V(x) ((x) << FW_PORT_CMD_MDIOCAP_S) 2936 #define FW_PORT_CMD_MDIOCAP_F FW_PORT_CMD_MDIOCAP_V(1U) 2937 2938 #define FW_PORT_CMD_MDIOADDR_S 16 2939 #define FW_PORT_CMD_MDIOADDR_M 0x1f 2940 #define FW_PORT_CMD_MDIOADDR_G(x) \ 2941 (((x) >> FW_PORT_CMD_MDIOADDR_S) & FW_PORT_CMD_MDIOADDR_M) 2942 2943 #define FW_PORT_CMD_LPTXPAUSE_S 15 2944 #define FW_PORT_CMD_LPTXPAUSE_V(x) ((x) << FW_PORT_CMD_LPTXPAUSE_S) 2945 #define FW_PORT_CMD_LPTXPAUSE_F FW_PORT_CMD_LPTXPAUSE_V(1U) 2946 2947 #define FW_PORT_CMD_LPRXPAUSE_S 14 2948 #define FW_PORT_CMD_LPRXPAUSE_V(x) ((x) << FW_PORT_CMD_LPRXPAUSE_S) 2949 #define FW_PORT_CMD_LPRXPAUSE_F FW_PORT_CMD_LPRXPAUSE_V(1U) 2950 2951 #define FW_PORT_CMD_PTYPE_S 8 2952 #define FW_PORT_CMD_PTYPE_M 0x1f 2953 #define FW_PORT_CMD_PTYPE_G(x) \ 2954 (((x) >> FW_PORT_CMD_PTYPE_S) & FW_PORT_CMD_PTYPE_M) 2955 2956 #define FW_PORT_CMD_LINKDNRC_S 5 2957 #define FW_PORT_CMD_LINKDNRC_M 0x7 2958 #define FW_PORT_CMD_LINKDNRC_G(x) \ 2959 (((x) >> FW_PORT_CMD_LINKDNRC_S) & FW_PORT_CMD_LINKDNRC_M) 2960 2961 #define FW_PORT_CMD_MODTYPE_S 0 2962 #define FW_PORT_CMD_MODTYPE_M 0x1f 2963 #define FW_PORT_CMD_MODTYPE_V(x) ((x) << FW_PORT_CMD_MODTYPE_S) 2964 #define FW_PORT_CMD_MODTYPE_G(x) \ 2965 (((x) >> FW_PORT_CMD_MODTYPE_S) & FW_PORT_CMD_MODTYPE_M) 2966 2967 #define FW_PORT_CMD_DCBXDIS_S 7 2968 #define FW_PORT_CMD_DCBXDIS_V(x) ((x) << FW_PORT_CMD_DCBXDIS_S) 2969 #define FW_PORT_CMD_DCBXDIS_F FW_PORT_CMD_DCBXDIS_V(1U) 2970 2971 #define FW_PORT_CMD_APPLY_S 7 2972 #define FW_PORT_CMD_APPLY_V(x) ((x) << FW_PORT_CMD_APPLY_S) 2973 #define FW_PORT_CMD_APPLY_F FW_PORT_CMD_APPLY_V(1U) 2974 2975 #define FW_PORT_CMD_ALL_SYNCD_S 7 2976 #define FW_PORT_CMD_ALL_SYNCD_V(x) ((x) << FW_PORT_CMD_ALL_SYNCD_S) 2977 #define FW_PORT_CMD_ALL_SYNCD_F FW_PORT_CMD_ALL_SYNCD_V(1U) 2978 2979 #define FW_PORT_CMD_DCB_VERSION_S 12 2980 #define FW_PORT_CMD_DCB_VERSION_M 0x7 2981 #define FW_PORT_CMD_DCB_VERSION_G(x) \ 2982 (((x) >> FW_PORT_CMD_DCB_VERSION_S) & FW_PORT_CMD_DCB_VERSION_M) 2983 2984 #define FW_PORT_CMD_LSTATUS32_S 31 2985 #define FW_PORT_CMD_LSTATUS32_M 0x1 2986 #define FW_PORT_CMD_LSTATUS32_V(x) ((x) << FW_PORT_CMD_LSTATUS32_S) 2987 #define FW_PORT_CMD_LSTATUS32_G(x) \ 2988 (((x) >> FW_PORT_CMD_LSTATUS32_S) & FW_PORT_CMD_LSTATUS32_M) 2989 #define FW_PORT_CMD_LSTATUS32_F FW_PORT_CMD_LSTATUS32_V(1U) 2990 2991 #define FW_PORT_CMD_LINKDNRC32_S 28 2992 #define FW_PORT_CMD_LINKDNRC32_M 0x7 2993 #define FW_PORT_CMD_LINKDNRC32_V(x) ((x) << FW_PORT_CMD_LINKDNRC32_S) 2994 #define FW_PORT_CMD_LINKDNRC32_G(x) \ 2995 (((x) >> FW_PORT_CMD_LINKDNRC32_S) & FW_PORT_CMD_LINKDNRC32_M) 2996 2997 #define FW_PORT_CMD_DCBXDIS32_S 27 2998 #define FW_PORT_CMD_DCBXDIS32_M 0x1 2999 #define FW_PORT_CMD_DCBXDIS32_V(x) ((x) << FW_PORT_CMD_DCBXDIS32_S) 3000 #define FW_PORT_CMD_DCBXDIS32_G(x) \ 3001 (((x) >> FW_PORT_CMD_DCBXDIS32_S) & FW_PORT_CMD_DCBXDIS32_M) 3002 #define FW_PORT_CMD_DCBXDIS32_F FW_PORT_CMD_DCBXDIS32_V(1U) 3003 3004 #define FW_PORT_CMD_MDIOCAP32_S 26 3005 #define FW_PORT_CMD_MDIOCAP32_M 0x1 3006 #define FW_PORT_CMD_MDIOCAP32_V(x) ((x) << FW_PORT_CMD_MDIOCAP32_S) 3007 #define FW_PORT_CMD_MDIOCAP32_G(x) \ 3008 (((x) >> FW_PORT_CMD_MDIOCAP32_S) & FW_PORT_CMD_MDIOCAP32_M) 3009 #define FW_PORT_CMD_MDIOCAP32_F FW_PORT_CMD_MDIOCAP32_V(1U) 3010 3011 #define FW_PORT_CMD_MDIOADDR32_S 21 3012 #define FW_PORT_CMD_MDIOADDR32_M 0x1f 3013 #define FW_PORT_CMD_MDIOADDR32_V(x) ((x) << FW_PORT_CMD_MDIOADDR32_S) 3014 #define FW_PORT_CMD_MDIOADDR32_G(x) \ 3015 (((x) >> FW_PORT_CMD_MDIOADDR32_S) & FW_PORT_CMD_MDIOADDR32_M) 3016 3017 #define FW_PORT_CMD_PORTTYPE32_S 13 3018 #define FW_PORT_CMD_PORTTYPE32_M 0xff 3019 #define FW_PORT_CMD_PORTTYPE32_V(x) ((x) << FW_PORT_CMD_PORTTYPE32_S) 3020 #define FW_PORT_CMD_PORTTYPE32_G(x) \ 3021 (((x) >> FW_PORT_CMD_PORTTYPE32_S) & FW_PORT_CMD_PORTTYPE32_M) 3022 3023 #define FW_PORT_CMD_MODTYPE32_S 8 3024 #define FW_PORT_CMD_MODTYPE32_M 0x1f 3025 #define FW_PORT_CMD_MODTYPE32_V(x) ((x) << FW_PORT_CMD_MODTYPE32_S) 3026 #define FW_PORT_CMD_MODTYPE32_G(x) \ 3027 (((x) >> FW_PORT_CMD_MODTYPE32_S) & FW_PORT_CMD_MODTYPE32_M) 3028 3029 #define FW_PORT_CMD_CBLLEN32_S 0 3030 #define FW_PORT_CMD_CBLLEN32_M 0xff 3031 #define FW_PORT_CMD_CBLLEN32_V(x) ((x) << FW_PORT_CMD_CBLLEN32_S) 3032 #define FW_PORT_CMD_CBLLEN32_G(x) \ 3033 (((x) >> FW_PORT_CMD_CBLLEN32_S) & FW_PORT_CMD_CBLLEN32_M) 3034 3035 #define FW_PORT_CMD_AUXLINFO32_S 24 3036 #define FW_PORT_CMD_AUXLINFO32_M 0xff 3037 #define FW_PORT_CMD_AUXLINFO32_V(x) ((x) << FW_PORT_CMD_AUXLINFO32_S) 3038 #define FW_PORT_CMD_AUXLINFO32_G(x) \ 3039 (((x) >> FW_PORT_CMD_AUXLINFO32_S) & FW_PORT_CMD_AUXLINFO32_M) 3040 3041 #define FW_PORT_AUXLINFO32_KX4_S 2 3042 #define FW_PORT_AUXLINFO32_KX4_M 0x1 3043 #define FW_PORT_AUXLINFO32_KX4_V(x) \ 3044 ((x) << FW_PORT_AUXLINFO32_KX4_S) 3045 #define FW_PORT_AUXLINFO32_KX4_G(x) \ 3046 (((x) >> FW_PORT_AUXLINFO32_KX4_S) & FW_PORT_AUXLINFO32_KX4_M) 3047 #define FW_PORT_AUXLINFO32_KX4_F FW_PORT_AUXLINFO32_KX4_V(1U) 3048 3049 #define FW_PORT_AUXLINFO32_KR_S 1 3050 #define FW_PORT_AUXLINFO32_KR_M 0x1 3051 #define FW_PORT_AUXLINFO32_KR_V(x) \ 3052 ((x) << FW_PORT_AUXLINFO32_KR_S) 3053 #define FW_PORT_AUXLINFO32_KR_G(x) \ 3054 (((x) >> FW_PORT_AUXLINFO32_KR_S) & FW_PORT_AUXLINFO32_KR_M) 3055 #define FW_PORT_AUXLINFO32_KR_F FW_PORT_AUXLINFO32_KR_V(1U) 3056 3057 #define FW_PORT_CMD_MTU32_S 0 3058 #define FW_PORT_CMD_MTU32_M 0xffff 3059 #define FW_PORT_CMD_MTU32_V(x) ((x) << FW_PORT_CMD_MTU32_S) 3060 #define FW_PORT_CMD_MTU32_G(x) \ 3061 (((x) >> FW_PORT_CMD_MTU32_S) & FW_PORT_CMD_MTU32_M) 3062 3063 enum fw_port_type { 3064 FW_PORT_TYPE_FIBER_XFI, 3065 FW_PORT_TYPE_FIBER_XAUI, 3066 FW_PORT_TYPE_BT_SGMII, 3067 FW_PORT_TYPE_BT_XFI, 3068 FW_PORT_TYPE_BT_XAUI, 3069 FW_PORT_TYPE_KX4, 3070 FW_PORT_TYPE_CX4, 3071 FW_PORT_TYPE_KX, 3072 FW_PORT_TYPE_KR, 3073 FW_PORT_TYPE_SFP, 3074 FW_PORT_TYPE_BP_AP, 3075 FW_PORT_TYPE_BP4_AP, 3076 FW_PORT_TYPE_QSFP_10G, 3077 FW_PORT_TYPE_QSA, 3078 FW_PORT_TYPE_QSFP, 3079 FW_PORT_TYPE_BP40_BA, 3080 FW_PORT_TYPE_KR4_100G, 3081 FW_PORT_TYPE_CR4_QSFP, 3082 FW_PORT_TYPE_CR_QSFP, 3083 FW_PORT_TYPE_CR2_QSFP, 3084 FW_PORT_TYPE_SFP28, 3085 FW_PORT_TYPE_KR_SFP28, 3086 FW_PORT_TYPE_KR_XLAUI, 3087 3088 FW_PORT_TYPE_NONE = FW_PORT_CMD_PTYPE_M 3089 }; 3090 3091 enum fw_port_module_type { 3092 FW_PORT_MOD_TYPE_NA, 3093 FW_PORT_MOD_TYPE_LR, 3094 FW_PORT_MOD_TYPE_SR, 3095 FW_PORT_MOD_TYPE_ER, 3096 FW_PORT_MOD_TYPE_TWINAX_PASSIVE, 3097 FW_PORT_MOD_TYPE_TWINAX_ACTIVE, 3098 FW_PORT_MOD_TYPE_LRM, 3099 FW_PORT_MOD_TYPE_ERROR = FW_PORT_CMD_MODTYPE_M - 3, 3100 FW_PORT_MOD_TYPE_UNKNOWN = FW_PORT_CMD_MODTYPE_M - 2, 3101 FW_PORT_MOD_TYPE_NOTSUPPORTED = FW_PORT_CMD_MODTYPE_M - 1, 3102 3103 FW_PORT_MOD_TYPE_NONE = FW_PORT_CMD_MODTYPE_M 3104 }; 3105 3106 enum fw_port_mod_sub_type { 3107 FW_PORT_MOD_SUB_TYPE_NA, 3108 FW_PORT_MOD_SUB_TYPE_MV88E114X = 0x1, 3109 FW_PORT_MOD_SUB_TYPE_TN8022 = 0x2, 3110 FW_PORT_MOD_SUB_TYPE_AQ1202 = 0x3, 3111 FW_PORT_MOD_SUB_TYPE_88x3120 = 0x4, 3112 FW_PORT_MOD_SUB_TYPE_BCM84834 = 0x5, 3113 FW_PORT_MOD_SUB_TYPE_BT_VSC8634 = 0x8, 3114 3115 /* The following will never been in the VPD. They are TWINAX cable 3116 * lengths decoded from SFP+ module i2c PROMs. These should 3117 * almost certainly go somewhere else ... 3118 */ 3119 FW_PORT_MOD_SUB_TYPE_TWINAX_1 = 0x9, 3120 FW_PORT_MOD_SUB_TYPE_TWINAX_3 = 0xA, 3121 FW_PORT_MOD_SUB_TYPE_TWINAX_5 = 0xB, 3122 FW_PORT_MOD_SUB_TYPE_TWINAX_7 = 0xC, 3123 }; 3124 3125 enum fw_port_stats_tx_index { 3126 FW_STAT_TX_PORT_BYTES_IX = 0, 3127 FW_STAT_TX_PORT_FRAMES_IX, 3128 FW_STAT_TX_PORT_BCAST_IX, 3129 FW_STAT_TX_PORT_MCAST_IX, 3130 FW_STAT_TX_PORT_UCAST_IX, 3131 FW_STAT_TX_PORT_ERROR_IX, 3132 FW_STAT_TX_PORT_64B_IX, 3133 FW_STAT_TX_PORT_65B_127B_IX, 3134 FW_STAT_TX_PORT_128B_255B_IX, 3135 FW_STAT_TX_PORT_256B_511B_IX, 3136 FW_STAT_TX_PORT_512B_1023B_IX, 3137 FW_STAT_TX_PORT_1024B_1518B_IX, 3138 FW_STAT_TX_PORT_1519B_MAX_IX, 3139 FW_STAT_TX_PORT_DROP_IX, 3140 FW_STAT_TX_PORT_PAUSE_IX, 3141 FW_STAT_TX_PORT_PPP0_IX, 3142 FW_STAT_TX_PORT_PPP1_IX, 3143 FW_STAT_TX_PORT_PPP2_IX, 3144 FW_STAT_TX_PORT_PPP3_IX, 3145 FW_STAT_TX_PORT_PPP4_IX, 3146 FW_STAT_TX_PORT_PPP5_IX, 3147 FW_STAT_TX_PORT_PPP6_IX, 3148 FW_STAT_TX_PORT_PPP7_IX, 3149 FW_NUM_PORT_TX_STATS 3150 }; 3151 3152 enum fw_port_stat_rx_index { 3153 FW_STAT_RX_PORT_BYTES_IX = 0, 3154 FW_STAT_RX_PORT_FRAMES_IX, 3155 FW_STAT_RX_PORT_BCAST_IX, 3156 FW_STAT_RX_PORT_MCAST_IX, 3157 FW_STAT_RX_PORT_UCAST_IX, 3158 FW_STAT_RX_PORT_MTU_ERROR_IX, 3159 FW_STAT_RX_PORT_MTU_CRC_ERROR_IX, 3160 FW_STAT_RX_PORT_CRC_ERROR_IX, 3161 FW_STAT_RX_PORT_LEN_ERROR_IX, 3162 FW_STAT_RX_PORT_SYM_ERROR_IX, 3163 FW_STAT_RX_PORT_64B_IX, 3164 FW_STAT_RX_PORT_65B_127B_IX, 3165 FW_STAT_RX_PORT_128B_255B_IX, 3166 FW_STAT_RX_PORT_256B_511B_IX, 3167 FW_STAT_RX_PORT_512B_1023B_IX, 3168 FW_STAT_RX_PORT_1024B_1518B_IX, 3169 FW_STAT_RX_PORT_1519B_MAX_IX, 3170 FW_STAT_RX_PORT_PAUSE_IX, 3171 FW_STAT_RX_PORT_PPP0_IX, 3172 FW_STAT_RX_PORT_PPP1_IX, 3173 FW_STAT_RX_PORT_PPP2_IX, 3174 FW_STAT_RX_PORT_PPP3_IX, 3175 FW_STAT_RX_PORT_PPP4_IX, 3176 FW_STAT_RX_PORT_PPP5_IX, 3177 FW_STAT_RX_PORT_PPP6_IX, 3178 FW_STAT_RX_PORT_PPP7_IX, 3179 FW_STAT_RX_PORT_LESS_64B_IX, 3180 FW_STAT_RX_PORT_MAC_ERROR_IX, 3181 FW_NUM_PORT_RX_STATS 3182 }; 3183 3184 /* port stats */ 3185 #define FW_NUM_PORT_STATS (FW_NUM_PORT_TX_STATS + FW_NUM_PORT_RX_STATS) 3186 3187 struct fw_port_stats_cmd { 3188 __be32 op_to_portid; 3189 __be32 retval_len16; 3190 union fw_port_stats { 3191 struct fw_port_stats_ctl { 3192 u8 nstats_bg_bm; 3193 u8 tx_ix; 3194 __be16 r6; 3195 __be32 r7; 3196 __be64 stat0; 3197 __be64 stat1; 3198 __be64 stat2; 3199 __be64 stat3; 3200 __be64 stat4; 3201 __be64 stat5; 3202 } ctl; 3203 struct fw_port_stats_all { 3204 __be64 tx_bytes; 3205 __be64 tx_frames; 3206 __be64 tx_bcast; 3207 __be64 tx_mcast; 3208 __be64 tx_ucast; 3209 __be64 tx_error; 3210 __be64 tx_64b; 3211 __be64 tx_65b_127b; 3212 __be64 tx_128b_255b; 3213 __be64 tx_256b_511b; 3214 __be64 tx_512b_1023b; 3215 __be64 tx_1024b_1518b; 3216 __be64 tx_1519b_max; 3217 __be64 tx_drop; 3218 __be64 tx_pause; 3219 __be64 tx_ppp0; 3220 __be64 tx_ppp1; 3221 __be64 tx_ppp2; 3222 __be64 tx_ppp3; 3223 __be64 tx_ppp4; 3224 __be64 tx_ppp5; 3225 __be64 tx_ppp6; 3226 __be64 tx_ppp7; 3227 __be64 rx_bytes; 3228 __be64 rx_frames; 3229 __be64 rx_bcast; 3230 __be64 rx_mcast; 3231 __be64 rx_ucast; 3232 __be64 rx_mtu_error; 3233 __be64 rx_mtu_crc_error; 3234 __be64 rx_crc_error; 3235 __be64 rx_len_error; 3236 __be64 rx_sym_error; 3237 __be64 rx_64b; 3238 __be64 rx_65b_127b; 3239 __be64 rx_128b_255b; 3240 __be64 rx_256b_511b; 3241 __be64 rx_512b_1023b; 3242 __be64 rx_1024b_1518b; 3243 __be64 rx_1519b_max; 3244 __be64 rx_pause; 3245 __be64 rx_ppp0; 3246 __be64 rx_ppp1; 3247 __be64 rx_ppp2; 3248 __be64 rx_ppp3; 3249 __be64 rx_ppp4; 3250 __be64 rx_ppp5; 3251 __be64 rx_ppp6; 3252 __be64 rx_ppp7; 3253 __be64 rx_less_64b; 3254 __be64 rx_bg_drop; 3255 __be64 rx_bg_trunc; 3256 } all; 3257 } u; 3258 }; 3259 3260 /* port loopback stats */ 3261 #define FW_NUM_LB_STATS 16 3262 enum fw_port_lb_stats_index { 3263 FW_STAT_LB_PORT_BYTES_IX, 3264 FW_STAT_LB_PORT_FRAMES_IX, 3265 FW_STAT_LB_PORT_BCAST_IX, 3266 FW_STAT_LB_PORT_MCAST_IX, 3267 FW_STAT_LB_PORT_UCAST_IX, 3268 FW_STAT_LB_PORT_ERROR_IX, 3269 FW_STAT_LB_PORT_64B_IX, 3270 FW_STAT_LB_PORT_65B_127B_IX, 3271 FW_STAT_LB_PORT_128B_255B_IX, 3272 FW_STAT_LB_PORT_256B_511B_IX, 3273 FW_STAT_LB_PORT_512B_1023B_IX, 3274 FW_STAT_LB_PORT_1024B_1518B_IX, 3275 FW_STAT_LB_PORT_1519B_MAX_IX, 3276 FW_STAT_LB_PORT_DROP_FRAMES_IX 3277 }; 3278 3279 struct fw_port_lb_stats_cmd { 3280 __be32 op_to_lbport; 3281 __be32 retval_len16; 3282 union fw_port_lb_stats { 3283 struct fw_port_lb_stats_ctl { 3284 u8 nstats_bg_bm; 3285 u8 ix_pkd; 3286 __be16 r6; 3287 __be32 r7; 3288 __be64 stat0; 3289 __be64 stat1; 3290 __be64 stat2; 3291 __be64 stat3; 3292 __be64 stat4; 3293 __be64 stat5; 3294 } ctl; 3295 struct fw_port_lb_stats_all { 3296 __be64 tx_bytes; 3297 __be64 tx_frames; 3298 __be64 tx_bcast; 3299 __be64 tx_mcast; 3300 __be64 tx_ucast; 3301 __be64 tx_error; 3302 __be64 tx_64b; 3303 __be64 tx_65b_127b; 3304 __be64 tx_128b_255b; 3305 __be64 tx_256b_511b; 3306 __be64 tx_512b_1023b; 3307 __be64 tx_1024b_1518b; 3308 __be64 tx_1519b_max; 3309 __be64 rx_lb_drop; 3310 __be64 rx_lb_trunc; 3311 } all; 3312 } u; 3313 }; 3314 3315 enum fw_ptp_subop { 3316 /* none */ 3317 FW_PTP_SC_INIT_TIMER = 0x00, 3318 FW_PTP_SC_TX_TYPE = 0x01, 3319 /* init */ 3320 FW_PTP_SC_RXTIME_STAMP = 0x08, 3321 FW_PTP_SC_RDRX_TYPE = 0x09, 3322 /* ts */ 3323 FW_PTP_SC_ADJ_FREQ = 0x10, 3324 FW_PTP_SC_ADJ_TIME = 0x11, 3325 FW_PTP_SC_ADJ_FTIME = 0x12, 3326 FW_PTP_SC_WALL_CLOCK = 0x13, 3327 FW_PTP_SC_GET_TIME = 0x14, 3328 FW_PTP_SC_SET_TIME = 0x15, 3329 }; 3330 3331 struct fw_ptp_cmd { 3332 __be32 op_to_portid; 3333 __be32 retval_len16; 3334 union fw_ptp { 3335 struct fw_ptp_sc { 3336 __u8 sc; 3337 __u8 r3[7]; 3338 } scmd; 3339 struct fw_ptp_init { 3340 __u8 sc; 3341 __u8 txchan; 3342 __be16 absid; 3343 __be16 mode; 3344 __be16 r3; 3345 } init; 3346 struct fw_ptp_ts { 3347 __u8 sc; 3348 __u8 sign; 3349 __be16 r3; 3350 __be32 ppb; 3351 __be64 tm; 3352 } ts; 3353 } u; 3354 __be64 r3; 3355 }; 3356 3357 #define FW_PTP_CMD_PORTID_S 0 3358 #define FW_PTP_CMD_PORTID_M 0xf 3359 #define FW_PTP_CMD_PORTID_V(x) ((x) << FW_PTP_CMD_PORTID_S) 3360 #define FW_PTP_CMD_PORTID_G(x) \ 3361 (((x) >> FW_PTP_CMD_PORTID_S) & FW_PTP_CMD_PORTID_M) 3362 3363 struct fw_rss_ind_tbl_cmd { 3364 __be32 op_to_viid; 3365 __be32 retval_len16; 3366 __be16 niqid; 3367 __be16 startidx; 3368 __be32 r3; 3369 __be32 iq0_to_iq2; 3370 __be32 iq3_to_iq5; 3371 __be32 iq6_to_iq8; 3372 __be32 iq9_to_iq11; 3373 __be32 iq12_to_iq14; 3374 __be32 iq15_to_iq17; 3375 __be32 iq18_to_iq20; 3376 __be32 iq21_to_iq23; 3377 __be32 iq24_to_iq26; 3378 __be32 iq27_to_iq29; 3379 __be32 iq30_iq31; 3380 __be32 r15_lo; 3381 }; 3382 3383 #define FW_RSS_IND_TBL_CMD_VIID_S 0 3384 #define FW_RSS_IND_TBL_CMD_VIID_V(x) ((x) << FW_RSS_IND_TBL_CMD_VIID_S) 3385 3386 #define FW_RSS_IND_TBL_CMD_IQ0_S 20 3387 #define FW_RSS_IND_TBL_CMD_IQ0_V(x) ((x) << FW_RSS_IND_TBL_CMD_IQ0_S) 3388 3389 #define FW_RSS_IND_TBL_CMD_IQ1_S 10 3390 #define FW_RSS_IND_TBL_CMD_IQ1_V(x) ((x) << FW_RSS_IND_TBL_CMD_IQ1_S) 3391 3392 #define FW_RSS_IND_TBL_CMD_IQ2_S 0 3393 #define FW_RSS_IND_TBL_CMD_IQ2_V(x) ((x) << FW_RSS_IND_TBL_CMD_IQ2_S) 3394 3395 struct fw_rss_glb_config_cmd { 3396 __be32 op_to_write; 3397 __be32 retval_len16; 3398 union fw_rss_glb_config { 3399 struct fw_rss_glb_config_manual { 3400 __be32 mode_pkd; 3401 __be32 r3; 3402 __be64 r4; 3403 __be64 r5; 3404 } manual; 3405 struct fw_rss_glb_config_basicvirtual { 3406 __be32 mode_pkd; 3407 __be32 synmapen_to_hashtoeplitz; 3408 __be64 r8; 3409 __be64 r9; 3410 } basicvirtual; 3411 } u; 3412 }; 3413 3414 #define FW_RSS_GLB_CONFIG_CMD_MODE_S 28 3415 #define FW_RSS_GLB_CONFIG_CMD_MODE_M 0xf 3416 #define FW_RSS_GLB_CONFIG_CMD_MODE_V(x) ((x) << FW_RSS_GLB_CONFIG_CMD_MODE_S) 3417 #define FW_RSS_GLB_CONFIG_CMD_MODE_G(x) \ 3418 (((x) >> FW_RSS_GLB_CONFIG_CMD_MODE_S) & FW_RSS_GLB_CONFIG_CMD_MODE_M) 3419 3420 #define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL 0 3421 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1 3422 3423 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_S 8 3424 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_V(x) \ 3425 ((x) << FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_S) 3426 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_F \ 3427 FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_V(1U) 3428 3429 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_S 7 3430 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_V(x) \ 3431 ((x) << FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_S) 3432 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_F \ 3433 FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_V(1U) 3434 3435 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_S 6 3436 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_V(x) \ 3437 ((x) << FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_S) 3438 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_F \ 3439 FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_V(1U) 3440 3441 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_S 5 3442 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_V(x) \ 3443 ((x) << FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_S) 3444 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_F \ 3445 FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_V(1U) 3446 3447 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_S 4 3448 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_V(x) \ 3449 ((x) << FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_S) 3450 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_F \ 3451 FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_V(1U) 3452 3453 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_S 3 3454 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_V(x) \ 3455 ((x) << FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_S) 3456 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_F \ 3457 FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_V(1U) 3458 3459 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_S 2 3460 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_V(x) \ 3461 ((x) << FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_S) 3462 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F \ 3463 FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_V(1U) 3464 3465 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_S 1 3466 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_V(x) \ 3467 ((x) << FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_S) 3468 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F \ 3469 FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_V(1U) 3470 3471 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_S 0 3472 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_V(x) \ 3473 ((x) << FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_S) 3474 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_F \ 3475 FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_V(1U) 3476 3477 struct fw_rss_vi_config_cmd { 3478 __be32 op_to_viid; 3479 #define FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << 0) 3480 __be32 retval_len16; 3481 union fw_rss_vi_config { 3482 struct fw_rss_vi_config_manual { 3483 __be64 r3; 3484 __be64 r4; 3485 __be64 r5; 3486 } manual; 3487 struct fw_rss_vi_config_basicvirtual { 3488 __be32 r6; 3489 __be32 defaultq_to_udpen; 3490 __be64 r9; 3491 __be64 r10; 3492 } basicvirtual; 3493 } u; 3494 }; 3495 3496 #define FW_RSS_VI_CONFIG_CMD_VIID_S 0 3497 #define FW_RSS_VI_CONFIG_CMD_VIID_V(x) ((x) << FW_RSS_VI_CONFIG_CMD_VIID_S) 3498 3499 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S 16 3500 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_M 0x3ff 3501 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_V(x) \ 3502 ((x) << FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S) 3503 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_G(x) \ 3504 (((x) >> FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S) & \ 3505 FW_RSS_VI_CONFIG_CMD_DEFAULTQ_M) 3506 3507 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_S 4 3508 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_V(x) \ 3509 ((x) << FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_S) 3510 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F \ 3511 FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_V(1U) 3512 3513 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_S 3 3514 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_V(x) \ 3515 ((x) << FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_S) 3516 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F \ 3517 FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_V(1U) 3518 3519 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_S 2 3520 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_V(x) \ 3521 ((x) << FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_S) 3522 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F \ 3523 FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_V(1U) 3524 3525 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_S 1 3526 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_V(x) \ 3527 ((x) << FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_S) 3528 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F \ 3529 FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_V(1U) 3530 3531 #define FW_RSS_VI_CONFIG_CMD_UDPEN_S 0 3532 #define FW_RSS_VI_CONFIG_CMD_UDPEN_V(x) ((x) << FW_RSS_VI_CONFIG_CMD_UDPEN_S) 3533 #define FW_RSS_VI_CONFIG_CMD_UDPEN_F FW_RSS_VI_CONFIG_CMD_UDPEN_V(1U) 3534 3535 enum fw_sched_sc { 3536 FW_SCHED_SC_PARAMS = 1, 3537 }; 3538 3539 struct fw_sched_cmd { 3540 __be32 op_to_write; 3541 __be32 retval_len16; 3542 union fw_sched { 3543 struct fw_sched_config { 3544 __u8 sc; 3545 __u8 type; 3546 __u8 minmaxen; 3547 __u8 r3[5]; 3548 __u8 nclasses[4]; 3549 __be32 r4; 3550 } config; 3551 struct fw_sched_params { 3552 __u8 sc; 3553 __u8 type; 3554 __u8 level; 3555 __u8 mode; 3556 __u8 unit; 3557 __u8 rate; 3558 __u8 ch; 3559 __u8 cl; 3560 __be32 min; 3561 __be32 max; 3562 __be16 weight; 3563 __be16 pktsize; 3564 __be16 burstsize; 3565 __be16 r4; 3566 } params; 3567 } u; 3568 }; 3569 3570 struct fw_clip_cmd { 3571 __be32 op_to_write; 3572 __be32 alloc_to_len16; 3573 __be64 ip_hi; 3574 __be64 ip_lo; 3575 __be32 r4[2]; 3576 }; 3577 3578 #define FW_CLIP_CMD_ALLOC_S 31 3579 #define FW_CLIP_CMD_ALLOC_V(x) ((x) << FW_CLIP_CMD_ALLOC_S) 3580 #define FW_CLIP_CMD_ALLOC_F FW_CLIP_CMD_ALLOC_V(1U) 3581 3582 #define FW_CLIP_CMD_FREE_S 30 3583 #define FW_CLIP_CMD_FREE_V(x) ((x) << FW_CLIP_CMD_FREE_S) 3584 #define FW_CLIP_CMD_FREE_F FW_CLIP_CMD_FREE_V(1U) 3585 3586 enum fw_error_type { 3587 FW_ERROR_TYPE_EXCEPTION = 0x0, 3588 FW_ERROR_TYPE_HWMODULE = 0x1, 3589 FW_ERROR_TYPE_WR = 0x2, 3590 FW_ERROR_TYPE_ACL = 0x3, 3591 }; 3592 3593 struct fw_error_cmd { 3594 __be32 op_to_type; 3595 __be32 len16_pkd; 3596 union fw_error { 3597 struct fw_error_exception { 3598 __be32 info[6]; 3599 } exception; 3600 struct fw_error_hwmodule { 3601 __be32 regaddr; 3602 __be32 regval; 3603 } hwmodule; 3604 struct fw_error_wr { 3605 __be16 cidx; 3606 __be16 pfn_vfn; 3607 __be32 eqid; 3608 u8 wrhdr[16]; 3609 } wr; 3610 struct fw_error_acl { 3611 __be16 cidx; 3612 __be16 pfn_vfn; 3613 __be32 eqid; 3614 __be16 mv_pkd; 3615 u8 val[6]; 3616 __be64 r4; 3617 } acl; 3618 } u; 3619 }; 3620 3621 struct fw_debug_cmd { 3622 __be32 op_type; 3623 __be32 len16_pkd; 3624 union fw_debug { 3625 struct fw_debug_assert { 3626 __be32 fcid; 3627 __be32 line; 3628 __be32 x; 3629 __be32 y; 3630 u8 filename_0_7[8]; 3631 u8 filename_8_15[8]; 3632 __be64 r3; 3633 } assert; 3634 struct fw_debug_prt { 3635 __be16 dprtstridx; 3636 __be16 r3[3]; 3637 __be32 dprtstrparam0; 3638 __be32 dprtstrparam1; 3639 __be32 dprtstrparam2; 3640 __be32 dprtstrparam3; 3641 } prt; 3642 } u; 3643 }; 3644 3645 #define FW_DEBUG_CMD_TYPE_S 0 3646 #define FW_DEBUG_CMD_TYPE_M 0xff 3647 #define FW_DEBUG_CMD_TYPE_G(x) \ 3648 (((x) >> FW_DEBUG_CMD_TYPE_S) & FW_DEBUG_CMD_TYPE_M) 3649 3650 struct fw_hma_cmd { 3651 __be32 op_pkd; 3652 __be32 retval_len16; 3653 __be32 mode_to_pcie_params; 3654 __be32 naddr_size; 3655 __be32 addr_size_pkd; 3656 __be32 r6; 3657 __be64 phy_address[5]; 3658 }; 3659 3660 #define FW_HMA_CMD_MODE_S 31 3661 #define FW_HMA_CMD_MODE_M 0x1 3662 #define FW_HMA_CMD_MODE_V(x) ((x) << FW_HMA_CMD_MODE_S) 3663 #define FW_HMA_CMD_MODE_G(x) \ 3664 (((x) >> FW_HMA_CMD_MODE_S) & FW_HMA_CMD_MODE_M) 3665 #define FW_HMA_CMD_MODE_F FW_HMA_CMD_MODE_V(1U) 3666 3667 #define FW_HMA_CMD_SOC_S 30 3668 #define FW_HMA_CMD_SOC_M 0x1 3669 #define FW_HMA_CMD_SOC_V(x) ((x) << FW_HMA_CMD_SOC_S) 3670 #define FW_HMA_CMD_SOC_G(x) (((x) >> FW_HMA_CMD_SOC_S) & FW_HMA_CMD_SOC_M) 3671 #define FW_HMA_CMD_SOC_F FW_HMA_CMD_SOC_V(1U) 3672 3673 #define FW_HMA_CMD_EOC_S 29 3674 #define FW_HMA_CMD_EOC_M 0x1 3675 #define FW_HMA_CMD_EOC_V(x) ((x) << FW_HMA_CMD_EOC_S) 3676 #define FW_HMA_CMD_EOC_G(x) (((x) >> FW_HMA_CMD_EOC_S) & FW_HMA_CMD_EOC_M) 3677 #define FW_HMA_CMD_EOC_F FW_HMA_CMD_EOC_V(1U) 3678 3679 #define FW_HMA_CMD_PCIE_PARAMS_S 0 3680 #define FW_HMA_CMD_PCIE_PARAMS_M 0x7ffffff 3681 #define FW_HMA_CMD_PCIE_PARAMS_V(x) ((x) << FW_HMA_CMD_PCIE_PARAMS_S) 3682 #define FW_HMA_CMD_PCIE_PARAMS_G(x) \ 3683 (((x) >> FW_HMA_CMD_PCIE_PARAMS_S) & FW_HMA_CMD_PCIE_PARAMS_M) 3684 3685 #define FW_HMA_CMD_NADDR_S 12 3686 #define FW_HMA_CMD_NADDR_M 0x3f 3687 #define FW_HMA_CMD_NADDR_V(x) ((x) << FW_HMA_CMD_NADDR_S) 3688 #define FW_HMA_CMD_NADDR_G(x) \ 3689 (((x) >> FW_HMA_CMD_NADDR_S) & FW_HMA_CMD_NADDR_M) 3690 3691 #define FW_HMA_CMD_SIZE_S 0 3692 #define FW_HMA_CMD_SIZE_M 0xfff 3693 #define FW_HMA_CMD_SIZE_V(x) ((x) << FW_HMA_CMD_SIZE_S) 3694 #define FW_HMA_CMD_SIZE_G(x) \ 3695 (((x) >> FW_HMA_CMD_SIZE_S) & FW_HMA_CMD_SIZE_M) 3696 3697 #define FW_HMA_CMD_ADDR_SIZE_S 11 3698 #define FW_HMA_CMD_ADDR_SIZE_M 0x1fffff 3699 #define FW_HMA_CMD_ADDR_SIZE_V(x) ((x) << FW_HMA_CMD_ADDR_SIZE_S) 3700 #define FW_HMA_CMD_ADDR_SIZE_G(x) \ 3701 (((x) >> FW_HMA_CMD_ADDR_SIZE_S) & FW_HMA_CMD_ADDR_SIZE_M) 3702 3703 enum pcie_fw_eval { 3704 PCIE_FW_EVAL_CRASH = 0, 3705 }; 3706 3707 #define PCIE_FW_ERR_S 31 3708 #define PCIE_FW_ERR_V(x) ((x) << PCIE_FW_ERR_S) 3709 #define PCIE_FW_ERR_F PCIE_FW_ERR_V(1U) 3710 3711 #define PCIE_FW_INIT_S 30 3712 #define PCIE_FW_INIT_V(x) ((x) << PCIE_FW_INIT_S) 3713 #define PCIE_FW_INIT_F PCIE_FW_INIT_V(1U) 3714 3715 #define PCIE_FW_HALT_S 29 3716 #define PCIE_FW_HALT_V(x) ((x) << PCIE_FW_HALT_S) 3717 #define PCIE_FW_HALT_F PCIE_FW_HALT_V(1U) 3718 3719 #define PCIE_FW_EVAL_S 24 3720 #define PCIE_FW_EVAL_M 0x7 3721 #define PCIE_FW_EVAL_G(x) (((x) >> PCIE_FW_EVAL_S) & PCIE_FW_EVAL_M) 3722 3723 #define PCIE_FW_MASTER_VLD_S 15 3724 #define PCIE_FW_MASTER_VLD_V(x) ((x) << PCIE_FW_MASTER_VLD_S) 3725 #define PCIE_FW_MASTER_VLD_F PCIE_FW_MASTER_VLD_V(1U) 3726 3727 #define PCIE_FW_MASTER_S 12 3728 #define PCIE_FW_MASTER_M 0x7 3729 #define PCIE_FW_MASTER_V(x) ((x) << PCIE_FW_MASTER_S) 3730 #define PCIE_FW_MASTER_G(x) (((x) >> PCIE_FW_MASTER_S) & PCIE_FW_MASTER_M) 3731 3732 struct fw_hdr { 3733 u8 ver; 3734 u8 chip; /* terminator chip type */ 3735 __be16 len512; /* bin length in units of 512-bytes */ 3736 __be32 fw_ver; /* firmware version */ 3737 __be32 tp_microcode_ver; 3738 u8 intfver_nic; 3739 u8 intfver_vnic; 3740 u8 intfver_ofld; 3741 u8 intfver_ri; 3742 u8 intfver_iscsipdu; 3743 u8 intfver_iscsi; 3744 u8 intfver_fcoepdu; 3745 u8 intfver_fcoe; 3746 __u32 reserved2; 3747 __u32 reserved3; 3748 __u32 reserved4; 3749 __be32 flags; 3750 __be32 reserved6[23]; 3751 }; 3752 3753 enum fw_hdr_chip { 3754 FW_HDR_CHIP_T4, 3755 FW_HDR_CHIP_T5, 3756 FW_HDR_CHIP_T6 3757 }; 3758 3759 #define FW_HDR_FW_VER_MAJOR_S 24 3760 #define FW_HDR_FW_VER_MAJOR_M 0xff 3761 #define FW_HDR_FW_VER_MAJOR_V(x) \ 3762 ((x) << FW_HDR_FW_VER_MAJOR_S) 3763 #define FW_HDR_FW_VER_MAJOR_G(x) \ 3764 (((x) >> FW_HDR_FW_VER_MAJOR_S) & FW_HDR_FW_VER_MAJOR_M) 3765 3766 #define FW_HDR_FW_VER_MINOR_S 16 3767 #define FW_HDR_FW_VER_MINOR_M 0xff 3768 #define FW_HDR_FW_VER_MINOR_V(x) \ 3769 ((x) << FW_HDR_FW_VER_MINOR_S) 3770 #define FW_HDR_FW_VER_MINOR_G(x) \ 3771 (((x) >> FW_HDR_FW_VER_MINOR_S) & FW_HDR_FW_VER_MINOR_M) 3772 3773 #define FW_HDR_FW_VER_MICRO_S 8 3774 #define FW_HDR_FW_VER_MICRO_M 0xff 3775 #define FW_HDR_FW_VER_MICRO_V(x) \ 3776 ((x) << FW_HDR_FW_VER_MICRO_S) 3777 #define FW_HDR_FW_VER_MICRO_G(x) \ 3778 (((x) >> FW_HDR_FW_VER_MICRO_S) & FW_HDR_FW_VER_MICRO_M) 3779 3780 #define FW_HDR_FW_VER_BUILD_S 0 3781 #define FW_HDR_FW_VER_BUILD_M 0xff 3782 #define FW_HDR_FW_VER_BUILD_V(x) \ 3783 ((x) << FW_HDR_FW_VER_BUILD_S) 3784 #define FW_HDR_FW_VER_BUILD_G(x) \ 3785 (((x) >> FW_HDR_FW_VER_BUILD_S) & FW_HDR_FW_VER_BUILD_M) 3786 3787 enum fw_hdr_intfver { 3788 FW_HDR_INTFVER_NIC = 0x00, 3789 FW_HDR_INTFVER_VNIC = 0x00, 3790 FW_HDR_INTFVER_OFLD = 0x00, 3791 FW_HDR_INTFVER_RI = 0x00, 3792 FW_HDR_INTFVER_ISCSIPDU = 0x00, 3793 FW_HDR_INTFVER_ISCSI = 0x00, 3794 FW_HDR_INTFVER_FCOEPDU = 0x00, 3795 FW_HDR_INTFVER_FCOE = 0x00, 3796 }; 3797 3798 enum fw_hdr_flags { 3799 FW_HDR_FLAGS_RESET_HALT = 0x00000001, 3800 }; 3801 3802 /* length of the formatting string */ 3803 #define FW_DEVLOG_FMT_LEN 192 3804 3805 /* maximum number of the formatting string parameters */ 3806 #define FW_DEVLOG_FMT_PARAMS_NUM 8 3807 3808 /* priority levels */ 3809 enum fw_devlog_level { 3810 FW_DEVLOG_LEVEL_EMERG = 0x0, 3811 FW_DEVLOG_LEVEL_CRIT = 0x1, 3812 FW_DEVLOG_LEVEL_ERR = 0x2, 3813 FW_DEVLOG_LEVEL_NOTICE = 0x3, 3814 FW_DEVLOG_LEVEL_INFO = 0x4, 3815 FW_DEVLOG_LEVEL_DEBUG = 0x5, 3816 FW_DEVLOG_LEVEL_MAX = 0x5, 3817 }; 3818 3819 /* facilities that may send a log message */ 3820 enum fw_devlog_facility { 3821 FW_DEVLOG_FACILITY_CORE = 0x00, 3822 FW_DEVLOG_FACILITY_CF = 0x01, 3823 FW_DEVLOG_FACILITY_SCHED = 0x02, 3824 FW_DEVLOG_FACILITY_TIMER = 0x04, 3825 FW_DEVLOG_FACILITY_RES = 0x06, 3826 FW_DEVLOG_FACILITY_HW = 0x08, 3827 FW_DEVLOG_FACILITY_FLR = 0x10, 3828 FW_DEVLOG_FACILITY_DMAQ = 0x12, 3829 FW_DEVLOG_FACILITY_PHY = 0x14, 3830 FW_DEVLOG_FACILITY_MAC = 0x16, 3831 FW_DEVLOG_FACILITY_PORT = 0x18, 3832 FW_DEVLOG_FACILITY_VI = 0x1A, 3833 FW_DEVLOG_FACILITY_FILTER = 0x1C, 3834 FW_DEVLOG_FACILITY_ACL = 0x1E, 3835 FW_DEVLOG_FACILITY_TM = 0x20, 3836 FW_DEVLOG_FACILITY_QFC = 0x22, 3837 FW_DEVLOG_FACILITY_DCB = 0x24, 3838 FW_DEVLOG_FACILITY_ETH = 0x26, 3839 FW_DEVLOG_FACILITY_OFLD = 0x28, 3840 FW_DEVLOG_FACILITY_RI = 0x2A, 3841 FW_DEVLOG_FACILITY_ISCSI = 0x2C, 3842 FW_DEVLOG_FACILITY_FCOE = 0x2E, 3843 FW_DEVLOG_FACILITY_FOISCSI = 0x30, 3844 FW_DEVLOG_FACILITY_FOFCOE = 0x32, 3845 FW_DEVLOG_FACILITY_CHNET = 0x34, 3846 FW_DEVLOG_FACILITY_MAX = 0x34, 3847 }; 3848 3849 /* log message format */ 3850 struct fw_devlog_e { 3851 __be64 timestamp; 3852 __be32 seqno; 3853 __be16 reserved1; 3854 __u8 level; 3855 __u8 facility; 3856 __u8 fmt[FW_DEVLOG_FMT_LEN]; 3857 __be32 params[FW_DEVLOG_FMT_PARAMS_NUM]; 3858 __be32 reserved3[4]; 3859 }; 3860 3861 struct fw_devlog_cmd { 3862 __be32 op_to_write; 3863 __be32 retval_len16; 3864 __u8 level; 3865 __u8 r2[7]; 3866 __be32 memtype_devlog_memaddr16_devlog; 3867 __be32 memsize_devlog; 3868 __be32 r3[2]; 3869 }; 3870 3871 #define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_S 28 3872 #define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_M 0xf 3873 #define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(x) \ 3874 (((x) >> FW_DEVLOG_CMD_MEMTYPE_DEVLOG_S) & \ 3875 FW_DEVLOG_CMD_MEMTYPE_DEVLOG_M) 3876 3877 #define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_S 0 3878 #define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_M 0xfffffff 3879 #define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(x) \ 3880 (((x) >> FW_DEVLOG_CMD_MEMADDR16_DEVLOG_S) & \ 3881 FW_DEVLOG_CMD_MEMADDR16_DEVLOG_M) 3882 3883 /* P C I E F W P F 7 R E G I S T E R */ 3884 3885 /* PF7 stores the Firmware Device Log parameters which allows Host Drivers to 3886 * access the "devlog" which needing to contact firmware. The encoding is 3887 * mostly the same as that returned by the DEVLOG command except for the size 3888 * which is encoded as the number of entries in multiples-1 of 128 here rather 3889 * than the memory size as is done in the DEVLOG command. Thus, 0 means 128 3890 * and 15 means 2048. This of course in turn constrains the allowed values 3891 * for the devlog size ... 3892 */ 3893 #define PCIE_FW_PF_DEVLOG 7 3894 3895 #define PCIE_FW_PF_DEVLOG_NENTRIES128_S 28 3896 #define PCIE_FW_PF_DEVLOG_NENTRIES128_M 0xf 3897 #define PCIE_FW_PF_DEVLOG_NENTRIES128_V(x) \ 3898 ((x) << PCIE_FW_PF_DEVLOG_NENTRIES128_S) 3899 #define PCIE_FW_PF_DEVLOG_NENTRIES128_G(x) \ 3900 (((x) >> PCIE_FW_PF_DEVLOG_NENTRIES128_S) & \ 3901 PCIE_FW_PF_DEVLOG_NENTRIES128_M) 3902 3903 #define PCIE_FW_PF_DEVLOG_ADDR16_S 4 3904 #define PCIE_FW_PF_DEVLOG_ADDR16_M 0xffffff 3905 #define PCIE_FW_PF_DEVLOG_ADDR16_V(x) ((x) << PCIE_FW_PF_DEVLOG_ADDR16_S) 3906 #define PCIE_FW_PF_DEVLOG_ADDR16_G(x) \ 3907 (((x) >> PCIE_FW_PF_DEVLOG_ADDR16_S) & PCIE_FW_PF_DEVLOG_ADDR16_M) 3908 3909 #define PCIE_FW_PF_DEVLOG_MEMTYPE_S 0 3910 #define PCIE_FW_PF_DEVLOG_MEMTYPE_M 0xf 3911 #define PCIE_FW_PF_DEVLOG_MEMTYPE_V(x) ((x) << PCIE_FW_PF_DEVLOG_MEMTYPE_S) 3912 #define PCIE_FW_PF_DEVLOG_MEMTYPE_G(x) \ 3913 (((x) >> PCIE_FW_PF_DEVLOG_MEMTYPE_S) & PCIE_FW_PF_DEVLOG_MEMTYPE_M) 3914 3915 #define MAX_IMM_OFLD_TX_DATA_WR_LEN (0xff + sizeof(struct fw_ofld_tx_data_wr)) 3916 3917 struct fw_crypto_lookaside_wr { 3918 __be32 op_to_cctx_size; 3919 __be32 len16_pkd; 3920 __be32 session_id; 3921 __be32 rx_chid_to_rx_q_id; 3922 __be32 key_addr; 3923 __be32 pld_size_hash_size; 3924 __be64 cookie; 3925 }; 3926 3927 #define FW_CRYPTO_LOOKASIDE_WR_OPCODE_S 24 3928 #define FW_CRYPTO_LOOKASIDE_WR_OPCODE_M 0xff 3929 #define FW_CRYPTO_LOOKASIDE_WR_OPCODE_V(x) \ 3930 ((x) << FW_CRYPTO_LOOKASIDE_WR_OPCODE_S) 3931 #define FW_CRYPTO_LOOKASIDE_WR_OPCODE_G(x) \ 3932 (((x) >> FW_CRYPTO_LOOKASIDE_WR_OPCODE_S) & \ 3933 FW_CRYPTO_LOOKASIDE_WR_OPCODE_M) 3934 3935 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_S 23 3936 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_M 0x1 3937 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_V(x) \ 3938 ((x) << FW_CRYPTO_LOOKASIDE_WR_COMPL_S) 3939 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_G(x) \ 3940 (((x) >> FW_CRYPTO_LOOKASIDE_WR_COMPL_S) & \ 3941 FW_CRYPTO_LOOKASIDE_WR_COMPL_M) 3942 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_F FW_CRYPTO_LOOKASIDE_WR_COMPL_V(1U) 3943 3944 #define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_S 15 3945 #define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_M 0xff 3946 #define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_V(x) \ 3947 ((x) << FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_S) 3948 #define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_G(x) \ 3949 (((x) >> FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_S) & \ 3950 FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_M) 3951 3952 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_S 5 3953 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_M 0x3 3954 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_V(x) \ 3955 ((x) << FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_S) 3956 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_G(x) \ 3957 (((x) >> FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_S) & \ 3958 FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_M) 3959 3960 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_S 0 3961 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_M 0x1f 3962 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_V(x) \ 3963 ((x) << FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_S) 3964 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_G(x) \ 3965 (((x) >> FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_S) & \ 3966 FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_M) 3967 3968 #define FW_CRYPTO_LOOKASIDE_WR_LEN16_S 0 3969 #define FW_CRYPTO_LOOKASIDE_WR_LEN16_M 0xff 3970 #define FW_CRYPTO_LOOKASIDE_WR_LEN16_V(x) \ 3971 ((x) << FW_CRYPTO_LOOKASIDE_WR_LEN16_S) 3972 #define FW_CRYPTO_LOOKASIDE_WR_LEN16_G(x) \ 3973 (((x) >> FW_CRYPTO_LOOKASIDE_WR_LEN16_S) & \ 3974 FW_CRYPTO_LOOKASIDE_WR_LEN16_M) 3975 3976 #define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_S 29 3977 #define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_M 0x3 3978 #define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_V(x) \ 3979 ((x) << FW_CRYPTO_LOOKASIDE_WR_RX_CHID_S) 3980 #define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_G(x) \ 3981 (((x) >> FW_CRYPTO_LOOKASIDE_WR_RX_CHID_S) & \ 3982 FW_CRYPTO_LOOKASIDE_WR_RX_CHID_M) 3983 3984 #define FW_CRYPTO_LOOKASIDE_WR_LCB_S 27 3985 #define FW_CRYPTO_LOOKASIDE_WR_LCB_M 0x3 3986 #define FW_CRYPTO_LOOKASIDE_WR_LCB_V(x) \ 3987 ((x) << FW_CRYPTO_LOOKASIDE_WR_LCB_S) 3988 #define FW_CRYPTO_LOOKASIDE_WR_LCB_G(x) \ 3989 (((x) >> FW_CRYPTO_LOOKASIDE_WR_LCB_S) & FW_CRYPTO_LOOKASIDE_WR_LCB_M) 3990 3991 #define FW_CRYPTO_LOOKASIDE_WR_PHASH_S 25 3992 #define FW_CRYPTO_LOOKASIDE_WR_PHASH_M 0x3 3993 #define FW_CRYPTO_LOOKASIDE_WR_PHASH_V(x) \ 3994 ((x) << FW_CRYPTO_LOOKASIDE_WR_PHASH_S) 3995 #define FW_CRYPTO_LOOKASIDE_WR_PHASH_G(x) \ 3996 (((x) >> FW_CRYPTO_LOOKASIDE_WR_PHASH_S) & \ 3997 FW_CRYPTO_LOOKASIDE_WR_PHASH_M) 3998 3999 #define FW_CRYPTO_LOOKASIDE_WR_IV_S 23 4000 #define FW_CRYPTO_LOOKASIDE_WR_IV_M 0x3 4001 #define FW_CRYPTO_LOOKASIDE_WR_IV_V(x) \ 4002 ((x) << FW_CRYPTO_LOOKASIDE_WR_IV_S) 4003 #define FW_CRYPTO_LOOKASIDE_WR_IV_G(x) \ 4004 (((x) >> FW_CRYPTO_LOOKASIDE_WR_IV_S) & FW_CRYPTO_LOOKASIDE_WR_IV_M) 4005 4006 #define FW_CRYPTO_LOOKASIDE_WR_FQIDX_S 15 4007 #define FW_CRYPTO_LOOKASIDE_WR_FQIDX_M 0xff 4008 #define FW_CRYPTO_LOOKASIDE_WR_FQIDX_V(x) \ 4009 ((x) << FW_CRYPTO_LOOKASIDE_WR_FQIDX_S) 4010 #define FW_CRYPTO_LOOKASIDE_WR_FQIDX_G(x) \ 4011 (((x) >> FW_CRYPTO_LOOKASIDE_WR_FQIDX_S) & \ 4012 FW_CRYPTO_LOOKASIDE_WR_FQIDX_M) 4013 4014 #define FW_CRYPTO_LOOKASIDE_WR_TX_CH_S 10 4015 #define FW_CRYPTO_LOOKASIDE_WR_TX_CH_M 0x3 4016 #define FW_CRYPTO_LOOKASIDE_WR_TX_CH_V(x) \ 4017 ((x) << FW_CRYPTO_LOOKASIDE_WR_TX_CH_S) 4018 #define FW_CRYPTO_LOOKASIDE_WR_TX_CH_G(x) \ 4019 (((x) >> FW_CRYPTO_LOOKASIDE_WR_TX_CH_S) & \ 4020 FW_CRYPTO_LOOKASIDE_WR_TX_CH_M) 4021 4022 #define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_S 0 4023 #define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_M 0x3ff 4024 #define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_V(x) \ 4025 ((x) << FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_S) 4026 #define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_G(x) \ 4027 (((x) >> FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_S) & \ 4028 FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_M) 4029 4030 #define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_S 24 4031 #define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_M 0xff 4032 #define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_V(x) \ 4033 ((x) << FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_S) 4034 #define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_G(x) \ 4035 (((x) >> FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_S) & \ 4036 FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_M) 4037 4038 #define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_S 17 4039 #define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_M 0x7f 4040 #define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_V(x) \ 4041 ((x) << FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_S) 4042 #define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_G(x) \ 4043 (((x) >> FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_S) & \ 4044 FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_M) 4045 4046 struct fw_tlstx_data_wr { 4047 __be32 op_to_immdlen; 4048 __be32 flowid_len16; 4049 __be32 plen; 4050 __be32 lsodisable_to_flags; 4051 __be32 r5; 4052 __be32 ctxloc_to_exp; 4053 __be16 mfs; 4054 __be16 adjustedplen_pkd; 4055 __be16 expinplenmax_pkd; 4056 u8 pdusinplenmax_pkd; 4057 u8 r10; 4058 }; 4059 4060 #define FW_TLSTX_DATA_WR_OPCODE_S 24 4061 #define FW_TLSTX_DATA_WR_OPCODE_M 0xff 4062 #define FW_TLSTX_DATA_WR_OPCODE_V(x) ((x) << FW_TLSTX_DATA_WR_OPCODE_S) 4063 #define FW_TLSTX_DATA_WR_OPCODE_G(x) \ 4064 (((x) >> FW_TLSTX_DATA_WR_OPCODE_S) & FW_TLSTX_DATA_WR_OPCODE_M) 4065 4066 #define FW_TLSTX_DATA_WR_COMPL_S 21 4067 #define FW_TLSTX_DATA_WR_COMPL_M 0x1 4068 #define FW_TLSTX_DATA_WR_COMPL_V(x) ((x) << FW_TLSTX_DATA_WR_COMPL_S) 4069 #define FW_TLSTX_DATA_WR_COMPL_G(x) \ 4070 (((x) >> FW_TLSTX_DATA_WR_COMPL_S) & FW_TLSTX_DATA_WR_COMPL_M) 4071 #define FW_TLSTX_DATA_WR_COMPL_F FW_TLSTX_DATA_WR_COMPL_V(1U) 4072 4073 #define FW_TLSTX_DATA_WR_IMMDLEN_S 0 4074 #define FW_TLSTX_DATA_WR_IMMDLEN_M 0xff 4075 #define FW_TLSTX_DATA_WR_IMMDLEN_V(x) ((x) << FW_TLSTX_DATA_WR_IMMDLEN_S) 4076 #define FW_TLSTX_DATA_WR_IMMDLEN_G(x) \ 4077 (((x) >> FW_TLSTX_DATA_WR_IMMDLEN_S) & FW_TLSTX_DATA_WR_IMMDLEN_M) 4078 4079 #define FW_TLSTX_DATA_WR_FLOWID_S 8 4080 #define FW_TLSTX_DATA_WR_FLOWID_M 0xfffff 4081 #define FW_TLSTX_DATA_WR_FLOWID_V(x) ((x) << FW_TLSTX_DATA_WR_FLOWID_S) 4082 #define FW_TLSTX_DATA_WR_FLOWID_G(x) \ 4083 (((x) >> FW_TLSTX_DATA_WR_FLOWID_S) & FW_TLSTX_DATA_WR_FLOWID_M) 4084 4085 #define FW_TLSTX_DATA_WR_LEN16_S 0 4086 #define FW_TLSTX_DATA_WR_LEN16_M 0xff 4087 #define FW_TLSTX_DATA_WR_LEN16_V(x) ((x) << FW_TLSTX_DATA_WR_LEN16_S) 4088 #define FW_TLSTX_DATA_WR_LEN16_G(x) \ 4089 (((x) >> FW_TLSTX_DATA_WR_LEN16_S) & FW_TLSTX_DATA_WR_LEN16_M) 4090 4091 #define FW_TLSTX_DATA_WR_LSODISABLE_S 31 4092 #define FW_TLSTX_DATA_WR_LSODISABLE_M 0x1 4093 #define FW_TLSTX_DATA_WR_LSODISABLE_V(x) \ 4094 ((x) << FW_TLSTX_DATA_WR_LSODISABLE_S) 4095 #define FW_TLSTX_DATA_WR_LSODISABLE_G(x) \ 4096 (((x) >> FW_TLSTX_DATA_WR_LSODISABLE_S) & FW_TLSTX_DATA_WR_LSODISABLE_M) 4097 #define FW_TLSTX_DATA_WR_LSODISABLE_F FW_TLSTX_DATA_WR_LSODISABLE_V(1U) 4098 4099 #define FW_TLSTX_DATA_WR_ALIGNPLD_S 30 4100 #define FW_TLSTX_DATA_WR_ALIGNPLD_M 0x1 4101 #define FW_TLSTX_DATA_WR_ALIGNPLD_V(x) ((x) << FW_TLSTX_DATA_WR_ALIGNPLD_S) 4102 #define FW_TLSTX_DATA_WR_ALIGNPLD_G(x) \ 4103 (((x) >> FW_TLSTX_DATA_WR_ALIGNPLD_S) & FW_TLSTX_DATA_WR_ALIGNPLD_M) 4104 #define FW_TLSTX_DATA_WR_ALIGNPLD_F FW_TLSTX_DATA_WR_ALIGNPLD_V(1U) 4105 4106 #define FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_S 29 4107 #define FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_M 0x1 4108 #define FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_V(x) \ 4109 ((x) << FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_S) 4110 #define FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_G(x) \ 4111 (((x) >> FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_S) & \ 4112 FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_M) 4113 #define FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_F FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_V(1U) 4114 4115 #define FW_TLSTX_DATA_WR_FLAGS_S 0 4116 #define FW_TLSTX_DATA_WR_FLAGS_M 0xfffffff 4117 #define FW_TLSTX_DATA_WR_FLAGS_V(x) ((x) << FW_TLSTX_DATA_WR_FLAGS_S) 4118 #define FW_TLSTX_DATA_WR_FLAGS_G(x) \ 4119 (((x) >> FW_TLSTX_DATA_WR_FLAGS_S) & FW_TLSTX_DATA_WR_FLAGS_M) 4120 4121 #define FW_TLSTX_DATA_WR_CTXLOC_S 30 4122 #define FW_TLSTX_DATA_WR_CTXLOC_M 0x3 4123 #define FW_TLSTX_DATA_WR_CTXLOC_V(x) ((x) << FW_TLSTX_DATA_WR_CTXLOC_S) 4124 #define FW_TLSTX_DATA_WR_CTXLOC_G(x) \ 4125 (((x) >> FW_TLSTX_DATA_WR_CTXLOC_S) & FW_TLSTX_DATA_WR_CTXLOC_M) 4126 4127 #define FW_TLSTX_DATA_WR_IVDSGL_S 29 4128 #define FW_TLSTX_DATA_WR_IVDSGL_M 0x1 4129 #define FW_TLSTX_DATA_WR_IVDSGL_V(x) ((x) << FW_TLSTX_DATA_WR_IVDSGL_S) 4130 #define FW_TLSTX_DATA_WR_IVDSGL_G(x) \ 4131 (((x) >> FW_TLSTX_DATA_WR_IVDSGL_S) & FW_TLSTX_DATA_WR_IVDSGL_M) 4132 #define FW_TLSTX_DATA_WR_IVDSGL_F FW_TLSTX_DATA_WR_IVDSGL_V(1U) 4133 4134 #define FW_TLSTX_DATA_WR_KEYSIZE_S 24 4135 #define FW_TLSTX_DATA_WR_KEYSIZE_M 0x1f 4136 #define FW_TLSTX_DATA_WR_KEYSIZE_V(x) ((x) << FW_TLSTX_DATA_WR_KEYSIZE_S) 4137 #define FW_TLSTX_DATA_WR_KEYSIZE_G(x) \ 4138 (((x) >> FW_TLSTX_DATA_WR_KEYSIZE_S) & FW_TLSTX_DATA_WR_KEYSIZE_M) 4139 4140 #define FW_TLSTX_DATA_WR_NUMIVS_S 14 4141 #define FW_TLSTX_DATA_WR_NUMIVS_M 0xff 4142 #define FW_TLSTX_DATA_WR_NUMIVS_V(x) ((x) << FW_TLSTX_DATA_WR_NUMIVS_S) 4143 #define FW_TLSTX_DATA_WR_NUMIVS_G(x) \ 4144 (((x) >> FW_TLSTX_DATA_WR_NUMIVS_S) & FW_TLSTX_DATA_WR_NUMIVS_M) 4145 4146 #define FW_TLSTX_DATA_WR_EXP_S 0 4147 #define FW_TLSTX_DATA_WR_EXP_M 0x3fff 4148 #define FW_TLSTX_DATA_WR_EXP_V(x) ((x) << FW_TLSTX_DATA_WR_EXP_S) 4149 #define FW_TLSTX_DATA_WR_EXP_G(x) \ 4150 (((x) >> FW_TLSTX_DATA_WR_EXP_S) & FW_TLSTX_DATA_WR_EXP_M) 4151 4152 #define FW_TLSTX_DATA_WR_ADJUSTEDPLEN_S 1 4153 #define FW_TLSTX_DATA_WR_ADJUSTEDPLEN_V(x) \ 4154 ((x) << FW_TLSTX_DATA_WR_ADJUSTEDPLEN_S) 4155 4156 #define FW_TLSTX_DATA_WR_EXPINPLENMAX_S 4 4157 #define FW_TLSTX_DATA_WR_EXPINPLENMAX_V(x) \ 4158 ((x) << FW_TLSTX_DATA_WR_EXPINPLENMAX_S) 4159 4160 #define FW_TLSTX_DATA_WR_PDUSINPLENMAX_S 2 4161 #define FW_TLSTX_DATA_WR_PDUSINPLENMAX_V(x) \ 4162 ((x) << FW_TLSTX_DATA_WR_PDUSINPLENMAX_S) 4163 4164 #endif /* _T4FW_INTERFACE_H_ */ 4165