1 /* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #ifndef __T4_MSG_H 36 #define __T4_MSG_H 37 38 #include <linux/types.h> 39 40 enum { 41 CPL_PASS_OPEN_REQ = 0x1, 42 CPL_PASS_ACCEPT_RPL = 0x2, 43 CPL_ACT_OPEN_REQ = 0x3, 44 CPL_SET_TCB_FIELD = 0x5, 45 CPL_GET_TCB = 0x6, 46 CPL_CLOSE_CON_REQ = 0x8, 47 CPL_CLOSE_LISTSRV_REQ = 0x9, 48 CPL_ABORT_REQ = 0xA, 49 CPL_ABORT_RPL = 0xB, 50 CPL_RX_DATA_ACK = 0xD, 51 CPL_TX_PKT = 0xE, 52 CPL_L2T_WRITE_REQ = 0x12, 53 CPL_SMT_WRITE_REQ = 0x14, 54 CPL_TID_RELEASE = 0x1A, 55 CPL_TX_DATA_ISO = 0x1F, 56 57 CPL_CLOSE_LISTSRV_RPL = 0x20, 58 CPL_L2T_WRITE_RPL = 0x23, 59 CPL_PASS_OPEN_RPL = 0x24, 60 CPL_ACT_OPEN_RPL = 0x25, 61 CPL_PEER_CLOSE = 0x26, 62 CPL_ABORT_REQ_RSS = 0x2B, 63 CPL_ABORT_RPL_RSS = 0x2D, 64 CPL_SMT_WRITE_RPL = 0x2E, 65 66 CPL_RX_PHYS_ADDR = 0x30, 67 CPL_CLOSE_CON_RPL = 0x32, 68 CPL_ISCSI_HDR = 0x33, 69 CPL_RDMA_CQE = 0x35, 70 CPL_RDMA_CQE_READ_RSP = 0x36, 71 CPL_RDMA_CQE_ERR = 0x37, 72 CPL_RX_DATA = 0x39, 73 CPL_SET_TCB_RPL = 0x3A, 74 CPL_RX_PKT = 0x3B, 75 CPL_RX_DDP_COMPLETE = 0x3F, 76 77 CPL_ACT_ESTABLISH = 0x40, 78 CPL_PASS_ESTABLISH = 0x41, 79 CPL_RX_DATA_DDP = 0x42, 80 CPL_PASS_ACCEPT_REQ = 0x44, 81 CPL_RX_ISCSI_CMP = 0x45, 82 CPL_TRACE_PKT_T5 = 0x48, 83 CPL_RX_ISCSI_DDP = 0x49, 84 85 CPL_RDMA_READ_REQ = 0x60, 86 87 CPL_PASS_OPEN_REQ6 = 0x81, 88 CPL_ACT_OPEN_REQ6 = 0x83, 89 90 CPL_TX_TLS_PDU = 0x88, 91 CPL_TX_SEC_PDU = 0x8A, 92 CPL_TX_TLS_ACK = 0x8B, 93 94 CPL_RDMA_TERMINATE = 0xA2, 95 CPL_RDMA_WRITE = 0xA4, 96 CPL_SGE_EGR_UPDATE = 0xA5, 97 CPL_RX_MPS_PKT = 0xAF, 98 99 CPL_TRACE_PKT = 0xB0, 100 CPL_ISCSI_DATA = 0xB2, 101 102 CPL_FW4_MSG = 0xC0, 103 CPL_FW4_PLD = 0xC1, 104 CPL_FW4_ACK = 0xC3, 105 106 CPL_RX_PHYS_DSGL = 0xD0, 107 108 CPL_FW6_MSG = 0xE0, 109 CPL_FW6_PLD = 0xE1, 110 CPL_TX_PKT_LSO = 0xED, 111 CPL_TX_PKT_XT = 0xEE, 112 113 NUM_CPL_CMDS 114 }; 115 116 enum CPL_error { 117 CPL_ERR_NONE = 0, 118 CPL_ERR_TCAM_PARITY = 1, 119 CPL_ERR_TCAM_MISS = 2, 120 CPL_ERR_TCAM_FULL = 3, 121 CPL_ERR_BAD_LENGTH = 15, 122 CPL_ERR_BAD_ROUTE = 18, 123 CPL_ERR_CONN_RESET = 20, 124 CPL_ERR_CONN_EXIST_SYNRECV = 21, 125 CPL_ERR_CONN_EXIST = 22, 126 CPL_ERR_ARP_MISS = 23, 127 CPL_ERR_BAD_SYN = 24, 128 CPL_ERR_CONN_TIMEDOUT = 30, 129 CPL_ERR_XMIT_TIMEDOUT = 31, 130 CPL_ERR_PERSIST_TIMEDOUT = 32, 131 CPL_ERR_FINWAIT2_TIMEDOUT = 33, 132 CPL_ERR_KEEPALIVE_TIMEDOUT = 34, 133 CPL_ERR_RTX_NEG_ADVICE = 35, 134 CPL_ERR_PERSIST_NEG_ADVICE = 36, 135 CPL_ERR_KEEPALV_NEG_ADVICE = 37, 136 CPL_ERR_ABORT_FAILED = 42, 137 CPL_ERR_IWARP_FLM = 50, 138 }; 139 140 enum { 141 CPL_CONN_POLICY_AUTO = 0, 142 CPL_CONN_POLICY_ASK = 1, 143 CPL_CONN_POLICY_FILTER = 2, 144 CPL_CONN_POLICY_DENY = 3 145 }; 146 147 enum { 148 ULP_MODE_NONE = 0, 149 ULP_MODE_ISCSI = 2, 150 ULP_MODE_RDMA = 4, 151 ULP_MODE_TCPDDP = 5, 152 ULP_MODE_FCOE = 6, 153 }; 154 155 enum { 156 ULP_CRC_HEADER = 1 << 0, 157 ULP_CRC_DATA = 1 << 1 158 }; 159 160 enum { 161 CPL_ABORT_SEND_RST = 0, 162 CPL_ABORT_NO_RST, 163 }; 164 165 enum { /* TX_PKT_XT checksum types */ 166 TX_CSUM_TCP = 0, 167 TX_CSUM_UDP = 1, 168 TX_CSUM_CRC16 = 4, 169 TX_CSUM_CRC32 = 5, 170 TX_CSUM_CRC32C = 6, 171 TX_CSUM_FCOE = 7, 172 TX_CSUM_TCPIP = 8, 173 TX_CSUM_UDPIP = 9, 174 TX_CSUM_TCPIP6 = 10, 175 TX_CSUM_UDPIP6 = 11, 176 TX_CSUM_IP = 12, 177 }; 178 179 union opcode_tid { 180 __be32 opcode_tid; 181 u8 opcode; 182 }; 183 184 #define CPL_OPCODE_S 24 185 #define CPL_OPCODE_V(x) ((x) << CPL_OPCODE_S) 186 #define CPL_OPCODE_G(x) (((x) >> CPL_OPCODE_S) & 0xFF) 187 #define TID_G(x) ((x) & 0xFFFFFF) 188 189 /* tid is assumed to be 24-bits */ 190 #define MK_OPCODE_TID(opcode, tid) (CPL_OPCODE_V(opcode) | (tid)) 191 192 #define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid) 193 194 /* extract the TID from a CPL command */ 195 #define GET_TID(cmd) (TID_G(be32_to_cpu(OPCODE_TID(cmd)))) 196 197 /* partitioning of TID fields that also carry a queue id */ 198 #define TID_TID_S 0 199 #define TID_TID_M 0x3fff 200 #define TID_TID_G(x) (((x) >> TID_TID_S) & TID_TID_M) 201 202 #define TID_QID_S 14 203 #define TID_QID_M 0x3ff 204 #define TID_QID_V(x) ((x) << TID_QID_S) 205 #define TID_QID_G(x) (((x) >> TID_QID_S) & TID_QID_M) 206 207 struct rss_header { 208 u8 opcode; 209 #if defined(__LITTLE_ENDIAN_BITFIELD) 210 u8 channel:2; 211 u8 filter_hit:1; 212 u8 filter_tid:1; 213 u8 hash_type:2; 214 u8 ipv6:1; 215 u8 send2fw:1; 216 #else 217 u8 send2fw:1; 218 u8 ipv6:1; 219 u8 hash_type:2; 220 u8 filter_tid:1; 221 u8 filter_hit:1; 222 u8 channel:2; 223 #endif 224 __be16 qid; 225 __be32 hash_val; 226 }; 227 228 struct work_request_hdr { 229 __be32 wr_hi; 230 __be32 wr_mid; 231 __be64 wr_lo; 232 }; 233 234 /* wr_hi fields */ 235 #define WR_OP_S 24 236 #define WR_OP_V(x) ((__u64)(x) << WR_OP_S) 237 238 #define WR_HDR struct work_request_hdr wr 239 240 /* option 0 fields */ 241 #define TX_CHAN_S 2 242 #define TX_CHAN_V(x) ((x) << TX_CHAN_S) 243 244 #define ULP_MODE_S 8 245 #define ULP_MODE_V(x) ((x) << ULP_MODE_S) 246 247 #define RCV_BUFSIZ_S 12 248 #define RCV_BUFSIZ_M 0x3FFU 249 #define RCV_BUFSIZ_V(x) ((x) << RCV_BUFSIZ_S) 250 251 #define SMAC_SEL_S 28 252 #define SMAC_SEL_V(x) ((__u64)(x) << SMAC_SEL_S) 253 254 #define L2T_IDX_S 36 255 #define L2T_IDX_V(x) ((__u64)(x) << L2T_IDX_S) 256 257 #define WND_SCALE_S 50 258 #define WND_SCALE_V(x) ((__u64)(x) << WND_SCALE_S) 259 260 #define KEEP_ALIVE_S 54 261 #define KEEP_ALIVE_V(x) ((__u64)(x) << KEEP_ALIVE_S) 262 #define KEEP_ALIVE_F KEEP_ALIVE_V(1ULL) 263 264 #define MSS_IDX_S 60 265 #define MSS_IDX_M 0xF 266 #define MSS_IDX_V(x) ((__u64)(x) << MSS_IDX_S) 267 #define MSS_IDX_G(x) (((x) >> MSS_IDX_S) & MSS_IDX_M) 268 269 /* option 2 fields */ 270 #define RSS_QUEUE_S 0 271 #define RSS_QUEUE_M 0x3FF 272 #define RSS_QUEUE_V(x) ((x) << RSS_QUEUE_S) 273 #define RSS_QUEUE_G(x) (((x) >> RSS_QUEUE_S) & RSS_QUEUE_M) 274 275 #define RSS_QUEUE_VALID_S 10 276 #define RSS_QUEUE_VALID_V(x) ((x) << RSS_QUEUE_VALID_S) 277 #define RSS_QUEUE_VALID_F RSS_QUEUE_VALID_V(1U) 278 279 #define RX_FC_DISABLE_S 20 280 #define RX_FC_DISABLE_V(x) ((x) << RX_FC_DISABLE_S) 281 #define RX_FC_DISABLE_F RX_FC_DISABLE_V(1U) 282 283 #define RX_FC_VALID_S 22 284 #define RX_FC_VALID_V(x) ((x) << RX_FC_VALID_S) 285 #define RX_FC_VALID_F RX_FC_VALID_V(1U) 286 287 #define RX_CHANNEL_S 26 288 #define RX_CHANNEL_V(x) ((x) << RX_CHANNEL_S) 289 290 #define WND_SCALE_EN_S 28 291 #define WND_SCALE_EN_V(x) ((x) << WND_SCALE_EN_S) 292 #define WND_SCALE_EN_F WND_SCALE_EN_V(1U) 293 294 #define T5_OPT_2_VALID_S 31 295 #define T5_OPT_2_VALID_V(x) ((x) << T5_OPT_2_VALID_S) 296 #define T5_OPT_2_VALID_F T5_OPT_2_VALID_V(1U) 297 298 struct cpl_pass_open_req { 299 WR_HDR; 300 union opcode_tid ot; 301 __be16 local_port; 302 __be16 peer_port; 303 __be32 local_ip; 304 __be32 peer_ip; 305 __be64 opt0; 306 __be64 opt1; 307 }; 308 309 /* option 0 fields */ 310 #define NO_CONG_S 4 311 #define NO_CONG_V(x) ((x) << NO_CONG_S) 312 #define NO_CONG_F NO_CONG_V(1U) 313 314 #define DELACK_S 5 315 #define DELACK_V(x) ((x) << DELACK_S) 316 #define DELACK_F DELACK_V(1U) 317 318 #define DSCP_S 22 319 #define DSCP_M 0x3F 320 #define DSCP_V(x) ((x) << DSCP_S) 321 #define DSCP_G(x) (((x) >> DSCP_S) & DSCP_M) 322 323 #define TCAM_BYPASS_S 48 324 #define TCAM_BYPASS_V(x) ((__u64)(x) << TCAM_BYPASS_S) 325 #define TCAM_BYPASS_F TCAM_BYPASS_V(1ULL) 326 327 #define NAGLE_S 49 328 #define NAGLE_V(x) ((__u64)(x) << NAGLE_S) 329 #define NAGLE_F NAGLE_V(1ULL) 330 331 /* option 1 fields */ 332 #define SYN_RSS_ENABLE_S 0 333 #define SYN_RSS_ENABLE_V(x) ((x) << SYN_RSS_ENABLE_S) 334 #define SYN_RSS_ENABLE_F SYN_RSS_ENABLE_V(1U) 335 336 #define SYN_RSS_QUEUE_S 2 337 #define SYN_RSS_QUEUE_V(x) ((x) << SYN_RSS_QUEUE_S) 338 339 #define CONN_POLICY_S 22 340 #define CONN_POLICY_V(x) ((x) << CONN_POLICY_S) 341 342 struct cpl_pass_open_req6 { 343 WR_HDR; 344 union opcode_tid ot; 345 __be16 local_port; 346 __be16 peer_port; 347 __be64 local_ip_hi; 348 __be64 local_ip_lo; 349 __be64 peer_ip_hi; 350 __be64 peer_ip_lo; 351 __be64 opt0; 352 __be64 opt1; 353 }; 354 355 struct cpl_pass_open_rpl { 356 union opcode_tid ot; 357 u8 rsvd[3]; 358 u8 status; 359 }; 360 361 struct tcp_options { 362 __be16 mss; 363 __u8 wsf; 364 #if defined(__LITTLE_ENDIAN_BITFIELD) 365 __u8:4; 366 __u8 unknown:1; 367 __u8:1; 368 __u8 sack:1; 369 __u8 tstamp:1; 370 #else 371 __u8 tstamp:1; 372 __u8 sack:1; 373 __u8:1; 374 __u8 unknown:1; 375 __u8:4; 376 #endif 377 }; 378 379 struct cpl_pass_accept_req { 380 union opcode_tid ot; 381 __be16 rsvd; 382 __be16 len; 383 __be32 hdr_len; 384 __be16 vlan; 385 __be16 l2info; 386 __be32 tos_stid; 387 struct tcp_options tcpopt; 388 }; 389 390 /* cpl_pass_accept_req.hdr_len fields */ 391 #define SYN_RX_CHAN_S 0 392 #define SYN_RX_CHAN_M 0xF 393 #define SYN_RX_CHAN_V(x) ((x) << SYN_RX_CHAN_S) 394 #define SYN_RX_CHAN_G(x) (((x) >> SYN_RX_CHAN_S) & SYN_RX_CHAN_M) 395 396 #define TCP_HDR_LEN_S 10 397 #define TCP_HDR_LEN_M 0x3F 398 #define TCP_HDR_LEN_V(x) ((x) << TCP_HDR_LEN_S) 399 #define TCP_HDR_LEN_G(x) (((x) >> TCP_HDR_LEN_S) & TCP_HDR_LEN_M) 400 401 #define IP_HDR_LEN_S 16 402 #define IP_HDR_LEN_M 0x3FF 403 #define IP_HDR_LEN_V(x) ((x) << IP_HDR_LEN_S) 404 #define IP_HDR_LEN_G(x) (((x) >> IP_HDR_LEN_S) & IP_HDR_LEN_M) 405 406 #define ETH_HDR_LEN_S 26 407 #define ETH_HDR_LEN_M 0x1F 408 #define ETH_HDR_LEN_V(x) ((x) << ETH_HDR_LEN_S) 409 #define ETH_HDR_LEN_G(x) (((x) >> ETH_HDR_LEN_S) & ETH_HDR_LEN_M) 410 411 /* cpl_pass_accept_req.l2info fields */ 412 #define SYN_MAC_IDX_S 0 413 #define SYN_MAC_IDX_M 0x1FF 414 #define SYN_MAC_IDX_V(x) ((x) << SYN_MAC_IDX_S) 415 #define SYN_MAC_IDX_G(x) (((x) >> SYN_MAC_IDX_S) & SYN_MAC_IDX_M) 416 417 #define SYN_XACT_MATCH_S 9 418 #define SYN_XACT_MATCH_V(x) ((x) << SYN_XACT_MATCH_S) 419 #define SYN_XACT_MATCH_F SYN_XACT_MATCH_V(1U) 420 421 #define SYN_INTF_S 12 422 #define SYN_INTF_M 0xF 423 #define SYN_INTF_V(x) ((x) << SYN_INTF_S) 424 #define SYN_INTF_G(x) (((x) >> SYN_INTF_S) & SYN_INTF_M) 425 426 enum { /* TCP congestion control algorithms */ 427 CONG_ALG_RENO, 428 CONG_ALG_TAHOE, 429 CONG_ALG_NEWRENO, 430 CONG_ALG_HIGHSPEED 431 }; 432 433 #define CONG_CNTRL_S 14 434 #define CONG_CNTRL_M 0x3 435 #define CONG_CNTRL_V(x) ((x) << CONG_CNTRL_S) 436 #define CONG_CNTRL_G(x) (((x) >> CONG_CNTRL_S) & CONG_CNTRL_M) 437 438 #define T5_ISS_S 18 439 #define T5_ISS_V(x) ((x) << T5_ISS_S) 440 #define T5_ISS_F T5_ISS_V(1U) 441 442 struct cpl_pass_accept_rpl { 443 WR_HDR; 444 union opcode_tid ot; 445 __be32 opt2; 446 __be64 opt0; 447 }; 448 449 /* option 2 fields */ 450 #define RX_COALESCE_VALID_S 11 451 #define RX_COALESCE_VALID_V(x) ((x) << RX_COALESCE_VALID_S) 452 #define RX_COALESCE_VALID_F RX_COALESCE_VALID_V(1U) 453 454 #define RX_COALESCE_S 12 455 #define RX_COALESCE_V(x) ((x) << RX_COALESCE_S) 456 457 #define PACE_S 16 458 #define PACE_V(x) ((x) << PACE_S) 459 460 #define TX_QUEUE_S 23 461 #define TX_QUEUE_M 0x7 462 #define TX_QUEUE_V(x) ((x) << TX_QUEUE_S) 463 #define TX_QUEUE_G(x) (((x) >> TX_QUEUE_S) & TX_QUEUE_M) 464 465 #define CCTRL_ECN_S 27 466 #define CCTRL_ECN_V(x) ((x) << CCTRL_ECN_S) 467 #define CCTRL_ECN_F CCTRL_ECN_V(1U) 468 469 #define TSTAMPS_EN_S 29 470 #define TSTAMPS_EN_V(x) ((x) << TSTAMPS_EN_S) 471 #define TSTAMPS_EN_F TSTAMPS_EN_V(1U) 472 473 #define SACK_EN_S 30 474 #define SACK_EN_V(x) ((x) << SACK_EN_S) 475 #define SACK_EN_F SACK_EN_V(1U) 476 477 struct cpl_t5_pass_accept_rpl { 478 WR_HDR; 479 union opcode_tid ot; 480 __be32 opt2; 481 __be64 opt0; 482 __be32 iss; 483 __be32 rsvd; 484 }; 485 486 struct cpl_act_open_req { 487 WR_HDR; 488 union opcode_tid ot; 489 __be16 local_port; 490 __be16 peer_port; 491 __be32 local_ip; 492 __be32 peer_ip; 493 __be64 opt0; 494 __be32 params; 495 __be32 opt2; 496 }; 497 498 #define FILTER_TUPLE_S 24 499 #define FILTER_TUPLE_M 0xFFFFFFFFFF 500 #define FILTER_TUPLE_V(x) ((x) << FILTER_TUPLE_S) 501 #define FILTER_TUPLE_G(x) (((x) >> FILTER_TUPLE_S) & FILTER_TUPLE_M) 502 struct cpl_t5_act_open_req { 503 WR_HDR; 504 union opcode_tid ot; 505 __be16 local_port; 506 __be16 peer_port; 507 __be32 local_ip; 508 __be32 peer_ip; 509 __be64 opt0; 510 __be32 rsvd; 511 __be32 opt2; 512 __be64 params; 513 }; 514 515 struct cpl_t6_act_open_req { 516 WR_HDR; 517 union opcode_tid ot; 518 __be16 local_port; 519 __be16 peer_port; 520 __be32 local_ip; 521 __be32 peer_ip; 522 __be64 opt0; 523 __be32 rsvd; 524 __be32 opt2; 525 __be64 params; 526 __be32 rsvd2; 527 __be32 opt3; 528 }; 529 530 struct cpl_act_open_req6 { 531 WR_HDR; 532 union opcode_tid ot; 533 __be16 local_port; 534 __be16 peer_port; 535 __be64 local_ip_hi; 536 __be64 local_ip_lo; 537 __be64 peer_ip_hi; 538 __be64 peer_ip_lo; 539 __be64 opt0; 540 __be32 params; 541 __be32 opt2; 542 }; 543 544 struct cpl_t5_act_open_req6 { 545 WR_HDR; 546 union opcode_tid ot; 547 __be16 local_port; 548 __be16 peer_port; 549 __be64 local_ip_hi; 550 __be64 local_ip_lo; 551 __be64 peer_ip_hi; 552 __be64 peer_ip_lo; 553 __be64 opt0; 554 __be32 rsvd; 555 __be32 opt2; 556 __be64 params; 557 }; 558 559 struct cpl_t6_act_open_req6 { 560 WR_HDR; 561 union opcode_tid ot; 562 __be16 local_port; 563 __be16 peer_port; 564 __be64 local_ip_hi; 565 __be64 local_ip_lo; 566 __be64 peer_ip_hi; 567 __be64 peer_ip_lo; 568 __be64 opt0; 569 __be32 rsvd; 570 __be32 opt2; 571 __be64 params; 572 __be32 rsvd2; 573 __be32 opt3; 574 }; 575 576 struct cpl_act_open_rpl { 577 union opcode_tid ot; 578 __be32 atid_status; 579 }; 580 581 /* cpl_act_open_rpl.atid_status fields */ 582 #define AOPEN_STATUS_S 0 583 #define AOPEN_STATUS_M 0xFF 584 #define AOPEN_STATUS_G(x) (((x) >> AOPEN_STATUS_S) & AOPEN_STATUS_M) 585 586 #define AOPEN_ATID_S 8 587 #define AOPEN_ATID_M 0xFFFFFF 588 #define AOPEN_ATID_G(x) (((x) >> AOPEN_ATID_S) & AOPEN_ATID_M) 589 590 struct cpl_pass_establish { 591 union opcode_tid ot; 592 __be32 rsvd; 593 __be32 tos_stid; 594 __be16 mac_idx; 595 __be16 tcp_opt; 596 __be32 snd_isn; 597 __be32 rcv_isn; 598 }; 599 600 /* cpl_pass_establish.tos_stid fields */ 601 #define PASS_OPEN_TID_S 0 602 #define PASS_OPEN_TID_M 0xFFFFFF 603 #define PASS_OPEN_TID_V(x) ((x) << PASS_OPEN_TID_S) 604 #define PASS_OPEN_TID_G(x) (((x) >> PASS_OPEN_TID_S) & PASS_OPEN_TID_M) 605 606 #define PASS_OPEN_TOS_S 24 607 #define PASS_OPEN_TOS_M 0xFF 608 #define PASS_OPEN_TOS_V(x) ((x) << PASS_OPEN_TOS_S) 609 #define PASS_OPEN_TOS_G(x) (((x) >> PASS_OPEN_TOS_S) & PASS_OPEN_TOS_M) 610 611 /* cpl_pass_establish.tcp_opt fields (also applies to act_open_establish) */ 612 #define TCPOPT_WSCALE_OK_S 5 613 #define TCPOPT_WSCALE_OK_M 0x1 614 #define TCPOPT_WSCALE_OK_G(x) \ 615 (((x) >> TCPOPT_WSCALE_OK_S) & TCPOPT_WSCALE_OK_M) 616 617 #define TCPOPT_SACK_S 6 618 #define TCPOPT_SACK_M 0x1 619 #define TCPOPT_SACK_G(x) (((x) >> TCPOPT_SACK_S) & TCPOPT_SACK_M) 620 621 #define TCPOPT_TSTAMP_S 7 622 #define TCPOPT_TSTAMP_M 0x1 623 #define TCPOPT_TSTAMP_G(x) (((x) >> TCPOPT_TSTAMP_S) & TCPOPT_TSTAMP_M) 624 625 #define TCPOPT_SND_WSCALE_S 8 626 #define TCPOPT_SND_WSCALE_M 0xF 627 #define TCPOPT_SND_WSCALE_G(x) \ 628 (((x) >> TCPOPT_SND_WSCALE_S) & TCPOPT_SND_WSCALE_M) 629 630 #define TCPOPT_MSS_S 12 631 #define TCPOPT_MSS_M 0xF 632 #define TCPOPT_MSS_G(x) (((x) >> TCPOPT_MSS_S) & TCPOPT_MSS_M) 633 634 #define T6_TCP_HDR_LEN_S 8 635 #define T6_TCP_HDR_LEN_V(x) ((x) << T6_TCP_HDR_LEN_S) 636 #define T6_TCP_HDR_LEN_G(x) (((x) >> T6_TCP_HDR_LEN_S) & TCP_HDR_LEN_M) 637 638 #define T6_IP_HDR_LEN_S 14 639 #define T6_IP_HDR_LEN_V(x) ((x) << T6_IP_HDR_LEN_S) 640 #define T6_IP_HDR_LEN_G(x) (((x) >> T6_IP_HDR_LEN_S) & IP_HDR_LEN_M) 641 642 #define T6_ETH_HDR_LEN_S 24 643 #define T6_ETH_HDR_LEN_M 0xFF 644 #define T6_ETH_HDR_LEN_V(x) ((x) << T6_ETH_HDR_LEN_S) 645 #define T6_ETH_HDR_LEN_G(x) (((x) >> T6_ETH_HDR_LEN_S) & T6_ETH_HDR_LEN_M) 646 647 struct cpl_act_establish { 648 union opcode_tid ot; 649 __be32 rsvd; 650 __be32 tos_atid; 651 __be16 mac_idx; 652 __be16 tcp_opt; 653 __be32 snd_isn; 654 __be32 rcv_isn; 655 }; 656 657 struct cpl_get_tcb { 658 WR_HDR; 659 union opcode_tid ot; 660 __be16 reply_ctrl; 661 __be16 cookie; 662 }; 663 664 /* cpl_get_tcb.reply_ctrl fields */ 665 #define QUEUENO_S 0 666 #define QUEUENO_V(x) ((x) << QUEUENO_S) 667 668 #define REPLY_CHAN_S 14 669 #define REPLY_CHAN_V(x) ((x) << REPLY_CHAN_S) 670 #define REPLY_CHAN_F REPLY_CHAN_V(1U) 671 672 #define NO_REPLY_S 15 673 #define NO_REPLY_V(x) ((x) << NO_REPLY_S) 674 #define NO_REPLY_F NO_REPLY_V(1U) 675 676 struct cpl_set_tcb_field { 677 WR_HDR; 678 union opcode_tid ot; 679 __be16 reply_ctrl; 680 __be16 word_cookie; 681 __be64 mask; 682 __be64 val; 683 }; 684 685 /* cpl_set_tcb_field.word_cookie fields */ 686 #define TCB_WORD_S 0 687 #define TCB_WORD_V(x) ((x) << TCB_WORD_S) 688 689 #define TCB_COOKIE_S 5 690 #define TCB_COOKIE_M 0x7 691 #define TCB_COOKIE_V(x) ((x) << TCB_COOKIE_S) 692 #define TCB_COOKIE_G(x) (((x) >> TCB_COOKIE_S) & TCB_COOKIE_M) 693 694 struct cpl_set_tcb_rpl { 695 union opcode_tid ot; 696 __be16 rsvd; 697 u8 cookie; 698 u8 status; 699 __be64 oldval; 700 }; 701 702 struct cpl_close_con_req { 703 WR_HDR; 704 union opcode_tid ot; 705 __be32 rsvd; 706 }; 707 708 struct cpl_close_con_rpl { 709 union opcode_tid ot; 710 u8 rsvd[3]; 711 u8 status; 712 __be32 snd_nxt; 713 __be32 rcv_nxt; 714 }; 715 716 struct cpl_close_listsvr_req { 717 WR_HDR; 718 union opcode_tid ot; 719 __be16 reply_ctrl; 720 __be16 rsvd; 721 }; 722 723 /* additional cpl_close_listsvr_req.reply_ctrl field */ 724 #define LISTSVR_IPV6_S 14 725 #define LISTSVR_IPV6_V(x) ((x) << LISTSVR_IPV6_S) 726 #define LISTSVR_IPV6_F LISTSVR_IPV6_V(1U) 727 728 struct cpl_close_listsvr_rpl { 729 union opcode_tid ot; 730 u8 rsvd[3]; 731 u8 status; 732 }; 733 734 struct cpl_abort_req_rss { 735 union opcode_tid ot; 736 u8 rsvd[3]; 737 u8 status; 738 }; 739 740 struct cpl_abort_req { 741 WR_HDR; 742 union opcode_tid ot; 743 __be32 rsvd0; 744 u8 rsvd1; 745 u8 cmd; 746 u8 rsvd2[6]; 747 }; 748 749 struct cpl_abort_rpl_rss { 750 union opcode_tid ot; 751 u8 rsvd[3]; 752 u8 status; 753 }; 754 755 struct cpl_abort_rpl { 756 WR_HDR; 757 union opcode_tid ot; 758 __be32 rsvd0; 759 u8 rsvd1; 760 u8 cmd; 761 u8 rsvd2[6]; 762 }; 763 764 struct cpl_peer_close { 765 union opcode_tid ot; 766 __be32 rcv_nxt; 767 }; 768 769 struct cpl_tid_release { 770 WR_HDR; 771 union opcode_tid ot; 772 __be32 rsvd; 773 }; 774 775 struct cpl_tx_pkt_core { 776 __be32 ctrl0; 777 __be16 pack; 778 __be16 len; 779 __be64 ctrl1; 780 }; 781 782 struct cpl_tx_pkt { 783 WR_HDR; 784 struct cpl_tx_pkt_core c; 785 }; 786 787 #define cpl_tx_pkt_xt cpl_tx_pkt 788 789 /* cpl_tx_pkt_core.ctrl0 fields */ 790 #define TXPKT_VF_S 0 791 #define TXPKT_VF_V(x) ((x) << TXPKT_VF_S) 792 793 #define TXPKT_PF_S 8 794 #define TXPKT_PF_V(x) ((x) << TXPKT_PF_S) 795 796 #define TXPKT_VF_VLD_S 11 797 #define TXPKT_VF_VLD_V(x) ((x) << TXPKT_VF_VLD_S) 798 #define TXPKT_VF_VLD_F TXPKT_VF_VLD_V(1U) 799 800 #define TXPKT_OVLAN_IDX_S 12 801 #define TXPKT_OVLAN_IDX_V(x) ((x) << TXPKT_OVLAN_IDX_S) 802 803 #define TXPKT_T5_OVLAN_IDX_S 12 804 #define TXPKT_T5_OVLAN_IDX_V(x) ((x) << TXPKT_T5_OVLAN_IDX_S) 805 806 #define TXPKT_INTF_S 16 807 #define TXPKT_INTF_V(x) ((x) << TXPKT_INTF_S) 808 809 #define TXPKT_INS_OVLAN_S 21 810 #define TXPKT_INS_OVLAN_V(x) ((x) << TXPKT_INS_OVLAN_S) 811 #define TXPKT_INS_OVLAN_F TXPKT_INS_OVLAN_V(1U) 812 813 #define TXPKT_TSTAMP_S 23 814 #define TXPKT_TSTAMP_V(x) ((x) << TXPKT_TSTAMP_S) 815 #define TXPKT_TSTAMP_F TXPKT_TSTAMP_V(1ULL) 816 817 #define TXPKT_OPCODE_S 24 818 #define TXPKT_OPCODE_V(x) ((x) << TXPKT_OPCODE_S) 819 820 /* cpl_tx_pkt_core.ctrl1 fields */ 821 #define TXPKT_CSUM_END_S 12 822 #define TXPKT_CSUM_END_V(x) ((x) << TXPKT_CSUM_END_S) 823 824 #define TXPKT_CSUM_START_S 20 825 #define TXPKT_CSUM_START_V(x) ((x) << TXPKT_CSUM_START_S) 826 827 #define TXPKT_IPHDR_LEN_S 20 828 #define TXPKT_IPHDR_LEN_V(x) ((__u64)(x) << TXPKT_IPHDR_LEN_S) 829 830 #define TXPKT_CSUM_LOC_S 30 831 #define TXPKT_CSUM_LOC_V(x) ((__u64)(x) << TXPKT_CSUM_LOC_S) 832 833 #define TXPKT_ETHHDR_LEN_S 34 834 #define TXPKT_ETHHDR_LEN_V(x) ((__u64)(x) << TXPKT_ETHHDR_LEN_S) 835 836 #define T6_TXPKT_ETHHDR_LEN_S 32 837 #define T6_TXPKT_ETHHDR_LEN_V(x) ((__u64)(x) << T6_TXPKT_ETHHDR_LEN_S) 838 839 #define TXPKT_CSUM_TYPE_S 40 840 #define TXPKT_CSUM_TYPE_V(x) ((__u64)(x) << TXPKT_CSUM_TYPE_S) 841 842 #define TXPKT_VLAN_S 44 843 #define TXPKT_VLAN_V(x) ((__u64)(x) << TXPKT_VLAN_S) 844 845 #define TXPKT_VLAN_VLD_S 60 846 #define TXPKT_VLAN_VLD_V(x) ((__u64)(x) << TXPKT_VLAN_VLD_S) 847 #define TXPKT_VLAN_VLD_F TXPKT_VLAN_VLD_V(1ULL) 848 849 #define TXPKT_IPCSUM_DIS_S 62 850 #define TXPKT_IPCSUM_DIS_V(x) ((__u64)(x) << TXPKT_IPCSUM_DIS_S) 851 #define TXPKT_IPCSUM_DIS_F TXPKT_IPCSUM_DIS_V(1ULL) 852 853 #define TXPKT_L4CSUM_DIS_S 63 854 #define TXPKT_L4CSUM_DIS_V(x) ((__u64)(x) << TXPKT_L4CSUM_DIS_S) 855 #define TXPKT_L4CSUM_DIS_F TXPKT_L4CSUM_DIS_V(1ULL) 856 857 struct cpl_tx_pkt_lso_core { 858 __be32 lso_ctrl; 859 __be16 ipid_ofst; 860 __be16 mss; 861 __be32 seqno_offset; 862 __be32 len; 863 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 864 }; 865 866 /* cpl_tx_pkt_lso_core.lso_ctrl fields */ 867 #define LSO_TCPHDR_LEN_S 0 868 #define LSO_TCPHDR_LEN_V(x) ((x) << LSO_TCPHDR_LEN_S) 869 870 #define LSO_IPHDR_LEN_S 4 871 #define LSO_IPHDR_LEN_V(x) ((x) << LSO_IPHDR_LEN_S) 872 873 #define LSO_ETHHDR_LEN_S 16 874 #define LSO_ETHHDR_LEN_V(x) ((x) << LSO_ETHHDR_LEN_S) 875 876 #define LSO_IPV6_S 20 877 #define LSO_IPV6_V(x) ((x) << LSO_IPV6_S) 878 #define LSO_IPV6_F LSO_IPV6_V(1U) 879 880 #define LSO_LAST_SLICE_S 22 881 #define LSO_LAST_SLICE_V(x) ((x) << LSO_LAST_SLICE_S) 882 #define LSO_LAST_SLICE_F LSO_LAST_SLICE_V(1U) 883 884 #define LSO_FIRST_SLICE_S 23 885 #define LSO_FIRST_SLICE_V(x) ((x) << LSO_FIRST_SLICE_S) 886 #define LSO_FIRST_SLICE_F LSO_FIRST_SLICE_V(1U) 887 888 #define LSO_OPCODE_S 24 889 #define LSO_OPCODE_V(x) ((x) << LSO_OPCODE_S) 890 891 #define LSO_T5_XFER_SIZE_S 0 892 #define LSO_T5_XFER_SIZE_V(x) ((x) << LSO_T5_XFER_SIZE_S) 893 894 struct cpl_tx_pkt_lso { 895 WR_HDR; 896 struct cpl_tx_pkt_lso_core c; 897 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 898 }; 899 900 struct cpl_iscsi_hdr { 901 union opcode_tid ot; 902 __be16 pdu_len_ddp; 903 __be16 len; 904 __be32 seq; 905 __be16 urg; 906 u8 rsvd; 907 u8 status; 908 }; 909 910 /* cpl_iscsi_hdr.pdu_len_ddp fields */ 911 #define ISCSI_PDU_LEN_S 0 912 #define ISCSI_PDU_LEN_M 0x7FFF 913 #define ISCSI_PDU_LEN_V(x) ((x) << ISCSI_PDU_LEN_S) 914 #define ISCSI_PDU_LEN_G(x) (((x) >> ISCSI_PDU_LEN_S) & ISCSI_PDU_LEN_M) 915 916 #define ISCSI_DDP_S 15 917 #define ISCSI_DDP_V(x) ((x) << ISCSI_DDP_S) 918 #define ISCSI_DDP_F ISCSI_DDP_V(1U) 919 920 struct cpl_rx_data_ddp { 921 union opcode_tid ot; 922 __be16 urg; 923 __be16 len; 924 __be32 seq; 925 union { 926 __be32 nxt_seq; 927 __be32 ddp_report; 928 }; 929 __be32 ulp_crc; 930 __be32 ddpvld; 931 }; 932 933 #define cpl_rx_iscsi_ddp cpl_rx_data_ddp 934 935 struct cpl_iscsi_data { 936 union opcode_tid ot; 937 __u8 rsvd0[2]; 938 __be16 len; 939 __be32 seq; 940 __be16 urg; 941 __u8 rsvd1; 942 __u8 status; 943 }; 944 945 struct cpl_rx_iscsi_cmp { 946 union opcode_tid ot; 947 __be16 pdu_len_ddp; 948 __be16 len; 949 __be32 seq; 950 __be16 urg; 951 __u8 rsvd; 952 __u8 status; 953 __be32 ulp_crc; 954 __be32 ddpvld; 955 }; 956 957 struct cpl_tx_data_iso { 958 __be32 op_to_scsi; 959 __u8 reserved1; 960 __u8 ahs_len; 961 __be16 mpdu; 962 __be32 burst_size; 963 __be32 len; 964 __be32 reserved2_seglen_offset; 965 __be32 datasn_offset; 966 __be32 buffer_offset; 967 __be32 reserved3; 968 969 /* encapsulated CPL_TX_DATA follows here */ 970 }; 971 972 /* cpl_tx_data_iso.op_to_scsi fields */ 973 #define CPL_TX_DATA_ISO_OP_S 24 974 #define CPL_TX_DATA_ISO_OP_M 0xff 975 #define CPL_TX_DATA_ISO_OP_V(x) ((x) << CPL_TX_DATA_ISO_OP_S) 976 #define CPL_TX_DATA_ISO_OP_G(x) \ 977 (((x) >> CPL_TX_DATA_ISO_OP_S) & CPL_TX_DATA_ISO_OP_M) 978 979 #define CPL_TX_DATA_ISO_FIRST_S 23 980 #define CPL_TX_DATA_ISO_FIRST_M 0x1 981 #define CPL_TX_DATA_ISO_FIRST_V(x) ((x) << CPL_TX_DATA_ISO_FIRST_S) 982 #define CPL_TX_DATA_ISO_FIRST_G(x) \ 983 (((x) >> CPL_TX_DATA_ISO_FIRST_S) & CPL_TX_DATA_ISO_FIRST_M) 984 #define CPL_TX_DATA_ISO_FIRST_F CPL_TX_DATA_ISO_FIRST_V(1U) 985 986 #define CPL_TX_DATA_ISO_LAST_S 22 987 #define CPL_TX_DATA_ISO_LAST_M 0x1 988 #define CPL_TX_DATA_ISO_LAST_V(x) ((x) << CPL_TX_DATA_ISO_LAST_S) 989 #define CPL_TX_DATA_ISO_LAST_G(x) \ 990 (((x) >> CPL_TX_DATA_ISO_LAST_S) & CPL_TX_DATA_ISO_LAST_M) 991 #define CPL_TX_DATA_ISO_LAST_F CPL_TX_DATA_ISO_LAST_V(1U) 992 993 #define CPL_TX_DATA_ISO_CPLHDRLEN_S 21 994 #define CPL_TX_DATA_ISO_CPLHDRLEN_M 0x1 995 #define CPL_TX_DATA_ISO_CPLHDRLEN_V(x) ((x) << CPL_TX_DATA_ISO_CPLHDRLEN_S) 996 #define CPL_TX_DATA_ISO_CPLHDRLEN_G(x) \ 997 (((x) >> CPL_TX_DATA_ISO_CPLHDRLEN_S) & CPL_TX_DATA_ISO_CPLHDRLEN_M) 998 #define CPL_TX_DATA_ISO_CPLHDRLEN_F CPL_TX_DATA_ISO_CPLHDRLEN_V(1U) 999 1000 #define CPL_TX_DATA_ISO_HDRCRC_S 20 1001 #define CPL_TX_DATA_ISO_HDRCRC_M 0x1 1002 #define CPL_TX_DATA_ISO_HDRCRC_V(x) ((x) << CPL_TX_DATA_ISO_HDRCRC_S) 1003 #define CPL_TX_DATA_ISO_HDRCRC_G(x) \ 1004 (((x) >> CPL_TX_DATA_ISO_HDRCRC_S) & CPL_TX_DATA_ISO_HDRCRC_M) 1005 #define CPL_TX_DATA_ISO_HDRCRC_F CPL_TX_DATA_ISO_HDRCRC_V(1U) 1006 1007 #define CPL_TX_DATA_ISO_PLDCRC_S 19 1008 #define CPL_TX_DATA_ISO_PLDCRC_M 0x1 1009 #define CPL_TX_DATA_ISO_PLDCRC_V(x) ((x) << CPL_TX_DATA_ISO_PLDCRC_S) 1010 #define CPL_TX_DATA_ISO_PLDCRC_G(x) \ 1011 (((x) >> CPL_TX_DATA_ISO_PLDCRC_S) & CPL_TX_DATA_ISO_PLDCRC_M) 1012 #define CPL_TX_DATA_ISO_PLDCRC_F CPL_TX_DATA_ISO_PLDCRC_V(1U) 1013 1014 #define CPL_TX_DATA_ISO_IMMEDIATE_S 18 1015 #define CPL_TX_DATA_ISO_IMMEDIATE_M 0x1 1016 #define CPL_TX_DATA_ISO_IMMEDIATE_V(x) ((x) << CPL_TX_DATA_ISO_IMMEDIATE_S) 1017 #define CPL_TX_DATA_ISO_IMMEDIATE_G(x) \ 1018 (((x) >> CPL_TX_DATA_ISO_IMMEDIATE_S) & CPL_TX_DATA_ISO_IMMEDIATE_M) 1019 #define CPL_TX_DATA_ISO_IMMEDIATE_F CPL_TX_DATA_ISO_IMMEDIATE_V(1U) 1020 1021 #define CPL_TX_DATA_ISO_SCSI_S 16 1022 #define CPL_TX_DATA_ISO_SCSI_M 0x3 1023 #define CPL_TX_DATA_ISO_SCSI_V(x) ((x) << CPL_TX_DATA_ISO_SCSI_S) 1024 #define CPL_TX_DATA_ISO_SCSI_G(x) \ 1025 (((x) >> CPL_TX_DATA_ISO_SCSI_S) & CPL_TX_DATA_ISO_SCSI_M) 1026 1027 /* cpl_tx_data_iso.reserved2_seglen_offset fields */ 1028 #define CPL_TX_DATA_ISO_SEGLEN_OFFSET_S 0 1029 #define CPL_TX_DATA_ISO_SEGLEN_OFFSET_M 0xffffff 1030 #define CPL_TX_DATA_ISO_SEGLEN_OFFSET_V(x) \ 1031 ((x) << CPL_TX_DATA_ISO_SEGLEN_OFFSET_S) 1032 #define CPL_TX_DATA_ISO_SEGLEN_OFFSET_G(x) \ 1033 (((x) >> CPL_TX_DATA_ISO_SEGLEN_OFFSET_S) & \ 1034 CPL_TX_DATA_ISO_SEGLEN_OFFSET_M) 1035 1036 struct cpl_rx_data { 1037 union opcode_tid ot; 1038 __be16 rsvd; 1039 __be16 len; 1040 __be32 seq; 1041 __be16 urg; 1042 #if defined(__LITTLE_ENDIAN_BITFIELD) 1043 u8 dack_mode:2; 1044 u8 psh:1; 1045 u8 heartbeat:1; 1046 u8 ddp_off:1; 1047 u8 :3; 1048 #else 1049 u8 :3; 1050 u8 ddp_off:1; 1051 u8 heartbeat:1; 1052 u8 psh:1; 1053 u8 dack_mode:2; 1054 #endif 1055 u8 status; 1056 }; 1057 1058 struct cpl_rx_data_ack { 1059 WR_HDR; 1060 union opcode_tid ot; 1061 __be32 credit_dack; 1062 }; 1063 1064 /* cpl_rx_data_ack.ack_seq fields */ 1065 #define RX_CREDITS_S 0 1066 #define RX_CREDITS_V(x) ((x) << RX_CREDITS_S) 1067 1068 #define RX_FORCE_ACK_S 28 1069 #define RX_FORCE_ACK_V(x) ((x) << RX_FORCE_ACK_S) 1070 #define RX_FORCE_ACK_F RX_FORCE_ACK_V(1U) 1071 1072 #define RX_DACK_MODE_S 29 1073 #define RX_DACK_MODE_M 0x3 1074 #define RX_DACK_MODE_V(x) ((x) << RX_DACK_MODE_S) 1075 #define RX_DACK_MODE_G(x) (((x) >> RX_DACK_MODE_S) & RX_DACK_MODE_M) 1076 1077 #define RX_DACK_CHANGE_S 31 1078 #define RX_DACK_CHANGE_V(x) ((x) << RX_DACK_CHANGE_S) 1079 #define RX_DACK_CHANGE_F RX_DACK_CHANGE_V(1U) 1080 1081 struct cpl_rx_pkt { 1082 struct rss_header rsshdr; 1083 u8 opcode; 1084 #if defined(__LITTLE_ENDIAN_BITFIELD) 1085 u8 iff:4; 1086 u8 csum_calc:1; 1087 u8 ipmi_pkt:1; 1088 u8 vlan_ex:1; 1089 u8 ip_frag:1; 1090 #else 1091 u8 ip_frag:1; 1092 u8 vlan_ex:1; 1093 u8 ipmi_pkt:1; 1094 u8 csum_calc:1; 1095 u8 iff:4; 1096 #endif 1097 __be16 csum; 1098 __be16 vlan; 1099 __be16 len; 1100 __be32 l2info; 1101 __be16 hdr_len; 1102 __be16 err_vec; 1103 }; 1104 1105 #define RX_T6_ETHHDR_LEN_M 0xFF 1106 #define RX_T6_ETHHDR_LEN_G(x) (((x) >> RX_ETHHDR_LEN_S) & RX_T6_ETHHDR_LEN_M) 1107 1108 #define RXF_PSH_S 20 1109 #define RXF_PSH_V(x) ((x) << RXF_PSH_S) 1110 #define RXF_PSH_F RXF_PSH_V(1U) 1111 1112 #define RXF_SYN_S 21 1113 #define RXF_SYN_V(x) ((x) << RXF_SYN_S) 1114 #define RXF_SYN_F RXF_SYN_V(1U) 1115 1116 #define RXF_UDP_S 22 1117 #define RXF_UDP_V(x) ((x) << RXF_UDP_S) 1118 #define RXF_UDP_F RXF_UDP_V(1U) 1119 1120 #define RXF_TCP_S 23 1121 #define RXF_TCP_V(x) ((x) << RXF_TCP_S) 1122 #define RXF_TCP_F RXF_TCP_V(1U) 1123 1124 #define RXF_IP_S 24 1125 #define RXF_IP_V(x) ((x) << RXF_IP_S) 1126 #define RXF_IP_F RXF_IP_V(1U) 1127 1128 #define RXF_IP6_S 25 1129 #define RXF_IP6_V(x) ((x) << RXF_IP6_S) 1130 #define RXF_IP6_F RXF_IP6_V(1U) 1131 1132 #define RXF_SYN_COOKIE_S 26 1133 #define RXF_SYN_COOKIE_V(x) ((x) << RXF_SYN_COOKIE_S) 1134 #define RXF_SYN_COOKIE_F RXF_SYN_COOKIE_V(1U) 1135 1136 #define RXF_FCOE_S 26 1137 #define RXF_FCOE_V(x) ((x) << RXF_FCOE_S) 1138 #define RXF_FCOE_F RXF_FCOE_V(1U) 1139 1140 #define RXF_LRO_S 27 1141 #define RXF_LRO_V(x) ((x) << RXF_LRO_S) 1142 #define RXF_LRO_F RXF_LRO_V(1U) 1143 1144 /* rx_pkt.l2info fields */ 1145 #define RX_ETHHDR_LEN_S 0 1146 #define RX_ETHHDR_LEN_M 0x1F 1147 #define RX_ETHHDR_LEN_V(x) ((x) << RX_ETHHDR_LEN_S) 1148 #define RX_ETHHDR_LEN_G(x) (((x) >> RX_ETHHDR_LEN_S) & RX_ETHHDR_LEN_M) 1149 1150 #define RX_T5_ETHHDR_LEN_S 0 1151 #define RX_T5_ETHHDR_LEN_M 0x3F 1152 #define RX_T5_ETHHDR_LEN_V(x) ((x) << RX_T5_ETHHDR_LEN_S) 1153 #define RX_T5_ETHHDR_LEN_G(x) (((x) >> RX_T5_ETHHDR_LEN_S) & RX_T5_ETHHDR_LEN_M) 1154 1155 #define RX_MACIDX_S 8 1156 #define RX_MACIDX_M 0x1FF 1157 #define RX_MACIDX_V(x) ((x) << RX_MACIDX_S) 1158 #define RX_MACIDX_G(x) (((x) >> RX_MACIDX_S) & RX_MACIDX_M) 1159 1160 #define RXF_SYN_S 21 1161 #define RXF_SYN_V(x) ((x) << RXF_SYN_S) 1162 #define RXF_SYN_F RXF_SYN_V(1U) 1163 1164 #define RX_CHAN_S 28 1165 #define RX_CHAN_M 0xF 1166 #define RX_CHAN_V(x) ((x) << RX_CHAN_S) 1167 #define RX_CHAN_G(x) (((x) >> RX_CHAN_S) & RX_CHAN_M) 1168 1169 /* rx_pkt.hdr_len fields */ 1170 #define RX_TCPHDR_LEN_S 0 1171 #define RX_TCPHDR_LEN_M 0x3F 1172 #define RX_TCPHDR_LEN_V(x) ((x) << RX_TCPHDR_LEN_S) 1173 #define RX_TCPHDR_LEN_G(x) (((x) >> RX_TCPHDR_LEN_S) & RX_TCPHDR_LEN_M) 1174 1175 #define RX_IPHDR_LEN_S 6 1176 #define RX_IPHDR_LEN_M 0x3FF 1177 #define RX_IPHDR_LEN_V(x) ((x) << RX_IPHDR_LEN_S) 1178 #define RX_IPHDR_LEN_G(x) (((x) >> RX_IPHDR_LEN_S) & RX_IPHDR_LEN_M) 1179 1180 /* rx_pkt.err_vec fields */ 1181 #define RXERR_CSUM_S 13 1182 #define RXERR_CSUM_V(x) ((x) << RXERR_CSUM_S) 1183 #define RXERR_CSUM_F RXERR_CSUM_V(1U) 1184 1185 #define T6_COMPR_RXERR_LEN_S 1 1186 #define T6_COMPR_RXERR_LEN_V(x) ((x) << T6_COMPR_RXERR_LEN_S) 1187 #define T6_COMPR_RXERR_LEN_F T6_COMPR_RXERR_LEN_V(1U) 1188 1189 #define T6_COMPR_RXERR_VEC_S 0 1190 #define T6_COMPR_RXERR_VEC_M 0x3F 1191 #define T6_COMPR_RXERR_VEC_V(x) ((x) << T6_COMPR_RXERR_LEN_S) 1192 #define T6_COMPR_RXERR_VEC_G(x) \ 1193 (((x) >> T6_COMPR_RXERR_VEC_S) & T6_COMPR_RXERR_VEC_M) 1194 1195 /* Logical OR of RX_ERROR_CSUM, RX_ERROR_CSIP */ 1196 #define T6_COMPR_RXERR_SUM_S 4 1197 #define T6_COMPR_RXERR_SUM_V(x) ((x) << T6_COMPR_RXERR_SUM_S) 1198 #define T6_COMPR_RXERR_SUM_F T6_COMPR_RXERR_SUM_V(1U) 1199 1200 struct cpl_trace_pkt { 1201 u8 opcode; 1202 u8 intf; 1203 #if defined(__LITTLE_ENDIAN_BITFIELD) 1204 u8 runt:4; 1205 u8 filter_hit:4; 1206 u8 :6; 1207 u8 err:1; 1208 u8 trunc:1; 1209 #else 1210 u8 filter_hit:4; 1211 u8 runt:4; 1212 u8 trunc:1; 1213 u8 err:1; 1214 u8 :6; 1215 #endif 1216 __be16 rsvd; 1217 __be16 len; 1218 __be64 tstamp; 1219 }; 1220 1221 struct cpl_t5_trace_pkt { 1222 __u8 opcode; 1223 __u8 intf; 1224 #if defined(__LITTLE_ENDIAN_BITFIELD) 1225 __u8 runt:4; 1226 __u8 filter_hit:4; 1227 __u8:6; 1228 __u8 err:1; 1229 __u8 trunc:1; 1230 #else 1231 __u8 filter_hit:4; 1232 __u8 runt:4; 1233 __u8 trunc:1; 1234 __u8 err:1; 1235 __u8:6; 1236 #endif 1237 __be16 rsvd; 1238 __be16 len; 1239 __be64 tstamp; 1240 __be64 rsvd1; 1241 }; 1242 1243 struct cpl_l2t_write_req { 1244 WR_HDR; 1245 union opcode_tid ot; 1246 __be16 params; 1247 __be16 l2t_idx; 1248 __be16 vlan; 1249 u8 dst_mac[6]; 1250 }; 1251 1252 /* cpl_l2t_write_req.params fields */ 1253 #define L2T_W_INFO_S 2 1254 #define L2T_W_INFO_V(x) ((x) << L2T_W_INFO_S) 1255 1256 #define L2T_W_PORT_S 8 1257 #define L2T_W_PORT_V(x) ((x) << L2T_W_PORT_S) 1258 1259 #define L2T_W_NOREPLY_S 15 1260 #define L2T_W_NOREPLY_V(x) ((x) << L2T_W_NOREPLY_S) 1261 #define L2T_W_NOREPLY_F L2T_W_NOREPLY_V(1U) 1262 1263 #define CPL_L2T_VLAN_NONE 0xfff 1264 1265 struct cpl_l2t_write_rpl { 1266 union opcode_tid ot; 1267 u8 status; 1268 u8 rsvd[3]; 1269 }; 1270 1271 struct cpl_smt_write_req { 1272 WR_HDR; 1273 union opcode_tid ot; 1274 __be32 params; 1275 __be16 pfvf1; 1276 u8 src_mac1[6]; 1277 __be16 pfvf0; 1278 u8 src_mac0[6]; 1279 }; 1280 1281 struct cpl_t6_smt_write_req { 1282 WR_HDR; 1283 union opcode_tid ot; 1284 __be32 params; 1285 __be64 tag; 1286 __be16 pfvf0; 1287 u8 src_mac0[6]; 1288 __be32 local_ip; 1289 __be32 rsvd; 1290 }; 1291 1292 struct cpl_smt_write_rpl { 1293 union opcode_tid ot; 1294 u8 status; 1295 u8 rsvd[3]; 1296 }; 1297 1298 /* cpl_smt_{read,write}_req.params fields */ 1299 #define SMTW_OVLAN_IDX_S 16 1300 #define SMTW_OVLAN_IDX_V(x) ((x) << SMTW_OVLAN_IDX_S) 1301 1302 #define SMTW_IDX_S 20 1303 #define SMTW_IDX_V(x) ((x) << SMTW_IDX_S) 1304 1305 #define SMTW_NORPL_S 31 1306 #define SMTW_NORPL_V(x) ((x) << SMTW_NORPL_S) 1307 #define SMTW_NORPL_F SMTW_NORPL_V(1U) 1308 1309 struct cpl_rdma_terminate { 1310 union opcode_tid ot; 1311 __be16 rsvd; 1312 __be16 len; 1313 }; 1314 1315 struct cpl_sge_egr_update { 1316 __be32 opcode_qid; 1317 __be16 cidx; 1318 __be16 pidx; 1319 }; 1320 1321 /* cpl_sge_egr_update.ot fields */ 1322 #define EGR_QID_S 0 1323 #define EGR_QID_M 0x1FFFF 1324 #define EGR_QID_G(x) (((x) >> EGR_QID_S) & EGR_QID_M) 1325 1326 /* cpl_fw*.type values */ 1327 enum { 1328 FW_TYPE_CMD_RPL = 0, 1329 FW_TYPE_WR_RPL = 1, 1330 FW_TYPE_CQE = 2, 1331 FW_TYPE_OFLD_CONNECTION_WR_RPL = 3, 1332 FW_TYPE_RSSCPL = 4, 1333 }; 1334 1335 struct cpl_fw4_pld { 1336 u8 opcode; 1337 u8 rsvd0[3]; 1338 u8 type; 1339 u8 rsvd1; 1340 __be16 len; 1341 __be64 data; 1342 __be64 rsvd2; 1343 }; 1344 1345 struct cpl_fw6_pld { 1346 u8 opcode; 1347 u8 rsvd[5]; 1348 __be16 len; 1349 __be64 data[4]; 1350 }; 1351 1352 struct cpl_fw4_msg { 1353 u8 opcode; 1354 u8 type; 1355 __be16 rsvd0; 1356 __be32 rsvd1; 1357 __be64 data[2]; 1358 }; 1359 1360 struct cpl_fw4_ack { 1361 union opcode_tid ot; 1362 u8 credits; 1363 u8 rsvd0[2]; 1364 u8 seq_vld; 1365 __be32 snd_nxt; 1366 __be32 snd_una; 1367 __be64 rsvd1; 1368 }; 1369 1370 enum { 1371 CPL_FW4_ACK_FLAGS_SEQVAL = 0x1, /* seqn valid */ 1372 CPL_FW4_ACK_FLAGS_CH = 0x2, /* channel change complete */ 1373 CPL_FW4_ACK_FLAGS_FLOWC = 0x4, /* fw_flowc_wr complete */ 1374 }; 1375 1376 struct cpl_fw6_msg { 1377 u8 opcode; 1378 u8 type; 1379 __be16 rsvd0; 1380 __be32 rsvd1; 1381 __be64 data[4]; 1382 }; 1383 1384 /* cpl_fw6_msg.type values */ 1385 enum { 1386 FW6_TYPE_CMD_RPL = 0, 1387 FW6_TYPE_WR_RPL = 1, 1388 FW6_TYPE_CQE = 2, 1389 FW6_TYPE_OFLD_CONNECTION_WR_RPL = 3, 1390 FW6_TYPE_RSSCPL = FW_TYPE_RSSCPL, 1391 }; 1392 1393 struct cpl_fw6_msg_ofld_connection_wr_rpl { 1394 __u64 cookie; 1395 __be32 tid; /* or atid in case of active failure */ 1396 __u8 t_state; 1397 __u8 retval; 1398 __u8 rsvd[2]; 1399 }; 1400 1401 struct cpl_tx_data { 1402 union opcode_tid ot; 1403 __be32 len; 1404 __be32 rsvd; 1405 __be32 flags; 1406 }; 1407 1408 /* cpl_tx_data.flags field */ 1409 #define TX_FORCE_S 13 1410 #define TX_FORCE_V(x) ((x) << TX_FORCE_S) 1411 1412 #define T6_TX_FORCE_S 20 1413 #define T6_TX_FORCE_V(x) ((x) << T6_TX_FORCE_S) 1414 #define T6_TX_FORCE_F T6_TX_FORCE_V(1U) 1415 1416 enum { 1417 ULP_TX_MEM_READ = 2, 1418 ULP_TX_MEM_WRITE = 3, 1419 ULP_TX_PKT = 4 1420 }; 1421 1422 enum { 1423 ULP_TX_SC_NOOP = 0x80, 1424 ULP_TX_SC_IMM = 0x81, 1425 ULP_TX_SC_DSGL = 0x82, 1426 ULP_TX_SC_ISGL = 0x83 1427 }; 1428 1429 #define ULPTX_CMD_S 24 1430 #define ULPTX_CMD_V(x) ((x) << ULPTX_CMD_S) 1431 1432 struct ulptx_sge_pair { 1433 __be32 len[2]; 1434 __be64 addr[2]; 1435 }; 1436 1437 struct ulptx_sgl { 1438 __be32 cmd_nsge; 1439 __be32 len0; 1440 __be64 addr0; 1441 struct ulptx_sge_pair sge[0]; 1442 }; 1443 1444 struct ulptx_idata { 1445 __be32 cmd_more; 1446 __be32 len; 1447 }; 1448 1449 struct ulp_txpkt { 1450 __be32 cmd_dest; 1451 __be32 len; 1452 }; 1453 1454 #define ULPTX_CMD_S 24 1455 #define ULPTX_CMD_M 0xFF 1456 #define ULPTX_CMD_V(x) ((x) << ULPTX_CMD_S) 1457 1458 #define ULPTX_NSGE_S 0 1459 #define ULPTX_NSGE_V(x) ((x) << ULPTX_NSGE_S) 1460 1461 #define ULPTX_MORE_S 23 1462 #define ULPTX_MORE_V(x) ((x) << ULPTX_MORE_S) 1463 #define ULPTX_MORE_F ULPTX_MORE_V(1U) 1464 1465 #define ULP_TXPKT_DEST_S 16 1466 #define ULP_TXPKT_DEST_M 0x3 1467 #define ULP_TXPKT_DEST_V(x) ((x) << ULP_TXPKT_DEST_S) 1468 1469 #define ULP_TXPKT_FID_S 4 1470 #define ULP_TXPKT_FID_M 0x7ff 1471 #define ULP_TXPKT_FID_V(x) ((x) << ULP_TXPKT_FID_S) 1472 1473 #define ULP_TXPKT_RO_S 3 1474 #define ULP_TXPKT_RO_V(x) ((x) << ULP_TXPKT_RO_S) 1475 #define ULP_TXPKT_RO_F ULP_TXPKT_RO_V(1U) 1476 1477 #define ULP_TX_SC_MORE_S 23 1478 #define ULP_TX_SC_MORE_V(x) ((x) << ULP_TX_SC_MORE_S) 1479 #define ULP_TX_SC_MORE_F ULP_TX_SC_MORE_V(1U) 1480 1481 struct ulp_mem_io { 1482 WR_HDR; 1483 __be32 cmd; 1484 __be32 len16; /* command length */ 1485 __be32 dlen; /* data length in 32-byte units */ 1486 __be32 lock_addr; 1487 }; 1488 1489 #define ULP_MEMIO_LOCK_S 31 1490 #define ULP_MEMIO_LOCK_V(x) ((x) << ULP_MEMIO_LOCK_S) 1491 #define ULP_MEMIO_LOCK_F ULP_MEMIO_LOCK_V(1U) 1492 1493 /* additional ulp_mem_io.cmd fields */ 1494 #define ULP_MEMIO_ORDER_S 23 1495 #define ULP_MEMIO_ORDER_V(x) ((x) << ULP_MEMIO_ORDER_S) 1496 #define ULP_MEMIO_ORDER_F ULP_MEMIO_ORDER_V(1U) 1497 1498 #define T5_ULP_MEMIO_IMM_S 23 1499 #define T5_ULP_MEMIO_IMM_V(x) ((x) << T5_ULP_MEMIO_IMM_S) 1500 #define T5_ULP_MEMIO_IMM_F T5_ULP_MEMIO_IMM_V(1U) 1501 1502 #define T5_ULP_MEMIO_ORDER_S 22 1503 #define T5_ULP_MEMIO_ORDER_V(x) ((x) << T5_ULP_MEMIO_ORDER_S) 1504 #define T5_ULP_MEMIO_ORDER_F T5_ULP_MEMIO_ORDER_V(1U) 1505 1506 #define T5_ULP_MEMIO_FID_S 4 1507 #define T5_ULP_MEMIO_FID_M 0x7ff 1508 #define T5_ULP_MEMIO_FID_V(x) ((x) << T5_ULP_MEMIO_FID_S) 1509 1510 /* ulp_mem_io.lock_addr fields */ 1511 #define ULP_MEMIO_ADDR_S 0 1512 #define ULP_MEMIO_ADDR_V(x) ((x) << ULP_MEMIO_ADDR_S) 1513 1514 /* ulp_mem_io.dlen fields */ 1515 #define ULP_MEMIO_DATA_LEN_S 0 1516 #define ULP_MEMIO_DATA_LEN_V(x) ((x) << ULP_MEMIO_DATA_LEN_S) 1517 1518 #define ULPTX_NSGE_S 0 1519 #define ULPTX_NSGE_M 0xFFFF 1520 #define ULPTX_NSGE_V(x) ((x) << ULPTX_NSGE_S) 1521 #define ULPTX_NSGE_G(x) (((x) >> ULPTX_NSGE_S) & ULPTX_NSGE_M) 1522 1523 struct ulptx_sc_memrd { 1524 __be32 cmd_to_len; 1525 __be32 addr; 1526 }; 1527 1528 #define ULP_TXPKT_DATAMODIFY_S 23 1529 #define ULP_TXPKT_DATAMODIFY_M 0x1 1530 #define ULP_TXPKT_DATAMODIFY_V(x) ((x) << ULP_TXPKT_DATAMODIFY_S) 1531 #define ULP_TXPKT_DATAMODIFY_G(x) \ 1532 (((x) >> ULP_TXPKT_DATAMODIFY_S) & ULP_TXPKT_DATAMODIFY__M) 1533 #define ULP_TXPKT_DATAMODIFY_F ULP_TXPKT_DATAMODIFY_V(1U) 1534 1535 #define ULP_TXPKT_CHANNELID_S 22 1536 #define ULP_TXPKT_CHANNELID_M 0x1 1537 #define ULP_TXPKT_CHANNELID_V(x) ((x) << ULP_TXPKT_CHANNELID_S) 1538 #define ULP_TXPKT_CHANNELID_G(x) \ 1539 (((x) >> ULP_TXPKT_CHANNELID_S) & ULP_TXPKT_CHANNELID_M) 1540 #define ULP_TXPKT_CHANNELID_F ULP_TXPKT_CHANNELID_V(1U) 1541 1542 #define SCMD_SEQ_NO_CTRL_S 29 1543 #define SCMD_SEQ_NO_CTRL_M 0x3 1544 #define SCMD_SEQ_NO_CTRL_V(x) ((x) << SCMD_SEQ_NO_CTRL_S) 1545 #define SCMD_SEQ_NO_CTRL_G(x) \ 1546 (((x) >> SCMD_SEQ_NO_CTRL_S) & SCMD_SEQ_NO_CTRL_M) 1547 1548 /* StsFieldPrsnt- Status field at the end of the TLS PDU */ 1549 #define SCMD_STATUS_PRESENT_S 28 1550 #define SCMD_STATUS_PRESENT_M 0x1 1551 #define SCMD_STATUS_PRESENT_V(x) ((x) << SCMD_STATUS_PRESENT_S) 1552 #define SCMD_STATUS_PRESENT_G(x) \ 1553 (((x) >> SCMD_STATUS_PRESENT_S) & SCMD_STATUS_PRESENT_M) 1554 #define SCMD_STATUS_PRESENT_F SCMD_STATUS_PRESENT_V(1U) 1555 1556 /* ProtoVersion - Protocol Version 0: 1.2, 1:1.1, 2:DTLS, 3:Generic, 1557 * 3-15: Reserved. 1558 */ 1559 #define SCMD_PROTO_VERSION_S 24 1560 #define SCMD_PROTO_VERSION_M 0xf 1561 #define SCMD_PROTO_VERSION_V(x) ((x) << SCMD_PROTO_VERSION_S) 1562 #define SCMD_PROTO_VERSION_G(x) \ 1563 (((x) >> SCMD_PROTO_VERSION_S) & SCMD_PROTO_VERSION_M) 1564 1565 /* EncDecCtrl - Encryption/Decryption Control. 0: Encrypt, 1: Decrypt */ 1566 #define SCMD_ENC_DEC_CTRL_S 23 1567 #define SCMD_ENC_DEC_CTRL_M 0x1 1568 #define SCMD_ENC_DEC_CTRL_V(x) ((x) << SCMD_ENC_DEC_CTRL_S) 1569 #define SCMD_ENC_DEC_CTRL_G(x) \ 1570 (((x) >> SCMD_ENC_DEC_CTRL_S) & SCMD_ENC_DEC_CTRL_M) 1571 #define SCMD_ENC_DEC_CTRL_F SCMD_ENC_DEC_CTRL_V(1U) 1572 1573 /* CipherAuthSeqCtrl - Cipher Authentication Sequence Control. */ 1574 #define SCMD_CIPH_AUTH_SEQ_CTRL_S 22 1575 #define SCMD_CIPH_AUTH_SEQ_CTRL_M 0x1 1576 #define SCMD_CIPH_AUTH_SEQ_CTRL_V(x) \ 1577 ((x) << SCMD_CIPH_AUTH_SEQ_CTRL_S) 1578 #define SCMD_CIPH_AUTH_SEQ_CTRL_G(x) \ 1579 (((x) >> SCMD_CIPH_AUTH_SEQ_CTRL_S) & SCMD_CIPH_AUTH_SEQ_CTRL_M) 1580 #define SCMD_CIPH_AUTH_SEQ_CTRL_F SCMD_CIPH_AUTH_SEQ_CTRL_V(1U) 1581 1582 /* CiphMode - Cipher Mode. 0: NOP, 1:AES-CBC, 2:AES-GCM, 3:AES-CTR, 1583 * 4:Generic-AES, 5-15: Reserved. 1584 */ 1585 #define SCMD_CIPH_MODE_S 18 1586 #define SCMD_CIPH_MODE_M 0xf 1587 #define SCMD_CIPH_MODE_V(x) ((x) << SCMD_CIPH_MODE_S) 1588 #define SCMD_CIPH_MODE_G(x) \ 1589 (((x) >> SCMD_CIPH_MODE_S) & SCMD_CIPH_MODE_M) 1590 1591 /* AuthMode - Auth Mode. 0: NOP, 1:SHA1, 2:SHA2-224, 3:SHA2-256 1592 * 4-15: Reserved 1593 */ 1594 #define SCMD_AUTH_MODE_S 14 1595 #define SCMD_AUTH_MODE_M 0xf 1596 #define SCMD_AUTH_MODE_V(x) ((x) << SCMD_AUTH_MODE_S) 1597 #define SCMD_AUTH_MODE_G(x) \ 1598 (((x) >> SCMD_AUTH_MODE_S) & SCMD_AUTH_MODE_M) 1599 1600 /* HmacCtrl - HMAC Control. 0:NOP, 1:No truncation, 2:Support HMAC Truncation 1601 * per RFC 4366, 3:IPSec 96 bits, 4-7:Reserved 1602 */ 1603 #define SCMD_HMAC_CTRL_S 11 1604 #define SCMD_HMAC_CTRL_M 0x7 1605 #define SCMD_HMAC_CTRL_V(x) ((x) << SCMD_HMAC_CTRL_S) 1606 #define SCMD_HMAC_CTRL_G(x) \ 1607 (((x) >> SCMD_HMAC_CTRL_S) & SCMD_HMAC_CTRL_M) 1608 1609 /* IvSize - IV size in units of 2 bytes */ 1610 #define SCMD_IV_SIZE_S 7 1611 #define SCMD_IV_SIZE_M 0xf 1612 #define SCMD_IV_SIZE_V(x) ((x) << SCMD_IV_SIZE_S) 1613 #define SCMD_IV_SIZE_G(x) \ 1614 (((x) >> SCMD_IV_SIZE_S) & SCMD_IV_SIZE_M) 1615 1616 /* NumIVs - Number of IVs */ 1617 #define SCMD_NUM_IVS_S 0 1618 #define SCMD_NUM_IVS_M 0x7f 1619 #define SCMD_NUM_IVS_V(x) ((x) << SCMD_NUM_IVS_S) 1620 #define SCMD_NUM_IVS_G(x) \ 1621 (((x) >> SCMD_NUM_IVS_S) & SCMD_NUM_IVS_M) 1622 1623 /* EnbDbgId - If this is enabled upper 20 (63:44) bits if SeqNumber 1624 * (below) are used as Cid (connection id for debug status), these 1625 * bits are padded to zero for forming the 64 bit 1626 * sequence number for TLS 1627 */ 1628 #define SCMD_ENB_DBGID_S 31 1629 #define SCMD_ENB_DBGID_M 0x1 1630 #define SCMD_ENB_DBGID_V(x) ((x) << SCMD_ENB_DBGID_S) 1631 #define SCMD_ENB_DBGID_G(x) \ 1632 (((x) >> SCMD_ENB_DBGID_S) & SCMD_ENB_DBGID_M) 1633 1634 /* IV generation in SW. */ 1635 #define SCMD_IV_GEN_CTRL_S 30 1636 #define SCMD_IV_GEN_CTRL_M 0x1 1637 #define SCMD_IV_GEN_CTRL_V(x) ((x) << SCMD_IV_GEN_CTRL_S) 1638 #define SCMD_IV_GEN_CTRL_G(x) \ 1639 (((x) >> SCMD_IV_GEN_CTRL_S) & SCMD_IV_GEN_CTRL_M) 1640 #define SCMD_IV_GEN_CTRL_F SCMD_IV_GEN_CTRL_V(1U) 1641 1642 /* More frags */ 1643 #define SCMD_MORE_FRAGS_S 20 1644 #define SCMD_MORE_FRAGS_M 0x1 1645 #define SCMD_MORE_FRAGS_V(x) ((x) << SCMD_MORE_FRAGS_S) 1646 #define SCMD_MORE_FRAGS_G(x) (((x) >> SCMD_MORE_FRAGS_S) & SCMD_MORE_FRAGS_M) 1647 1648 /*last frag */ 1649 #define SCMD_LAST_FRAG_S 19 1650 #define SCMD_LAST_FRAG_M 0x1 1651 #define SCMD_LAST_FRAG_V(x) ((x) << SCMD_LAST_FRAG_S) 1652 #define SCMD_LAST_FRAG_G(x) (((x) >> SCMD_LAST_FRAG_S) & SCMD_LAST_FRAG_M) 1653 1654 /* TlsCompPdu */ 1655 #define SCMD_TLS_COMPPDU_S 18 1656 #define SCMD_TLS_COMPPDU_M 0x1 1657 #define SCMD_TLS_COMPPDU_V(x) ((x) << SCMD_TLS_COMPPDU_S) 1658 #define SCMD_TLS_COMPPDU_G(x) (((x) >> SCMD_TLS_COMPPDU_S) & SCMD_TLS_COMPPDU_M) 1659 1660 /* KeyCntxtInline - Key context inline after the scmd OR PayloadOnly*/ 1661 #define SCMD_KEY_CTX_INLINE_S 17 1662 #define SCMD_KEY_CTX_INLINE_M 0x1 1663 #define SCMD_KEY_CTX_INLINE_V(x) ((x) << SCMD_KEY_CTX_INLINE_S) 1664 #define SCMD_KEY_CTX_INLINE_G(x) \ 1665 (((x) >> SCMD_KEY_CTX_INLINE_S) & SCMD_KEY_CTX_INLINE_M) 1666 #define SCMD_KEY_CTX_INLINE_F SCMD_KEY_CTX_INLINE_V(1U) 1667 1668 /* TLSFragEnable - 0: Host created TLS PDUs, 1: TLS Framgmentation in ASIC */ 1669 #define SCMD_TLS_FRAG_ENABLE_S 16 1670 #define SCMD_TLS_FRAG_ENABLE_M 0x1 1671 #define SCMD_TLS_FRAG_ENABLE_V(x) ((x) << SCMD_TLS_FRAG_ENABLE_S) 1672 #define SCMD_TLS_FRAG_ENABLE_G(x) \ 1673 (((x) >> SCMD_TLS_FRAG_ENABLE_S) & SCMD_TLS_FRAG_ENABLE_M) 1674 #define SCMD_TLS_FRAG_ENABLE_F SCMD_TLS_FRAG_ENABLE_V(1U) 1675 1676 /* MacOnly - Only send the MAC and discard PDU. This is valid for hash only 1677 * modes, in this case TLS_TX will drop the PDU and only 1678 * send back the MAC bytes. 1679 */ 1680 #define SCMD_MAC_ONLY_S 15 1681 #define SCMD_MAC_ONLY_M 0x1 1682 #define SCMD_MAC_ONLY_V(x) ((x) << SCMD_MAC_ONLY_S) 1683 #define SCMD_MAC_ONLY_G(x) \ 1684 (((x) >> SCMD_MAC_ONLY_S) & SCMD_MAC_ONLY_M) 1685 #define SCMD_MAC_ONLY_F SCMD_MAC_ONLY_V(1U) 1686 1687 /* AadIVDrop - Drop the AAD and IV fields. Useful in protocols 1688 * which have complex AAD and IV formations Eg:AES-CCM 1689 */ 1690 #define SCMD_AADIVDROP_S 14 1691 #define SCMD_AADIVDROP_M 0x1 1692 #define SCMD_AADIVDROP_V(x) ((x) << SCMD_AADIVDROP_S) 1693 #define SCMD_AADIVDROP_G(x) \ 1694 (((x) >> SCMD_AADIVDROP_S) & SCMD_AADIVDROP_M) 1695 #define SCMD_AADIVDROP_F SCMD_AADIVDROP_V(1U) 1696 1697 /* HdrLength - Length of all headers excluding TLS header 1698 * present before start of crypto PDU/payload. 1699 */ 1700 #define SCMD_HDR_LEN_S 0 1701 #define SCMD_HDR_LEN_M 0x3fff 1702 #define SCMD_HDR_LEN_V(x) ((x) << SCMD_HDR_LEN_S) 1703 #define SCMD_HDR_LEN_G(x) \ 1704 (((x) >> SCMD_HDR_LEN_S) & SCMD_HDR_LEN_M) 1705 1706 struct cpl_tx_sec_pdu { 1707 __be32 op_ivinsrtofst; 1708 __be32 pldlen; 1709 __be32 aadstart_cipherstop_hi; 1710 __be32 cipherstop_lo_authinsert; 1711 __be32 seqno_numivs; 1712 __be32 ivgen_hdrlen; 1713 __be64 scmd1; 1714 }; 1715 1716 #define CPL_TX_SEC_PDU_OPCODE_S 24 1717 #define CPL_TX_SEC_PDU_OPCODE_M 0xff 1718 #define CPL_TX_SEC_PDU_OPCODE_V(x) ((x) << CPL_TX_SEC_PDU_OPCODE_S) 1719 #define CPL_TX_SEC_PDU_OPCODE_G(x) \ 1720 (((x) >> CPL_TX_SEC_PDU_OPCODE_S) & CPL_TX_SEC_PDU_OPCODE_M) 1721 1722 /* RX Channel Id */ 1723 #define CPL_TX_SEC_PDU_RXCHID_S 22 1724 #define CPL_TX_SEC_PDU_RXCHID_M 0x1 1725 #define CPL_TX_SEC_PDU_RXCHID_V(x) ((x) << CPL_TX_SEC_PDU_RXCHID_S) 1726 #define CPL_TX_SEC_PDU_RXCHID_G(x) \ 1727 (((x) >> CPL_TX_SEC_PDU_RXCHID_S) & CPL_TX_SEC_PDU_RXCHID_M) 1728 #define CPL_TX_SEC_PDU_RXCHID_F CPL_TX_SEC_PDU_RXCHID_V(1U) 1729 1730 /* Ack Follows */ 1731 #define CPL_TX_SEC_PDU_ACKFOLLOWS_S 21 1732 #define CPL_TX_SEC_PDU_ACKFOLLOWS_M 0x1 1733 #define CPL_TX_SEC_PDU_ACKFOLLOWS_V(x) ((x) << CPL_TX_SEC_PDU_ACKFOLLOWS_S) 1734 #define CPL_TX_SEC_PDU_ACKFOLLOWS_G(x) \ 1735 (((x) >> CPL_TX_SEC_PDU_ACKFOLLOWS_S) & CPL_TX_SEC_PDU_ACKFOLLOWS_M) 1736 #define CPL_TX_SEC_PDU_ACKFOLLOWS_F CPL_TX_SEC_PDU_ACKFOLLOWS_V(1U) 1737 1738 /* Loopback bit in cpl_tx_sec_pdu */ 1739 #define CPL_TX_SEC_PDU_ULPTXLPBK_S 20 1740 #define CPL_TX_SEC_PDU_ULPTXLPBK_M 0x1 1741 #define CPL_TX_SEC_PDU_ULPTXLPBK_V(x) ((x) << CPL_TX_SEC_PDU_ULPTXLPBK_S) 1742 #define CPL_TX_SEC_PDU_ULPTXLPBK_G(x) \ 1743 (((x) >> CPL_TX_SEC_PDU_ULPTXLPBK_S) & CPL_TX_SEC_PDU_ULPTXLPBK_M) 1744 #define CPL_TX_SEC_PDU_ULPTXLPBK_F CPL_TX_SEC_PDU_ULPTXLPBK_V(1U) 1745 1746 /* Length of cpl header encapsulated */ 1747 #define CPL_TX_SEC_PDU_CPLLEN_S 16 1748 #define CPL_TX_SEC_PDU_CPLLEN_M 0xf 1749 #define CPL_TX_SEC_PDU_CPLLEN_V(x) ((x) << CPL_TX_SEC_PDU_CPLLEN_S) 1750 #define CPL_TX_SEC_PDU_CPLLEN_G(x) \ 1751 (((x) >> CPL_TX_SEC_PDU_CPLLEN_S) & CPL_TX_SEC_PDU_CPLLEN_M) 1752 1753 /* PlaceHolder */ 1754 #define CPL_TX_SEC_PDU_PLACEHOLDER_S 10 1755 #define CPL_TX_SEC_PDU_PLACEHOLDER_M 0x1 1756 #define CPL_TX_SEC_PDU_PLACEHOLDER_V(x) ((x) << CPL_TX_SEC_PDU_PLACEHOLDER_S) 1757 #define CPL_TX_SEC_PDU_PLACEHOLDER_G(x) \ 1758 (((x) >> CPL_TX_SEC_PDU_PLACEHOLDER_S) & \ 1759 CPL_TX_SEC_PDU_PLACEHOLDER_M) 1760 1761 /* IvInsrtOffset: Insertion location for IV */ 1762 #define CPL_TX_SEC_PDU_IVINSRTOFST_S 0 1763 #define CPL_TX_SEC_PDU_IVINSRTOFST_M 0x3ff 1764 #define CPL_TX_SEC_PDU_IVINSRTOFST_V(x) ((x) << CPL_TX_SEC_PDU_IVINSRTOFST_S) 1765 #define CPL_TX_SEC_PDU_IVINSRTOFST_G(x) \ 1766 (((x) >> CPL_TX_SEC_PDU_IVINSRTOFST_S) & \ 1767 CPL_TX_SEC_PDU_IVINSRTOFST_M) 1768 1769 /* AadStartOffset: Offset in bytes for AAD start from 1770 * the first byte following the pkt headers (0-255 bytes) 1771 */ 1772 #define CPL_TX_SEC_PDU_AADSTART_S 24 1773 #define CPL_TX_SEC_PDU_AADSTART_M 0xff 1774 #define CPL_TX_SEC_PDU_AADSTART_V(x) ((x) << CPL_TX_SEC_PDU_AADSTART_S) 1775 #define CPL_TX_SEC_PDU_AADSTART_G(x) \ 1776 (((x) >> CPL_TX_SEC_PDU_AADSTART_S) & \ 1777 CPL_TX_SEC_PDU_AADSTART_M) 1778 1779 /* AadStopOffset: offset in bytes for AAD stop/end from the first byte following 1780 * the pkt headers (0-511 bytes) 1781 */ 1782 #define CPL_TX_SEC_PDU_AADSTOP_S 15 1783 #define CPL_TX_SEC_PDU_AADSTOP_M 0x1ff 1784 #define CPL_TX_SEC_PDU_AADSTOP_V(x) ((x) << CPL_TX_SEC_PDU_AADSTOP_S) 1785 #define CPL_TX_SEC_PDU_AADSTOP_G(x) \ 1786 (((x) >> CPL_TX_SEC_PDU_AADSTOP_S) & CPL_TX_SEC_PDU_AADSTOP_M) 1787 1788 /* CipherStartOffset: offset in bytes for encryption/decryption start from the 1789 * first byte following the pkt headers (0-1023 bytes) 1790 */ 1791 #define CPL_TX_SEC_PDU_CIPHERSTART_S 5 1792 #define CPL_TX_SEC_PDU_CIPHERSTART_M 0x3ff 1793 #define CPL_TX_SEC_PDU_CIPHERSTART_V(x) ((x) << CPL_TX_SEC_PDU_CIPHERSTART_S) 1794 #define CPL_TX_SEC_PDU_CIPHERSTART_G(x) \ 1795 (((x) >> CPL_TX_SEC_PDU_CIPHERSTART_S) & \ 1796 CPL_TX_SEC_PDU_CIPHERSTART_M) 1797 1798 /* CipherStopOffset: offset in bytes for encryption/decryption end 1799 * from end of the payload of this command (0-511 bytes) 1800 */ 1801 #define CPL_TX_SEC_PDU_CIPHERSTOP_HI_S 0 1802 #define CPL_TX_SEC_PDU_CIPHERSTOP_HI_M 0x1f 1803 #define CPL_TX_SEC_PDU_CIPHERSTOP_HI_V(x) \ 1804 ((x) << CPL_TX_SEC_PDU_CIPHERSTOP_HI_S) 1805 #define CPL_TX_SEC_PDU_CIPHERSTOP_HI_G(x) \ 1806 (((x) >> CPL_TX_SEC_PDU_CIPHERSTOP_HI_S) & \ 1807 CPL_TX_SEC_PDU_CIPHERSTOP_HI_M) 1808 1809 #define CPL_TX_SEC_PDU_CIPHERSTOP_LO_S 28 1810 #define CPL_TX_SEC_PDU_CIPHERSTOP_LO_M 0xf 1811 #define CPL_TX_SEC_PDU_CIPHERSTOP_LO_V(x) \ 1812 ((x) << CPL_TX_SEC_PDU_CIPHERSTOP_LO_S) 1813 #define CPL_TX_SEC_PDU_CIPHERSTOP_LO_G(x) \ 1814 (((x) >> CPL_TX_SEC_PDU_CIPHERSTOP_LO_S) & \ 1815 CPL_TX_SEC_PDU_CIPHERSTOP_LO_M) 1816 1817 /* AuthStartOffset: offset in bytes for authentication start from 1818 * the first byte following the pkt headers (0-1023) 1819 */ 1820 #define CPL_TX_SEC_PDU_AUTHSTART_S 18 1821 #define CPL_TX_SEC_PDU_AUTHSTART_M 0x3ff 1822 #define CPL_TX_SEC_PDU_AUTHSTART_V(x) ((x) << CPL_TX_SEC_PDU_AUTHSTART_S) 1823 #define CPL_TX_SEC_PDU_AUTHSTART_G(x) \ 1824 (((x) >> CPL_TX_SEC_PDU_AUTHSTART_S) & \ 1825 CPL_TX_SEC_PDU_AUTHSTART_M) 1826 1827 /* AuthStopOffset: offset in bytes for authentication 1828 * end from end of the payload of this command (0-511 Bytes) 1829 */ 1830 #define CPL_TX_SEC_PDU_AUTHSTOP_S 9 1831 #define CPL_TX_SEC_PDU_AUTHSTOP_M 0x1ff 1832 #define CPL_TX_SEC_PDU_AUTHSTOP_V(x) ((x) << CPL_TX_SEC_PDU_AUTHSTOP_S) 1833 #define CPL_TX_SEC_PDU_AUTHSTOP_G(x) \ 1834 (((x) >> CPL_TX_SEC_PDU_AUTHSTOP_S) & \ 1835 CPL_TX_SEC_PDU_AUTHSTOP_M) 1836 1837 /* AuthInsrtOffset: offset in bytes for authentication insertion 1838 * from end of the payload of this command (0-511 bytes) 1839 */ 1840 #define CPL_TX_SEC_PDU_AUTHINSERT_S 0 1841 #define CPL_TX_SEC_PDU_AUTHINSERT_M 0x1ff 1842 #define CPL_TX_SEC_PDU_AUTHINSERT_V(x) ((x) << CPL_TX_SEC_PDU_AUTHINSERT_S) 1843 #define CPL_TX_SEC_PDU_AUTHINSERT_G(x) \ 1844 (((x) >> CPL_TX_SEC_PDU_AUTHINSERT_S) & \ 1845 CPL_TX_SEC_PDU_AUTHINSERT_M) 1846 1847 struct cpl_rx_phys_dsgl { 1848 __be32 op_to_tid; 1849 __be32 pcirlxorder_to_noofsgentr; 1850 struct rss_header rss_hdr_int; 1851 }; 1852 1853 #define CPL_RX_PHYS_DSGL_OPCODE_S 24 1854 #define CPL_RX_PHYS_DSGL_OPCODE_M 0xff 1855 #define CPL_RX_PHYS_DSGL_OPCODE_V(x) ((x) << CPL_RX_PHYS_DSGL_OPCODE_S) 1856 #define CPL_RX_PHYS_DSGL_OPCODE_G(x) \ 1857 (((x) >> CPL_RX_PHYS_DSGL_OPCODE_S) & CPL_RX_PHYS_DSGL_OPCODE_M) 1858 1859 #define CPL_RX_PHYS_DSGL_ISRDMA_S 23 1860 #define CPL_RX_PHYS_DSGL_ISRDMA_M 0x1 1861 #define CPL_RX_PHYS_DSGL_ISRDMA_V(x) ((x) << CPL_RX_PHYS_DSGL_ISRDMA_S) 1862 #define CPL_RX_PHYS_DSGL_ISRDMA_G(x) \ 1863 (((x) >> CPL_RX_PHYS_DSGL_ISRDMA_S) & CPL_RX_PHYS_DSGL_ISRDMA_M) 1864 #define CPL_RX_PHYS_DSGL_ISRDMA_F CPL_RX_PHYS_DSGL_ISRDMA_V(1U) 1865 1866 #define CPL_RX_PHYS_DSGL_RSVD1_S 20 1867 #define CPL_RX_PHYS_DSGL_RSVD1_M 0x7 1868 #define CPL_RX_PHYS_DSGL_RSVD1_V(x) ((x) << CPL_RX_PHYS_DSGL_RSVD1_S) 1869 #define CPL_RX_PHYS_DSGL_RSVD1_G(x) \ 1870 (((x) >> CPL_RX_PHYS_DSGL_RSVD1_S) & \ 1871 CPL_RX_PHYS_DSGL_RSVD1_M) 1872 1873 #define CPL_RX_PHYS_DSGL_PCIRLXORDER_S 31 1874 #define CPL_RX_PHYS_DSGL_PCIRLXORDER_M 0x1 1875 #define CPL_RX_PHYS_DSGL_PCIRLXORDER_V(x) \ 1876 ((x) << CPL_RX_PHYS_DSGL_PCIRLXORDER_S) 1877 #define CPL_RX_PHYS_DSGL_PCIRLXORDER_G(x) \ 1878 (((x) >> CPL_RX_PHYS_DSGL_PCIRLXORDER_S) & \ 1879 CPL_RX_PHYS_DSGL_PCIRLXORDER_M) 1880 #define CPL_RX_PHYS_DSGL_PCIRLXORDER_F CPL_RX_PHYS_DSGL_PCIRLXORDER_V(1U) 1881 1882 #define CPL_RX_PHYS_DSGL_PCINOSNOOP_S 30 1883 #define CPL_RX_PHYS_DSGL_PCINOSNOOP_M 0x1 1884 #define CPL_RX_PHYS_DSGL_PCINOSNOOP_V(x) \ 1885 ((x) << CPL_RX_PHYS_DSGL_PCINOSNOOP_S) 1886 #define CPL_RX_PHYS_DSGL_PCINOSNOOP_G(x) \ 1887 (((x) >> CPL_RX_PHYS_DSGL_PCINOSNOOP_S) & \ 1888 CPL_RX_PHYS_DSGL_PCINOSNOOP_M) 1889 1890 #define CPL_RX_PHYS_DSGL_PCINOSNOOP_F CPL_RX_PHYS_DSGL_PCINOSNOOP_V(1U) 1891 1892 #define CPL_RX_PHYS_DSGL_PCITPHNTENB_S 29 1893 #define CPL_RX_PHYS_DSGL_PCITPHNTENB_M 0x1 1894 #define CPL_RX_PHYS_DSGL_PCITPHNTENB_V(x) \ 1895 ((x) << CPL_RX_PHYS_DSGL_PCITPHNTENB_S) 1896 #define CPL_RX_PHYS_DSGL_PCITPHNTENB_G(x) \ 1897 (((x) >> CPL_RX_PHYS_DSGL_PCITPHNTENB_S) & \ 1898 CPL_RX_PHYS_DSGL_PCITPHNTENB_M) 1899 #define CPL_RX_PHYS_DSGL_PCITPHNTENB_F CPL_RX_PHYS_DSGL_PCITPHNTENB_V(1U) 1900 1901 #define CPL_RX_PHYS_DSGL_PCITPHNT_S 27 1902 #define CPL_RX_PHYS_DSGL_PCITPHNT_M 0x3 1903 #define CPL_RX_PHYS_DSGL_PCITPHNT_V(x) ((x) << CPL_RX_PHYS_DSGL_PCITPHNT_S) 1904 #define CPL_RX_PHYS_DSGL_PCITPHNT_G(x) \ 1905 (((x) >> CPL_RX_PHYS_DSGL_PCITPHNT_S) & \ 1906 CPL_RX_PHYS_DSGL_PCITPHNT_M) 1907 1908 #define CPL_RX_PHYS_DSGL_DCAID_S 16 1909 #define CPL_RX_PHYS_DSGL_DCAID_M 0x7ff 1910 #define CPL_RX_PHYS_DSGL_DCAID_V(x) ((x) << CPL_RX_PHYS_DSGL_DCAID_S) 1911 #define CPL_RX_PHYS_DSGL_DCAID_G(x) \ 1912 (((x) >> CPL_RX_PHYS_DSGL_DCAID_S) & \ 1913 CPL_RX_PHYS_DSGL_DCAID_M) 1914 1915 #define CPL_RX_PHYS_DSGL_NOOFSGENTR_S 0 1916 #define CPL_RX_PHYS_DSGL_NOOFSGENTR_M 0xffff 1917 #define CPL_RX_PHYS_DSGL_NOOFSGENTR_V(x) \ 1918 ((x) << CPL_RX_PHYS_DSGL_NOOFSGENTR_S) 1919 #define CPL_RX_PHYS_DSGL_NOOFSGENTR_G(x) \ 1920 (((x) >> CPL_RX_PHYS_DSGL_NOOFSGENTR_S) & \ 1921 CPL_RX_PHYS_DSGL_NOOFSGENTR_M) 1922 1923 struct cpl_rx_mps_pkt { 1924 __be32 op_to_r1_hi; 1925 __be32 r1_lo_length; 1926 }; 1927 1928 #define CPL_RX_MPS_PKT_OP_S 24 1929 #define CPL_RX_MPS_PKT_OP_M 0xff 1930 #define CPL_RX_MPS_PKT_OP_V(x) ((x) << CPL_RX_MPS_PKT_OP_S) 1931 #define CPL_RX_MPS_PKT_OP_G(x) \ 1932 (((x) >> CPL_RX_MPS_PKT_OP_S) & CPL_RX_MPS_PKT_OP_M) 1933 1934 #define CPL_RX_MPS_PKT_TYPE_S 20 1935 #define CPL_RX_MPS_PKT_TYPE_M 0xf 1936 #define CPL_RX_MPS_PKT_TYPE_V(x) ((x) << CPL_RX_MPS_PKT_TYPE_S) 1937 #define CPL_RX_MPS_PKT_TYPE_G(x) \ 1938 (((x) >> CPL_RX_MPS_PKT_TYPE_S) & CPL_RX_MPS_PKT_TYPE_M) 1939 1940 enum { 1941 X_CPL_RX_MPS_PKT_TYPE_PAUSE = 1 << 0, 1942 X_CPL_RX_MPS_PKT_TYPE_PPP = 1 << 1, 1943 X_CPL_RX_MPS_PKT_TYPE_QFC = 1 << 2, 1944 X_CPL_RX_MPS_PKT_TYPE_PTP = 1 << 3 1945 }; 1946 #endif /* __T4_MSG_H */ 1947