1 /* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #ifndef __T4_MSG_H 36 #define __T4_MSG_H 37 38 #include <linux/types.h> 39 40 enum { 41 CPL_PASS_OPEN_REQ = 0x1, 42 CPL_PASS_ACCEPT_RPL = 0x2, 43 CPL_ACT_OPEN_REQ = 0x3, 44 CPL_SET_TCB_FIELD = 0x5, 45 CPL_GET_TCB = 0x6, 46 CPL_CLOSE_CON_REQ = 0x8, 47 CPL_CLOSE_LISTSRV_REQ = 0x9, 48 CPL_ABORT_REQ = 0xA, 49 CPL_ABORT_RPL = 0xB, 50 CPL_RX_DATA_ACK = 0xD, 51 CPL_TX_PKT = 0xE, 52 CPL_L2T_WRITE_REQ = 0x12, 53 CPL_TID_RELEASE = 0x1A, 54 CPL_TX_DATA_ISO = 0x1F, 55 56 CPL_CLOSE_LISTSRV_RPL = 0x20, 57 CPL_L2T_WRITE_RPL = 0x23, 58 CPL_PASS_OPEN_RPL = 0x24, 59 CPL_ACT_OPEN_RPL = 0x25, 60 CPL_PEER_CLOSE = 0x26, 61 CPL_ABORT_REQ_RSS = 0x2B, 62 CPL_ABORT_RPL_RSS = 0x2D, 63 64 CPL_CLOSE_CON_RPL = 0x32, 65 CPL_ISCSI_HDR = 0x33, 66 CPL_RDMA_CQE = 0x35, 67 CPL_RDMA_CQE_READ_RSP = 0x36, 68 CPL_RDMA_CQE_ERR = 0x37, 69 CPL_RX_DATA = 0x39, 70 CPL_SET_TCB_RPL = 0x3A, 71 CPL_RX_PKT = 0x3B, 72 CPL_RX_DDP_COMPLETE = 0x3F, 73 74 CPL_ACT_ESTABLISH = 0x40, 75 CPL_PASS_ESTABLISH = 0x41, 76 CPL_RX_DATA_DDP = 0x42, 77 CPL_PASS_ACCEPT_REQ = 0x44, 78 CPL_TRACE_PKT_T5 = 0x48, 79 CPL_RX_ISCSI_DDP = 0x49, 80 81 CPL_RDMA_READ_REQ = 0x60, 82 83 CPL_PASS_OPEN_REQ6 = 0x81, 84 CPL_ACT_OPEN_REQ6 = 0x83, 85 86 CPL_RDMA_TERMINATE = 0xA2, 87 CPL_RDMA_WRITE = 0xA4, 88 CPL_SGE_EGR_UPDATE = 0xA5, 89 90 CPL_TRACE_PKT = 0xB0, 91 CPL_ISCSI_DATA = 0xB2, 92 93 CPL_FW4_MSG = 0xC0, 94 CPL_FW4_PLD = 0xC1, 95 CPL_FW4_ACK = 0xC3, 96 97 CPL_FW6_MSG = 0xE0, 98 CPL_FW6_PLD = 0xE1, 99 CPL_TX_PKT_LSO = 0xED, 100 CPL_TX_PKT_XT = 0xEE, 101 102 NUM_CPL_CMDS 103 }; 104 105 enum CPL_error { 106 CPL_ERR_NONE = 0, 107 CPL_ERR_TCAM_FULL = 3, 108 CPL_ERR_BAD_LENGTH = 15, 109 CPL_ERR_BAD_ROUTE = 18, 110 CPL_ERR_CONN_RESET = 20, 111 CPL_ERR_CONN_EXIST_SYNRECV = 21, 112 CPL_ERR_CONN_EXIST = 22, 113 CPL_ERR_ARP_MISS = 23, 114 CPL_ERR_BAD_SYN = 24, 115 CPL_ERR_CONN_TIMEDOUT = 30, 116 CPL_ERR_XMIT_TIMEDOUT = 31, 117 CPL_ERR_PERSIST_TIMEDOUT = 32, 118 CPL_ERR_FINWAIT2_TIMEDOUT = 33, 119 CPL_ERR_KEEPALIVE_TIMEDOUT = 34, 120 CPL_ERR_RTX_NEG_ADVICE = 35, 121 CPL_ERR_PERSIST_NEG_ADVICE = 36, 122 CPL_ERR_KEEPALV_NEG_ADVICE = 37, 123 CPL_ERR_ABORT_FAILED = 42, 124 CPL_ERR_IWARP_FLM = 50, 125 }; 126 127 enum { 128 CPL_CONN_POLICY_AUTO = 0, 129 CPL_CONN_POLICY_ASK = 1, 130 CPL_CONN_POLICY_FILTER = 2, 131 CPL_CONN_POLICY_DENY = 3 132 }; 133 134 enum { 135 ULP_MODE_NONE = 0, 136 ULP_MODE_ISCSI = 2, 137 ULP_MODE_RDMA = 4, 138 ULP_MODE_TCPDDP = 5, 139 ULP_MODE_FCOE = 6, 140 }; 141 142 enum { 143 ULP_CRC_HEADER = 1 << 0, 144 ULP_CRC_DATA = 1 << 1 145 }; 146 147 enum { 148 CPL_ABORT_SEND_RST = 0, 149 CPL_ABORT_NO_RST, 150 }; 151 152 enum { /* TX_PKT_XT checksum types */ 153 TX_CSUM_TCP = 0, 154 TX_CSUM_UDP = 1, 155 TX_CSUM_CRC16 = 4, 156 TX_CSUM_CRC32 = 5, 157 TX_CSUM_CRC32C = 6, 158 TX_CSUM_FCOE = 7, 159 TX_CSUM_TCPIP = 8, 160 TX_CSUM_UDPIP = 9, 161 TX_CSUM_TCPIP6 = 10, 162 TX_CSUM_UDPIP6 = 11, 163 TX_CSUM_IP = 12, 164 }; 165 166 union opcode_tid { 167 __be32 opcode_tid; 168 u8 opcode; 169 }; 170 171 #define CPL_OPCODE_S 24 172 #define CPL_OPCODE_V(x) ((x) << CPL_OPCODE_S) 173 #define CPL_OPCODE_G(x) (((x) >> CPL_OPCODE_S) & 0xFF) 174 #define TID_G(x) ((x) & 0xFFFFFF) 175 176 /* tid is assumed to be 24-bits */ 177 #define MK_OPCODE_TID(opcode, tid) (CPL_OPCODE_V(opcode) | (tid)) 178 179 #define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid) 180 181 /* extract the TID from a CPL command */ 182 #define GET_TID(cmd) (TID_G(be32_to_cpu(OPCODE_TID(cmd)))) 183 184 /* partitioning of TID fields that also carry a queue id */ 185 #define TID_TID_S 0 186 #define TID_TID_M 0x3fff 187 #define TID_TID_G(x) (((x) >> TID_TID_S) & TID_TID_M) 188 189 #define TID_QID_S 14 190 #define TID_QID_M 0x3ff 191 #define TID_QID_V(x) ((x) << TID_QID_S) 192 #define TID_QID_G(x) (((x) >> TID_QID_S) & TID_QID_M) 193 194 struct rss_header { 195 u8 opcode; 196 #if defined(__LITTLE_ENDIAN_BITFIELD) 197 u8 channel:2; 198 u8 filter_hit:1; 199 u8 filter_tid:1; 200 u8 hash_type:2; 201 u8 ipv6:1; 202 u8 send2fw:1; 203 #else 204 u8 send2fw:1; 205 u8 ipv6:1; 206 u8 hash_type:2; 207 u8 filter_tid:1; 208 u8 filter_hit:1; 209 u8 channel:2; 210 #endif 211 __be16 qid; 212 __be32 hash_val; 213 }; 214 215 struct work_request_hdr { 216 __be32 wr_hi; 217 __be32 wr_mid; 218 __be64 wr_lo; 219 }; 220 221 /* wr_hi fields */ 222 #define WR_OP_S 24 223 #define WR_OP_V(x) ((__u64)(x) << WR_OP_S) 224 225 #define WR_HDR struct work_request_hdr wr 226 227 /* option 0 fields */ 228 #define TX_CHAN_S 2 229 #define TX_CHAN_V(x) ((x) << TX_CHAN_S) 230 231 #define ULP_MODE_S 8 232 #define ULP_MODE_V(x) ((x) << ULP_MODE_S) 233 234 #define RCV_BUFSIZ_S 12 235 #define RCV_BUFSIZ_M 0x3FFU 236 #define RCV_BUFSIZ_V(x) ((x) << RCV_BUFSIZ_S) 237 238 #define SMAC_SEL_S 28 239 #define SMAC_SEL_V(x) ((__u64)(x) << SMAC_SEL_S) 240 241 #define L2T_IDX_S 36 242 #define L2T_IDX_V(x) ((__u64)(x) << L2T_IDX_S) 243 244 #define WND_SCALE_S 50 245 #define WND_SCALE_V(x) ((__u64)(x) << WND_SCALE_S) 246 247 #define KEEP_ALIVE_S 54 248 #define KEEP_ALIVE_V(x) ((__u64)(x) << KEEP_ALIVE_S) 249 #define KEEP_ALIVE_F KEEP_ALIVE_V(1ULL) 250 251 #define MSS_IDX_S 60 252 #define MSS_IDX_M 0xF 253 #define MSS_IDX_V(x) ((__u64)(x) << MSS_IDX_S) 254 #define MSS_IDX_G(x) (((x) >> MSS_IDX_S) & MSS_IDX_M) 255 256 /* option 2 fields */ 257 #define RSS_QUEUE_S 0 258 #define RSS_QUEUE_M 0x3FF 259 #define RSS_QUEUE_V(x) ((x) << RSS_QUEUE_S) 260 #define RSS_QUEUE_G(x) (((x) >> RSS_QUEUE_S) & RSS_QUEUE_M) 261 262 #define RSS_QUEUE_VALID_S 10 263 #define RSS_QUEUE_VALID_V(x) ((x) << RSS_QUEUE_VALID_S) 264 #define RSS_QUEUE_VALID_F RSS_QUEUE_VALID_V(1U) 265 266 #define RX_FC_DISABLE_S 20 267 #define RX_FC_DISABLE_V(x) ((x) << RX_FC_DISABLE_S) 268 #define RX_FC_DISABLE_F RX_FC_DISABLE_V(1U) 269 270 #define RX_FC_VALID_S 22 271 #define RX_FC_VALID_V(x) ((x) << RX_FC_VALID_S) 272 #define RX_FC_VALID_F RX_FC_VALID_V(1U) 273 274 #define RX_CHANNEL_S 26 275 #define RX_CHANNEL_V(x) ((x) << RX_CHANNEL_S) 276 277 #define WND_SCALE_EN_S 28 278 #define WND_SCALE_EN_V(x) ((x) << WND_SCALE_EN_S) 279 #define WND_SCALE_EN_F WND_SCALE_EN_V(1U) 280 281 #define T5_OPT_2_VALID_S 31 282 #define T5_OPT_2_VALID_V(x) ((x) << T5_OPT_2_VALID_S) 283 #define T5_OPT_2_VALID_F T5_OPT_2_VALID_V(1U) 284 285 struct cpl_pass_open_req { 286 WR_HDR; 287 union opcode_tid ot; 288 __be16 local_port; 289 __be16 peer_port; 290 __be32 local_ip; 291 __be32 peer_ip; 292 __be64 opt0; 293 __be64 opt1; 294 }; 295 296 /* option 0 fields */ 297 #define NO_CONG_S 4 298 #define NO_CONG_V(x) ((x) << NO_CONG_S) 299 #define NO_CONG_F NO_CONG_V(1U) 300 301 #define DELACK_S 5 302 #define DELACK_V(x) ((x) << DELACK_S) 303 #define DELACK_F DELACK_V(1U) 304 305 #define DSCP_S 22 306 #define DSCP_M 0x3F 307 #define DSCP_V(x) ((x) << DSCP_S) 308 #define DSCP_G(x) (((x) >> DSCP_S) & DSCP_M) 309 310 #define TCAM_BYPASS_S 48 311 #define TCAM_BYPASS_V(x) ((__u64)(x) << TCAM_BYPASS_S) 312 #define TCAM_BYPASS_F TCAM_BYPASS_V(1ULL) 313 314 #define NAGLE_S 49 315 #define NAGLE_V(x) ((__u64)(x) << NAGLE_S) 316 #define NAGLE_F NAGLE_V(1ULL) 317 318 /* option 1 fields */ 319 #define SYN_RSS_ENABLE_S 0 320 #define SYN_RSS_ENABLE_V(x) ((x) << SYN_RSS_ENABLE_S) 321 #define SYN_RSS_ENABLE_F SYN_RSS_ENABLE_V(1U) 322 323 #define SYN_RSS_QUEUE_S 2 324 #define SYN_RSS_QUEUE_V(x) ((x) << SYN_RSS_QUEUE_S) 325 326 #define CONN_POLICY_S 22 327 #define CONN_POLICY_V(x) ((x) << CONN_POLICY_S) 328 329 struct cpl_pass_open_req6 { 330 WR_HDR; 331 union opcode_tid ot; 332 __be16 local_port; 333 __be16 peer_port; 334 __be64 local_ip_hi; 335 __be64 local_ip_lo; 336 __be64 peer_ip_hi; 337 __be64 peer_ip_lo; 338 __be64 opt0; 339 __be64 opt1; 340 }; 341 342 struct cpl_pass_open_rpl { 343 union opcode_tid ot; 344 u8 rsvd[3]; 345 u8 status; 346 }; 347 348 struct tcp_options { 349 __be16 mss; 350 __u8 wsf; 351 #if defined(__LITTLE_ENDIAN_BITFIELD) 352 __u8:4; 353 __u8 unknown:1; 354 __u8:1; 355 __u8 sack:1; 356 __u8 tstamp:1; 357 #else 358 __u8 tstamp:1; 359 __u8 sack:1; 360 __u8:1; 361 __u8 unknown:1; 362 __u8:4; 363 #endif 364 }; 365 366 struct cpl_pass_accept_req { 367 union opcode_tid ot; 368 __be16 rsvd; 369 __be16 len; 370 __be32 hdr_len; 371 __be16 vlan; 372 __be16 l2info; 373 __be32 tos_stid; 374 struct tcp_options tcpopt; 375 }; 376 377 /* cpl_pass_accept_req.hdr_len fields */ 378 #define SYN_RX_CHAN_S 0 379 #define SYN_RX_CHAN_M 0xF 380 #define SYN_RX_CHAN_V(x) ((x) << SYN_RX_CHAN_S) 381 #define SYN_RX_CHAN_G(x) (((x) >> SYN_RX_CHAN_S) & SYN_RX_CHAN_M) 382 383 #define TCP_HDR_LEN_S 10 384 #define TCP_HDR_LEN_M 0x3F 385 #define TCP_HDR_LEN_V(x) ((x) << TCP_HDR_LEN_S) 386 #define TCP_HDR_LEN_G(x) (((x) >> TCP_HDR_LEN_S) & TCP_HDR_LEN_M) 387 388 #define IP_HDR_LEN_S 16 389 #define IP_HDR_LEN_M 0x3FF 390 #define IP_HDR_LEN_V(x) ((x) << IP_HDR_LEN_S) 391 #define IP_HDR_LEN_G(x) (((x) >> IP_HDR_LEN_S) & IP_HDR_LEN_M) 392 393 #define ETH_HDR_LEN_S 26 394 #define ETH_HDR_LEN_M 0x1F 395 #define ETH_HDR_LEN_V(x) ((x) << ETH_HDR_LEN_S) 396 #define ETH_HDR_LEN_G(x) (((x) >> ETH_HDR_LEN_S) & ETH_HDR_LEN_M) 397 398 /* cpl_pass_accept_req.l2info fields */ 399 #define SYN_MAC_IDX_S 0 400 #define SYN_MAC_IDX_M 0x1FF 401 #define SYN_MAC_IDX_V(x) ((x) << SYN_MAC_IDX_S) 402 #define SYN_MAC_IDX_G(x) (((x) >> SYN_MAC_IDX_S) & SYN_MAC_IDX_M) 403 404 #define SYN_XACT_MATCH_S 9 405 #define SYN_XACT_MATCH_V(x) ((x) << SYN_XACT_MATCH_S) 406 #define SYN_XACT_MATCH_F SYN_XACT_MATCH_V(1U) 407 408 #define SYN_INTF_S 12 409 #define SYN_INTF_M 0xF 410 #define SYN_INTF_V(x) ((x) << SYN_INTF_S) 411 #define SYN_INTF_G(x) (((x) >> SYN_INTF_S) & SYN_INTF_M) 412 413 enum { /* TCP congestion control algorithms */ 414 CONG_ALG_RENO, 415 CONG_ALG_TAHOE, 416 CONG_ALG_NEWRENO, 417 CONG_ALG_HIGHSPEED 418 }; 419 420 #define CONG_CNTRL_S 14 421 #define CONG_CNTRL_M 0x3 422 #define CONG_CNTRL_V(x) ((x) << CONG_CNTRL_S) 423 #define CONG_CNTRL_G(x) (((x) >> CONG_CNTRL_S) & CONG_CNTRL_M) 424 425 #define T5_ISS_S 18 426 #define T5_ISS_V(x) ((x) << T5_ISS_S) 427 #define T5_ISS_F T5_ISS_V(1U) 428 429 struct cpl_pass_accept_rpl { 430 WR_HDR; 431 union opcode_tid ot; 432 __be32 opt2; 433 __be64 opt0; 434 }; 435 436 /* option 2 fields */ 437 #define RX_COALESCE_VALID_S 11 438 #define RX_COALESCE_VALID_V(x) ((x) << RX_COALESCE_VALID_S) 439 #define RX_COALESCE_VALID_F RX_COALESCE_VALID_V(1U) 440 441 #define RX_COALESCE_S 12 442 #define RX_COALESCE_V(x) ((x) << RX_COALESCE_S) 443 444 #define PACE_S 16 445 #define PACE_V(x) ((x) << PACE_S) 446 447 #define TX_QUEUE_S 23 448 #define TX_QUEUE_M 0x7 449 #define TX_QUEUE_V(x) ((x) << TX_QUEUE_S) 450 #define TX_QUEUE_G(x) (((x) >> TX_QUEUE_S) & TX_QUEUE_M) 451 452 #define CCTRL_ECN_S 27 453 #define CCTRL_ECN_V(x) ((x) << CCTRL_ECN_S) 454 #define CCTRL_ECN_F CCTRL_ECN_V(1U) 455 456 #define TSTAMPS_EN_S 29 457 #define TSTAMPS_EN_V(x) ((x) << TSTAMPS_EN_S) 458 #define TSTAMPS_EN_F TSTAMPS_EN_V(1U) 459 460 #define SACK_EN_S 30 461 #define SACK_EN_V(x) ((x) << SACK_EN_S) 462 #define SACK_EN_F SACK_EN_V(1U) 463 464 struct cpl_t5_pass_accept_rpl { 465 WR_HDR; 466 union opcode_tid ot; 467 __be32 opt2; 468 __be64 opt0; 469 __be32 iss; 470 __be32 rsvd; 471 }; 472 473 struct cpl_act_open_req { 474 WR_HDR; 475 union opcode_tid ot; 476 __be16 local_port; 477 __be16 peer_port; 478 __be32 local_ip; 479 __be32 peer_ip; 480 __be64 opt0; 481 __be32 params; 482 __be32 opt2; 483 }; 484 485 #define FILTER_TUPLE_S 24 486 #define FILTER_TUPLE_M 0xFFFFFFFFFF 487 #define FILTER_TUPLE_V(x) ((x) << FILTER_TUPLE_S) 488 #define FILTER_TUPLE_G(x) (((x) >> FILTER_TUPLE_S) & FILTER_TUPLE_M) 489 struct cpl_t5_act_open_req { 490 WR_HDR; 491 union opcode_tid ot; 492 __be16 local_port; 493 __be16 peer_port; 494 __be32 local_ip; 495 __be32 peer_ip; 496 __be64 opt0; 497 __be32 rsvd; 498 __be32 opt2; 499 __be64 params; 500 }; 501 502 struct cpl_t6_act_open_req { 503 WR_HDR; 504 union opcode_tid ot; 505 __be16 local_port; 506 __be16 peer_port; 507 __be32 local_ip; 508 __be32 peer_ip; 509 __be64 opt0; 510 __be32 rsvd; 511 __be32 opt2; 512 __be64 params; 513 __be32 rsvd2; 514 __be32 opt3; 515 }; 516 517 struct cpl_act_open_req6 { 518 WR_HDR; 519 union opcode_tid ot; 520 __be16 local_port; 521 __be16 peer_port; 522 __be64 local_ip_hi; 523 __be64 local_ip_lo; 524 __be64 peer_ip_hi; 525 __be64 peer_ip_lo; 526 __be64 opt0; 527 __be32 params; 528 __be32 opt2; 529 }; 530 531 struct cpl_t5_act_open_req6 { 532 WR_HDR; 533 union opcode_tid ot; 534 __be16 local_port; 535 __be16 peer_port; 536 __be64 local_ip_hi; 537 __be64 local_ip_lo; 538 __be64 peer_ip_hi; 539 __be64 peer_ip_lo; 540 __be64 opt0; 541 __be32 rsvd; 542 __be32 opt2; 543 __be64 params; 544 }; 545 546 struct cpl_t6_act_open_req6 { 547 WR_HDR; 548 union opcode_tid ot; 549 __be16 local_port; 550 __be16 peer_port; 551 __be64 local_ip_hi; 552 __be64 local_ip_lo; 553 __be64 peer_ip_hi; 554 __be64 peer_ip_lo; 555 __be64 opt0; 556 __be32 rsvd; 557 __be32 opt2; 558 __be64 params; 559 __be32 rsvd2; 560 __be32 opt3; 561 }; 562 563 struct cpl_act_open_rpl { 564 union opcode_tid ot; 565 __be32 atid_status; 566 }; 567 568 /* cpl_act_open_rpl.atid_status fields */ 569 #define AOPEN_STATUS_S 0 570 #define AOPEN_STATUS_M 0xFF 571 #define AOPEN_STATUS_G(x) (((x) >> AOPEN_STATUS_S) & AOPEN_STATUS_M) 572 573 #define AOPEN_ATID_S 8 574 #define AOPEN_ATID_M 0xFFFFFF 575 #define AOPEN_ATID_G(x) (((x) >> AOPEN_ATID_S) & AOPEN_ATID_M) 576 577 struct cpl_pass_establish { 578 union opcode_tid ot; 579 __be32 rsvd; 580 __be32 tos_stid; 581 __be16 mac_idx; 582 __be16 tcp_opt; 583 __be32 snd_isn; 584 __be32 rcv_isn; 585 }; 586 587 /* cpl_pass_establish.tos_stid fields */ 588 #define PASS_OPEN_TID_S 0 589 #define PASS_OPEN_TID_M 0xFFFFFF 590 #define PASS_OPEN_TID_V(x) ((x) << PASS_OPEN_TID_S) 591 #define PASS_OPEN_TID_G(x) (((x) >> PASS_OPEN_TID_S) & PASS_OPEN_TID_M) 592 593 #define PASS_OPEN_TOS_S 24 594 #define PASS_OPEN_TOS_M 0xFF 595 #define PASS_OPEN_TOS_V(x) ((x) << PASS_OPEN_TOS_S) 596 #define PASS_OPEN_TOS_G(x) (((x) >> PASS_OPEN_TOS_S) & PASS_OPEN_TOS_M) 597 598 /* cpl_pass_establish.tcp_opt fields (also applies to act_open_establish) */ 599 #define TCPOPT_WSCALE_OK_S 5 600 #define TCPOPT_WSCALE_OK_M 0x1 601 #define TCPOPT_WSCALE_OK_G(x) \ 602 (((x) >> TCPOPT_WSCALE_OK_S) & TCPOPT_WSCALE_OK_M) 603 604 #define TCPOPT_SACK_S 6 605 #define TCPOPT_SACK_M 0x1 606 #define TCPOPT_SACK_G(x) (((x) >> TCPOPT_SACK_S) & TCPOPT_SACK_M) 607 608 #define TCPOPT_TSTAMP_S 7 609 #define TCPOPT_TSTAMP_M 0x1 610 #define TCPOPT_TSTAMP_G(x) (((x) >> TCPOPT_TSTAMP_S) & TCPOPT_TSTAMP_M) 611 612 #define TCPOPT_SND_WSCALE_S 8 613 #define TCPOPT_SND_WSCALE_M 0xF 614 #define TCPOPT_SND_WSCALE_G(x) \ 615 (((x) >> TCPOPT_SND_WSCALE_S) & TCPOPT_SND_WSCALE_M) 616 617 #define TCPOPT_MSS_S 12 618 #define TCPOPT_MSS_M 0xF 619 #define TCPOPT_MSS_G(x) (((x) >> TCPOPT_MSS_S) & TCPOPT_MSS_M) 620 621 #define T6_TCP_HDR_LEN_S 8 622 #define T6_TCP_HDR_LEN_V(x) ((x) << T6_TCP_HDR_LEN_S) 623 #define T6_TCP_HDR_LEN_G(x) (((x) >> T6_TCP_HDR_LEN_S) & TCP_HDR_LEN_M) 624 625 #define T6_IP_HDR_LEN_S 14 626 #define T6_IP_HDR_LEN_V(x) ((x) << T6_IP_HDR_LEN_S) 627 #define T6_IP_HDR_LEN_G(x) (((x) >> T6_IP_HDR_LEN_S) & IP_HDR_LEN_M) 628 629 #define T6_ETH_HDR_LEN_S 24 630 #define T6_ETH_HDR_LEN_M 0xFF 631 #define T6_ETH_HDR_LEN_V(x) ((x) << T6_ETH_HDR_LEN_S) 632 #define T6_ETH_HDR_LEN_G(x) (((x) >> T6_ETH_HDR_LEN_S) & T6_ETH_HDR_LEN_M) 633 634 struct cpl_act_establish { 635 union opcode_tid ot; 636 __be32 rsvd; 637 __be32 tos_atid; 638 __be16 mac_idx; 639 __be16 tcp_opt; 640 __be32 snd_isn; 641 __be32 rcv_isn; 642 }; 643 644 struct cpl_get_tcb { 645 WR_HDR; 646 union opcode_tid ot; 647 __be16 reply_ctrl; 648 __be16 cookie; 649 }; 650 651 /* cpl_get_tcb.reply_ctrl fields */ 652 #define QUEUENO_S 0 653 #define QUEUENO_V(x) ((x) << QUEUENO_S) 654 655 #define REPLY_CHAN_S 14 656 #define REPLY_CHAN_V(x) ((x) << REPLY_CHAN_S) 657 #define REPLY_CHAN_F REPLY_CHAN_V(1U) 658 659 #define NO_REPLY_S 15 660 #define NO_REPLY_V(x) ((x) << NO_REPLY_S) 661 #define NO_REPLY_F NO_REPLY_V(1U) 662 663 struct cpl_set_tcb_field { 664 WR_HDR; 665 union opcode_tid ot; 666 __be16 reply_ctrl; 667 __be16 word_cookie; 668 __be64 mask; 669 __be64 val; 670 }; 671 672 /* cpl_set_tcb_field.word_cookie fields */ 673 #define TCB_WORD_S 0 674 #define TCB_WORD(x) ((x) << TCB_WORD_S) 675 676 #define TCB_COOKIE_S 5 677 #define TCB_COOKIE_M 0x7 678 #define TCB_COOKIE_V(x) ((x) << TCB_COOKIE_S) 679 #define TCB_COOKIE_G(x) (((x) >> TCB_COOKIE_S) & TCB_COOKIE_M) 680 681 struct cpl_set_tcb_rpl { 682 union opcode_tid ot; 683 __be16 rsvd; 684 u8 cookie; 685 u8 status; 686 __be64 oldval; 687 }; 688 689 struct cpl_close_con_req { 690 WR_HDR; 691 union opcode_tid ot; 692 __be32 rsvd; 693 }; 694 695 struct cpl_close_con_rpl { 696 union opcode_tid ot; 697 u8 rsvd[3]; 698 u8 status; 699 __be32 snd_nxt; 700 __be32 rcv_nxt; 701 }; 702 703 struct cpl_close_listsvr_req { 704 WR_HDR; 705 union opcode_tid ot; 706 __be16 reply_ctrl; 707 __be16 rsvd; 708 }; 709 710 /* additional cpl_close_listsvr_req.reply_ctrl field */ 711 #define LISTSVR_IPV6_S 14 712 #define LISTSVR_IPV6_V(x) ((x) << LISTSVR_IPV6_S) 713 #define LISTSVR_IPV6_F LISTSVR_IPV6_V(1U) 714 715 struct cpl_close_listsvr_rpl { 716 union opcode_tid ot; 717 u8 rsvd[3]; 718 u8 status; 719 }; 720 721 struct cpl_abort_req_rss { 722 union opcode_tid ot; 723 u8 rsvd[3]; 724 u8 status; 725 }; 726 727 struct cpl_abort_req { 728 WR_HDR; 729 union opcode_tid ot; 730 __be32 rsvd0; 731 u8 rsvd1; 732 u8 cmd; 733 u8 rsvd2[6]; 734 }; 735 736 struct cpl_abort_rpl_rss { 737 union opcode_tid ot; 738 u8 rsvd[3]; 739 u8 status; 740 }; 741 742 struct cpl_abort_rpl { 743 WR_HDR; 744 union opcode_tid ot; 745 __be32 rsvd0; 746 u8 rsvd1; 747 u8 cmd; 748 u8 rsvd2[6]; 749 }; 750 751 struct cpl_peer_close { 752 union opcode_tid ot; 753 __be32 rcv_nxt; 754 }; 755 756 struct cpl_tid_release { 757 WR_HDR; 758 union opcode_tid ot; 759 __be32 rsvd; 760 }; 761 762 struct cpl_tx_pkt_core { 763 __be32 ctrl0; 764 __be16 pack; 765 __be16 len; 766 __be64 ctrl1; 767 }; 768 769 struct cpl_tx_pkt { 770 WR_HDR; 771 struct cpl_tx_pkt_core c; 772 }; 773 774 #define cpl_tx_pkt_xt cpl_tx_pkt 775 776 /* cpl_tx_pkt_core.ctrl0 fields */ 777 #define TXPKT_VF_S 0 778 #define TXPKT_VF_V(x) ((x) << TXPKT_VF_S) 779 780 #define TXPKT_PF_S 8 781 #define TXPKT_PF_V(x) ((x) << TXPKT_PF_S) 782 783 #define TXPKT_VF_VLD_S 11 784 #define TXPKT_VF_VLD_V(x) ((x) << TXPKT_VF_VLD_S) 785 #define TXPKT_VF_VLD_F TXPKT_VF_VLD_V(1U) 786 787 #define TXPKT_OVLAN_IDX_S 12 788 #define TXPKT_OVLAN_IDX_V(x) ((x) << TXPKT_OVLAN_IDX_S) 789 790 #define TXPKT_T5_OVLAN_IDX_S 12 791 #define TXPKT_T5_OVLAN_IDX_V(x) ((x) << TXPKT_T5_OVLAN_IDX_S) 792 793 #define TXPKT_INTF_S 16 794 #define TXPKT_INTF_V(x) ((x) << TXPKT_INTF_S) 795 796 #define TXPKT_INS_OVLAN_S 21 797 #define TXPKT_INS_OVLAN_V(x) ((x) << TXPKT_INS_OVLAN_S) 798 #define TXPKT_INS_OVLAN_F TXPKT_INS_OVLAN_V(1U) 799 800 #define TXPKT_OPCODE_S 24 801 #define TXPKT_OPCODE_V(x) ((x) << TXPKT_OPCODE_S) 802 803 /* cpl_tx_pkt_core.ctrl1 fields */ 804 #define TXPKT_CSUM_END_S 12 805 #define TXPKT_CSUM_END_V(x) ((x) << TXPKT_CSUM_END_S) 806 807 #define TXPKT_CSUM_START_S 20 808 #define TXPKT_CSUM_START_V(x) ((x) << TXPKT_CSUM_START_S) 809 810 #define TXPKT_IPHDR_LEN_S 20 811 #define TXPKT_IPHDR_LEN_V(x) ((__u64)(x) << TXPKT_IPHDR_LEN_S) 812 813 #define TXPKT_CSUM_LOC_S 30 814 #define TXPKT_CSUM_LOC_V(x) ((__u64)(x) << TXPKT_CSUM_LOC_S) 815 816 #define TXPKT_ETHHDR_LEN_S 34 817 #define TXPKT_ETHHDR_LEN_V(x) ((__u64)(x) << TXPKT_ETHHDR_LEN_S) 818 819 #define T6_TXPKT_ETHHDR_LEN_S 32 820 #define T6_TXPKT_ETHHDR_LEN_V(x) ((__u64)(x) << T6_TXPKT_ETHHDR_LEN_S) 821 822 #define TXPKT_CSUM_TYPE_S 40 823 #define TXPKT_CSUM_TYPE_V(x) ((__u64)(x) << TXPKT_CSUM_TYPE_S) 824 825 #define TXPKT_VLAN_S 44 826 #define TXPKT_VLAN_V(x) ((__u64)(x) << TXPKT_VLAN_S) 827 828 #define TXPKT_VLAN_VLD_S 60 829 #define TXPKT_VLAN_VLD_V(x) ((__u64)(x) << TXPKT_VLAN_VLD_S) 830 #define TXPKT_VLAN_VLD_F TXPKT_VLAN_VLD_V(1ULL) 831 832 #define TXPKT_IPCSUM_DIS_S 62 833 #define TXPKT_IPCSUM_DIS_V(x) ((__u64)(x) << TXPKT_IPCSUM_DIS_S) 834 #define TXPKT_IPCSUM_DIS_F TXPKT_IPCSUM_DIS_V(1ULL) 835 836 #define TXPKT_L4CSUM_DIS_S 63 837 #define TXPKT_L4CSUM_DIS_V(x) ((__u64)(x) << TXPKT_L4CSUM_DIS_S) 838 #define TXPKT_L4CSUM_DIS_F TXPKT_L4CSUM_DIS_V(1ULL) 839 840 struct cpl_tx_pkt_lso_core { 841 __be32 lso_ctrl; 842 __be16 ipid_ofst; 843 __be16 mss; 844 __be32 seqno_offset; 845 __be32 len; 846 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 847 }; 848 849 /* cpl_tx_pkt_lso_core.lso_ctrl fields */ 850 #define LSO_TCPHDR_LEN_S 0 851 #define LSO_TCPHDR_LEN_V(x) ((x) << LSO_TCPHDR_LEN_S) 852 853 #define LSO_IPHDR_LEN_S 4 854 #define LSO_IPHDR_LEN_V(x) ((x) << LSO_IPHDR_LEN_S) 855 856 #define LSO_ETHHDR_LEN_S 16 857 #define LSO_ETHHDR_LEN_V(x) ((x) << LSO_ETHHDR_LEN_S) 858 859 #define LSO_IPV6_S 20 860 #define LSO_IPV6_V(x) ((x) << LSO_IPV6_S) 861 #define LSO_IPV6_F LSO_IPV6_V(1U) 862 863 #define LSO_LAST_SLICE_S 22 864 #define LSO_LAST_SLICE_V(x) ((x) << LSO_LAST_SLICE_S) 865 #define LSO_LAST_SLICE_F LSO_LAST_SLICE_V(1U) 866 867 #define LSO_FIRST_SLICE_S 23 868 #define LSO_FIRST_SLICE_V(x) ((x) << LSO_FIRST_SLICE_S) 869 #define LSO_FIRST_SLICE_F LSO_FIRST_SLICE_V(1U) 870 871 #define LSO_OPCODE_S 24 872 #define LSO_OPCODE_V(x) ((x) << LSO_OPCODE_S) 873 874 #define LSO_T5_XFER_SIZE_S 0 875 #define LSO_T5_XFER_SIZE_V(x) ((x) << LSO_T5_XFER_SIZE_S) 876 877 struct cpl_tx_pkt_lso { 878 WR_HDR; 879 struct cpl_tx_pkt_lso_core c; 880 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 881 }; 882 883 struct cpl_iscsi_hdr { 884 union opcode_tid ot; 885 __be16 pdu_len_ddp; 886 __be16 len; 887 __be32 seq; 888 __be16 urg; 889 u8 rsvd; 890 u8 status; 891 }; 892 893 /* cpl_iscsi_hdr.pdu_len_ddp fields */ 894 #define ISCSI_PDU_LEN_S 0 895 #define ISCSI_PDU_LEN_M 0x7FFF 896 #define ISCSI_PDU_LEN_V(x) ((x) << ISCSI_PDU_LEN_S) 897 #define ISCSI_PDU_LEN_G(x) (((x) >> ISCSI_PDU_LEN_S) & ISCSI_PDU_LEN_M) 898 899 #define ISCSI_DDP_S 15 900 #define ISCSI_DDP_V(x) ((x) << ISCSI_DDP_S) 901 #define ISCSI_DDP_F ISCSI_DDP_V(1U) 902 903 struct cpl_rx_data_ddp { 904 union opcode_tid ot; 905 __be16 urg; 906 __be16 len; 907 __be32 seq; 908 union { 909 __be32 nxt_seq; 910 __be32 ddp_report; 911 }; 912 __be32 ulp_crc; 913 __be32 ddpvld; 914 }; 915 916 #define cpl_rx_iscsi_ddp cpl_rx_data_ddp 917 918 struct cpl_iscsi_data { 919 union opcode_tid ot; 920 __u8 rsvd0[2]; 921 __be16 len; 922 __be32 seq; 923 __be16 urg; 924 __u8 rsvd1; 925 __u8 status; 926 }; 927 928 struct cpl_tx_data_iso { 929 __be32 op_to_scsi; 930 __u8 reserved1; 931 __u8 ahs_len; 932 __be16 mpdu; 933 __be32 burst_size; 934 __be32 len; 935 __be32 reserved2_seglen_offset; 936 __be32 datasn_offset; 937 __be32 buffer_offset; 938 __be32 reserved3; 939 940 /* encapsulated CPL_TX_DATA follows here */ 941 }; 942 943 /* cpl_tx_data_iso.op_to_scsi fields */ 944 #define CPL_TX_DATA_ISO_OP_S 24 945 #define CPL_TX_DATA_ISO_OP_M 0xff 946 #define CPL_TX_DATA_ISO_OP_V(x) ((x) << CPL_TX_DATA_ISO_OP_S) 947 #define CPL_TX_DATA_ISO_OP_G(x) \ 948 (((x) >> CPL_TX_DATA_ISO_OP_S) & CPL_TX_DATA_ISO_OP_M) 949 950 #define CPL_TX_DATA_ISO_FIRST_S 23 951 #define CPL_TX_DATA_ISO_FIRST_M 0x1 952 #define CPL_TX_DATA_ISO_FIRST_V(x) ((x) << CPL_TX_DATA_ISO_FIRST_S) 953 #define CPL_TX_DATA_ISO_FIRST_G(x) \ 954 (((x) >> CPL_TX_DATA_ISO_FIRST_S) & CPL_TX_DATA_ISO_FIRST_M) 955 #define CPL_TX_DATA_ISO_FIRST_F CPL_TX_DATA_ISO_FIRST_V(1U) 956 957 #define CPL_TX_DATA_ISO_LAST_S 22 958 #define CPL_TX_DATA_ISO_LAST_M 0x1 959 #define CPL_TX_DATA_ISO_LAST_V(x) ((x) << CPL_TX_DATA_ISO_LAST_S) 960 #define CPL_TX_DATA_ISO_LAST_G(x) \ 961 (((x) >> CPL_TX_DATA_ISO_LAST_S) & CPL_TX_DATA_ISO_LAST_M) 962 #define CPL_TX_DATA_ISO_LAST_F CPL_TX_DATA_ISO_LAST_V(1U) 963 964 #define CPL_TX_DATA_ISO_CPLHDRLEN_S 21 965 #define CPL_TX_DATA_ISO_CPLHDRLEN_M 0x1 966 #define CPL_TX_DATA_ISO_CPLHDRLEN_V(x) ((x) << CPL_TX_DATA_ISO_CPLHDRLEN_S) 967 #define CPL_TX_DATA_ISO_CPLHDRLEN_G(x) \ 968 (((x) >> CPL_TX_DATA_ISO_CPLHDRLEN_S) & CPL_TX_DATA_ISO_CPLHDRLEN_M) 969 #define CPL_TX_DATA_ISO_CPLHDRLEN_F CPL_TX_DATA_ISO_CPLHDRLEN_V(1U) 970 971 #define CPL_TX_DATA_ISO_HDRCRC_S 20 972 #define CPL_TX_DATA_ISO_HDRCRC_M 0x1 973 #define CPL_TX_DATA_ISO_HDRCRC_V(x) ((x) << CPL_TX_DATA_ISO_HDRCRC_S) 974 #define CPL_TX_DATA_ISO_HDRCRC_G(x) \ 975 (((x) >> CPL_TX_DATA_ISO_HDRCRC_S) & CPL_TX_DATA_ISO_HDRCRC_M) 976 #define CPL_TX_DATA_ISO_HDRCRC_F CPL_TX_DATA_ISO_HDRCRC_V(1U) 977 978 #define CPL_TX_DATA_ISO_PLDCRC_S 19 979 #define CPL_TX_DATA_ISO_PLDCRC_M 0x1 980 #define CPL_TX_DATA_ISO_PLDCRC_V(x) ((x) << CPL_TX_DATA_ISO_PLDCRC_S) 981 #define CPL_TX_DATA_ISO_PLDCRC_G(x) \ 982 (((x) >> CPL_TX_DATA_ISO_PLDCRC_S) & CPL_TX_DATA_ISO_PLDCRC_M) 983 #define CPL_TX_DATA_ISO_PLDCRC_F CPL_TX_DATA_ISO_PLDCRC_V(1U) 984 985 #define CPL_TX_DATA_ISO_IMMEDIATE_S 18 986 #define CPL_TX_DATA_ISO_IMMEDIATE_M 0x1 987 #define CPL_TX_DATA_ISO_IMMEDIATE_V(x) ((x) << CPL_TX_DATA_ISO_IMMEDIATE_S) 988 #define CPL_TX_DATA_ISO_IMMEDIATE_G(x) \ 989 (((x) >> CPL_TX_DATA_ISO_IMMEDIATE_S) & CPL_TX_DATA_ISO_IMMEDIATE_M) 990 #define CPL_TX_DATA_ISO_IMMEDIATE_F CPL_TX_DATA_ISO_IMMEDIATE_V(1U) 991 992 #define CPL_TX_DATA_ISO_SCSI_S 16 993 #define CPL_TX_DATA_ISO_SCSI_M 0x3 994 #define CPL_TX_DATA_ISO_SCSI_V(x) ((x) << CPL_TX_DATA_ISO_SCSI_S) 995 #define CPL_TX_DATA_ISO_SCSI_G(x) \ 996 (((x) >> CPL_TX_DATA_ISO_SCSI_S) & CPL_TX_DATA_ISO_SCSI_M) 997 998 /* cpl_tx_data_iso.reserved2_seglen_offset fields */ 999 #define CPL_TX_DATA_ISO_SEGLEN_OFFSET_S 0 1000 #define CPL_TX_DATA_ISO_SEGLEN_OFFSET_M 0xffffff 1001 #define CPL_TX_DATA_ISO_SEGLEN_OFFSET_V(x) \ 1002 ((x) << CPL_TX_DATA_ISO_SEGLEN_OFFSET_S) 1003 #define CPL_TX_DATA_ISO_SEGLEN_OFFSET_G(x) \ 1004 (((x) >> CPL_TX_DATA_ISO_SEGLEN_OFFSET_S) & \ 1005 CPL_TX_DATA_ISO_SEGLEN_OFFSET_M) 1006 1007 struct cpl_rx_data { 1008 union opcode_tid ot; 1009 __be16 rsvd; 1010 __be16 len; 1011 __be32 seq; 1012 __be16 urg; 1013 #if defined(__LITTLE_ENDIAN_BITFIELD) 1014 u8 dack_mode:2; 1015 u8 psh:1; 1016 u8 heartbeat:1; 1017 u8 ddp_off:1; 1018 u8 :3; 1019 #else 1020 u8 :3; 1021 u8 ddp_off:1; 1022 u8 heartbeat:1; 1023 u8 psh:1; 1024 u8 dack_mode:2; 1025 #endif 1026 u8 status; 1027 }; 1028 1029 struct cpl_rx_data_ack { 1030 WR_HDR; 1031 union opcode_tid ot; 1032 __be32 credit_dack; 1033 }; 1034 1035 /* cpl_rx_data_ack.ack_seq fields */ 1036 #define RX_CREDITS_S 0 1037 #define RX_CREDITS_V(x) ((x) << RX_CREDITS_S) 1038 1039 #define RX_FORCE_ACK_S 28 1040 #define RX_FORCE_ACK_V(x) ((x) << RX_FORCE_ACK_S) 1041 #define RX_FORCE_ACK_F RX_FORCE_ACK_V(1U) 1042 1043 #define RX_DACK_MODE_S 29 1044 #define RX_DACK_MODE_M 0x3 1045 #define RX_DACK_MODE_V(x) ((x) << RX_DACK_MODE_S) 1046 #define RX_DACK_MODE_G(x) (((x) >> RX_DACK_MODE_S) & RX_DACK_MODE_M) 1047 1048 #define RX_DACK_CHANGE_S 31 1049 #define RX_DACK_CHANGE_V(x) ((x) << RX_DACK_CHANGE_S) 1050 #define RX_DACK_CHANGE_F RX_DACK_CHANGE_V(1U) 1051 1052 struct cpl_rx_pkt { 1053 struct rss_header rsshdr; 1054 u8 opcode; 1055 #if defined(__LITTLE_ENDIAN_BITFIELD) 1056 u8 iff:4; 1057 u8 csum_calc:1; 1058 u8 ipmi_pkt:1; 1059 u8 vlan_ex:1; 1060 u8 ip_frag:1; 1061 #else 1062 u8 ip_frag:1; 1063 u8 vlan_ex:1; 1064 u8 ipmi_pkt:1; 1065 u8 csum_calc:1; 1066 u8 iff:4; 1067 #endif 1068 __be16 csum; 1069 __be16 vlan; 1070 __be16 len; 1071 __be32 l2info; 1072 __be16 hdr_len; 1073 __be16 err_vec; 1074 }; 1075 1076 #define RX_T6_ETHHDR_LEN_M 0xFF 1077 #define RX_T6_ETHHDR_LEN_G(x) (((x) >> RX_ETHHDR_LEN_S) & RX_T6_ETHHDR_LEN_M) 1078 1079 #define RXF_PSH_S 20 1080 #define RXF_PSH_V(x) ((x) << RXF_PSH_S) 1081 #define RXF_PSH_F RXF_PSH_V(1U) 1082 1083 #define RXF_SYN_S 21 1084 #define RXF_SYN_V(x) ((x) << RXF_SYN_S) 1085 #define RXF_SYN_F RXF_SYN_V(1U) 1086 1087 #define RXF_UDP_S 22 1088 #define RXF_UDP_V(x) ((x) << RXF_UDP_S) 1089 #define RXF_UDP_F RXF_UDP_V(1U) 1090 1091 #define RXF_TCP_S 23 1092 #define RXF_TCP_V(x) ((x) << RXF_TCP_S) 1093 #define RXF_TCP_F RXF_TCP_V(1U) 1094 1095 #define RXF_IP_S 24 1096 #define RXF_IP_V(x) ((x) << RXF_IP_S) 1097 #define RXF_IP_F RXF_IP_V(1U) 1098 1099 #define RXF_IP6_S 25 1100 #define RXF_IP6_V(x) ((x) << RXF_IP6_S) 1101 #define RXF_IP6_F RXF_IP6_V(1U) 1102 1103 #define RXF_SYN_COOKIE_S 26 1104 #define RXF_SYN_COOKIE_V(x) ((x) << RXF_SYN_COOKIE_S) 1105 #define RXF_SYN_COOKIE_F RXF_SYN_COOKIE_V(1U) 1106 1107 #define RXF_FCOE_S 26 1108 #define RXF_FCOE_V(x) ((x) << RXF_FCOE_S) 1109 #define RXF_FCOE_F RXF_FCOE_V(1U) 1110 1111 #define RXF_LRO_S 27 1112 #define RXF_LRO_V(x) ((x) << RXF_LRO_S) 1113 #define RXF_LRO_F RXF_LRO_V(1U) 1114 1115 /* rx_pkt.l2info fields */ 1116 #define RX_ETHHDR_LEN_S 0 1117 #define RX_ETHHDR_LEN_M 0x1F 1118 #define RX_ETHHDR_LEN_V(x) ((x) << RX_ETHHDR_LEN_S) 1119 #define RX_ETHHDR_LEN_G(x) (((x) >> RX_ETHHDR_LEN_S) & RX_ETHHDR_LEN_M) 1120 1121 #define RX_T5_ETHHDR_LEN_S 0 1122 #define RX_T5_ETHHDR_LEN_M 0x3F 1123 #define RX_T5_ETHHDR_LEN_V(x) ((x) << RX_T5_ETHHDR_LEN_S) 1124 #define RX_T5_ETHHDR_LEN_G(x) (((x) >> RX_T5_ETHHDR_LEN_S) & RX_T5_ETHHDR_LEN_M) 1125 1126 #define RX_MACIDX_S 8 1127 #define RX_MACIDX_M 0x1FF 1128 #define RX_MACIDX_V(x) ((x) << RX_MACIDX_S) 1129 #define RX_MACIDX_G(x) (((x) >> RX_MACIDX_S) & RX_MACIDX_M) 1130 1131 #define RXF_SYN_S 21 1132 #define RXF_SYN_V(x) ((x) << RXF_SYN_S) 1133 #define RXF_SYN_F RXF_SYN_V(1U) 1134 1135 #define RX_CHAN_S 28 1136 #define RX_CHAN_M 0xF 1137 #define RX_CHAN_V(x) ((x) << RX_CHAN_S) 1138 #define RX_CHAN_G(x) (((x) >> RX_CHAN_S) & RX_CHAN_M) 1139 1140 /* rx_pkt.hdr_len fields */ 1141 #define RX_TCPHDR_LEN_S 0 1142 #define RX_TCPHDR_LEN_M 0x3F 1143 #define RX_TCPHDR_LEN_V(x) ((x) << RX_TCPHDR_LEN_S) 1144 #define RX_TCPHDR_LEN_G(x) (((x) >> RX_TCPHDR_LEN_S) & RX_TCPHDR_LEN_M) 1145 1146 #define RX_IPHDR_LEN_S 6 1147 #define RX_IPHDR_LEN_M 0x3FF 1148 #define RX_IPHDR_LEN_V(x) ((x) << RX_IPHDR_LEN_S) 1149 #define RX_IPHDR_LEN_G(x) (((x) >> RX_IPHDR_LEN_S) & RX_IPHDR_LEN_M) 1150 1151 /* rx_pkt.err_vec fields */ 1152 #define RXERR_CSUM_S 13 1153 #define RXERR_CSUM_V(x) ((x) << RXERR_CSUM_S) 1154 #define RXERR_CSUM_F RXERR_CSUM_V(1U) 1155 1156 struct cpl_trace_pkt { 1157 u8 opcode; 1158 u8 intf; 1159 #if defined(__LITTLE_ENDIAN_BITFIELD) 1160 u8 runt:4; 1161 u8 filter_hit:4; 1162 u8 :6; 1163 u8 err:1; 1164 u8 trunc:1; 1165 #else 1166 u8 filter_hit:4; 1167 u8 runt:4; 1168 u8 trunc:1; 1169 u8 err:1; 1170 u8 :6; 1171 #endif 1172 __be16 rsvd; 1173 __be16 len; 1174 __be64 tstamp; 1175 }; 1176 1177 struct cpl_t5_trace_pkt { 1178 __u8 opcode; 1179 __u8 intf; 1180 #if defined(__LITTLE_ENDIAN_BITFIELD) 1181 __u8 runt:4; 1182 __u8 filter_hit:4; 1183 __u8:6; 1184 __u8 err:1; 1185 __u8 trunc:1; 1186 #else 1187 __u8 filter_hit:4; 1188 __u8 runt:4; 1189 __u8 trunc:1; 1190 __u8 err:1; 1191 __u8:6; 1192 #endif 1193 __be16 rsvd; 1194 __be16 len; 1195 __be64 tstamp; 1196 __be64 rsvd1; 1197 }; 1198 1199 struct cpl_l2t_write_req { 1200 WR_HDR; 1201 union opcode_tid ot; 1202 __be16 params; 1203 __be16 l2t_idx; 1204 __be16 vlan; 1205 u8 dst_mac[6]; 1206 }; 1207 1208 /* cpl_l2t_write_req.params fields */ 1209 #define L2T_W_INFO_S 2 1210 #define L2T_W_INFO_V(x) ((x) << L2T_W_INFO_S) 1211 1212 #define L2T_W_PORT_S 8 1213 #define L2T_W_PORT_V(x) ((x) << L2T_W_PORT_S) 1214 1215 #define L2T_W_NOREPLY_S 15 1216 #define L2T_W_NOREPLY_V(x) ((x) << L2T_W_NOREPLY_S) 1217 #define L2T_W_NOREPLY_F L2T_W_NOREPLY_V(1U) 1218 1219 #define CPL_L2T_VLAN_NONE 0xfff 1220 1221 struct cpl_l2t_write_rpl { 1222 union opcode_tid ot; 1223 u8 status; 1224 u8 rsvd[3]; 1225 }; 1226 1227 struct cpl_rdma_terminate { 1228 union opcode_tid ot; 1229 __be16 rsvd; 1230 __be16 len; 1231 }; 1232 1233 struct cpl_sge_egr_update { 1234 __be32 opcode_qid; 1235 __be16 cidx; 1236 __be16 pidx; 1237 }; 1238 1239 /* cpl_sge_egr_update.ot fields */ 1240 #define EGR_QID_S 0 1241 #define EGR_QID_M 0x1FFFF 1242 #define EGR_QID_G(x) (((x) >> EGR_QID_S) & EGR_QID_M) 1243 1244 /* cpl_fw*.type values */ 1245 enum { 1246 FW_TYPE_CMD_RPL = 0, 1247 FW_TYPE_WR_RPL = 1, 1248 FW_TYPE_CQE = 2, 1249 FW_TYPE_OFLD_CONNECTION_WR_RPL = 3, 1250 FW_TYPE_RSSCPL = 4, 1251 }; 1252 1253 struct cpl_fw4_pld { 1254 u8 opcode; 1255 u8 rsvd0[3]; 1256 u8 type; 1257 u8 rsvd1; 1258 __be16 len; 1259 __be64 data; 1260 __be64 rsvd2; 1261 }; 1262 1263 struct cpl_fw6_pld { 1264 u8 opcode; 1265 u8 rsvd[5]; 1266 __be16 len; 1267 __be64 data[4]; 1268 }; 1269 1270 struct cpl_fw4_msg { 1271 u8 opcode; 1272 u8 type; 1273 __be16 rsvd0; 1274 __be32 rsvd1; 1275 __be64 data[2]; 1276 }; 1277 1278 struct cpl_fw4_ack { 1279 union opcode_tid ot; 1280 u8 credits; 1281 u8 rsvd0[2]; 1282 u8 seq_vld; 1283 __be32 snd_nxt; 1284 __be32 snd_una; 1285 __be64 rsvd1; 1286 }; 1287 1288 enum { 1289 CPL_FW4_ACK_FLAGS_SEQVAL = 0x1, /* seqn valid */ 1290 CPL_FW4_ACK_FLAGS_CH = 0x2, /* channel change complete */ 1291 CPL_FW4_ACK_FLAGS_FLOWC = 0x4, /* fw_flowc_wr complete */ 1292 }; 1293 1294 struct cpl_fw6_msg { 1295 u8 opcode; 1296 u8 type; 1297 __be16 rsvd0; 1298 __be32 rsvd1; 1299 __be64 data[4]; 1300 }; 1301 1302 /* cpl_fw6_msg.type values */ 1303 enum { 1304 FW6_TYPE_CMD_RPL = 0, 1305 FW6_TYPE_WR_RPL = 1, 1306 FW6_TYPE_CQE = 2, 1307 FW6_TYPE_OFLD_CONNECTION_WR_RPL = 3, 1308 FW6_TYPE_RSSCPL = FW_TYPE_RSSCPL, 1309 }; 1310 1311 struct cpl_fw6_msg_ofld_connection_wr_rpl { 1312 __u64 cookie; 1313 __be32 tid; /* or atid in case of active failure */ 1314 __u8 t_state; 1315 __u8 retval; 1316 __u8 rsvd[2]; 1317 }; 1318 1319 struct cpl_tx_data { 1320 union opcode_tid ot; 1321 __be32 len; 1322 __be32 rsvd; 1323 __be32 flags; 1324 }; 1325 1326 /* cpl_tx_data.flags field */ 1327 #define TX_FORCE_S 13 1328 #define TX_FORCE_V(x) ((x) << TX_FORCE_S) 1329 1330 enum { 1331 ULP_TX_MEM_READ = 2, 1332 ULP_TX_MEM_WRITE = 3, 1333 ULP_TX_PKT = 4 1334 }; 1335 1336 enum { 1337 ULP_TX_SC_NOOP = 0x80, 1338 ULP_TX_SC_IMM = 0x81, 1339 ULP_TX_SC_DSGL = 0x82, 1340 ULP_TX_SC_ISGL = 0x83 1341 }; 1342 1343 #define ULPTX_CMD_S 24 1344 #define ULPTX_CMD_V(x) ((x) << ULPTX_CMD_S) 1345 1346 struct ulptx_sge_pair { 1347 __be32 len[2]; 1348 __be64 addr[2]; 1349 }; 1350 1351 struct ulptx_sgl { 1352 __be32 cmd_nsge; 1353 __be32 len0; 1354 __be64 addr0; 1355 struct ulptx_sge_pair sge[0]; 1356 }; 1357 1358 struct ulptx_idata { 1359 __be32 cmd_more; 1360 __be32 len; 1361 }; 1362 1363 #define ULPTX_NSGE_S 0 1364 #define ULPTX_NSGE_V(x) ((x) << ULPTX_NSGE_S) 1365 1366 #define ULPTX_MORE_S 23 1367 #define ULPTX_MORE_V(x) ((x) << ULPTX_MORE_S) 1368 #define ULPTX_MORE_F ULPTX_MORE_V(1U) 1369 1370 struct ulp_mem_io { 1371 WR_HDR; 1372 __be32 cmd; 1373 __be32 len16; /* command length */ 1374 __be32 dlen; /* data length in 32-byte units */ 1375 __be32 lock_addr; 1376 }; 1377 1378 #define ULP_MEMIO_LOCK_S 31 1379 #define ULP_MEMIO_LOCK_V(x) ((x) << ULP_MEMIO_LOCK_S) 1380 #define ULP_MEMIO_LOCK_F ULP_MEMIO_LOCK_V(1U) 1381 1382 /* additional ulp_mem_io.cmd fields */ 1383 #define ULP_MEMIO_ORDER_S 23 1384 #define ULP_MEMIO_ORDER_V(x) ((x) << ULP_MEMIO_ORDER_S) 1385 #define ULP_MEMIO_ORDER_F ULP_MEMIO_ORDER_V(1U) 1386 1387 #define T5_ULP_MEMIO_IMM_S 23 1388 #define T5_ULP_MEMIO_IMM_V(x) ((x) << T5_ULP_MEMIO_IMM_S) 1389 #define T5_ULP_MEMIO_IMM_F T5_ULP_MEMIO_IMM_V(1U) 1390 1391 #define T5_ULP_MEMIO_ORDER_S 22 1392 #define T5_ULP_MEMIO_ORDER_V(x) ((x) << T5_ULP_MEMIO_ORDER_S) 1393 #define T5_ULP_MEMIO_ORDER_F T5_ULP_MEMIO_ORDER_V(1U) 1394 1395 #define T5_ULP_MEMIO_FID_S 4 1396 #define T5_ULP_MEMIO_FID_M 0x7ff 1397 #define T5_ULP_MEMIO_FID_V(x) ((x) << T5_ULP_MEMIO_FID_S) 1398 1399 /* ulp_mem_io.lock_addr fields */ 1400 #define ULP_MEMIO_ADDR_S 0 1401 #define ULP_MEMIO_ADDR_V(x) ((x) << ULP_MEMIO_ADDR_S) 1402 1403 /* ulp_mem_io.dlen fields */ 1404 #define ULP_MEMIO_DATA_LEN_S 0 1405 #define ULP_MEMIO_DATA_LEN_V(x) ((x) << ULP_MEMIO_DATA_LEN_S) 1406 1407 #endif /* __T4_MSG_H */ 1408