1 /* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #ifndef __T4_HW_H 36 #define __T4_HW_H 37 38 #include <linux/types.h> 39 40 enum { 41 NCHAN = 4, /* # of HW channels */ 42 MAX_MTU = 9600, /* max MAC MTU, excluding header + FCS */ 43 EEPROMSIZE = 17408, /* Serial EEPROM physical size */ 44 EEPROMVSIZE = 32768, /* Serial EEPROM virtual address space size */ 45 EEPROMPFSIZE = 1024, /* EEPROM writable area size for PFn, n>0 */ 46 RSS_NENTRIES = 2048, /* # of entries in RSS mapping table */ 47 TCB_SIZE = 128, /* TCB size */ 48 NMTUS = 16, /* size of MTU table */ 49 NCCTRL_WIN = 32, /* # of congestion control windows */ 50 L2T_SIZE = 4096, /* # of L2T entries */ 51 MBOX_LEN = 64, /* mailbox size in bytes */ 52 TRACE_LEN = 112, /* length of trace data and mask */ 53 FILTER_OPT_LEN = 36, /* filter tuple width for optional components */ 54 NWOL_PAT = 8, /* # of WoL patterns */ 55 WOL_PAT_LEN = 128, /* length of WoL patterns */ 56 }; 57 58 enum { 59 SF_PAGE_SIZE = 256, /* serial flash page size */ 60 SF_SEC_SIZE = 64 * 1024, /* serial flash sector size */ 61 }; 62 63 enum { RSP_TYPE_FLBUF, RSP_TYPE_CPL, RSP_TYPE_INTR }; /* response entry types */ 64 65 enum { MBOX_OWNER_NONE, MBOX_OWNER_FW, MBOX_OWNER_DRV }; /* mailbox owners */ 66 67 enum { 68 SGE_MAX_WR_LEN = 512, /* max WR size in bytes */ 69 SGE_NTIMERS = 6, /* # of interrupt holdoff timer values */ 70 SGE_NCOUNTERS = 4, /* # of interrupt packet counter values */ 71 SGE_MAX_IQ_SIZE = 65520, 72 73 SGE_TIMER_RSTRT_CNTR = 6, /* restart RX packet threshold counter */ 74 SGE_TIMER_UPD_CIDX = 7, /* update cidx only */ 75 76 SGE_EQ_IDXSIZE = 64, /* egress queue pidx/cidx unit size */ 77 78 SGE_INTRDST_PCI = 0, /* interrupt destination is PCI-E */ 79 SGE_INTRDST_IQ = 1, /* destination is an ingress queue */ 80 81 SGE_UPDATEDEL_NONE = 0, /* ingress queue pidx update delivery */ 82 SGE_UPDATEDEL_INTR = 1, /* interrupt */ 83 SGE_UPDATEDEL_STPG = 2, /* status page */ 84 SGE_UPDATEDEL_BOTH = 3, /* interrupt and status page */ 85 86 SGE_HOSTFCMODE_NONE = 0, /* egress queue cidx updates */ 87 SGE_HOSTFCMODE_IQ = 1, /* sent to ingress queue */ 88 SGE_HOSTFCMODE_STPG = 2, /* sent to status page */ 89 SGE_HOSTFCMODE_BOTH = 3, /* ingress queue and status page */ 90 91 SGE_FETCHBURSTMIN_16B = 0,/* egress queue descriptor fetch minimum */ 92 SGE_FETCHBURSTMIN_32B = 1, 93 SGE_FETCHBURSTMIN_64B = 2, 94 SGE_FETCHBURSTMIN_128B = 3, 95 96 SGE_FETCHBURSTMAX_64B = 0,/* egress queue descriptor fetch maximum */ 97 SGE_FETCHBURSTMAX_128B = 1, 98 SGE_FETCHBURSTMAX_256B = 2, 99 SGE_FETCHBURSTMAX_512B = 3, 100 101 SGE_CIDXFLUSHTHRESH_1 = 0,/* egress queue cidx flush threshold */ 102 SGE_CIDXFLUSHTHRESH_2 = 1, 103 SGE_CIDXFLUSHTHRESH_4 = 2, 104 SGE_CIDXFLUSHTHRESH_8 = 3, 105 SGE_CIDXFLUSHTHRESH_16 = 4, 106 SGE_CIDXFLUSHTHRESH_32 = 5, 107 SGE_CIDXFLUSHTHRESH_64 = 6, 108 SGE_CIDXFLUSHTHRESH_128 = 7, 109 110 SGE_INGPADBOUNDARY_SHIFT = 5,/* ingress queue pad boundary */ 111 }; 112 113 struct sge_qstat { /* data written to SGE queue status entries */ 114 __be32 qid; 115 __be16 cidx; 116 __be16 pidx; 117 }; 118 119 /* 120 * Structure for last 128 bits of response descriptors 121 */ 122 struct rsp_ctrl { 123 __be32 hdrbuflen_pidx; 124 __be32 pldbuflen_qid; 125 union { 126 u8 type_gen; 127 __be64 last_flit; 128 }; 129 }; 130 131 #define RSPD_NEWBUF 0x80000000U 132 #define RSPD_LEN(x) (((x) >> 0) & 0x7fffffffU) 133 #define RSPD_QID(x) RSPD_LEN(x) 134 135 #define RSPD_GEN(x) ((x) >> 7) 136 #define RSPD_TYPE(x) (((x) >> 4) & 3) 137 138 #define V_QINTR_CNT_EN 0x0 139 #define QINTR_CNT_EN 0x1 140 #define QINTR_TIMER_IDX(x) ((x) << 1) 141 #define QINTR_TIMER_IDX_GET(x) (((x) >> 1) & 0x7) 142 143 /* 144 * Flash layout. 145 */ 146 #define FLASH_START(start) ((start) * SF_SEC_SIZE) 147 #define FLASH_MAX_SIZE(nsecs) ((nsecs) * SF_SEC_SIZE) 148 149 enum { 150 /* 151 * Various Expansion-ROM boot images, etc. 152 */ 153 FLASH_EXP_ROM_START_SEC = 0, 154 FLASH_EXP_ROM_NSECS = 6, 155 FLASH_EXP_ROM_START = FLASH_START(FLASH_EXP_ROM_START_SEC), 156 FLASH_EXP_ROM_MAX_SIZE = FLASH_MAX_SIZE(FLASH_EXP_ROM_NSECS), 157 158 /* 159 * iSCSI Boot Firmware Table (iBFT) and other driver-related 160 * parameters ... 161 */ 162 FLASH_IBFT_START_SEC = 6, 163 FLASH_IBFT_NSECS = 1, 164 FLASH_IBFT_START = FLASH_START(FLASH_IBFT_START_SEC), 165 FLASH_IBFT_MAX_SIZE = FLASH_MAX_SIZE(FLASH_IBFT_NSECS), 166 167 /* 168 * Boot configuration data. 169 */ 170 FLASH_BOOTCFG_START_SEC = 7, 171 FLASH_BOOTCFG_NSECS = 1, 172 FLASH_BOOTCFG_START = FLASH_START(FLASH_BOOTCFG_START_SEC), 173 FLASH_BOOTCFG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_BOOTCFG_NSECS), 174 175 /* 176 * Location of firmware image in FLASH. 177 */ 178 FLASH_FW_START_SEC = 8, 179 FLASH_FW_NSECS = 16, 180 FLASH_FW_START = FLASH_START(FLASH_FW_START_SEC), 181 FLASH_FW_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FW_NSECS), 182 183 /* 184 * iSCSI persistent/crash information. 185 */ 186 FLASH_ISCSI_CRASH_START_SEC = 29, 187 FLASH_ISCSI_CRASH_NSECS = 1, 188 FLASH_ISCSI_CRASH_START = FLASH_START(FLASH_ISCSI_CRASH_START_SEC), 189 FLASH_ISCSI_CRASH_MAX_SIZE = FLASH_MAX_SIZE(FLASH_ISCSI_CRASH_NSECS), 190 191 /* 192 * FCoE persistent/crash information. 193 */ 194 FLASH_FCOE_CRASH_START_SEC = 30, 195 FLASH_FCOE_CRASH_NSECS = 1, 196 FLASH_FCOE_CRASH_START = FLASH_START(FLASH_FCOE_CRASH_START_SEC), 197 FLASH_FCOE_CRASH_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FCOE_CRASH_NSECS), 198 199 /* 200 * Location of Firmware Configuration File in FLASH. Since the FPGA 201 * "FLASH" is smaller we need to store the Configuration File in a 202 * different location -- which will overlap the end of the firmware 203 * image if firmware ever gets that large ... 204 */ 205 FLASH_CFG_START_SEC = 31, 206 FLASH_CFG_NSECS = 1, 207 FLASH_CFG_START = FLASH_START(FLASH_CFG_START_SEC), 208 FLASH_CFG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_CFG_NSECS), 209 210 /* We don't support FLASH devices which can't support the full 211 * standard set of sections which we need for normal 212 * operations. 213 */ 214 FLASH_MIN_SIZE = FLASH_CFG_START + FLASH_CFG_MAX_SIZE, 215 216 FLASH_FPGA_CFG_START_SEC = 15, 217 FLASH_FPGA_CFG_START = FLASH_START(FLASH_FPGA_CFG_START_SEC), 218 219 /* 220 * Sectors 32-63 are reserved for FLASH failover. 221 */ 222 }; 223 224 #undef FLASH_START 225 #undef FLASH_MAX_SIZE 226 227 #endif /* __T4_HW_H */ 228