1 /* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #include <linux/delay.h> 36 #include "cxgb4.h" 37 #include "t4_regs.h" 38 #include "t4_values.h" 39 #include "t4fw_api.h" 40 #include "t4fw_version.h" 41 42 /** 43 * t4_wait_op_done_val - wait until an operation is completed 44 * @adapter: the adapter performing the operation 45 * @reg: the register to check for completion 46 * @mask: a single-bit field within @reg that indicates completion 47 * @polarity: the value of the field when the operation is completed 48 * @attempts: number of check iterations 49 * @delay: delay in usecs between iterations 50 * @valp: where to store the value of the register at completion time 51 * 52 * Wait until an operation is completed by checking a bit in a register 53 * up to @attempts times. If @valp is not NULL the value of the register 54 * at the time it indicated completion is stored there. Returns 0 if the 55 * operation completes and -EAGAIN otherwise. 56 */ 57 static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask, 58 int polarity, int attempts, int delay, u32 *valp) 59 { 60 while (1) { 61 u32 val = t4_read_reg(adapter, reg); 62 63 if (!!(val & mask) == polarity) { 64 if (valp) 65 *valp = val; 66 return 0; 67 } 68 if (--attempts == 0) 69 return -EAGAIN; 70 if (delay) 71 udelay(delay); 72 } 73 } 74 75 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask, 76 int polarity, int attempts, int delay) 77 { 78 return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts, 79 delay, NULL); 80 } 81 82 /** 83 * t4_set_reg_field - set a register field to a value 84 * @adapter: the adapter to program 85 * @addr: the register address 86 * @mask: specifies the portion of the register to modify 87 * @val: the new value for the register field 88 * 89 * Sets a register field specified by the supplied mask to the 90 * given value. 91 */ 92 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask, 93 u32 val) 94 { 95 u32 v = t4_read_reg(adapter, addr) & ~mask; 96 97 t4_write_reg(adapter, addr, v | val); 98 (void) t4_read_reg(adapter, addr); /* flush */ 99 } 100 101 /** 102 * t4_read_indirect - read indirectly addressed registers 103 * @adap: the adapter 104 * @addr_reg: register holding the indirect address 105 * @data_reg: register holding the value of the indirect register 106 * @vals: where the read register values are stored 107 * @nregs: how many indirect registers to read 108 * @start_idx: index of first indirect register to read 109 * 110 * Reads registers that are accessed indirectly through an address/data 111 * register pair. 112 */ 113 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 114 unsigned int data_reg, u32 *vals, 115 unsigned int nregs, unsigned int start_idx) 116 { 117 while (nregs--) { 118 t4_write_reg(adap, addr_reg, start_idx); 119 *vals++ = t4_read_reg(adap, data_reg); 120 start_idx++; 121 } 122 } 123 124 /** 125 * t4_write_indirect - write indirectly addressed registers 126 * @adap: the adapter 127 * @addr_reg: register holding the indirect addresses 128 * @data_reg: register holding the value for the indirect registers 129 * @vals: values to write 130 * @nregs: how many indirect registers to write 131 * @start_idx: address of first indirect register to write 132 * 133 * Writes a sequential block of registers that are accessed indirectly 134 * through an address/data register pair. 135 */ 136 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 137 unsigned int data_reg, const u32 *vals, 138 unsigned int nregs, unsigned int start_idx) 139 { 140 while (nregs--) { 141 t4_write_reg(adap, addr_reg, start_idx++); 142 t4_write_reg(adap, data_reg, *vals++); 143 } 144 } 145 146 /* 147 * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor 148 * mechanism. This guarantees that we get the real value even if we're 149 * operating within a Virtual Machine and the Hypervisor is trapping our 150 * Configuration Space accesses. 151 */ 152 void t4_hw_pci_read_cfg4(struct adapter *adap, int reg, u32 *val) 153 { 154 u32 req = FUNCTION_V(adap->pf) | REGISTER_V(reg); 155 156 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5) 157 req |= ENABLE_F; 158 else 159 req |= T6_ENABLE_F; 160 161 if (is_t4(adap->params.chip)) 162 req |= LOCALCFG_F; 163 164 t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, req); 165 *val = t4_read_reg(adap, PCIE_CFG_SPACE_DATA_A); 166 167 /* Reset ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a 168 * Configuration Space read. (None of the other fields matter when 169 * ENABLE is 0 so a simple register write is easier than a 170 * read-modify-write via t4_set_reg_field().) 171 */ 172 t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, 0); 173 } 174 175 /* 176 * t4_report_fw_error - report firmware error 177 * @adap: the adapter 178 * 179 * The adapter firmware can indicate error conditions to the host. 180 * If the firmware has indicated an error, print out the reason for 181 * the firmware error. 182 */ 183 static void t4_report_fw_error(struct adapter *adap) 184 { 185 static const char *const reason[] = { 186 "Crash", /* PCIE_FW_EVAL_CRASH */ 187 "During Device Preparation", /* PCIE_FW_EVAL_PREP */ 188 "During Device Configuration", /* PCIE_FW_EVAL_CONF */ 189 "During Device Initialization", /* PCIE_FW_EVAL_INIT */ 190 "Unexpected Event", /* PCIE_FW_EVAL_UNEXPECTEDEVENT */ 191 "Insufficient Airflow", /* PCIE_FW_EVAL_OVERHEAT */ 192 "Device Shutdown", /* PCIE_FW_EVAL_DEVICESHUTDOWN */ 193 "Reserved", /* reserved */ 194 }; 195 u32 pcie_fw; 196 197 pcie_fw = t4_read_reg(adap, PCIE_FW_A); 198 if (pcie_fw & PCIE_FW_ERR_F) 199 dev_err(adap->pdev_dev, "Firmware reports adapter error: %s\n", 200 reason[PCIE_FW_EVAL_G(pcie_fw)]); 201 } 202 203 /* 204 * Get the reply to a mailbox command and store it in @rpl in big-endian order. 205 */ 206 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit, 207 u32 mbox_addr) 208 { 209 for ( ; nflit; nflit--, mbox_addr += 8) 210 *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr)); 211 } 212 213 /* 214 * Handle a FW assertion reported in a mailbox. 215 */ 216 static void fw_asrt(struct adapter *adap, u32 mbox_addr) 217 { 218 struct fw_debug_cmd asrt; 219 220 get_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr); 221 dev_alert(adap->pdev_dev, 222 "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n", 223 asrt.u.assert.filename_0_7, be32_to_cpu(asrt.u.assert.line), 224 be32_to_cpu(asrt.u.assert.x), be32_to_cpu(asrt.u.assert.y)); 225 } 226 227 static void dump_mbox(struct adapter *adap, int mbox, u32 data_reg) 228 { 229 dev_err(adap->pdev_dev, 230 "mbox %d: %llx %llx %llx %llx %llx %llx %llx %llx\n", mbox, 231 (unsigned long long)t4_read_reg64(adap, data_reg), 232 (unsigned long long)t4_read_reg64(adap, data_reg + 8), 233 (unsigned long long)t4_read_reg64(adap, data_reg + 16), 234 (unsigned long long)t4_read_reg64(adap, data_reg + 24), 235 (unsigned long long)t4_read_reg64(adap, data_reg + 32), 236 (unsigned long long)t4_read_reg64(adap, data_reg + 40), 237 (unsigned long long)t4_read_reg64(adap, data_reg + 48), 238 (unsigned long long)t4_read_reg64(adap, data_reg + 56)); 239 } 240 241 /** 242 * t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox 243 * @adap: the adapter 244 * @mbox: index of the mailbox to use 245 * @cmd: the command to write 246 * @size: command length in bytes 247 * @rpl: where to optionally store the reply 248 * @sleep_ok: if true we may sleep while awaiting command completion 249 * @timeout: time to wait for command to finish before timing out 250 * 251 * Sends the given command to FW through the selected mailbox and waits 252 * for the FW to execute the command. If @rpl is not %NULL it is used to 253 * store the FW's reply to the command. The command and its optional 254 * reply are of the same length. FW can take up to %FW_CMD_MAX_TIMEOUT ms 255 * to respond. @sleep_ok determines whether we may sleep while awaiting 256 * the response. If sleeping is allowed we use progressive backoff 257 * otherwise we spin. 258 * 259 * The return value is 0 on success or a negative errno on failure. A 260 * failure can happen either because we are not able to execute the 261 * command or FW executes it but signals an error. In the latter case 262 * the return value is the error code indicated by FW (negated). 263 */ 264 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 265 int size, void *rpl, bool sleep_ok, int timeout) 266 { 267 static const int delay[] = { 268 1, 1, 3, 5, 10, 10, 20, 50, 100, 200 269 }; 270 271 u32 v; 272 u64 res; 273 int i, ms, delay_idx; 274 const __be64 *p = cmd; 275 u32 data_reg = PF_REG(mbox, CIM_PF_MAILBOX_DATA_A); 276 u32 ctl_reg = PF_REG(mbox, CIM_PF_MAILBOX_CTRL_A); 277 278 if ((size & 15) || size > MBOX_LEN) 279 return -EINVAL; 280 281 /* 282 * If the device is off-line, as in EEH, commands will time out. 283 * Fail them early so we don't waste time waiting. 284 */ 285 if (adap->pdev->error_state != pci_channel_io_normal) 286 return -EIO; 287 288 v = MBOWNER_G(t4_read_reg(adap, ctl_reg)); 289 for (i = 0; v == MBOX_OWNER_NONE && i < 3; i++) 290 v = MBOWNER_G(t4_read_reg(adap, ctl_reg)); 291 292 if (v != MBOX_OWNER_DRV) 293 return v ? -EBUSY : -ETIMEDOUT; 294 295 for (i = 0; i < size; i += 8) 296 t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p++)); 297 298 t4_write_reg(adap, ctl_reg, MBMSGVALID_F | MBOWNER_V(MBOX_OWNER_FW)); 299 t4_read_reg(adap, ctl_reg); /* flush write */ 300 301 delay_idx = 0; 302 ms = delay[0]; 303 304 for (i = 0; i < timeout; i += ms) { 305 if (sleep_ok) { 306 ms = delay[delay_idx]; /* last element may repeat */ 307 if (delay_idx < ARRAY_SIZE(delay) - 1) 308 delay_idx++; 309 msleep(ms); 310 } else 311 mdelay(ms); 312 313 v = t4_read_reg(adap, ctl_reg); 314 if (MBOWNER_G(v) == MBOX_OWNER_DRV) { 315 if (!(v & MBMSGVALID_F)) { 316 t4_write_reg(adap, ctl_reg, 0); 317 continue; 318 } 319 320 res = t4_read_reg64(adap, data_reg); 321 if (FW_CMD_OP_G(res >> 32) == FW_DEBUG_CMD) { 322 fw_asrt(adap, data_reg); 323 res = FW_CMD_RETVAL_V(EIO); 324 } else if (rpl) { 325 get_mbox_rpl(adap, rpl, size / 8, data_reg); 326 } 327 328 if (FW_CMD_RETVAL_G((int)res)) 329 dump_mbox(adap, mbox, data_reg); 330 t4_write_reg(adap, ctl_reg, 0); 331 return -FW_CMD_RETVAL_G((int)res); 332 } 333 } 334 335 dump_mbox(adap, mbox, data_reg); 336 dev_err(adap->pdev_dev, "command %#x in mailbox %d timed out\n", 337 *(const u8 *)cmd, mbox); 338 t4_report_fw_error(adap); 339 return -ETIMEDOUT; 340 } 341 342 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 343 void *rpl, bool sleep_ok) 344 { 345 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, sleep_ok, 346 FW_CMD_MAX_TIMEOUT); 347 } 348 349 static int t4_edc_err_read(struct adapter *adap, int idx) 350 { 351 u32 edc_ecc_err_addr_reg; 352 u32 rdata_reg; 353 354 if (is_t4(adap->params.chip)) { 355 CH_WARN(adap, "%s: T4 NOT supported.\n", __func__); 356 return 0; 357 } 358 if (idx != 0 && idx != 1) { 359 CH_WARN(adap, "%s: idx %d NOT supported.\n", __func__, idx); 360 return 0; 361 } 362 363 edc_ecc_err_addr_reg = EDC_T5_REG(EDC_H_ECC_ERR_ADDR_A, idx); 364 rdata_reg = EDC_T5_REG(EDC_H_BIST_STATUS_RDATA_A, idx); 365 366 CH_WARN(adap, 367 "edc%d err addr 0x%x: 0x%x.\n", 368 idx, edc_ecc_err_addr_reg, 369 t4_read_reg(adap, edc_ecc_err_addr_reg)); 370 CH_WARN(adap, 371 "bist: 0x%x, status %llx %llx %llx %llx %llx %llx %llx %llx %llx.\n", 372 rdata_reg, 373 (unsigned long long)t4_read_reg64(adap, rdata_reg), 374 (unsigned long long)t4_read_reg64(adap, rdata_reg + 8), 375 (unsigned long long)t4_read_reg64(adap, rdata_reg + 16), 376 (unsigned long long)t4_read_reg64(adap, rdata_reg + 24), 377 (unsigned long long)t4_read_reg64(adap, rdata_reg + 32), 378 (unsigned long long)t4_read_reg64(adap, rdata_reg + 40), 379 (unsigned long long)t4_read_reg64(adap, rdata_reg + 48), 380 (unsigned long long)t4_read_reg64(adap, rdata_reg + 56), 381 (unsigned long long)t4_read_reg64(adap, rdata_reg + 64)); 382 383 return 0; 384 } 385 386 /** 387 * t4_memory_rw - read/write EDC 0, EDC 1 or MC via PCIE memory window 388 * @adap: the adapter 389 * @win: PCI-E Memory Window to use 390 * @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC 391 * @addr: address within indicated memory type 392 * @len: amount of memory to transfer 393 * @hbuf: host memory buffer 394 * @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0) 395 * 396 * Reads/writes an [almost] arbitrary memory region in the firmware: the 397 * firmware memory address and host buffer must be aligned on 32-bit 398 * boudaries; the length may be arbitrary. The memory is transferred as 399 * a raw byte sequence from/to the firmware's memory. If this memory 400 * contains data structures which contain multi-byte integers, it's the 401 * caller's responsibility to perform appropriate byte order conversions. 402 */ 403 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, 404 u32 len, void *hbuf, int dir) 405 { 406 u32 pos, offset, resid, memoffset; 407 u32 edc_size, mc_size, win_pf, mem_reg, mem_aperture, mem_base; 408 u32 *buf; 409 410 /* Argument sanity checks ... 411 */ 412 if (addr & 0x3 || (uintptr_t)hbuf & 0x3) 413 return -EINVAL; 414 buf = (u32 *)hbuf; 415 416 /* It's convenient to be able to handle lengths which aren't a 417 * multiple of 32-bits because we often end up transferring files to 418 * the firmware. So we'll handle that by normalizing the length here 419 * and then handling any residual transfer at the end. 420 */ 421 resid = len & 0x3; 422 len -= resid; 423 424 /* Offset into the region of memory which is being accessed 425 * MEM_EDC0 = 0 426 * MEM_EDC1 = 1 427 * MEM_MC = 2 -- MEM_MC for chips with only 1 memory controller 428 * MEM_MC1 = 3 -- for chips with 2 memory controllers (e.g. T5) 429 */ 430 edc_size = EDRAM0_SIZE_G(t4_read_reg(adap, MA_EDRAM0_BAR_A)); 431 if (mtype != MEM_MC1) 432 memoffset = (mtype * (edc_size * 1024 * 1024)); 433 else { 434 mc_size = EXT_MEM0_SIZE_G(t4_read_reg(adap, 435 MA_EXT_MEMORY0_BAR_A)); 436 memoffset = (MEM_MC0 * edc_size + mc_size) * 1024 * 1024; 437 } 438 439 /* Determine the PCIE_MEM_ACCESS_OFFSET */ 440 addr = addr + memoffset; 441 442 /* Each PCI-E Memory Window is programmed with a window size -- or 443 * "aperture" -- which controls the granularity of its mapping onto 444 * adapter memory. We need to grab that aperture in order to know 445 * how to use the specified window. The window is also programmed 446 * with the base address of the Memory Window in BAR0's address 447 * space. For T4 this is an absolute PCI-E Bus Address. For T5 448 * the address is relative to BAR0. 449 */ 450 mem_reg = t4_read_reg(adap, 451 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 452 win)); 453 mem_aperture = 1 << (WINDOW_G(mem_reg) + WINDOW_SHIFT_X); 454 mem_base = PCIEOFST_G(mem_reg) << PCIEOFST_SHIFT_X; 455 if (is_t4(adap->params.chip)) 456 mem_base -= adap->t4_bar0; 457 win_pf = is_t4(adap->params.chip) ? 0 : PFNUM_V(adap->pf); 458 459 /* Calculate our initial PCI-E Memory Window Position and Offset into 460 * that Window. 461 */ 462 pos = addr & ~(mem_aperture-1); 463 offset = addr - pos; 464 465 /* Set up initial PCI-E Memory Window to cover the start of our 466 * transfer. (Read it back to ensure that changes propagate before we 467 * attempt to use the new value.) 468 */ 469 t4_write_reg(adap, 470 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win), 471 pos | win_pf); 472 t4_read_reg(adap, 473 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win)); 474 475 /* Transfer data to/from the adapter as long as there's an integral 476 * number of 32-bit transfers to complete. 477 * 478 * A note on Endianness issues: 479 * 480 * The "register" reads and writes below from/to the PCI-E Memory 481 * Window invoke the standard adapter Big-Endian to PCI-E Link 482 * Little-Endian "swizzel." As a result, if we have the following 483 * data in adapter memory: 484 * 485 * Memory: ... | b0 | b1 | b2 | b3 | ... 486 * Address: i+0 i+1 i+2 i+3 487 * 488 * Then a read of the adapter memory via the PCI-E Memory Window 489 * will yield: 490 * 491 * x = readl(i) 492 * 31 0 493 * [ b3 | b2 | b1 | b0 ] 494 * 495 * If this value is stored into local memory on a Little-Endian system 496 * it will show up correctly in local memory as: 497 * 498 * ( ..., b0, b1, b2, b3, ... ) 499 * 500 * But on a Big-Endian system, the store will show up in memory 501 * incorrectly swizzled as: 502 * 503 * ( ..., b3, b2, b1, b0, ... ) 504 * 505 * So we need to account for this in the reads and writes to the 506 * PCI-E Memory Window below by undoing the register read/write 507 * swizzels. 508 */ 509 while (len > 0) { 510 if (dir == T4_MEMORY_READ) 511 *buf++ = le32_to_cpu((__force __le32)t4_read_reg(adap, 512 mem_base + offset)); 513 else 514 t4_write_reg(adap, mem_base + offset, 515 (__force u32)cpu_to_le32(*buf++)); 516 offset += sizeof(__be32); 517 len -= sizeof(__be32); 518 519 /* If we've reached the end of our current window aperture, 520 * move the PCI-E Memory Window on to the next. Note that 521 * doing this here after "len" may be 0 allows us to set up 522 * the PCI-E Memory Window for a possible final residual 523 * transfer below ... 524 */ 525 if (offset == mem_aperture) { 526 pos += mem_aperture; 527 offset = 0; 528 t4_write_reg(adap, 529 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 530 win), pos | win_pf); 531 t4_read_reg(adap, 532 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 533 win)); 534 } 535 } 536 537 /* If the original transfer had a length which wasn't a multiple of 538 * 32-bits, now's where we need to finish off the transfer of the 539 * residual amount. The PCI-E Memory Window has already been moved 540 * above (if necessary) to cover this final transfer. 541 */ 542 if (resid) { 543 union { 544 u32 word; 545 char byte[4]; 546 } last; 547 unsigned char *bp; 548 int i; 549 550 if (dir == T4_MEMORY_READ) { 551 last.word = le32_to_cpu( 552 (__force __le32)t4_read_reg(adap, 553 mem_base + offset)); 554 for (bp = (unsigned char *)buf, i = resid; i < 4; i++) 555 bp[i] = last.byte[i]; 556 } else { 557 last.word = *buf; 558 for (i = resid; i < 4; i++) 559 last.byte[i] = 0; 560 t4_write_reg(adap, mem_base + offset, 561 (__force u32)cpu_to_le32(last.word)); 562 } 563 } 564 565 return 0; 566 } 567 568 /* Return the specified PCI-E Configuration Space register from our Physical 569 * Function. We try first via a Firmware LDST Command since we prefer to let 570 * the firmware own all of these registers, but if that fails we go for it 571 * directly ourselves. 572 */ 573 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg) 574 { 575 u32 val, ldst_addrspace; 576 577 /* If fw_attach != 0, construct and send the Firmware LDST Command to 578 * retrieve the specified PCI-E Configuration Space register. 579 */ 580 struct fw_ldst_cmd ldst_cmd; 581 int ret; 582 583 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 584 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FUNC_PCIE); 585 ldst_cmd.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) | 586 FW_CMD_REQUEST_F | 587 FW_CMD_READ_F | 588 ldst_addrspace); 589 ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd)); 590 ldst_cmd.u.pcie.select_naccess = FW_LDST_CMD_NACCESS_V(1); 591 ldst_cmd.u.pcie.ctrl_to_fn = 592 (FW_LDST_CMD_LC_F | FW_LDST_CMD_FN_V(adap->pf)); 593 ldst_cmd.u.pcie.r = reg; 594 595 /* If the LDST Command succeeds, return the result, otherwise 596 * fall through to reading it directly ourselves ... 597 */ 598 ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd), 599 &ldst_cmd); 600 if (ret == 0) 601 val = be32_to_cpu(ldst_cmd.u.pcie.data[0]); 602 else 603 /* Read the desired Configuration Space register via the PCI-E 604 * Backdoor mechanism. 605 */ 606 t4_hw_pci_read_cfg4(adap, reg, &val); 607 return val; 608 } 609 610 /* Get the window based on base passed to it. 611 * Window aperture is currently unhandled, but there is no use case for it 612 * right now 613 */ 614 static u32 t4_get_window(struct adapter *adap, u32 pci_base, u64 pci_mask, 615 u32 memwin_base) 616 { 617 u32 ret; 618 619 if (is_t4(adap->params.chip)) { 620 u32 bar0; 621 622 /* Truncation intentional: we only read the bottom 32-bits of 623 * the 64-bit BAR0/BAR1 ... We use the hardware backdoor 624 * mechanism to read BAR0 instead of using 625 * pci_resource_start() because we could be operating from 626 * within a Virtual Machine which is trapping our accesses to 627 * our Configuration Space and we need to set up the PCI-E 628 * Memory Window decoders with the actual addresses which will 629 * be coming across the PCI-E link. 630 */ 631 bar0 = t4_read_pcie_cfg4(adap, pci_base); 632 bar0 &= pci_mask; 633 adap->t4_bar0 = bar0; 634 635 ret = bar0 + memwin_base; 636 } else { 637 /* For T5, only relative offset inside the PCIe BAR is passed */ 638 ret = memwin_base; 639 } 640 return ret; 641 } 642 643 /* Get the default utility window (win0) used by everyone */ 644 u32 t4_get_util_window(struct adapter *adap) 645 { 646 return t4_get_window(adap, PCI_BASE_ADDRESS_0, 647 PCI_BASE_ADDRESS_MEM_MASK, MEMWIN0_BASE); 648 } 649 650 /* Set up memory window for accessing adapter memory ranges. (Read 651 * back MA register to ensure that changes propagate before we attempt 652 * to use the new values.) 653 */ 654 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window) 655 { 656 t4_write_reg(adap, 657 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window), 658 memwin_base | BIR_V(0) | 659 WINDOW_V(ilog2(MEMWIN0_APERTURE) - WINDOW_SHIFT_X)); 660 t4_read_reg(adap, 661 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window)); 662 } 663 664 /** 665 * t4_get_regs_len - return the size of the chips register set 666 * @adapter: the adapter 667 * 668 * Returns the size of the chip's BAR0 register space. 669 */ 670 unsigned int t4_get_regs_len(struct adapter *adapter) 671 { 672 unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip); 673 674 switch (chip_version) { 675 case CHELSIO_T4: 676 return T4_REGMAP_SIZE; 677 678 case CHELSIO_T5: 679 case CHELSIO_T6: 680 return T5_REGMAP_SIZE; 681 } 682 683 dev_err(adapter->pdev_dev, 684 "Unsupported chip version %d\n", chip_version); 685 return 0; 686 } 687 688 /** 689 * t4_get_regs - read chip registers into provided buffer 690 * @adap: the adapter 691 * @buf: register buffer 692 * @buf_size: size (in bytes) of register buffer 693 * 694 * If the provided register buffer isn't large enough for the chip's 695 * full register range, the register dump will be truncated to the 696 * register buffer's size. 697 */ 698 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size) 699 { 700 static const unsigned int t4_reg_ranges[] = { 701 0x1008, 0x1108, 702 0x1180, 0x11b4, 703 0x11fc, 0x123c, 704 0x1300, 0x173c, 705 0x1800, 0x18fc, 706 0x3000, 0x305c, 707 0x3068, 0x30d8, 708 0x30e0, 0x5924, 709 0x5960, 0x59d4, 710 0x5a00, 0x5af8, 711 0x6000, 0x6098, 712 0x6100, 0x6150, 713 0x6200, 0x6208, 714 0x6240, 0x6248, 715 0x6280, 0x6338, 716 0x6370, 0x638c, 717 0x6400, 0x643c, 718 0x6500, 0x6524, 719 0x6a00, 0x6a38, 720 0x6a60, 0x6a78, 721 0x6b00, 0x6b84, 722 0x6bf0, 0x6c84, 723 0x6cf0, 0x6d84, 724 0x6df0, 0x6e84, 725 0x6ef0, 0x6f84, 726 0x6ff0, 0x7084, 727 0x70f0, 0x7184, 728 0x71f0, 0x7284, 729 0x72f0, 0x7384, 730 0x73f0, 0x7450, 731 0x7500, 0x7530, 732 0x7600, 0x761c, 733 0x7680, 0x76cc, 734 0x7700, 0x7798, 735 0x77c0, 0x77fc, 736 0x7900, 0x79fc, 737 0x7b00, 0x7c38, 738 0x7d00, 0x7efc, 739 0x8dc0, 0x8e1c, 740 0x8e30, 0x8e78, 741 0x8ea0, 0x8f6c, 742 0x8fc0, 0x9074, 743 0x90fc, 0x90fc, 744 0x9400, 0x9458, 745 0x9600, 0x96bc, 746 0x9800, 0x9808, 747 0x9820, 0x983c, 748 0x9850, 0x9864, 749 0x9c00, 0x9c6c, 750 0x9c80, 0x9cec, 751 0x9d00, 0x9d6c, 752 0x9d80, 0x9dec, 753 0x9e00, 0x9e6c, 754 0x9e80, 0x9eec, 755 0x9f00, 0x9f6c, 756 0x9f80, 0x9fec, 757 0xd004, 0xd03c, 758 0xdfc0, 0xdfe0, 759 0xe000, 0xea7c, 760 0xf000, 0x11110, 761 0x11118, 0x11190, 762 0x19040, 0x1906c, 763 0x19078, 0x19080, 764 0x1908c, 0x19124, 765 0x19150, 0x191b0, 766 0x191d0, 0x191e8, 767 0x19238, 0x1924c, 768 0x193f8, 0x19474, 769 0x19490, 0x194f8, 770 0x19800, 0x19f4c, 771 0x1a000, 0x1a06c, 772 0x1a0b0, 0x1a120, 773 0x1a128, 0x1a138, 774 0x1a190, 0x1a1c4, 775 0x1a1fc, 0x1a1fc, 776 0x1e040, 0x1e04c, 777 0x1e284, 0x1e28c, 778 0x1e2c0, 0x1e2c0, 779 0x1e2e0, 0x1e2e0, 780 0x1e300, 0x1e384, 781 0x1e3c0, 0x1e3c8, 782 0x1e440, 0x1e44c, 783 0x1e684, 0x1e68c, 784 0x1e6c0, 0x1e6c0, 785 0x1e6e0, 0x1e6e0, 786 0x1e700, 0x1e784, 787 0x1e7c0, 0x1e7c8, 788 0x1e840, 0x1e84c, 789 0x1ea84, 0x1ea8c, 790 0x1eac0, 0x1eac0, 791 0x1eae0, 0x1eae0, 792 0x1eb00, 0x1eb84, 793 0x1ebc0, 0x1ebc8, 794 0x1ec40, 0x1ec4c, 795 0x1ee84, 0x1ee8c, 796 0x1eec0, 0x1eec0, 797 0x1eee0, 0x1eee0, 798 0x1ef00, 0x1ef84, 799 0x1efc0, 0x1efc8, 800 0x1f040, 0x1f04c, 801 0x1f284, 0x1f28c, 802 0x1f2c0, 0x1f2c0, 803 0x1f2e0, 0x1f2e0, 804 0x1f300, 0x1f384, 805 0x1f3c0, 0x1f3c8, 806 0x1f440, 0x1f44c, 807 0x1f684, 0x1f68c, 808 0x1f6c0, 0x1f6c0, 809 0x1f6e0, 0x1f6e0, 810 0x1f700, 0x1f784, 811 0x1f7c0, 0x1f7c8, 812 0x1f840, 0x1f84c, 813 0x1fa84, 0x1fa8c, 814 0x1fac0, 0x1fac0, 815 0x1fae0, 0x1fae0, 816 0x1fb00, 0x1fb84, 817 0x1fbc0, 0x1fbc8, 818 0x1fc40, 0x1fc4c, 819 0x1fe84, 0x1fe8c, 820 0x1fec0, 0x1fec0, 821 0x1fee0, 0x1fee0, 822 0x1ff00, 0x1ff84, 823 0x1ffc0, 0x1ffc8, 824 0x20000, 0x2002c, 825 0x20100, 0x2013c, 826 0x20190, 0x201c8, 827 0x20200, 0x20318, 828 0x20400, 0x20528, 829 0x20540, 0x20614, 830 0x21000, 0x21040, 831 0x2104c, 0x21060, 832 0x210c0, 0x210ec, 833 0x21200, 0x21268, 834 0x21270, 0x21284, 835 0x212fc, 0x21388, 836 0x21400, 0x21404, 837 0x21500, 0x21518, 838 0x2152c, 0x2153c, 839 0x21550, 0x21554, 840 0x21600, 0x21600, 841 0x21608, 0x21628, 842 0x21630, 0x2163c, 843 0x21700, 0x2171c, 844 0x21780, 0x2178c, 845 0x21800, 0x21c38, 846 0x21c80, 0x21d7c, 847 0x21e00, 0x21e04, 848 0x22000, 0x2202c, 849 0x22100, 0x2213c, 850 0x22190, 0x221c8, 851 0x22200, 0x22318, 852 0x22400, 0x22528, 853 0x22540, 0x22614, 854 0x23000, 0x23040, 855 0x2304c, 0x23060, 856 0x230c0, 0x230ec, 857 0x23200, 0x23268, 858 0x23270, 0x23284, 859 0x232fc, 0x23388, 860 0x23400, 0x23404, 861 0x23500, 0x23518, 862 0x2352c, 0x2353c, 863 0x23550, 0x23554, 864 0x23600, 0x23600, 865 0x23608, 0x23628, 866 0x23630, 0x2363c, 867 0x23700, 0x2371c, 868 0x23780, 0x2378c, 869 0x23800, 0x23c38, 870 0x23c80, 0x23d7c, 871 0x23e00, 0x23e04, 872 0x24000, 0x2402c, 873 0x24100, 0x2413c, 874 0x24190, 0x241c8, 875 0x24200, 0x24318, 876 0x24400, 0x24528, 877 0x24540, 0x24614, 878 0x25000, 0x25040, 879 0x2504c, 0x25060, 880 0x250c0, 0x250ec, 881 0x25200, 0x25268, 882 0x25270, 0x25284, 883 0x252fc, 0x25388, 884 0x25400, 0x25404, 885 0x25500, 0x25518, 886 0x2552c, 0x2553c, 887 0x25550, 0x25554, 888 0x25600, 0x25600, 889 0x25608, 0x25628, 890 0x25630, 0x2563c, 891 0x25700, 0x2571c, 892 0x25780, 0x2578c, 893 0x25800, 0x25c38, 894 0x25c80, 0x25d7c, 895 0x25e00, 0x25e04, 896 0x26000, 0x2602c, 897 0x26100, 0x2613c, 898 0x26190, 0x261c8, 899 0x26200, 0x26318, 900 0x26400, 0x26528, 901 0x26540, 0x26614, 902 0x27000, 0x27040, 903 0x2704c, 0x27060, 904 0x270c0, 0x270ec, 905 0x27200, 0x27268, 906 0x27270, 0x27284, 907 0x272fc, 0x27388, 908 0x27400, 0x27404, 909 0x27500, 0x27518, 910 0x2752c, 0x2753c, 911 0x27550, 0x27554, 912 0x27600, 0x27600, 913 0x27608, 0x27628, 914 0x27630, 0x2763c, 915 0x27700, 0x2771c, 916 0x27780, 0x2778c, 917 0x27800, 0x27c38, 918 0x27c80, 0x27d7c, 919 0x27e00, 0x27e04, 920 }; 921 922 static const unsigned int t5_reg_ranges[] = { 923 0x1008, 0x1148, 924 0x1180, 0x11b4, 925 0x11fc, 0x123c, 926 0x1280, 0x173c, 927 0x1800, 0x18fc, 928 0x3000, 0x3028, 929 0x3068, 0x30d8, 930 0x30e0, 0x30fc, 931 0x3140, 0x357c, 932 0x35a8, 0x35cc, 933 0x35ec, 0x35ec, 934 0x3600, 0x5624, 935 0x56cc, 0x575c, 936 0x580c, 0x5814, 937 0x5890, 0x58bc, 938 0x5940, 0x59dc, 939 0x59fc, 0x5a18, 940 0x5a60, 0x5a9c, 941 0x5b94, 0x5bfc, 942 0x6000, 0x6040, 943 0x6058, 0x614c, 944 0x7700, 0x7798, 945 0x77c0, 0x78fc, 946 0x7b00, 0x7c54, 947 0x7d00, 0x7efc, 948 0x8dc0, 0x8de0, 949 0x8df8, 0x8e84, 950 0x8ea0, 0x8f84, 951 0x8fc0, 0x90f8, 952 0x9400, 0x9470, 953 0x9600, 0x96f4, 954 0x9800, 0x9808, 955 0x9820, 0x983c, 956 0x9850, 0x9864, 957 0x9c00, 0x9c6c, 958 0x9c80, 0x9cec, 959 0x9d00, 0x9d6c, 960 0x9d80, 0x9dec, 961 0x9e00, 0x9e6c, 962 0x9e80, 0x9eec, 963 0x9f00, 0x9f6c, 964 0x9f80, 0xa020, 965 0xd004, 0xd03c, 966 0xdfc0, 0xdfe0, 967 0xe000, 0x11088, 968 0x1109c, 0x11110, 969 0x11118, 0x1117c, 970 0x11190, 0x11204, 971 0x19040, 0x1906c, 972 0x19078, 0x19080, 973 0x1908c, 0x19124, 974 0x19150, 0x191b0, 975 0x191d0, 0x191e8, 976 0x19238, 0x19290, 977 0x193f8, 0x19474, 978 0x19490, 0x194cc, 979 0x194f0, 0x194f8, 980 0x19c00, 0x19c60, 981 0x19c94, 0x19e10, 982 0x19e50, 0x19f34, 983 0x19f40, 0x19f50, 984 0x19f90, 0x19fe4, 985 0x1a000, 0x1a06c, 986 0x1a0b0, 0x1a120, 987 0x1a128, 0x1a138, 988 0x1a190, 0x1a1c4, 989 0x1a1fc, 0x1a1fc, 990 0x1e008, 0x1e00c, 991 0x1e040, 0x1e04c, 992 0x1e284, 0x1e290, 993 0x1e2c0, 0x1e2c0, 994 0x1e2e0, 0x1e2e0, 995 0x1e300, 0x1e384, 996 0x1e3c0, 0x1e3c8, 997 0x1e408, 0x1e40c, 998 0x1e440, 0x1e44c, 999 0x1e684, 0x1e690, 1000 0x1e6c0, 0x1e6c0, 1001 0x1e6e0, 0x1e6e0, 1002 0x1e700, 0x1e784, 1003 0x1e7c0, 0x1e7c8, 1004 0x1e808, 0x1e80c, 1005 0x1e840, 0x1e84c, 1006 0x1ea84, 0x1ea90, 1007 0x1eac0, 0x1eac0, 1008 0x1eae0, 0x1eae0, 1009 0x1eb00, 0x1eb84, 1010 0x1ebc0, 0x1ebc8, 1011 0x1ec08, 0x1ec0c, 1012 0x1ec40, 0x1ec4c, 1013 0x1ee84, 0x1ee90, 1014 0x1eec0, 0x1eec0, 1015 0x1eee0, 0x1eee0, 1016 0x1ef00, 0x1ef84, 1017 0x1efc0, 0x1efc8, 1018 0x1f008, 0x1f00c, 1019 0x1f040, 0x1f04c, 1020 0x1f284, 0x1f290, 1021 0x1f2c0, 0x1f2c0, 1022 0x1f2e0, 0x1f2e0, 1023 0x1f300, 0x1f384, 1024 0x1f3c0, 0x1f3c8, 1025 0x1f408, 0x1f40c, 1026 0x1f440, 0x1f44c, 1027 0x1f684, 0x1f690, 1028 0x1f6c0, 0x1f6c0, 1029 0x1f6e0, 0x1f6e0, 1030 0x1f700, 0x1f784, 1031 0x1f7c0, 0x1f7c8, 1032 0x1f808, 0x1f80c, 1033 0x1f840, 0x1f84c, 1034 0x1fa84, 0x1fa90, 1035 0x1fac0, 0x1fac0, 1036 0x1fae0, 0x1fae0, 1037 0x1fb00, 0x1fb84, 1038 0x1fbc0, 0x1fbc8, 1039 0x1fc08, 0x1fc0c, 1040 0x1fc40, 0x1fc4c, 1041 0x1fe84, 0x1fe90, 1042 0x1fec0, 0x1fec0, 1043 0x1fee0, 0x1fee0, 1044 0x1ff00, 0x1ff84, 1045 0x1ffc0, 0x1ffc8, 1046 0x30000, 0x30030, 1047 0x30100, 0x30144, 1048 0x30190, 0x301d0, 1049 0x30200, 0x30318, 1050 0x30400, 0x3052c, 1051 0x30540, 0x3061c, 1052 0x30800, 0x30834, 1053 0x308c0, 0x30908, 1054 0x30910, 0x309ac, 1055 0x30a00, 0x30a2c, 1056 0x30a44, 0x30a50, 1057 0x30a74, 0x30c24, 1058 0x30d00, 0x30d00, 1059 0x30d08, 0x30d14, 1060 0x30d1c, 0x30d20, 1061 0x30d3c, 0x30d50, 1062 0x31200, 0x3120c, 1063 0x31220, 0x31220, 1064 0x31240, 0x31240, 1065 0x31600, 0x3160c, 1066 0x31a00, 0x31a1c, 1067 0x31e00, 0x31e20, 1068 0x31e38, 0x31e3c, 1069 0x31e80, 0x31e80, 1070 0x31e88, 0x31ea8, 1071 0x31eb0, 0x31eb4, 1072 0x31ec8, 0x31ed4, 1073 0x31fb8, 0x32004, 1074 0x32200, 0x32200, 1075 0x32208, 0x32240, 1076 0x32248, 0x32280, 1077 0x32288, 0x322c0, 1078 0x322c8, 0x322fc, 1079 0x32600, 0x32630, 1080 0x32a00, 0x32abc, 1081 0x32b00, 0x32b70, 1082 0x33000, 0x33048, 1083 0x33060, 0x3309c, 1084 0x330f0, 0x33148, 1085 0x33160, 0x3319c, 1086 0x331f0, 0x332e4, 1087 0x332f8, 0x333e4, 1088 0x333f8, 0x33448, 1089 0x33460, 0x3349c, 1090 0x334f0, 0x33548, 1091 0x33560, 0x3359c, 1092 0x335f0, 0x336e4, 1093 0x336f8, 0x337e4, 1094 0x337f8, 0x337fc, 1095 0x33814, 0x33814, 1096 0x3382c, 0x3382c, 1097 0x33880, 0x3388c, 1098 0x338e8, 0x338ec, 1099 0x33900, 0x33948, 1100 0x33960, 0x3399c, 1101 0x339f0, 0x33ae4, 1102 0x33af8, 0x33b10, 1103 0x33b28, 0x33b28, 1104 0x33b3c, 0x33b50, 1105 0x33bf0, 0x33c10, 1106 0x33c28, 0x33c28, 1107 0x33c3c, 0x33c50, 1108 0x33cf0, 0x33cfc, 1109 0x34000, 0x34030, 1110 0x34100, 0x34144, 1111 0x34190, 0x341d0, 1112 0x34200, 0x34318, 1113 0x34400, 0x3452c, 1114 0x34540, 0x3461c, 1115 0x34800, 0x34834, 1116 0x348c0, 0x34908, 1117 0x34910, 0x349ac, 1118 0x34a00, 0x34a2c, 1119 0x34a44, 0x34a50, 1120 0x34a74, 0x34c24, 1121 0x34d00, 0x34d00, 1122 0x34d08, 0x34d14, 1123 0x34d1c, 0x34d20, 1124 0x34d3c, 0x34d50, 1125 0x35200, 0x3520c, 1126 0x35220, 0x35220, 1127 0x35240, 0x35240, 1128 0x35600, 0x3560c, 1129 0x35a00, 0x35a1c, 1130 0x35e00, 0x35e20, 1131 0x35e38, 0x35e3c, 1132 0x35e80, 0x35e80, 1133 0x35e88, 0x35ea8, 1134 0x35eb0, 0x35eb4, 1135 0x35ec8, 0x35ed4, 1136 0x35fb8, 0x36004, 1137 0x36200, 0x36200, 1138 0x36208, 0x36240, 1139 0x36248, 0x36280, 1140 0x36288, 0x362c0, 1141 0x362c8, 0x362fc, 1142 0x36600, 0x36630, 1143 0x36a00, 0x36abc, 1144 0x36b00, 0x36b70, 1145 0x37000, 0x37048, 1146 0x37060, 0x3709c, 1147 0x370f0, 0x37148, 1148 0x37160, 0x3719c, 1149 0x371f0, 0x372e4, 1150 0x372f8, 0x373e4, 1151 0x373f8, 0x37448, 1152 0x37460, 0x3749c, 1153 0x374f0, 0x37548, 1154 0x37560, 0x3759c, 1155 0x375f0, 0x376e4, 1156 0x376f8, 0x377e4, 1157 0x377f8, 0x377fc, 1158 0x37814, 0x37814, 1159 0x3782c, 0x3782c, 1160 0x37880, 0x3788c, 1161 0x378e8, 0x378ec, 1162 0x37900, 0x37948, 1163 0x37960, 0x3799c, 1164 0x379f0, 0x37ae4, 1165 0x37af8, 0x37b10, 1166 0x37b28, 0x37b28, 1167 0x37b3c, 0x37b50, 1168 0x37bf0, 0x37c10, 1169 0x37c28, 0x37c28, 1170 0x37c3c, 0x37c50, 1171 0x37cf0, 0x37cfc, 1172 0x38000, 0x38030, 1173 0x38100, 0x38144, 1174 0x38190, 0x381d0, 1175 0x38200, 0x38318, 1176 0x38400, 0x3852c, 1177 0x38540, 0x3861c, 1178 0x38800, 0x38834, 1179 0x388c0, 0x38908, 1180 0x38910, 0x389ac, 1181 0x38a00, 0x38a2c, 1182 0x38a44, 0x38a50, 1183 0x38a74, 0x38c24, 1184 0x38d00, 0x38d00, 1185 0x38d08, 0x38d14, 1186 0x38d1c, 0x38d20, 1187 0x38d3c, 0x38d50, 1188 0x39200, 0x3920c, 1189 0x39220, 0x39220, 1190 0x39240, 0x39240, 1191 0x39600, 0x3960c, 1192 0x39a00, 0x39a1c, 1193 0x39e00, 0x39e20, 1194 0x39e38, 0x39e3c, 1195 0x39e80, 0x39e80, 1196 0x39e88, 0x39ea8, 1197 0x39eb0, 0x39eb4, 1198 0x39ec8, 0x39ed4, 1199 0x39fb8, 0x3a004, 1200 0x3a200, 0x3a200, 1201 0x3a208, 0x3a240, 1202 0x3a248, 0x3a280, 1203 0x3a288, 0x3a2c0, 1204 0x3a2c8, 0x3a2fc, 1205 0x3a600, 0x3a630, 1206 0x3aa00, 0x3aabc, 1207 0x3ab00, 0x3ab70, 1208 0x3b000, 0x3b048, 1209 0x3b060, 0x3b09c, 1210 0x3b0f0, 0x3b148, 1211 0x3b160, 0x3b19c, 1212 0x3b1f0, 0x3b2e4, 1213 0x3b2f8, 0x3b3e4, 1214 0x3b3f8, 0x3b448, 1215 0x3b460, 0x3b49c, 1216 0x3b4f0, 0x3b548, 1217 0x3b560, 0x3b59c, 1218 0x3b5f0, 0x3b6e4, 1219 0x3b6f8, 0x3b7e4, 1220 0x3b7f8, 0x3b7fc, 1221 0x3b814, 0x3b814, 1222 0x3b82c, 0x3b82c, 1223 0x3b880, 0x3b88c, 1224 0x3b8e8, 0x3b8ec, 1225 0x3b900, 0x3b948, 1226 0x3b960, 0x3b99c, 1227 0x3b9f0, 0x3bae4, 1228 0x3baf8, 0x3bb10, 1229 0x3bb28, 0x3bb28, 1230 0x3bb3c, 0x3bb50, 1231 0x3bbf0, 0x3bc10, 1232 0x3bc28, 0x3bc28, 1233 0x3bc3c, 0x3bc50, 1234 0x3bcf0, 0x3bcfc, 1235 0x3c000, 0x3c030, 1236 0x3c100, 0x3c144, 1237 0x3c190, 0x3c1d0, 1238 0x3c200, 0x3c318, 1239 0x3c400, 0x3c52c, 1240 0x3c540, 0x3c61c, 1241 0x3c800, 0x3c834, 1242 0x3c8c0, 0x3c908, 1243 0x3c910, 0x3c9ac, 1244 0x3ca00, 0x3ca2c, 1245 0x3ca44, 0x3ca50, 1246 0x3ca74, 0x3cc24, 1247 0x3cd00, 0x3cd00, 1248 0x3cd08, 0x3cd14, 1249 0x3cd1c, 0x3cd20, 1250 0x3cd3c, 0x3cd50, 1251 0x3d200, 0x3d20c, 1252 0x3d220, 0x3d220, 1253 0x3d240, 0x3d240, 1254 0x3d600, 0x3d60c, 1255 0x3da00, 0x3da1c, 1256 0x3de00, 0x3de20, 1257 0x3de38, 0x3de3c, 1258 0x3de80, 0x3de80, 1259 0x3de88, 0x3dea8, 1260 0x3deb0, 0x3deb4, 1261 0x3dec8, 0x3ded4, 1262 0x3dfb8, 0x3e004, 1263 0x3e200, 0x3e200, 1264 0x3e208, 0x3e240, 1265 0x3e248, 0x3e280, 1266 0x3e288, 0x3e2c0, 1267 0x3e2c8, 0x3e2fc, 1268 0x3e600, 0x3e630, 1269 0x3ea00, 0x3eabc, 1270 0x3eb00, 0x3eb70, 1271 0x3f000, 0x3f048, 1272 0x3f060, 0x3f09c, 1273 0x3f0f0, 0x3f148, 1274 0x3f160, 0x3f19c, 1275 0x3f1f0, 0x3f2e4, 1276 0x3f2f8, 0x3f3e4, 1277 0x3f3f8, 0x3f448, 1278 0x3f460, 0x3f49c, 1279 0x3f4f0, 0x3f548, 1280 0x3f560, 0x3f59c, 1281 0x3f5f0, 0x3f6e4, 1282 0x3f6f8, 0x3f7e4, 1283 0x3f7f8, 0x3f7fc, 1284 0x3f814, 0x3f814, 1285 0x3f82c, 0x3f82c, 1286 0x3f880, 0x3f88c, 1287 0x3f8e8, 0x3f8ec, 1288 0x3f900, 0x3f948, 1289 0x3f960, 0x3f99c, 1290 0x3f9f0, 0x3fae4, 1291 0x3faf8, 0x3fb10, 1292 0x3fb28, 0x3fb28, 1293 0x3fb3c, 0x3fb50, 1294 0x3fbf0, 0x3fc10, 1295 0x3fc28, 0x3fc28, 1296 0x3fc3c, 0x3fc50, 1297 0x3fcf0, 0x3fcfc, 1298 0x40000, 0x4000c, 1299 0x40040, 0x40068, 1300 0x4007c, 0x40144, 1301 0x40180, 0x4018c, 1302 0x40200, 0x40298, 1303 0x402ac, 0x4033c, 1304 0x403f8, 0x403fc, 1305 0x41304, 0x413c4, 1306 0x41400, 0x4141c, 1307 0x41480, 0x414d0, 1308 0x44000, 0x44078, 1309 0x440c0, 0x44278, 1310 0x442c0, 0x44478, 1311 0x444c0, 0x44678, 1312 0x446c0, 0x44878, 1313 0x448c0, 0x449fc, 1314 0x45000, 0x45068, 1315 0x45080, 0x45084, 1316 0x450a0, 0x450b0, 1317 0x45200, 0x45268, 1318 0x45280, 0x45284, 1319 0x452a0, 0x452b0, 1320 0x460c0, 0x460e4, 1321 0x47000, 0x4708c, 1322 0x47200, 0x47250, 1323 0x47400, 0x47420, 1324 0x47600, 0x47618, 1325 0x47800, 0x47814, 1326 0x48000, 0x4800c, 1327 0x48040, 0x48068, 1328 0x4807c, 0x48144, 1329 0x48180, 0x4818c, 1330 0x48200, 0x48298, 1331 0x482ac, 0x4833c, 1332 0x483f8, 0x483fc, 1333 0x49304, 0x493c4, 1334 0x49400, 0x4941c, 1335 0x49480, 0x494d0, 1336 0x4c000, 0x4c078, 1337 0x4c0c0, 0x4c278, 1338 0x4c2c0, 0x4c478, 1339 0x4c4c0, 0x4c678, 1340 0x4c6c0, 0x4c878, 1341 0x4c8c0, 0x4c9fc, 1342 0x4d000, 0x4d068, 1343 0x4d080, 0x4d084, 1344 0x4d0a0, 0x4d0b0, 1345 0x4d200, 0x4d268, 1346 0x4d280, 0x4d284, 1347 0x4d2a0, 0x4d2b0, 1348 0x4e0c0, 0x4e0e4, 1349 0x4f000, 0x4f08c, 1350 0x4f200, 0x4f250, 1351 0x4f400, 0x4f420, 1352 0x4f600, 0x4f618, 1353 0x4f800, 0x4f814, 1354 0x50000, 0x500cc, 1355 0x50400, 0x50400, 1356 0x50800, 0x508cc, 1357 0x50c00, 0x50c00, 1358 0x51000, 0x5101c, 1359 0x51300, 0x51308, 1360 }; 1361 1362 static const unsigned int t6_reg_ranges[] = { 1363 0x1008, 0x1124, 1364 0x1138, 0x114c, 1365 0x1180, 0x11b4, 1366 0x11fc, 0x1254, 1367 0x1280, 0x133c, 1368 0x1800, 0x18fc, 1369 0x3000, 0x302c, 1370 0x3060, 0x30d8, 1371 0x30e0, 0x30fc, 1372 0x3140, 0x357c, 1373 0x35a8, 0x35cc, 1374 0x35ec, 0x35ec, 1375 0x3600, 0x5624, 1376 0x56cc, 0x575c, 1377 0x580c, 0x5814, 1378 0x5890, 0x58bc, 1379 0x5940, 0x595c, 1380 0x5980, 0x598c, 1381 0x59b0, 0x59dc, 1382 0x59fc, 0x5a18, 1383 0x5a60, 0x5a6c, 1384 0x5a80, 0x5a9c, 1385 0x5b94, 0x5bfc, 1386 0x5c10, 0x5ec0, 1387 0x5ec8, 0x5ecc, 1388 0x6000, 0x6040, 1389 0x6058, 0x619c, 1390 0x7700, 0x7798, 1391 0x77c0, 0x7880, 1392 0x78cc, 0x78fc, 1393 0x7b00, 0x7c54, 1394 0x7d00, 0x7efc, 1395 0x8dc0, 0x8de4, 1396 0x8df8, 0x8e84, 1397 0x8ea0, 0x8f88, 1398 0x8fb8, 0x9124, 1399 0x9400, 0x9470, 1400 0x9600, 0x971c, 1401 0x9800, 0x9808, 1402 0x9820, 0x983c, 1403 0x9850, 0x9864, 1404 0x9c00, 0x9c6c, 1405 0x9c80, 0x9cec, 1406 0x9d00, 0x9d6c, 1407 0x9d80, 0x9dec, 1408 0x9e00, 0x9e6c, 1409 0x9e80, 0x9eec, 1410 0x9f00, 0x9f6c, 1411 0x9f80, 0xa020, 1412 0xd004, 0xd03c, 1413 0xd100, 0xd118, 1414 0xd200, 0xd31c, 1415 0xdfc0, 0xdfe0, 1416 0xe000, 0xf008, 1417 0x11000, 0x11014, 1418 0x11048, 0x1117c, 1419 0x11190, 0x11270, 1420 0x11300, 0x1130c, 1421 0x12000, 0x1206c, 1422 0x19040, 0x1906c, 1423 0x19078, 0x19080, 1424 0x1908c, 0x19124, 1425 0x19150, 0x191b0, 1426 0x191d0, 0x191e8, 1427 0x19238, 0x192bc, 1428 0x193f8, 0x19474, 1429 0x19490, 0x194cc, 1430 0x194f0, 0x194f8, 1431 0x19c00, 0x19c80, 1432 0x19c94, 0x19cbc, 1433 0x19ce4, 0x19d28, 1434 0x19d50, 0x19d78, 1435 0x19d94, 0x19dc8, 1436 0x19df0, 0x19e10, 1437 0x19e50, 0x19e6c, 1438 0x19ea0, 0x19f34, 1439 0x19f40, 0x19f50, 1440 0x19f90, 0x19fac, 1441 0x19fc4, 0x19fe4, 1442 0x1a000, 0x1a06c, 1443 0x1a0b0, 0x1a120, 1444 0x1a128, 0x1a138, 1445 0x1a190, 0x1a1c4, 1446 0x1a1fc, 0x1a1fc, 1447 0x1e008, 0x1e00c, 1448 0x1e040, 0x1e04c, 1449 0x1e284, 0x1e290, 1450 0x1e2c0, 0x1e2c0, 1451 0x1e2e0, 0x1e2e0, 1452 0x1e300, 0x1e384, 1453 0x1e3c0, 0x1e3c8, 1454 0x1e408, 0x1e40c, 1455 0x1e440, 0x1e44c, 1456 0x1e684, 0x1e690, 1457 0x1e6c0, 0x1e6c0, 1458 0x1e6e0, 0x1e6e0, 1459 0x1e700, 0x1e784, 1460 0x1e7c0, 0x1e7c8, 1461 0x1e808, 0x1e80c, 1462 0x1e840, 0x1e84c, 1463 0x1ea84, 0x1ea90, 1464 0x1eac0, 0x1eac0, 1465 0x1eae0, 0x1eae0, 1466 0x1eb00, 0x1eb84, 1467 0x1ebc0, 0x1ebc8, 1468 0x1ec08, 0x1ec0c, 1469 0x1ec40, 0x1ec4c, 1470 0x1ee84, 0x1ee90, 1471 0x1eec0, 0x1eec0, 1472 0x1eee0, 0x1eee0, 1473 0x1ef00, 0x1ef84, 1474 0x1efc0, 0x1efc8, 1475 0x1f008, 0x1f00c, 1476 0x1f040, 0x1f04c, 1477 0x1f284, 0x1f290, 1478 0x1f2c0, 0x1f2c0, 1479 0x1f2e0, 0x1f2e0, 1480 0x1f300, 0x1f384, 1481 0x1f3c0, 0x1f3c8, 1482 0x1f408, 0x1f40c, 1483 0x1f440, 0x1f44c, 1484 0x1f684, 0x1f690, 1485 0x1f6c0, 0x1f6c0, 1486 0x1f6e0, 0x1f6e0, 1487 0x1f700, 0x1f784, 1488 0x1f7c0, 0x1f7c8, 1489 0x1f808, 0x1f80c, 1490 0x1f840, 0x1f84c, 1491 0x1fa84, 0x1fa90, 1492 0x1fac0, 0x1fac0, 1493 0x1fae0, 0x1fae0, 1494 0x1fb00, 0x1fb84, 1495 0x1fbc0, 0x1fbc8, 1496 0x1fc08, 0x1fc0c, 1497 0x1fc40, 0x1fc4c, 1498 0x1fe84, 0x1fe90, 1499 0x1fec0, 0x1fec0, 1500 0x1fee0, 0x1fee0, 1501 0x1ff00, 0x1ff84, 1502 0x1ffc0, 0x1ffc8, 1503 0x30000, 0x30070, 1504 0x30100, 0x301d0, 1505 0x30200, 0x30320, 1506 0x30400, 0x3052c, 1507 0x30540, 0x3061c, 1508 0x30800, 0x30890, 1509 0x308c0, 0x30908, 1510 0x30910, 0x309b8, 1511 0x30a00, 0x30a04, 1512 0x30a0c, 0x30a2c, 1513 0x30a44, 0x30a50, 1514 0x30a74, 0x30c24, 1515 0x30d00, 0x30d3c, 1516 0x30d44, 0x30d7c, 1517 0x30de0, 0x30de0, 1518 0x30e00, 0x30ed4, 1519 0x30f00, 0x30fa4, 1520 0x30fc0, 0x30fc4, 1521 0x31000, 0x31004, 1522 0x31080, 0x310fc, 1523 0x31208, 0x31220, 1524 0x3123c, 0x31254, 1525 0x31300, 0x31300, 1526 0x31308, 0x3131c, 1527 0x31338, 0x3133c, 1528 0x31380, 0x31380, 1529 0x31388, 0x313a8, 1530 0x313b4, 0x313b4, 1531 0x31400, 0x31420, 1532 0x31438, 0x3143c, 1533 0x31480, 0x31480, 1534 0x314a8, 0x314a8, 1535 0x314b0, 0x314b4, 1536 0x314c8, 0x314d4, 1537 0x31a40, 0x31a4c, 1538 0x31af0, 0x31b20, 1539 0x31b38, 0x31b3c, 1540 0x31b80, 0x31b80, 1541 0x31ba8, 0x31ba8, 1542 0x31bb0, 0x31bb4, 1543 0x31bc8, 0x31bd4, 1544 0x32140, 0x3218c, 1545 0x321f0, 0x32200, 1546 0x32218, 0x32218, 1547 0x32400, 0x32400, 1548 0x32408, 0x3241c, 1549 0x32618, 0x32620, 1550 0x32664, 0x32664, 1551 0x326a8, 0x326a8, 1552 0x326ec, 0x326ec, 1553 0x32a00, 0x32abc, 1554 0x32b00, 0x32b78, 1555 0x32c00, 0x32c00, 1556 0x32c08, 0x32c3c, 1557 0x32e00, 0x32e2c, 1558 0x32f00, 0x32f2c, 1559 0x33000, 0x330ac, 1560 0x330c0, 0x331ac, 1561 0x331c0, 0x332c4, 1562 0x332e4, 0x333c4, 1563 0x333e4, 0x334ac, 1564 0x334c0, 0x335ac, 1565 0x335c0, 0x336c4, 1566 0x336e4, 0x337c4, 1567 0x337e4, 0x337fc, 1568 0x33814, 0x33814, 1569 0x33854, 0x33868, 1570 0x33880, 0x3388c, 1571 0x338c0, 0x338d0, 1572 0x338e8, 0x338ec, 1573 0x33900, 0x339ac, 1574 0x339c0, 0x33ac4, 1575 0x33ae4, 0x33b10, 1576 0x33b24, 0x33b50, 1577 0x33bf0, 0x33c10, 1578 0x33c24, 0x33c50, 1579 0x33cf0, 0x33cfc, 1580 0x34000, 0x34070, 1581 0x34100, 0x341d0, 1582 0x34200, 0x34320, 1583 0x34400, 0x3452c, 1584 0x34540, 0x3461c, 1585 0x34800, 0x34890, 1586 0x348c0, 0x34908, 1587 0x34910, 0x349b8, 1588 0x34a00, 0x34a04, 1589 0x34a0c, 0x34a2c, 1590 0x34a44, 0x34a50, 1591 0x34a74, 0x34c24, 1592 0x34d00, 0x34d3c, 1593 0x34d44, 0x34d7c, 1594 0x34de0, 0x34de0, 1595 0x34e00, 0x34ed4, 1596 0x34f00, 0x34fa4, 1597 0x34fc0, 0x34fc4, 1598 0x35000, 0x35004, 1599 0x35080, 0x350fc, 1600 0x35208, 0x35220, 1601 0x3523c, 0x35254, 1602 0x35300, 0x35300, 1603 0x35308, 0x3531c, 1604 0x35338, 0x3533c, 1605 0x35380, 0x35380, 1606 0x35388, 0x353a8, 1607 0x353b4, 0x353b4, 1608 0x35400, 0x35420, 1609 0x35438, 0x3543c, 1610 0x35480, 0x35480, 1611 0x354a8, 0x354a8, 1612 0x354b0, 0x354b4, 1613 0x354c8, 0x354d4, 1614 0x35a40, 0x35a4c, 1615 0x35af0, 0x35b20, 1616 0x35b38, 0x35b3c, 1617 0x35b80, 0x35b80, 1618 0x35ba8, 0x35ba8, 1619 0x35bb0, 0x35bb4, 1620 0x35bc8, 0x35bd4, 1621 0x36140, 0x3618c, 1622 0x361f0, 0x36200, 1623 0x36218, 0x36218, 1624 0x36400, 0x36400, 1625 0x36408, 0x3641c, 1626 0x36618, 0x36620, 1627 0x36664, 0x36664, 1628 0x366a8, 0x366a8, 1629 0x366ec, 0x366ec, 1630 0x36a00, 0x36abc, 1631 0x36b00, 0x36b78, 1632 0x36c00, 0x36c00, 1633 0x36c08, 0x36c3c, 1634 0x36e00, 0x36e2c, 1635 0x36f00, 0x36f2c, 1636 0x37000, 0x370ac, 1637 0x370c0, 0x371ac, 1638 0x371c0, 0x372c4, 1639 0x372e4, 0x373c4, 1640 0x373e4, 0x374ac, 1641 0x374c0, 0x375ac, 1642 0x375c0, 0x376c4, 1643 0x376e4, 0x377c4, 1644 0x377e4, 0x377fc, 1645 0x37814, 0x37814, 1646 0x37854, 0x37868, 1647 0x37880, 0x3788c, 1648 0x378c0, 0x378d0, 1649 0x378e8, 0x378ec, 1650 0x37900, 0x379ac, 1651 0x379c0, 0x37ac4, 1652 0x37ae4, 0x37b10, 1653 0x37b24, 0x37b50, 1654 0x37bf0, 0x37c10, 1655 0x37c24, 0x37c50, 1656 0x37cf0, 0x37cfc, 1657 0x40040, 0x40040, 1658 0x40080, 0x40084, 1659 0x40100, 0x40100, 1660 0x40140, 0x401bc, 1661 0x40200, 0x40214, 1662 0x40228, 0x40228, 1663 0x40240, 0x40258, 1664 0x40280, 0x40280, 1665 0x40304, 0x40304, 1666 0x40330, 0x4033c, 1667 0x41304, 0x413dc, 1668 0x41400, 0x4141c, 1669 0x41480, 0x414d0, 1670 0x44000, 0x4407c, 1671 0x440c0, 0x4427c, 1672 0x442c0, 0x4447c, 1673 0x444c0, 0x4467c, 1674 0x446c0, 0x4487c, 1675 0x448c0, 0x44a7c, 1676 0x44ac0, 0x44c7c, 1677 0x44cc0, 0x44e7c, 1678 0x44ec0, 0x4507c, 1679 0x450c0, 0x451fc, 1680 0x45800, 0x45868, 1681 0x45880, 0x45884, 1682 0x458a0, 0x458b0, 1683 0x45a00, 0x45a68, 1684 0x45a80, 0x45a84, 1685 0x45aa0, 0x45ab0, 1686 0x460c0, 0x460e4, 1687 0x47000, 0x4708c, 1688 0x47200, 0x47250, 1689 0x47400, 0x47420, 1690 0x47600, 0x47618, 1691 0x47800, 0x4782c, 1692 0x50000, 0x500cc, 1693 0x50400, 0x50400, 1694 0x50800, 0x508cc, 1695 0x50c00, 0x50c00, 1696 0x51000, 0x510b0, 1697 0x51300, 0x51324, 1698 }; 1699 1700 u32 *buf_end = (u32 *)((char *)buf + buf_size); 1701 const unsigned int *reg_ranges; 1702 int reg_ranges_size, range; 1703 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip); 1704 1705 /* Select the right set of register ranges to dump depending on the 1706 * adapter chip type. 1707 */ 1708 switch (chip_version) { 1709 case CHELSIO_T4: 1710 reg_ranges = t4_reg_ranges; 1711 reg_ranges_size = ARRAY_SIZE(t4_reg_ranges); 1712 break; 1713 1714 case CHELSIO_T5: 1715 reg_ranges = t5_reg_ranges; 1716 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges); 1717 break; 1718 1719 case CHELSIO_T6: 1720 reg_ranges = t6_reg_ranges; 1721 reg_ranges_size = ARRAY_SIZE(t6_reg_ranges); 1722 break; 1723 1724 default: 1725 dev_err(adap->pdev_dev, 1726 "Unsupported chip version %d\n", chip_version); 1727 return; 1728 } 1729 1730 /* Clear the register buffer and insert the appropriate register 1731 * values selected by the above register ranges. 1732 */ 1733 memset(buf, 0, buf_size); 1734 for (range = 0; range < reg_ranges_size; range += 2) { 1735 unsigned int reg = reg_ranges[range]; 1736 unsigned int last_reg = reg_ranges[range + 1]; 1737 u32 *bufp = (u32 *)((char *)buf + reg); 1738 1739 /* Iterate across the register range filling in the register 1740 * buffer but don't write past the end of the register buffer. 1741 */ 1742 while (reg <= last_reg && bufp < buf_end) { 1743 *bufp++ = t4_read_reg(adap, reg); 1744 reg += sizeof(u32); 1745 } 1746 } 1747 } 1748 1749 #define EEPROM_STAT_ADDR 0x7bfc 1750 #define VPD_BASE 0x400 1751 #define VPD_BASE_OLD 0 1752 #define VPD_LEN 1024 1753 #define CHELSIO_VPD_UNIQUE_ID 0x82 1754 1755 /** 1756 * t4_seeprom_wp - enable/disable EEPROM write protection 1757 * @adapter: the adapter 1758 * @enable: whether to enable or disable write protection 1759 * 1760 * Enables or disables write protection on the serial EEPROM. 1761 */ 1762 int t4_seeprom_wp(struct adapter *adapter, bool enable) 1763 { 1764 unsigned int v = enable ? 0xc : 0; 1765 int ret = pci_write_vpd(adapter->pdev, EEPROM_STAT_ADDR, 4, &v); 1766 return ret < 0 ? ret : 0; 1767 } 1768 1769 /** 1770 * t4_get_raw_vpd_params - read VPD parameters from VPD EEPROM 1771 * @adapter: adapter to read 1772 * @p: where to store the parameters 1773 * 1774 * Reads card parameters stored in VPD EEPROM. 1775 */ 1776 int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p) 1777 { 1778 int i, ret = 0, addr; 1779 int ec, sn, pn, na; 1780 u8 *vpd, csum; 1781 unsigned int vpdr_len, kw_offset, id_len; 1782 1783 vpd = vmalloc(VPD_LEN); 1784 if (!vpd) 1785 return -ENOMEM; 1786 1787 /* Card information normally starts at VPD_BASE but early cards had 1788 * it at 0. 1789 */ 1790 ret = pci_read_vpd(adapter->pdev, VPD_BASE, sizeof(u32), vpd); 1791 if (ret < 0) 1792 goto out; 1793 1794 /* The VPD shall have a unique identifier specified by the PCI SIG. 1795 * For chelsio adapters, the identifier is 0x82. The first byte of a VPD 1796 * shall be CHELSIO_VPD_UNIQUE_ID (0x82). The VPD programming software 1797 * is expected to automatically put this entry at the 1798 * beginning of the VPD. 1799 */ 1800 addr = *vpd == CHELSIO_VPD_UNIQUE_ID ? VPD_BASE : VPD_BASE_OLD; 1801 1802 ret = pci_read_vpd(adapter->pdev, addr, VPD_LEN, vpd); 1803 if (ret < 0) 1804 goto out; 1805 1806 if (vpd[0] != PCI_VPD_LRDT_ID_STRING) { 1807 dev_err(adapter->pdev_dev, "missing VPD ID string\n"); 1808 ret = -EINVAL; 1809 goto out; 1810 } 1811 1812 id_len = pci_vpd_lrdt_size(vpd); 1813 if (id_len > ID_LEN) 1814 id_len = ID_LEN; 1815 1816 i = pci_vpd_find_tag(vpd, 0, VPD_LEN, PCI_VPD_LRDT_RO_DATA); 1817 if (i < 0) { 1818 dev_err(adapter->pdev_dev, "missing VPD-R section\n"); 1819 ret = -EINVAL; 1820 goto out; 1821 } 1822 1823 vpdr_len = pci_vpd_lrdt_size(&vpd[i]); 1824 kw_offset = i + PCI_VPD_LRDT_TAG_SIZE; 1825 if (vpdr_len + kw_offset > VPD_LEN) { 1826 dev_err(adapter->pdev_dev, "bad VPD-R length %u\n", vpdr_len); 1827 ret = -EINVAL; 1828 goto out; 1829 } 1830 1831 #define FIND_VPD_KW(var, name) do { \ 1832 var = pci_vpd_find_info_keyword(vpd, kw_offset, vpdr_len, name); \ 1833 if (var < 0) { \ 1834 dev_err(adapter->pdev_dev, "missing VPD keyword " name "\n"); \ 1835 ret = -EINVAL; \ 1836 goto out; \ 1837 } \ 1838 var += PCI_VPD_INFO_FLD_HDR_SIZE; \ 1839 } while (0) 1840 1841 FIND_VPD_KW(i, "RV"); 1842 for (csum = 0; i >= 0; i--) 1843 csum += vpd[i]; 1844 1845 if (csum) { 1846 dev_err(adapter->pdev_dev, 1847 "corrupted VPD EEPROM, actual csum %u\n", csum); 1848 ret = -EINVAL; 1849 goto out; 1850 } 1851 1852 FIND_VPD_KW(ec, "EC"); 1853 FIND_VPD_KW(sn, "SN"); 1854 FIND_VPD_KW(pn, "PN"); 1855 FIND_VPD_KW(na, "NA"); 1856 #undef FIND_VPD_KW 1857 1858 memcpy(p->id, vpd + PCI_VPD_LRDT_TAG_SIZE, id_len); 1859 strim(p->id); 1860 memcpy(p->ec, vpd + ec, EC_LEN); 1861 strim(p->ec); 1862 i = pci_vpd_info_field_size(vpd + sn - PCI_VPD_INFO_FLD_HDR_SIZE); 1863 memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN)); 1864 strim(p->sn); 1865 i = pci_vpd_info_field_size(vpd + pn - PCI_VPD_INFO_FLD_HDR_SIZE); 1866 memcpy(p->pn, vpd + pn, min(i, PN_LEN)); 1867 strim(p->pn); 1868 memcpy(p->na, vpd + na, min(i, MACADDR_LEN)); 1869 strim((char *)p->na); 1870 1871 out: 1872 vfree(vpd); 1873 return ret; 1874 } 1875 1876 /** 1877 * t4_get_vpd_params - read VPD parameters & retrieve Core Clock 1878 * @adapter: adapter to read 1879 * @p: where to store the parameters 1880 * 1881 * Reads card parameters stored in VPD EEPROM and retrieves the Core 1882 * Clock. This can only be called after a connection to the firmware 1883 * is established. 1884 */ 1885 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p) 1886 { 1887 u32 cclk_param, cclk_val; 1888 int ret; 1889 1890 /* Grab the raw VPD parameters. 1891 */ 1892 ret = t4_get_raw_vpd_params(adapter, p); 1893 if (ret) 1894 return ret; 1895 1896 /* Ask firmware for the Core Clock since it knows how to translate the 1897 * Reference Clock ('V2') VPD field into a Core Clock value ... 1898 */ 1899 cclk_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | 1900 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CCLK)); 1901 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0, 1902 1, &cclk_param, &cclk_val); 1903 1904 if (ret) 1905 return ret; 1906 p->cclk = cclk_val; 1907 1908 return 0; 1909 } 1910 1911 /* serial flash and firmware constants */ 1912 enum { 1913 SF_ATTEMPTS = 10, /* max retries for SF operations */ 1914 1915 /* flash command opcodes */ 1916 SF_PROG_PAGE = 2, /* program page */ 1917 SF_WR_DISABLE = 4, /* disable writes */ 1918 SF_RD_STATUS = 5, /* read status register */ 1919 SF_WR_ENABLE = 6, /* enable writes */ 1920 SF_RD_DATA_FAST = 0xb, /* read flash */ 1921 SF_RD_ID = 0x9f, /* read ID */ 1922 SF_ERASE_SECTOR = 0xd8, /* erase sector */ 1923 1924 FW_MAX_SIZE = 16 * SF_SEC_SIZE, 1925 }; 1926 1927 /** 1928 * sf1_read - read data from the serial flash 1929 * @adapter: the adapter 1930 * @byte_cnt: number of bytes to read 1931 * @cont: whether another operation will be chained 1932 * @lock: whether to lock SF for PL access only 1933 * @valp: where to store the read data 1934 * 1935 * Reads up to 4 bytes of data from the serial flash. The location of 1936 * the read needs to be specified prior to calling this by issuing the 1937 * appropriate commands to the serial flash. 1938 */ 1939 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont, 1940 int lock, u32 *valp) 1941 { 1942 int ret; 1943 1944 if (!byte_cnt || byte_cnt > 4) 1945 return -EINVAL; 1946 if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F) 1947 return -EBUSY; 1948 t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) | 1949 SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1)); 1950 ret = t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5); 1951 if (!ret) 1952 *valp = t4_read_reg(adapter, SF_DATA_A); 1953 return ret; 1954 } 1955 1956 /** 1957 * sf1_write - write data to the serial flash 1958 * @adapter: the adapter 1959 * @byte_cnt: number of bytes to write 1960 * @cont: whether another operation will be chained 1961 * @lock: whether to lock SF for PL access only 1962 * @val: value to write 1963 * 1964 * Writes up to 4 bytes of data to the serial flash. The location of 1965 * the write needs to be specified prior to calling this by issuing the 1966 * appropriate commands to the serial flash. 1967 */ 1968 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont, 1969 int lock, u32 val) 1970 { 1971 if (!byte_cnt || byte_cnt > 4) 1972 return -EINVAL; 1973 if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F) 1974 return -EBUSY; 1975 t4_write_reg(adapter, SF_DATA_A, val); 1976 t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) | 1977 SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1) | OP_V(1)); 1978 return t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5); 1979 } 1980 1981 /** 1982 * flash_wait_op - wait for a flash operation to complete 1983 * @adapter: the adapter 1984 * @attempts: max number of polls of the status register 1985 * @delay: delay between polls in ms 1986 * 1987 * Wait for a flash operation to complete by polling the status register. 1988 */ 1989 static int flash_wait_op(struct adapter *adapter, int attempts, int delay) 1990 { 1991 int ret; 1992 u32 status; 1993 1994 while (1) { 1995 if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 || 1996 (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0) 1997 return ret; 1998 if (!(status & 1)) 1999 return 0; 2000 if (--attempts == 0) 2001 return -EAGAIN; 2002 if (delay) 2003 msleep(delay); 2004 } 2005 } 2006 2007 /** 2008 * t4_read_flash - read words from serial flash 2009 * @adapter: the adapter 2010 * @addr: the start address for the read 2011 * @nwords: how many 32-bit words to read 2012 * @data: where to store the read data 2013 * @byte_oriented: whether to store data as bytes or as words 2014 * 2015 * Read the specified number of 32-bit words from the serial flash. 2016 * If @byte_oriented is set the read data is stored as a byte array 2017 * (i.e., big-endian), otherwise as 32-bit words in the platform's 2018 * natural endianness. 2019 */ 2020 int t4_read_flash(struct adapter *adapter, unsigned int addr, 2021 unsigned int nwords, u32 *data, int byte_oriented) 2022 { 2023 int ret; 2024 2025 if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3)) 2026 return -EINVAL; 2027 2028 addr = swab32(addr) | SF_RD_DATA_FAST; 2029 2030 if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 || 2031 (ret = sf1_read(adapter, 1, 1, 0, data)) != 0) 2032 return ret; 2033 2034 for ( ; nwords; nwords--, data++) { 2035 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data); 2036 if (nwords == 1) 2037 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */ 2038 if (ret) 2039 return ret; 2040 if (byte_oriented) 2041 *data = (__force __u32)(cpu_to_be32(*data)); 2042 } 2043 return 0; 2044 } 2045 2046 /** 2047 * t4_write_flash - write up to a page of data to the serial flash 2048 * @adapter: the adapter 2049 * @addr: the start address to write 2050 * @n: length of data to write in bytes 2051 * @data: the data to write 2052 * 2053 * Writes up to a page of data (256 bytes) to the serial flash starting 2054 * at the given address. All the data must be written to the same page. 2055 */ 2056 static int t4_write_flash(struct adapter *adapter, unsigned int addr, 2057 unsigned int n, const u8 *data) 2058 { 2059 int ret; 2060 u32 buf[64]; 2061 unsigned int i, c, left, val, offset = addr & 0xff; 2062 2063 if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE) 2064 return -EINVAL; 2065 2066 val = swab32(addr) | SF_PROG_PAGE; 2067 2068 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 || 2069 (ret = sf1_write(adapter, 4, 1, 1, val)) != 0) 2070 goto unlock; 2071 2072 for (left = n; left; left -= c) { 2073 c = min(left, 4U); 2074 for (val = 0, i = 0; i < c; ++i) 2075 val = (val << 8) + *data++; 2076 2077 ret = sf1_write(adapter, c, c != left, 1, val); 2078 if (ret) 2079 goto unlock; 2080 } 2081 ret = flash_wait_op(adapter, 8, 1); 2082 if (ret) 2083 goto unlock; 2084 2085 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */ 2086 2087 /* Read the page to verify the write succeeded */ 2088 ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 1); 2089 if (ret) 2090 return ret; 2091 2092 if (memcmp(data - n, (u8 *)buf + offset, n)) { 2093 dev_err(adapter->pdev_dev, 2094 "failed to correctly write the flash page at %#x\n", 2095 addr); 2096 return -EIO; 2097 } 2098 return 0; 2099 2100 unlock: 2101 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */ 2102 return ret; 2103 } 2104 2105 /** 2106 * t4_get_fw_version - read the firmware version 2107 * @adapter: the adapter 2108 * @vers: where to place the version 2109 * 2110 * Reads the FW version from flash. 2111 */ 2112 int t4_get_fw_version(struct adapter *adapter, u32 *vers) 2113 { 2114 return t4_read_flash(adapter, FLASH_FW_START + 2115 offsetof(struct fw_hdr, fw_ver), 1, 2116 vers, 0); 2117 } 2118 2119 /** 2120 * t4_get_tp_version - read the TP microcode version 2121 * @adapter: the adapter 2122 * @vers: where to place the version 2123 * 2124 * Reads the TP microcode version from flash. 2125 */ 2126 int t4_get_tp_version(struct adapter *adapter, u32 *vers) 2127 { 2128 return t4_read_flash(adapter, FLASH_FW_START + 2129 offsetof(struct fw_hdr, tp_microcode_ver), 2130 1, vers, 0); 2131 } 2132 2133 /** 2134 * t4_get_exprom_version - return the Expansion ROM version (if any) 2135 * @adapter: the adapter 2136 * @vers: where to place the version 2137 * 2138 * Reads the Expansion ROM header from FLASH and returns the version 2139 * number (if present) through the @vers return value pointer. We return 2140 * this in the Firmware Version Format since it's convenient. Return 2141 * 0 on success, -ENOENT if no Expansion ROM is present. 2142 */ 2143 int t4_get_exprom_version(struct adapter *adap, u32 *vers) 2144 { 2145 struct exprom_header { 2146 unsigned char hdr_arr[16]; /* must start with 0x55aa */ 2147 unsigned char hdr_ver[4]; /* Expansion ROM version */ 2148 } *hdr; 2149 u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header), 2150 sizeof(u32))]; 2151 int ret; 2152 2153 ret = t4_read_flash(adap, FLASH_EXP_ROM_START, 2154 ARRAY_SIZE(exprom_header_buf), exprom_header_buf, 2155 0); 2156 if (ret) 2157 return ret; 2158 2159 hdr = (struct exprom_header *)exprom_header_buf; 2160 if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa) 2161 return -ENOENT; 2162 2163 *vers = (FW_HDR_FW_VER_MAJOR_V(hdr->hdr_ver[0]) | 2164 FW_HDR_FW_VER_MINOR_V(hdr->hdr_ver[1]) | 2165 FW_HDR_FW_VER_MICRO_V(hdr->hdr_ver[2]) | 2166 FW_HDR_FW_VER_BUILD_V(hdr->hdr_ver[3])); 2167 return 0; 2168 } 2169 2170 /** 2171 * t4_check_fw_version - check if the FW is supported with this driver 2172 * @adap: the adapter 2173 * 2174 * Checks if an adapter's FW is compatible with the driver. Returns 0 2175 * if there's exact match, a negative error if the version could not be 2176 * read or there's a major version mismatch 2177 */ 2178 int t4_check_fw_version(struct adapter *adap) 2179 { 2180 int ret, major, minor, micro; 2181 int exp_major, exp_minor, exp_micro; 2182 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip); 2183 2184 ret = t4_get_fw_version(adap, &adap->params.fw_vers); 2185 if (ret) 2186 return ret; 2187 2188 major = FW_HDR_FW_VER_MAJOR_G(adap->params.fw_vers); 2189 minor = FW_HDR_FW_VER_MINOR_G(adap->params.fw_vers); 2190 micro = FW_HDR_FW_VER_MICRO_G(adap->params.fw_vers); 2191 2192 switch (chip_version) { 2193 case CHELSIO_T4: 2194 exp_major = T4FW_MIN_VERSION_MAJOR; 2195 exp_minor = T4FW_MIN_VERSION_MINOR; 2196 exp_micro = T4FW_MIN_VERSION_MICRO; 2197 break; 2198 case CHELSIO_T5: 2199 exp_major = T5FW_MIN_VERSION_MAJOR; 2200 exp_minor = T5FW_MIN_VERSION_MINOR; 2201 exp_micro = T5FW_MIN_VERSION_MICRO; 2202 break; 2203 case CHELSIO_T6: 2204 exp_major = T6FW_MIN_VERSION_MAJOR; 2205 exp_minor = T6FW_MIN_VERSION_MINOR; 2206 exp_micro = T6FW_MIN_VERSION_MICRO; 2207 break; 2208 default: 2209 dev_err(adap->pdev_dev, "Unsupported chip type, %x\n", 2210 adap->chip); 2211 return -EINVAL; 2212 } 2213 2214 if (major < exp_major || (major == exp_major && minor < exp_minor) || 2215 (major == exp_major && minor == exp_minor && micro < exp_micro)) { 2216 dev_err(adap->pdev_dev, 2217 "Card has firmware version %u.%u.%u, minimum " 2218 "supported firmware is %u.%u.%u.\n", major, minor, 2219 micro, exp_major, exp_minor, exp_micro); 2220 return -EFAULT; 2221 } 2222 return 0; 2223 } 2224 2225 /* Is the given firmware API compatible with the one the driver was compiled 2226 * with? 2227 */ 2228 static int fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2) 2229 { 2230 2231 /* short circuit if it's the exact same firmware version */ 2232 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver) 2233 return 1; 2234 2235 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x) 2236 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) && 2237 SAME_INTF(ri) && SAME_INTF(iscsi) && SAME_INTF(fcoe)) 2238 return 1; 2239 #undef SAME_INTF 2240 2241 return 0; 2242 } 2243 2244 /* The firmware in the filesystem is usable, but should it be installed? 2245 * This routine explains itself in detail if it indicates the filesystem 2246 * firmware should be installed. 2247 */ 2248 static int should_install_fs_fw(struct adapter *adap, int card_fw_usable, 2249 int k, int c) 2250 { 2251 const char *reason; 2252 2253 if (!card_fw_usable) { 2254 reason = "incompatible or unusable"; 2255 goto install; 2256 } 2257 2258 if (k > c) { 2259 reason = "older than the version supported with this driver"; 2260 goto install; 2261 } 2262 2263 return 0; 2264 2265 install: 2266 dev_err(adap->pdev_dev, "firmware on card (%u.%u.%u.%u) is %s, " 2267 "installing firmware %u.%u.%u.%u on card.\n", 2268 FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c), 2269 FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c), reason, 2270 FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k), 2271 FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k)); 2272 2273 return 1; 2274 } 2275 2276 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info, 2277 const u8 *fw_data, unsigned int fw_size, 2278 struct fw_hdr *card_fw, enum dev_state state, 2279 int *reset) 2280 { 2281 int ret, card_fw_usable, fs_fw_usable; 2282 const struct fw_hdr *fs_fw; 2283 const struct fw_hdr *drv_fw; 2284 2285 drv_fw = &fw_info->fw_hdr; 2286 2287 /* Read the header of the firmware on the card */ 2288 ret = -t4_read_flash(adap, FLASH_FW_START, 2289 sizeof(*card_fw) / sizeof(uint32_t), 2290 (uint32_t *)card_fw, 1); 2291 if (ret == 0) { 2292 card_fw_usable = fw_compatible(drv_fw, (const void *)card_fw); 2293 } else { 2294 dev_err(adap->pdev_dev, 2295 "Unable to read card's firmware header: %d\n", ret); 2296 card_fw_usable = 0; 2297 } 2298 2299 if (fw_data != NULL) { 2300 fs_fw = (const void *)fw_data; 2301 fs_fw_usable = fw_compatible(drv_fw, fs_fw); 2302 } else { 2303 fs_fw = NULL; 2304 fs_fw_usable = 0; 2305 } 2306 2307 if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver && 2308 (!fs_fw_usable || fs_fw->fw_ver == drv_fw->fw_ver)) { 2309 /* Common case: the firmware on the card is an exact match and 2310 * the filesystem one is an exact match too, or the filesystem 2311 * one is absent/incompatible. 2312 */ 2313 } else if (fs_fw_usable && state == DEV_STATE_UNINIT && 2314 should_install_fs_fw(adap, card_fw_usable, 2315 be32_to_cpu(fs_fw->fw_ver), 2316 be32_to_cpu(card_fw->fw_ver))) { 2317 ret = -t4_fw_upgrade(adap, adap->mbox, fw_data, 2318 fw_size, 0); 2319 if (ret != 0) { 2320 dev_err(adap->pdev_dev, 2321 "failed to install firmware: %d\n", ret); 2322 goto bye; 2323 } 2324 2325 /* Installed successfully, update the cached header too. */ 2326 *card_fw = *fs_fw; 2327 card_fw_usable = 1; 2328 *reset = 0; /* already reset as part of load_fw */ 2329 } 2330 2331 if (!card_fw_usable) { 2332 uint32_t d, c, k; 2333 2334 d = be32_to_cpu(drv_fw->fw_ver); 2335 c = be32_to_cpu(card_fw->fw_ver); 2336 k = fs_fw ? be32_to_cpu(fs_fw->fw_ver) : 0; 2337 2338 dev_err(adap->pdev_dev, "Cannot find a usable firmware: " 2339 "chip state %d, " 2340 "driver compiled with %d.%d.%d.%d, " 2341 "card has %d.%d.%d.%d, filesystem has %d.%d.%d.%d\n", 2342 state, 2343 FW_HDR_FW_VER_MAJOR_G(d), FW_HDR_FW_VER_MINOR_G(d), 2344 FW_HDR_FW_VER_MICRO_G(d), FW_HDR_FW_VER_BUILD_G(d), 2345 FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c), 2346 FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c), 2347 FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k), 2348 FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k)); 2349 ret = EINVAL; 2350 goto bye; 2351 } 2352 2353 /* We're using whatever's on the card and it's known to be good. */ 2354 adap->params.fw_vers = be32_to_cpu(card_fw->fw_ver); 2355 adap->params.tp_vers = be32_to_cpu(card_fw->tp_microcode_ver); 2356 2357 bye: 2358 return ret; 2359 } 2360 2361 /** 2362 * t4_flash_erase_sectors - erase a range of flash sectors 2363 * @adapter: the adapter 2364 * @start: the first sector to erase 2365 * @end: the last sector to erase 2366 * 2367 * Erases the sectors in the given inclusive range. 2368 */ 2369 static int t4_flash_erase_sectors(struct adapter *adapter, int start, int end) 2370 { 2371 int ret = 0; 2372 2373 if (end >= adapter->params.sf_nsec) 2374 return -EINVAL; 2375 2376 while (start <= end) { 2377 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 || 2378 (ret = sf1_write(adapter, 4, 0, 1, 2379 SF_ERASE_SECTOR | (start << 8))) != 0 || 2380 (ret = flash_wait_op(adapter, 14, 500)) != 0) { 2381 dev_err(adapter->pdev_dev, 2382 "erase of flash sector %d failed, error %d\n", 2383 start, ret); 2384 break; 2385 } 2386 start++; 2387 } 2388 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */ 2389 return ret; 2390 } 2391 2392 /** 2393 * t4_flash_cfg_addr - return the address of the flash configuration file 2394 * @adapter: the adapter 2395 * 2396 * Return the address within the flash where the Firmware Configuration 2397 * File is stored. 2398 */ 2399 unsigned int t4_flash_cfg_addr(struct adapter *adapter) 2400 { 2401 if (adapter->params.sf_size == 0x100000) 2402 return FLASH_FPGA_CFG_START; 2403 else 2404 return FLASH_CFG_START; 2405 } 2406 2407 /* Return TRUE if the specified firmware matches the adapter. I.e. T4 2408 * firmware for T4 adapters, T5 firmware for T5 adapters, etc. We go ahead 2409 * and emit an error message for mismatched firmware to save our caller the 2410 * effort ... 2411 */ 2412 static bool t4_fw_matches_chip(const struct adapter *adap, 2413 const struct fw_hdr *hdr) 2414 { 2415 /* The expression below will return FALSE for any unsupported adapter 2416 * which will keep us "honest" in the future ... 2417 */ 2418 if ((is_t4(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T4) || 2419 (is_t5(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T5) || 2420 (is_t6(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T6)) 2421 return true; 2422 2423 dev_err(adap->pdev_dev, 2424 "FW image (%d) is not suitable for this adapter (%d)\n", 2425 hdr->chip, CHELSIO_CHIP_VERSION(adap->params.chip)); 2426 return false; 2427 } 2428 2429 /** 2430 * t4_load_fw - download firmware 2431 * @adap: the adapter 2432 * @fw_data: the firmware image to write 2433 * @size: image size 2434 * 2435 * Write the supplied firmware image to the card's serial flash. 2436 */ 2437 int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size) 2438 { 2439 u32 csum; 2440 int ret, addr; 2441 unsigned int i; 2442 u8 first_page[SF_PAGE_SIZE]; 2443 const __be32 *p = (const __be32 *)fw_data; 2444 const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data; 2445 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; 2446 unsigned int fw_img_start = adap->params.sf_fw_start; 2447 unsigned int fw_start_sec = fw_img_start / sf_sec_size; 2448 2449 if (!size) { 2450 dev_err(adap->pdev_dev, "FW image has no data\n"); 2451 return -EINVAL; 2452 } 2453 if (size & 511) { 2454 dev_err(adap->pdev_dev, 2455 "FW image size not multiple of 512 bytes\n"); 2456 return -EINVAL; 2457 } 2458 if ((unsigned int)be16_to_cpu(hdr->len512) * 512 != size) { 2459 dev_err(adap->pdev_dev, 2460 "FW image size differs from size in FW header\n"); 2461 return -EINVAL; 2462 } 2463 if (size > FW_MAX_SIZE) { 2464 dev_err(adap->pdev_dev, "FW image too large, max is %u bytes\n", 2465 FW_MAX_SIZE); 2466 return -EFBIG; 2467 } 2468 if (!t4_fw_matches_chip(adap, hdr)) 2469 return -EINVAL; 2470 2471 for (csum = 0, i = 0; i < size / sizeof(csum); i++) 2472 csum += be32_to_cpu(p[i]); 2473 2474 if (csum != 0xffffffff) { 2475 dev_err(adap->pdev_dev, 2476 "corrupted firmware image, checksum %#x\n", csum); 2477 return -EINVAL; 2478 } 2479 2480 i = DIV_ROUND_UP(size, sf_sec_size); /* # of sectors spanned */ 2481 ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1); 2482 if (ret) 2483 goto out; 2484 2485 /* 2486 * We write the correct version at the end so the driver can see a bad 2487 * version if the FW write fails. Start by writing a copy of the 2488 * first page with a bad version. 2489 */ 2490 memcpy(first_page, fw_data, SF_PAGE_SIZE); 2491 ((struct fw_hdr *)first_page)->fw_ver = cpu_to_be32(0xffffffff); 2492 ret = t4_write_flash(adap, fw_img_start, SF_PAGE_SIZE, first_page); 2493 if (ret) 2494 goto out; 2495 2496 addr = fw_img_start; 2497 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) { 2498 addr += SF_PAGE_SIZE; 2499 fw_data += SF_PAGE_SIZE; 2500 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data); 2501 if (ret) 2502 goto out; 2503 } 2504 2505 ret = t4_write_flash(adap, 2506 fw_img_start + offsetof(struct fw_hdr, fw_ver), 2507 sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver); 2508 out: 2509 if (ret) 2510 dev_err(adap->pdev_dev, "firmware download failed, error %d\n", 2511 ret); 2512 else 2513 ret = t4_get_fw_version(adap, &adap->params.fw_vers); 2514 return ret; 2515 } 2516 2517 /** 2518 * t4_phy_fw_ver - return current PHY firmware version 2519 * @adap: the adapter 2520 * @phy_fw_ver: return value buffer for PHY firmware version 2521 * 2522 * Returns the current version of external PHY firmware on the 2523 * adapter. 2524 */ 2525 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver) 2526 { 2527 u32 param, val; 2528 int ret; 2529 2530 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | 2531 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) | 2532 FW_PARAMS_PARAM_Y_V(adap->params.portvec) | 2533 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_VERSION)); 2534 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, 2535 ¶m, &val); 2536 if (ret < 0) 2537 return ret; 2538 *phy_fw_ver = val; 2539 return 0; 2540 } 2541 2542 /** 2543 * t4_load_phy_fw - download port PHY firmware 2544 * @adap: the adapter 2545 * @win: the PCI-E Memory Window index to use for t4_memory_rw() 2546 * @win_lock: the lock to use to guard the memory copy 2547 * @phy_fw_version: function to check PHY firmware versions 2548 * @phy_fw_data: the PHY firmware image to write 2549 * @phy_fw_size: image size 2550 * 2551 * Transfer the specified PHY firmware to the adapter. If a non-NULL 2552 * @phy_fw_version is supplied, then it will be used to determine if 2553 * it's necessary to perform the transfer by comparing the version 2554 * of any existing adapter PHY firmware with that of the passed in 2555 * PHY firmware image. If @win_lock is non-NULL then it will be used 2556 * around the call to t4_memory_rw() which transfers the PHY firmware 2557 * to the adapter. 2558 * 2559 * A negative error number will be returned if an error occurs. If 2560 * version number support is available and there's no need to upgrade 2561 * the firmware, 0 will be returned. If firmware is successfully 2562 * transferred to the adapter, 1 will be retured. 2563 * 2564 * NOTE: some adapters only have local RAM to store the PHY firmware. As 2565 * a result, a RESET of the adapter would cause that RAM to lose its 2566 * contents. Thus, loading PHY firmware on such adapters must happen 2567 * after any FW_RESET_CMDs ... 2568 */ 2569 int t4_load_phy_fw(struct adapter *adap, 2570 int win, spinlock_t *win_lock, 2571 int (*phy_fw_version)(const u8 *, size_t), 2572 const u8 *phy_fw_data, size_t phy_fw_size) 2573 { 2574 unsigned long mtype = 0, maddr = 0; 2575 u32 param, val; 2576 int cur_phy_fw_ver = 0, new_phy_fw_vers = 0; 2577 int ret; 2578 2579 /* If we have version number support, then check to see if the adapter 2580 * already has up-to-date PHY firmware loaded. 2581 */ 2582 if (phy_fw_version) { 2583 new_phy_fw_vers = phy_fw_version(phy_fw_data, phy_fw_size); 2584 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver); 2585 if (ret < 0) 2586 return ret; 2587 2588 if (cur_phy_fw_ver >= new_phy_fw_vers) { 2589 CH_WARN(adap, "PHY Firmware already up-to-date, " 2590 "version %#x\n", cur_phy_fw_ver); 2591 return 0; 2592 } 2593 } 2594 2595 /* Ask the firmware where it wants us to copy the PHY firmware image. 2596 * The size of the file requires a special version of the READ coommand 2597 * which will pass the file size via the values field in PARAMS_CMD and 2598 * retrieve the return value from firmware and place it in the same 2599 * buffer values 2600 */ 2601 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | 2602 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) | 2603 FW_PARAMS_PARAM_Y_V(adap->params.portvec) | 2604 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD)); 2605 val = phy_fw_size; 2606 ret = t4_query_params_rw(adap, adap->mbox, adap->pf, 0, 1, 2607 ¶m, &val, 1); 2608 if (ret < 0) 2609 return ret; 2610 mtype = val >> 8; 2611 maddr = (val & 0xff) << 16; 2612 2613 /* Copy the supplied PHY Firmware image to the adapter memory location 2614 * allocated by the adapter firmware. 2615 */ 2616 if (win_lock) 2617 spin_lock_bh(win_lock); 2618 ret = t4_memory_rw(adap, win, mtype, maddr, 2619 phy_fw_size, (__be32 *)phy_fw_data, 2620 T4_MEMORY_WRITE); 2621 if (win_lock) 2622 spin_unlock_bh(win_lock); 2623 if (ret) 2624 return ret; 2625 2626 /* Tell the firmware that the PHY firmware image has been written to 2627 * RAM and it can now start copying it over to the PHYs. The chip 2628 * firmware will RESET the affected PHYs as part of this operation 2629 * leaving them running the new PHY firmware image. 2630 */ 2631 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | 2632 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) | 2633 FW_PARAMS_PARAM_Y_V(adap->params.portvec) | 2634 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD)); 2635 ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1, 2636 ¶m, &val, 30000); 2637 2638 /* If we have version number support, then check to see that the new 2639 * firmware got loaded properly. 2640 */ 2641 if (phy_fw_version) { 2642 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver); 2643 if (ret < 0) 2644 return ret; 2645 2646 if (cur_phy_fw_ver != new_phy_fw_vers) { 2647 CH_WARN(adap, "PHY Firmware did not update: " 2648 "version on adapter %#x, " 2649 "version flashed %#x\n", 2650 cur_phy_fw_ver, new_phy_fw_vers); 2651 return -ENXIO; 2652 } 2653 } 2654 2655 return 1; 2656 } 2657 2658 /** 2659 * t4_fwcache - firmware cache operation 2660 * @adap: the adapter 2661 * @op : the operation (flush or flush and invalidate) 2662 */ 2663 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op) 2664 { 2665 struct fw_params_cmd c; 2666 2667 memset(&c, 0, sizeof(c)); 2668 c.op_to_vfn = 2669 cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) | 2670 FW_CMD_REQUEST_F | FW_CMD_WRITE_F | 2671 FW_PARAMS_CMD_PFN_V(adap->pf) | 2672 FW_PARAMS_CMD_VFN_V(0)); 2673 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 2674 c.param[0].mnem = 2675 cpu_to_be32(FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | 2676 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_FWCACHE)); 2677 c.param[0].val = (__force __be32)op; 2678 2679 return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL); 2680 } 2681 2682 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, 2683 unsigned int *pif_req_wrptr, 2684 unsigned int *pif_rsp_wrptr) 2685 { 2686 int i, j; 2687 u32 cfg, val, req, rsp; 2688 2689 cfg = t4_read_reg(adap, CIM_DEBUGCFG_A); 2690 if (cfg & LADBGEN_F) 2691 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F); 2692 2693 val = t4_read_reg(adap, CIM_DEBUGSTS_A); 2694 req = POLADBGWRPTR_G(val); 2695 rsp = PILADBGWRPTR_G(val); 2696 if (pif_req_wrptr) 2697 *pif_req_wrptr = req; 2698 if (pif_rsp_wrptr) 2699 *pif_rsp_wrptr = rsp; 2700 2701 for (i = 0; i < CIM_PIFLA_SIZE; i++) { 2702 for (j = 0; j < 6; j++) { 2703 t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(req) | 2704 PILADBGRDPTR_V(rsp)); 2705 *pif_req++ = t4_read_reg(adap, CIM_PO_LA_DEBUGDATA_A); 2706 *pif_rsp++ = t4_read_reg(adap, CIM_PI_LA_DEBUGDATA_A); 2707 req++; 2708 rsp++; 2709 } 2710 req = (req + 2) & POLADBGRDPTR_M; 2711 rsp = (rsp + 2) & PILADBGRDPTR_M; 2712 } 2713 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg); 2714 } 2715 2716 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp) 2717 { 2718 u32 cfg; 2719 int i, j, idx; 2720 2721 cfg = t4_read_reg(adap, CIM_DEBUGCFG_A); 2722 if (cfg & LADBGEN_F) 2723 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F); 2724 2725 for (i = 0; i < CIM_MALA_SIZE; i++) { 2726 for (j = 0; j < 5; j++) { 2727 idx = 8 * i + j; 2728 t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(idx) | 2729 PILADBGRDPTR_V(idx)); 2730 *ma_req++ = t4_read_reg(adap, CIM_PO_LA_MADEBUGDATA_A); 2731 *ma_rsp++ = t4_read_reg(adap, CIM_PI_LA_MADEBUGDATA_A); 2732 } 2733 } 2734 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg); 2735 } 2736 2737 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf) 2738 { 2739 unsigned int i, j; 2740 2741 for (i = 0; i < 8; i++) { 2742 u32 *p = la_buf + i; 2743 2744 t4_write_reg(adap, ULP_RX_LA_CTL_A, i); 2745 j = t4_read_reg(adap, ULP_RX_LA_WRPTR_A); 2746 t4_write_reg(adap, ULP_RX_LA_RDPTR_A, j); 2747 for (j = 0; j < ULPRX_LA_SIZE; j++, p += 8) 2748 *p = t4_read_reg(adap, ULP_RX_LA_RDDATA_A); 2749 } 2750 } 2751 2752 #define ADVERT_MASK (FW_PORT_CAP_SPEED_100M | FW_PORT_CAP_SPEED_1G |\ 2753 FW_PORT_CAP_SPEED_10G | FW_PORT_CAP_SPEED_40G | \ 2754 FW_PORT_CAP_ANEG) 2755 2756 /** 2757 * t4_link_l1cfg - apply link configuration to MAC/PHY 2758 * @phy: the PHY to setup 2759 * @mac: the MAC to setup 2760 * @lc: the requested link configuration 2761 * 2762 * Set up a port's MAC and PHY according to a desired link configuration. 2763 * - If the PHY can auto-negotiate first decide what to advertise, then 2764 * enable/disable auto-negotiation as desired, and reset. 2765 * - If the PHY does not auto-negotiate just reset it. 2766 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC, 2767 * otherwise do it later based on the outcome of auto-negotiation. 2768 */ 2769 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port, 2770 struct link_config *lc) 2771 { 2772 struct fw_port_cmd c; 2773 unsigned int fc = 0, mdi = FW_PORT_CAP_MDI_V(FW_PORT_CAP_MDI_AUTO); 2774 2775 lc->link_ok = 0; 2776 if (lc->requested_fc & PAUSE_RX) 2777 fc |= FW_PORT_CAP_FC_RX; 2778 if (lc->requested_fc & PAUSE_TX) 2779 fc |= FW_PORT_CAP_FC_TX; 2780 2781 memset(&c, 0, sizeof(c)); 2782 c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) | 2783 FW_CMD_REQUEST_F | FW_CMD_EXEC_F | 2784 FW_PORT_CMD_PORTID_V(port)); 2785 c.action_to_len16 = 2786 cpu_to_be32(FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_L1_CFG) | 2787 FW_LEN16(c)); 2788 2789 if (!(lc->supported & FW_PORT_CAP_ANEG)) { 2790 c.u.l1cfg.rcap = cpu_to_be32((lc->supported & ADVERT_MASK) | 2791 fc); 2792 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX); 2793 } else if (lc->autoneg == AUTONEG_DISABLE) { 2794 c.u.l1cfg.rcap = cpu_to_be32(lc->requested_speed | fc | mdi); 2795 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX); 2796 } else 2797 c.u.l1cfg.rcap = cpu_to_be32(lc->advertising | fc | mdi); 2798 2799 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 2800 } 2801 2802 /** 2803 * t4_restart_aneg - restart autonegotiation 2804 * @adap: the adapter 2805 * @mbox: mbox to use for the FW command 2806 * @port: the port id 2807 * 2808 * Restarts autonegotiation for the selected port. 2809 */ 2810 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port) 2811 { 2812 struct fw_port_cmd c; 2813 2814 memset(&c, 0, sizeof(c)); 2815 c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) | 2816 FW_CMD_REQUEST_F | FW_CMD_EXEC_F | 2817 FW_PORT_CMD_PORTID_V(port)); 2818 c.action_to_len16 = 2819 cpu_to_be32(FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_L1_CFG) | 2820 FW_LEN16(c)); 2821 c.u.l1cfg.rcap = cpu_to_be32(FW_PORT_CAP_ANEG); 2822 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 2823 } 2824 2825 typedef void (*int_handler_t)(struct adapter *adap); 2826 2827 struct intr_info { 2828 unsigned int mask; /* bits to check in interrupt status */ 2829 const char *msg; /* message to print or NULL */ 2830 short stat_idx; /* stat counter to increment or -1 */ 2831 unsigned short fatal; /* whether the condition reported is fatal */ 2832 int_handler_t int_handler; /* platform-specific int handler */ 2833 }; 2834 2835 /** 2836 * t4_handle_intr_status - table driven interrupt handler 2837 * @adapter: the adapter that generated the interrupt 2838 * @reg: the interrupt status register to process 2839 * @acts: table of interrupt actions 2840 * 2841 * A table driven interrupt handler that applies a set of masks to an 2842 * interrupt status word and performs the corresponding actions if the 2843 * interrupts described by the mask have occurred. The actions include 2844 * optionally emitting a warning or alert message. The table is terminated 2845 * by an entry specifying mask 0. Returns the number of fatal interrupt 2846 * conditions. 2847 */ 2848 static int t4_handle_intr_status(struct adapter *adapter, unsigned int reg, 2849 const struct intr_info *acts) 2850 { 2851 int fatal = 0; 2852 unsigned int mask = 0; 2853 unsigned int status = t4_read_reg(adapter, reg); 2854 2855 for ( ; acts->mask; ++acts) { 2856 if (!(status & acts->mask)) 2857 continue; 2858 if (acts->fatal) { 2859 fatal++; 2860 dev_alert(adapter->pdev_dev, "%s (0x%x)\n", acts->msg, 2861 status & acts->mask); 2862 } else if (acts->msg && printk_ratelimit()) 2863 dev_warn(adapter->pdev_dev, "%s (0x%x)\n", acts->msg, 2864 status & acts->mask); 2865 if (acts->int_handler) 2866 acts->int_handler(adapter); 2867 mask |= acts->mask; 2868 } 2869 status &= mask; 2870 if (status) /* clear processed interrupts */ 2871 t4_write_reg(adapter, reg, status); 2872 return fatal; 2873 } 2874 2875 /* 2876 * Interrupt handler for the PCIE module. 2877 */ 2878 static void pcie_intr_handler(struct adapter *adapter) 2879 { 2880 static const struct intr_info sysbus_intr_info[] = { 2881 { RNPP_F, "RXNP array parity error", -1, 1 }, 2882 { RPCP_F, "RXPC array parity error", -1, 1 }, 2883 { RCIP_F, "RXCIF array parity error", -1, 1 }, 2884 { RCCP_F, "Rx completions control array parity error", -1, 1 }, 2885 { RFTP_F, "RXFT array parity error", -1, 1 }, 2886 { 0 } 2887 }; 2888 static const struct intr_info pcie_port_intr_info[] = { 2889 { TPCP_F, "TXPC array parity error", -1, 1 }, 2890 { TNPP_F, "TXNP array parity error", -1, 1 }, 2891 { TFTP_F, "TXFT array parity error", -1, 1 }, 2892 { TCAP_F, "TXCA array parity error", -1, 1 }, 2893 { TCIP_F, "TXCIF array parity error", -1, 1 }, 2894 { RCAP_F, "RXCA array parity error", -1, 1 }, 2895 { OTDD_F, "outbound request TLP discarded", -1, 1 }, 2896 { RDPE_F, "Rx data parity error", -1, 1 }, 2897 { TDUE_F, "Tx uncorrectable data error", -1, 1 }, 2898 { 0 } 2899 }; 2900 static const struct intr_info pcie_intr_info[] = { 2901 { MSIADDRLPERR_F, "MSI AddrL parity error", -1, 1 }, 2902 { MSIADDRHPERR_F, "MSI AddrH parity error", -1, 1 }, 2903 { MSIDATAPERR_F, "MSI data parity error", -1, 1 }, 2904 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 }, 2905 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 }, 2906 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 }, 2907 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 }, 2908 { PIOCPLPERR_F, "PCI PIO completion FIFO parity error", -1, 1 }, 2909 { PIOREQPERR_F, "PCI PIO request FIFO parity error", -1, 1 }, 2910 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 }, 2911 { CCNTPERR_F, "PCI CMD channel count parity error", -1, 1 }, 2912 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 }, 2913 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 }, 2914 { DCNTPERR_F, "PCI DMA channel count parity error", -1, 1 }, 2915 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 }, 2916 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 }, 2917 { HCNTPERR_F, "PCI HMA channel count parity error", -1, 1 }, 2918 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 }, 2919 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 }, 2920 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 }, 2921 { FIDPERR_F, "PCI FID parity error", -1, 1 }, 2922 { INTXCLRPERR_F, "PCI INTx clear parity error", -1, 1 }, 2923 { MATAGPERR_F, "PCI MA tag parity error", -1, 1 }, 2924 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 }, 2925 { RXCPLPERR_F, "PCI Rx completion parity error", -1, 1 }, 2926 { RXWRPERR_F, "PCI Rx write parity error", -1, 1 }, 2927 { RPLPERR_F, "PCI replay buffer parity error", -1, 1 }, 2928 { PCIESINT_F, "PCI core secondary fault", -1, 1 }, 2929 { PCIEPINT_F, "PCI core primary fault", -1, 1 }, 2930 { UNXSPLCPLERR_F, "PCI unexpected split completion error", 2931 -1, 0 }, 2932 { 0 } 2933 }; 2934 2935 static struct intr_info t5_pcie_intr_info[] = { 2936 { MSTGRPPERR_F, "Master Response Read Queue parity error", 2937 -1, 1 }, 2938 { MSTTIMEOUTPERR_F, "Master Timeout FIFO parity error", -1, 1 }, 2939 { MSIXSTIPERR_F, "MSI-X STI SRAM parity error", -1, 1 }, 2940 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 }, 2941 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 }, 2942 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 }, 2943 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 }, 2944 { PIOCPLGRPPERR_F, "PCI PIO completion Group FIFO parity error", 2945 -1, 1 }, 2946 { PIOREQGRPPERR_F, "PCI PIO request Group FIFO parity error", 2947 -1, 1 }, 2948 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 }, 2949 { MSTTAGQPERR_F, "PCI master tag queue parity error", -1, 1 }, 2950 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 }, 2951 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 }, 2952 { DREQWRPERR_F, "PCI DMA channel write request parity error", 2953 -1, 1 }, 2954 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 }, 2955 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 }, 2956 { HREQWRPERR_F, "PCI HMA channel count parity error", -1, 1 }, 2957 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 }, 2958 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 }, 2959 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 }, 2960 { FIDPERR_F, "PCI FID parity error", -1, 1 }, 2961 { VFIDPERR_F, "PCI INTx clear parity error", -1, 1 }, 2962 { MAGRPPERR_F, "PCI MA group FIFO parity error", -1, 1 }, 2963 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 }, 2964 { IPRXHDRGRPPERR_F, "PCI IP Rx header group parity error", 2965 -1, 1 }, 2966 { IPRXDATAGRPPERR_F, "PCI IP Rx data group parity error", 2967 -1, 1 }, 2968 { RPLPERR_F, "PCI IP replay buffer parity error", -1, 1 }, 2969 { IPSOTPERR_F, "PCI IP SOT buffer parity error", -1, 1 }, 2970 { TRGT1GRPPERR_F, "PCI TRGT1 group FIFOs parity error", -1, 1 }, 2971 { READRSPERR_F, "Outbound read error", -1, 0 }, 2972 { 0 } 2973 }; 2974 2975 int fat; 2976 2977 if (is_t4(adapter->params.chip)) 2978 fat = t4_handle_intr_status(adapter, 2979 PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A, 2980 sysbus_intr_info) + 2981 t4_handle_intr_status(adapter, 2982 PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A, 2983 pcie_port_intr_info) + 2984 t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A, 2985 pcie_intr_info); 2986 else 2987 fat = t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A, 2988 t5_pcie_intr_info); 2989 2990 if (fat) 2991 t4_fatal_err(adapter); 2992 } 2993 2994 /* 2995 * TP interrupt handler. 2996 */ 2997 static void tp_intr_handler(struct adapter *adapter) 2998 { 2999 static const struct intr_info tp_intr_info[] = { 3000 { 0x3fffffff, "TP parity error", -1, 1 }, 3001 { FLMTXFLSTEMPTY_F, "TP out of Tx pages", -1, 1 }, 3002 { 0 } 3003 }; 3004 3005 if (t4_handle_intr_status(adapter, TP_INT_CAUSE_A, tp_intr_info)) 3006 t4_fatal_err(adapter); 3007 } 3008 3009 /* 3010 * SGE interrupt handler. 3011 */ 3012 static void sge_intr_handler(struct adapter *adapter) 3013 { 3014 u64 v; 3015 u32 err; 3016 3017 static const struct intr_info sge_intr_info[] = { 3018 { ERR_CPL_EXCEED_IQE_SIZE_F, 3019 "SGE received CPL exceeding IQE size", -1, 1 }, 3020 { ERR_INVALID_CIDX_INC_F, 3021 "SGE GTS CIDX increment too large", -1, 0 }, 3022 { ERR_CPL_OPCODE_0_F, "SGE received 0-length CPL", -1, 0 }, 3023 { DBFIFO_LP_INT_F, NULL, -1, 0, t4_db_full }, 3024 { ERR_DATA_CPL_ON_HIGH_QID1_F | ERR_DATA_CPL_ON_HIGH_QID0_F, 3025 "SGE IQID > 1023 received CPL for FL", -1, 0 }, 3026 { ERR_BAD_DB_PIDX3_F, "SGE DBP 3 pidx increment too large", -1, 3027 0 }, 3028 { ERR_BAD_DB_PIDX2_F, "SGE DBP 2 pidx increment too large", -1, 3029 0 }, 3030 { ERR_BAD_DB_PIDX1_F, "SGE DBP 1 pidx increment too large", -1, 3031 0 }, 3032 { ERR_BAD_DB_PIDX0_F, "SGE DBP 0 pidx increment too large", -1, 3033 0 }, 3034 { ERR_ING_CTXT_PRIO_F, 3035 "SGE too many priority ingress contexts", -1, 0 }, 3036 { INGRESS_SIZE_ERR_F, "SGE illegal ingress QID", -1, 0 }, 3037 { EGRESS_SIZE_ERR_F, "SGE illegal egress QID", -1, 0 }, 3038 { 0 } 3039 }; 3040 3041 static struct intr_info t4t5_sge_intr_info[] = { 3042 { ERR_DROPPED_DB_F, NULL, -1, 0, t4_db_dropped }, 3043 { DBFIFO_HP_INT_F, NULL, -1, 0, t4_db_full }, 3044 { ERR_EGR_CTXT_PRIO_F, 3045 "SGE too many priority egress contexts", -1, 0 }, 3046 { 0 } 3047 }; 3048 3049 v = (u64)t4_read_reg(adapter, SGE_INT_CAUSE1_A) | 3050 ((u64)t4_read_reg(adapter, SGE_INT_CAUSE2_A) << 32); 3051 if (v) { 3052 dev_alert(adapter->pdev_dev, "SGE parity error (%#llx)\n", 3053 (unsigned long long)v); 3054 t4_write_reg(adapter, SGE_INT_CAUSE1_A, v); 3055 t4_write_reg(adapter, SGE_INT_CAUSE2_A, v >> 32); 3056 } 3057 3058 v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A, sge_intr_info); 3059 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) 3060 v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A, 3061 t4t5_sge_intr_info); 3062 3063 err = t4_read_reg(adapter, SGE_ERROR_STATS_A); 3064 if (err & ERROR_QID_VALID_F) { 3065 dev_err(adapter->pdev_dev, "SGE error for queue %u\n", 3066 ERROR_QID_G(err)); 3067 if (err & UNCAPTURED_ERROR_F) 3068 dev_err(adapter->pdev_dev, 3069 "SGE UNCAPTURED_ERROR set (clearing)\n"); 3070 t4_write_reg(adapter, SGE_ERROR_STATS_A, ERROR_QID_VALID_F | 3071 UNCAPTURED_ERROR_F); 3072 } 3073 3074 if (v != 0) 3075 t4_fatal_err(adapter); 3076 } 3077 3078 #define CIM_OBQ_INTR (OBQULP0PARERR_F | OBQULP1PARERR_F | OBQULP2PARERR_F |\ 3079 OBQULP3PARERR_F | OBQSGEPARERR_F | OBQNCSIPARERR_F) 3080 #define CIM_IBQ_INTR (IBQTP0PARERR_F | IBQTP1PARERR_F | IBQULPPARERR_F |\ 3081 IBQSGEHIPARERR_F | IBQSGELOPARERR_F | IBQNCSIPARERR_F) 3082 3083 /* 3084 * CIM interrupt handler. 3085 */ 3086 static void cim_intr_handler(struct adapter *adapter) 3087 { 3088 static const struct intr_info cim_intr_info[] = { 3089 { PREFDROPINT_F, "CIM control register prefetch drop", -1, 1 }, 3090 { CIM_OBQ_INTR, "CIM OBQ parity error", -1, 1 }, 3091 { CIM_IBQ_INTR, "CIM IBQ parity error", -1, 1 }, 3092 { MBUPPARERR_F, "CIM mailbox uP parity error", -1, 1 }, 3093 { MBHOSTPARERR_F, "CIM mailbox host parity error", -1, 1 }, 3094 { TIEQINPARERRINT_F, "CIM TIEQ outgoing parity error", -1, 1 }, 3095 { TIEQOUTPARERRINT_F, "CIM TIEQ incoming parity error", -1, 1 }, 3096 { 0 } 3097 }; 3098 static const struct intr_info cim_upintr_info[] = { 3099 { RSVDSPACEINT_F, "CIM reserved space access", -1, 1 }, 3100 { ILLTRANSINT_F, "CIM illegal transaction", -1, 1 }, 3101 { ILLWRINT_F, "CIM illegal write", -1, 1 }, 3102 { ILLRDINT_F, "CIM illegal read", -1, 1 }, 3103 { ILLRDBEINT_F, "CIM illegal read BE", -1, 1 }, 3104 { ILLWRBEINT_F, "CIM illegal write BE", -1, 1 }, 3105 { SGLRDBOOTINT_F, "CIM single read from boot space", -1, 1 }, 3106 { SGLWRBOOTINT_F, "CIM single write to boot space", -1, 1 }, 3107 { BLKWRBOOTINT_F, "CIM block write to boot space", -1, 1 }, 3108 { SGLRDFLASHINT_F, "CIM single read from flash space", -1, 1 }, 3109 { SGLWRFLASHINT_F, "CIM single write to flash space", -1, 1 }, 3110 { BLKWRFLASHINT_F, "CIM block write to flash space", -1, 1 }, 3111 { SGLRDEEPROMINT_F, "CIM single EEPROM read", -1, 1 }, 3112 { SGLWREEPROMINT_F, "CIM single EEPROM write", -1, 1 }, 3113 { BLKRDEEPROMINT_F, "CIM block EEPROM read", -1, 1 }, 3114 { BLKWREEPROMINT_F, "CIM block EEPROM write", -1, 1 }, 3115 { SGLRDCTLINT_F, "CIM single read from CTL space", -1, 1 }, 3116 { SGLWRCTLINT_F, "CIM single write to CTL space", -1, 1 }, 3117 { BLKRDCTLINT_F, "CIM block read from CTL space", -1, 1 }, 3118 { BLKWRCTLINT_F, "CIM block write to CTL space", -1, 1 }, 3119 { SGLRDPLINT_F, "CIM single read from PL space", -1, 1 }, 3120 { SGLWRPLINT_F, "CIM single write to PL space", -1, 1 }, 3121 { BLKRDPLINT_F, "CIM block read from PL space", -1, 1 }, 3122 { BLKWRPLINT_F, "CIM block write to PL space", -1, 1 }, 3123 { REQOVRLOOKUPINT_F, "CIM request FIFO overwrite", -1, 1 }, 3124 { RSPOVRLOOKUPINT_F, "CIM response FIFO overwrite", -1, 1 }, 3125 { TIMEOUTINT_F, "CIM PIF timeout", -1, 1 }, 3126 { TIMEOUTMAINT_F, "CIM PIF MA timeout", -1, 1 }, 3127 { 0 } 3128 }; 3129 3130 int fat; 3131 3132 if (t4_read_reg(adapter, PCIE_FW_A) & PCIE_FW_ERR_F) 3133 t4_report_fw_error(adapter); 3134 3135 fat = t4_handle_intr_status(adapter, CIM_HOST_INT_CAUSE_A, 3136 cim_intr_info) + 3137 t4_handle_intr_status(adapter, CIM_HOST_UPACC_INT_CAUSE_A, 3138 cim_upintr_info); 3139 if (fat) 3140 t4_fatal_err(adapter); 3141 } 3142 3143 /* 3144 * ULP RX interrupt handler. 3145 */ 3146 static void ulprx_intr_handler(struct adapter *adapter) 3147 { 3148 static const struct intr_info ulprx_intr_info[] = { 3149 { 0x1800000, "ULPRX context error", -1, 1 }, 3150 { 0x7fffff, "ULPRX parity error", -1, 1 }, 3151 { 0 } 3152 }; 3153 3154 if (t4_handle_intr_status(adapter, ULP_RX_INT_CAUSE_A, ulprx_intr_info)) 3155 t4_fatal_err(adapter); 3156 } 3157 3158 /* 3159 * ULP TX interrupt handler. 3160 */ 3161 static void ulptx_intr_handler(struct adapter *adapter) 3162 { 3163 static const struct intr_info ulptx_intr_info[] = { 3164 { PBL_BOUND_ERR_CH3_F, "ULPTX channel 3 PBL out of bounds", -1, 3165 0 }, 3166 { PBL_BOUND_ERR_CH2_F, "ULPTX channel 2 PBL out of bounds", -1, 3167 0 }, 3168 { PBL_BOUND_ERR_CH1_F, "ULPTX channel 1 PBL out of bounds", -1, 3169 0 }, 3170 { PBL_BOUND_ERR_CH0_F, "ULPTX channel 0 PBL out of bounds", -1, 3171 0 }, 3172 { 0xfffffff, "ULPTX parity error", -1, 1 }, 3173 { 0 } 3174 }; 3175 3176 if (t4_handle_intr_status(adapter, ULP_TX_INT_CAUSE_A, ulptx_intr_info)) 3177 t4_fatal_err(adapter); 3178 } 3179 3180 /* 3181 * PM TX interrupt handler. 3182 */ 3183 static void pmtx_intr_handler(struct adapter *adapter) 3184 { 3185 static const struct intr_info pmtx_intr_info[] = { 3186 { PCMD_LEN_OVFL0_F, "PMTX channel 0 pcmd too large", -1, 1 }, 3187 { PCMD_LEN_OVFL1_F, "PMTX channel 1 pcmd too large", -1, 1 }, 3188 { PCMD_LEN_OVFL2_F, "PMTX channel 2 pcmd too large", -1, 1 }, 3189 { ZERO_C_CMD_ERROR_F, "PMTX 0-length pcmd", -1, 1 }, 3190 { PMTX_FRAMING_ERROR_F, "PMTX framing error", -1, 1 }, 3191 { OESPI_PAR_ERROR_F, "PMTX oespi parity error", -1, 1 }, 3192 { DB_OPTIONS_PAR_ERROR_F, "PMTX db_options parity error", 3193 -1, 1 }, 3194 { ICSPI_PAR_ERROR_F, "PMTX icspi parity error", -1, 1 }, 3195 { PMTX_C_PCMD_PAR_ERROR_F, "PMTX c_pcmd parity error", -1, 1}, 3196 { 0 } 3197 }; 3198 3199 if (t4_handle_intr_status(adapter, PM_TX_INT_CAUSE_A, pmtx_intr_info)) 3200 t4_fatal_err(adapter); 3201 } 3202 3203 /* 3204 * PM RX interrupt handler. 3205 */ 3206 static void pmrx_intr_handler(struct adapter *adapter) 3207 { 3208 static const struct intr_info pmrx_intr_info[] = { 3209 { ZERO_E_CMD_ERROR_F, "PMRX 0-length pcmd", -1, 1 }, 3210 { PMRX_FRAMING_ERROR_F, "PMRX framing error", -1, 1 }, 3211 { OCSPI_PAR_ERROR_F, "PMRX ocspi parity error", -1, 1 }, 3212 { DB_OPTIONS_PAR_ERROR_F, "PMRX db_options parity error", 3213 -1, 1 }, 3214 { IESPI_PAR_ERROR_F, "PMRX iespi parity error", -1, 1 }, 3215 { PMRX_E_PCMD_PAR_ERROR_F, "PMRX e_pcmd parity error", -1, 1}, 3216 { 0 } 3217 }; 3218 3219 if (t4_handle_intr_status(adapter, PM_RX_INT_CAUSE_A, pmrx_intr_info)) 3220 t4_fatal_err(adapter); 3221 } 3222 3223 /* 3224 * CPL switch interrupt handler. 3225 */ 3226 static void cplsw_intr_handler(struct adapter *adapter) 3227 { 3228 static const struct intr_info cplsw_intr_info[] = { 3229 { CIM_OP_MAP_PERR_F, "CPLSW CIM op_map parity error", -1, 1 }, 3230 { CIM_OVFL_ERROR_F, "CPLSW CIM overflow", -1, 1 }, 3231 { TP_FRAMING_ERROR_F, "CPLSW TP framing error", -1, 1 }, 3232 { SGE_FRAMING_ERROR_F, "CPLSW SGE framing error", -1, 1 }, 3233 { CIM_FRAMING_ERROR_F, "CPLSW CIM framing error", -1, 1 }, 3234 { ZERO_SWITCH_ERROR_F, "CPLSW no-switch error", -1, 1 }, 3235 { 0 } 3236 }; 3237 3238 if (t4_handle_intr_status(adapter, CPL_INTR_CAUSE_A, cplsw_intr_info)) 3239 t4_fatal_err(adapter); 3240 } 3241 3242 /* 3243 * LE interrupt handler. 3244 */ 3245 static void le_intr_handler(struct adapter *adap) 3246 { 3247 enum chip_type chip = CHELSIO_CHIP_VERSION(adap->params.chip); 3248 static const struct intr_info le_intr_info[] = { 3249 { LIPMISS_F, "LE LIP miss", -1, 0 }, 3250 { LIP0_F, "LE 0 LIP error", -1, 0 }, 3251 { PARITYERR_F, "LE parity error", -1, 1 }, 3252 { UNKNOWNCMD_F, "LE unknown command", -1, 1 }, 3253 { REQQPARERR_F, "LE request queue parity error", -1, 1 }, 3254 { 0 } 3255 }; 3256 3257 static struct intr_info t6_le_intr_info[] = { 3258 { T6_LIPMISS_F, "LE LIP miss", -1, 0 }, 3259 { T6_LIP0_F, "LE 0 LIP error", -1, 0 }, 3260 { TCAMINTPERR_F, "LE parity error", -1, 1 }, 3261 { T6_UNKNOWNCMD_F, "LE unknown command", -1, 1 }, 3262 { SSRAMINTPERR_F, "LE request queue parity error", -1, 1 }, 3263 { 0 } 3264 }; 3265 3266 if (t4_handle_intr_status(adap, LE_DB_INT_CAUSE_A, 3267 (chip <= CHELSIO_T5) ? 3268 le_intr_info : t6_le_intr_info)) 3269 t4_fatal_err(adap); 3270 } 3271 3272 /* 3273 * MPS interrupt handler. 3274 */ 3275 static void mps_intr_handler(struct adapter *adapter) 3276 { 3277 static const struct intr_info mps_rx_intr_info[] = { 3278 { 0xffffff, "MPS Rx parity error", -1, 1 }, 3279 { 0 } 3280 }; 3281 static const struct intr_info mps_tx_intr_info[] = { 3282 { TPFIFO_V(TPFIFO_M), "MPS Tx TP FIFO parity error", -1, 1 }, 3283 { NCSIFIFO_F, "MPS Tx NC-SI FIFO parity error", -1, 1 }, 3284 { TXDATAFIFO_V(TXDATAFIFO_M), "MPS Tx data FIFO parity error", 3285 -1, 1 }, 3286 { TXDESCFIFO_V(TXDESCFIFO_M), "MPS Tx desc FIFO parity error", 3287 -1, 1 }, 3288 { BUBBLE_F, "MPS Tx underflow", -1, 1 }, 3289 { SECNTERR_F, "MPS Tx SOP/EOP error", -1, 1 }, 3290 { FRMERR_F, "MPS Tx framing error", -1, 1 }, 3291 { 0 } 3292 }; 3293 static const struct intr_info mps_trc_intr_info[] = { 3294 { FILTMEM_V(FILTMEM_M), "MPS TRC filter parity error", -1, 1 }, 3295 { PKTFIFO_V(PKTFIFO_M), "MPS TRC packet FIFO parity error", 3296 -1, 1 }, 3297 { MISCPERR_F, "MPS TRC misc parity error", -1, 1 }, 3298 { 0 } 3299 }; 3300 static const struct intr_info mps_stat_sram_intr_info[] = { 3301 { 0x1fffff, "MPS statistics SRAM parity error", -1, 1 }, 3302 { 0 } 3303 }; 3304 static const struct intr_info mps_stat_tx_intr_info[] = { 3305 { 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 }, 3306 { 0 } 3307 }; 3308 static const struct intr_info mps_stat_rx_intr_info[] = { 3309 { 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 }, 3310 { 0 } 3311 }; 3312 static const struct intr_info mps_cls_intr_info[] = { 3313 { MATCHSRAM_F, "MPS match SRAM parity error", -1, 1 }, 3314 { MATCHTCAM_F, "MPS match TCAM parity error", -1, 1 }, 3315 { HASHSRAM_F, "MPS hash SRAM parity error", -1, 1 }, 3316 { 0 } 3317 }; 3318 3319 int fat; 3320 3321 fat = t4_handle_intr_status(adapter, MPS_RX_PERR_INT_CAUSE_A, 3322 mps_rx_intr_info) + 3323 t4_handle_intr_status(adapter, MPS_TX_INT_CAUSE_A, 3324 mps_tx_intr_info) + 3325 t4_handle_intr_status(adapter, MPS_TRC_INT_CAUSE_A, 3326 mps_trc_intr_info) + 3327 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_SRAM_A, 3328 mps_stat_sram_intr_info) + 3329 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_TX_FIFO_A, 3330 mps_stat_tx_intr_info) + 3331 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_RX_FIFO_A, 3332 mps_stat_rx_intr_info) + 3333 t4_handle_intr_status(adapter, MPS_CLS_INT_CAUSE_A, 3334 mps_cls_intr_info); 3335 3336 t4_write_reg(adapter, MPS_INT_CAUSE_A, 0); 3337 t4_read_reg(adapter, MPS_INT_CAUSE_A); /* flush */ 3338 if (fat) 3339 t4_fatal_err(adapter); 3340 } 3341 3342 #define MEM_INT_MASK (PERR_INT_CAUSE_F | ECC_CE_INT_CAUSE_F | \ 3343 ECC_UE_INT_CAUSE_F) 3344 3345 /* 3346 * EDC/MC interrupt handler. 3347 */ 3348 static void mem_intr_handler(struct adapter *adapter, int idx) 3349 { 3350 static const char name[4][7] = { "EDC0", "EDC1", "MC/MC0", "MC1" }; 3351 3352 unsigned int addr, cnt_addr, v; 3353 3354 if (idx <= MEM_EDC1) { 3355 addr = EDC_REG(EDC_INT_CAUSE_A, idx); 3356 cnt_addr = EDC_REG(EDC_ECC_STATUS_A, idx); 3357 } else if (idx == MEM_MC) { 3358 if (is_t4(adapter->params.chip)) { 3359 addr = MC_INT_CAUSE_A; 3360 cnt_addr = MC_ECC_STATUS_A; 3361 } else { 3362 addr = MC_P_INT_CAUSE_A; 3363 cnt_addr = MC_P_ECC_STATUS_A; 3364 } 3365 } else { 3366 addr = MC_REG(MC_P_INT_CAUSE_A, 1); 3367 cnt_addr = MC_REG(MC_P_ECC_STATUS_A, 1); 3368 } 3369 3370 v = t4_read_reg(adapter, addr) & MEM_INT_MASK; 3371 if (v & PERR_INT_CAUSE_F) 3372 dev_alert(adapter->pdev_dev, "%s FIFO parity error\n", 3373 name[idx]); 3374 if (v & ECC_CE_INT_CAUSE_F) { 3375 u32 cnt = ECC_CECNT_G(t4_read_reg(adapter, cnt_addr)); 3376 3377 t4_edc_err_read(adapter, idx); 3378 3379 t4_write_reg(adapter, cnt_addr, ECC_CECNT_V(ECC_CECNT_M)); 3380 if (printk_ratelimit()) 3381 dev_warn(adapter->pdev_dev, 3382 "%u %s correctable ECC data error%s\n", 3383 cnt, name[idx], cnt > 1 ? "s" : ""); 3384 } 3385 if (v & ECC_UE_INT_CAUSE_F) 3386 dev_alert(adapter->pdev_dev, 3387 "%s uncorrectable ECC data error\n", name[idx]); 3388 3389 t4_write_reg(adapter, addr, v); 3390 if (v & (PERR_INT_CAUSE_F | ECC_UE_INT_CAUSE_F)) 3391 t4_fatal_err(adapter); 3392 } 3393 3394 /* 3395 * MA interrupt handler. 3396 */ 3397 static void ma_intr_handler(struct adapter *adap) 3398 { 3399 u32 v, status = t4_read_reg(adap, MA_INT_CAUSE_A); 3400 3401 if (status & MEM_PERR_INT_CAUSE_F) { 3402 dev_alert(adap->pdev_dev, 3403 "MA parity error, parity status %#x\n", 3404 t4_read_reg(adap, MA_PARITY_ERROR_STATUS1_A)); 3405 if (is_t5(adap->params.chip)) 3406 dev_alert(adap->pdev_dev, 3407 "MA parity error, parity status %#x\n", 3408 t4_read_reg(adap, 3409 MA_PARITY_ERROR_STATUS2_A)); 3410 } 3411 if (status & MEM_WRAP_INT_CAUSE_F) { 3412 v = t4_read_reg(adap, MA_INT_WRAP_STATUS_A); 3413 dev_alert(adap->pdev_dev, "MA address wrap-around error by " 3414 "client %u to address %#x\n", 3415 MEM_WRAP_CLIENT_NUM_G(v), 3416 MEM_WRAP_ADDRESS_G(v) << 4); 3417 } 3418 t4_write_reg(adap, MA_INT_CAUSE_A, status); 3419 t4_fatal_err(adap); 3420 } 3421 3422 /* 3423 * SMB interrupt handler. 3424 */ 3425 static void smb_intr_handler(struct adapter *adap) 3426 { 3427 static const struct intr_info smb_intr_info[] = { 3428 { MSTTXFIFOPARINT_F, "SMB master Tx FIFO parity error", -1, 1 }, 3429 { MSTRXFIFOPARINT_F, "SMB master Rx FIFO parity error", -1, 1 }, 3430 { SLVFIFOPARINT_F, "SMB slave FIFO parity error", -1, 1 }, 3431 { 0 } 3432 }; 3433 3434 if (t4_handle_intr_status(adap, SMB_INT_CAUSE_A, smb_intr_info)) 3435 t4_fatal_err(adap); 3436 } 3437 3438 /* 3439 * NC-SI interrupt handler. 3440 */ 3441 static void ncsi_intr_handler(struct adapter *adap) 3442 { 3443 static const struct intr_info ncsi_intr_info[] = { 3444 { CIM_DM_PRTY_ERR_F, "NC-SI CIM parity error", -1, 1 }, 3445 { MPS_DM_PRTY_ERR_F, "NC-SI MPS parity error", -1, 1 }, 3446 { TXFIFO_PRTY_ERR_F, "NC-SI Tx FIFO parity error", -1, 1 }, 3447 { RXFIFO_PRTY_ERR_F, "NC-SI Rx FIFO parity error", -1, 1 }, 3448 { 0 } 3449 }; 3450 3451 if (t4_handle_intr_status(adap, NCSI_INT_CAUSE_A, ncsi_intr_info)) 3452 t4_fatal_err(adap); 3453 } 3454 3455 /* 3456 * XGMAC interrupt handler. 3457 */ 3458 static void xgmac_intr_handler(struct adapter *adap, int port) 3459 { 3460 u32 v, int_cause_reg; 3461 3462 if (is_t4(adap->params.chip)) 3463 int_cause_reg = PORT_REG(port, XGMAC_PORT_INT_CAUSE_A); 3464 else 3465 int_cause_reg = T5_PORT_REG(port, MAC_PORT_INT_CAUSE_A); 3466 3467 v = t4_read_reg(adap, int_cause_reg); 3468 3469 v &= TXFIFO_PRTY_ERR_F | RXFIFO_PRTY_ERR_F; 3470 if (!v) 3471 return; 3472 3473 if (v & TXFIFO_PRTY_ERR_F) 3474 dev_alert(adap->pdev_dev, "XGMAC %d Tx FIFO parity error\n", 3475 port); 3476 if (v & RXFIFO_PRTY_ERR_F) 3477 dev_alert(adap->pdev_dev, "XGMAC %d Rx FIFO parity error\n", 3478 port); 3479 t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_INT_CAUSE_A), v); 3480 t4_fatal_err(adap); 3481 } 3482 3483 /* 3484 * PL interrupt handler. 3485 */ 3486 static void pl_intr_handler(struct adapter *adap) 3487 { 3488 static const struct intr_info pl_intr_info[] = { 3489 { FATALPERR_F, "T4 fatal parity error", -1, 1 }, 3490 { PERRVFID_F, "PL VFID_MAP parity error", -1, 1 }, 3491 { 0 } 3492 }; 3493 3494 if (t4_handle_intr_status(adap, PL_PL_INT_CAUSE_A, pl_intr_info)) 3495 t4_fatal_err(adap); 3496 } 3497 3498 #define PF_INTR_MASK (PFSW_F) 3499 #define GLBL_INTR_MASK (CIM_F | MPS_F | PL_F | PCIE_F | MC_F | EDC0_F | \ 3500 EDC1_F | LE_F | TP_F | MA_F | PM_TX_F | PM_RX_F | ULP_RX_F | \ 3501 CPL_SWITCH_F | SGE_F | ULP_TX_F) 3502 3503 /** 3504 * t4_slow_intr_handler - control path interrupt handler 3505 * @adapter: the adapter 3506 * 3507 * T4 interrupt handler for non-data global interrupt events, e.g., errors. 3508 * The designation 'slow' is because it involves register reads, while 3509 * data interrupts typically don't involve any MMIOs. 3510 */ 3511 int t4_slow_intr_handler(struct adapter *adapter) 3512 { 3513 u32 cause = t4_read_reg(adapter, PL_INT_CAUSE_A); 3514 3515 if (!(cause & GLBL_INTR_MASK)) 3516 return 0; 3517 if (cause & CIM_F) 3518 cim_intr_handler(adapter); 3519 if (cause & MPS_F) 3520 mps_intr_handler(adapter); 3521 if (cause & NCSI_F) 3522 ncsi_intr_handler(adapter); 3523 if (cause & PL_F) 3524 pl_intr_handler(adapter); 3525 if (cause & SMB_F) 3526 smb_intr_handler(adapter); 3527 if (cause & XGMAC0_F) 3528 xgmac_intr_handler(adapter, 0); 3529 if (cause & XGMAC1_F) 3530 xgmac_intr_handler(adapter, 1); 3531 if (cause & XGMAC_KR0_F) 3532 xgmac_intr_handler(adapter, 2); 3533 if (cause & XGMAC_KR1_F) 3534 xgmac_intr_handler(adapter, 3); 3535 if (cause & PCIE_F) 3536 pcie_intr_handler(adapter); 3537 if (cause & MC_F) 3538 mem_intr_handler(adapter, MEM_MC); 3539 if (is_t5(adapter->params.chip) && (cause & MC1_F)) 3540 mem_intr_handler(adapter, MEM_MC1); 3541 if (cause & EDC0_F) 3542 mem_intr_handler(adapter, MEM_EDC0); 3543 if (cause & EDC1_F) 3544 mem_intr_handler(adapter, MEM_EDC1); 3545 if (cause & LE_F) 3546 le_intr_handler(adapter); 3547 if (cause & TP_F) 3548 tp_intr_handler(adapter); 3549 if (cause & MA_F) 3550 ma_intr_handler(adapter); 3551 if (cause & PM_TX_F) 3552 pmtx_intr_handler(adapter); 3553 if (cause & PM_RX_F) 3554 pmrx_intr_handler(adapter); 3555 if (cause & ULP_RX_F) 3556 ulprx_intr_handler(adapter); 3557 if (cause & CPL_SWITCH_F) 3558 cplsw_intr_handler(adapter); 3559 if (cause & SGE_F) 3560 sge_intr_handler(adapter); 3561 if (cause & ULP_TX_F) 3562 ulptx_intr_handler(adapter); 3563 3564 /* Clear the interrupts just processed for which we are the master. */ 3565 t4_write_reg(adapter, PL_INT_CAUSE_A, cause & GLBL_INTR_MASK); 3566 (void)t4_read_reg(adapter, PL_INT_CAUSE_A); /* flush */ 3567 return 1; 3568 } 3569 3570 /** 3571 * t4_intr_enable - enable interrupts 3572 * @adapter: the adapter whose interrupts should be enabled 3573 * 3574 * Enable PF-specific interrupts for the calling function and the top-level 3575 * interrupt concentrator for global interrupts. Interrupts are already 3576 * enabled at each module, here we just enable the roots of the interrupt 3577 * hierarchies. 3578 * 3579 * Note: this function should be called only when the driver manages 3580 * non PF-specific interrupts from the various HW modules. Only one PCI 3581 * function at a time should be doing this. 3582 */ 3583 void t4_intr_enable(struct adapter *adapter) 3584 { 3585 u32 val = 0; 3586 u32 whoami = t4_read_reg(adapter, PL_WHOAMI_A); 3587 u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ? 3588 SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami); 3589 3590 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) 3591 val = ERR_DROPPED_DB_F | ERR_EGR_CTXT_PRIO_F | DBFIFO_HP_INT_F; 3592 t4_write_reg(adapter, SGE_INT_ENABLE3_A, ERR_CPL_EXCEED_IQE_SIZE_F | 3593 ERR_INVALID_CIDX_INC_F | ERR_CPL_OPCODE_0_F | 3594 ERR_DATA_CPL_ON_HIGH_QID1_F | INGRESS_SIZE_ERR_F | 3595 ERR_DATA_CPL_ON_HIGH_QID0_F | ERR_BAD_DB_PIDX3_F | 3596 ERR_BAD_DB_PIDX2_F | ERR_BAD_DB_PIDX1_F | 3597 ERR_BAD_DB_PIDX0_F | ERR_ING_CTXT_PRIO_F | 3598 DBFIFO_LP_INT_F | EGRESS_SIZE_ERR_F | val); 3599 t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), PF_INTR_MASK); 3600 t4_set_reg_field(adapter, PL_INT_MAP0_A, 0, 1 << pf); 3601 } 3602 3603 /** 3604 * t4_intr_disable - disable interrupts 3605 * @adapter: the adapter whose interrupts should be disabled 3606 * 3607 * Disable interrupts. We only disable the top-level interrupt 3608 * concentrators. The caller must be a PCI function managing global 3609 * interrupts. 3610 */ 3611 void t4_intr_disable(struct adapter *adapter) 3612 { 3613 u32 whoami = t4_read_reg(adapter, PL_WHOAMI_A); 3614 u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ? 3615 SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami); 3616 3617 t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), 0); 3618 t4_set_reg_field(adapter, PL_INT_MAP0_A, 1 << pf, 0); 3619 } 3620 3621 /** 3622 * hash_mac_addr - return the hash value of a MAC address 3623 * @addr: the 48-bit Ethernet MAC address 3624 * 3625 * Hashes a MAC address according to the hash function used by HW inexact 3626 * (hash) address matching. 3627 */ 3628 static int hash_mac_addr(const u8 *addr) 3629 { 3630 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2]; 3631 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5]; 3632 a ^= b; 3633 a ^= (a >> 12); 3634 a ^= (a >> 6); 3635 return a & 0x3f; 3636 } 3637 3638 /** 3639 * t4_config_rss_range - configure a portion of the RSS mapping table 3640 * @adapter: the adapter 3641 * @mbox: mbox to use for the FW command 3642 * @viid: virtual interface whose RSS subtable is to be written 3643 * @start: start entry in the table to write 3644 * @n: how many table entries to write 3645 * @rspq: values for the response queue lookup table 3646 * @nrspq: number of values in @rspq 3647 * 3648 * Programs the selected part of the VI's RSS mapping table with the 3649 * provided values. If @nrspq < @n the supplied values are used repeatedly 3650 * until the full table range is populated. 3651 * 3652 * The caller must ensure the values in @rspq are in the range allowed for 3653 * @viid. 3654 */ 3655 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 3656 int start, int n, const u16 *rspq, unsigned int nrspq) 3657 { 3658 int ret; 3659 const u16 *rsp = rspq; 3660 const u16 *rsp_end = rspq + nrspq; 3661 struct fw_rss_ind_tbl_cmd cmd; 3662 3663 memset(&cmd, 0, sizeof(cmd)); 3664 cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_IND_TBL_CMD) | 3665 FW_CMD_REQUEST_F | FW_CMD_WRITE_F | 3666 FW_RSS_IND_TBL_CMD_VIID_V(viid)); 3667 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 3668 3669 /* each fw_rss_ind_tbl_cmd takes up to 32 entries */ 3670 while (n > 0) { 3671 int nq = min(n, 32); 3672 __be32 *qp = &cmd.iq0_to_iq2; 3673 3674 cmd.niqid = cpu_to_be16(nq); 3675 cmd.startidx = cpu_to_be16(start); 3676 3677 start += nq; 3678 n -= nq; 3679 3680 while (nq > 0) { 3681 unsigned int v; 3682 3683 v = FW_RSS_IND_TBL_CMD_IQ0_V(*rsp); 3684 if (++rsp >= rsp_end) 3685 rsp = rspq; 3686 v |= FW_RSS_IND_TBL_CMD_IQ1_V(*rsp); 3687 if (++rsp >= rsp_end) 3688 rsp = rspq; 3689 v |= FW_RSS_IND_TBL_CMD_IQ2_V(*rsp); 3690 if (++rsp >= rsp_end) 3691 rsp = rspq; 3692 3693 *qp++ = cpu_to_be32(v); 3694 nq -= 3; 3695 } 3696 3697 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL); 3698 if (ret) 3699 return ret; 3700 } 3701 return 0; 3702 } 3703 3704 /** 3705 * t4_config_glbl_rss - configure the global RSS mode 3706 * @adapter: the adapter 3707 * @mbox: mbox to use for the FW command 3708 * @mode: global RSS mode 3709 * @flags: mode-specific flags 3710 * 3711 * Sets the global RSS mode. 3712 */ 3713 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 3714 unsigned int flags) 3715 { 3716 struct fw_rss_glb_config_cmd c; 3717 3718 memset(&c, 0, sizeof(c)); 3719 c.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_RSS_GLB_CONFIG_CMD) | 3720 FW_CMD_REQUEST_F | FW_CMD_WRITE_F); 3721 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 3722 if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) { 3723 c.u.manual.mode_pkd = 3724 cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode)); 3725 } else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) { 3726 c.u.basicvirtual.mode_pkd = 3727 cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode)); 3728 c.u.basicvirtual.synmapen_to_hashtoeplitz = cpu_to_be32(flags); 3729 } else 3730 return -EINVAL; 3731 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL); 3732 } 3733 3734 /** 3735 * t4_config_vi_rss - configure per VI RSS settings 3736 * @adapter: the adapter 3737 * @mbox: mbox to use for the FW command 3738 * @viid: the VI id 3739 * @flags: RSS flags 3740 * @defq: id of the default RSS queue for the VI. 3741 * 3742 * Configures VI-specific RSS properties. 3743 */ 3744 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 3745 unsigned int flags, unsigned int defq) 3746 { 3747 struct fw_rss_vi_config_cmd c; 3748 3749 memset(&c, 0, sizeof(c)); 3750 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) | 3751 FW_CMD_REQUEST_F | FW_CMD_WRITE_F | 3752 FW_RSS_VI_CONFIG_CMD_VIID_V(viid)); 3753 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 3754 c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags | 3755 FW_RSS_VI_CONFIG_CMD_DEFAULTQ_V(defq)); 3756 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL); 3757 } 3758 3759 /* Read an RSS table row */ 3760 static int rd_rss_row(struct adapter *adap, int row, u32 *val) 3761 { 3762 t4_write_reg(adap, TP_RSS_LKP_TABLE_A, 0xfff00000 | row); 3763 return t4_wait_op_done_val(adap, TP_RSS_LKP_TABLE_A, LKPTBLROWVLD_F, 1, 3764 5, 0, val); 3765 } 3766 3767 /** 3768 * t4_read_rss - read the contents of the RSS mapping table 3769 * @adapter: the adapter 3770 * @map: holds the contents of the RSS mapping table 3771 * 3772 * Reads the contents of the RSS hash->queue mapping table. 3773 */ 3774 int t4_read_rss(struct adapter *adapter, u16 *map) 3775 { 3776 u32 val; 3777 int i, ret; 3778 3779 for (i = 0; i < RSS_NENTRIES / 2; ++i) { 3780 ret = rd_rss_row(adapter, i, &val); 3781 if (ret) 3782 return ret; 3783 *map++ = LKPTBLQUEUE0_G(val); 3784 *map++ = LKPTBLQUEUE1_G(val); 3785 } 3786 return 0; 3787 } 3788 3789 static unsigned int t4_use_ldst(struct adapter *adap) 3790 { 3791 return (adap->flags & FW_OK) || !adap->use_bd; 3792 } 3793 3794 /** 3795 * t4_fw_tp_pio_rw - Access TP PIO through LDST 3796 * @adap: the adapter 3797 * @vals: where the indirect register values are stored/written 3798 * @nregs: how many indirect registers to read/write 3799 * @start_idx: index of first indirect register to read/write 3800 * @rw: Read (1) or Write (0) 3801 * 3802 * Access TP PIO registers through LDST 3803 */ 3804 static void t4_fw_tp_pio_rw(struct adapter *adap, u32 *vals, unsigned int nregs, 3805 unsigned int start_index, unsigned int rw) 3806 { 3807 int ret, i; 3808 int cmd = FW_LDST_ADDRSPC_TP_PIO; 3809 struct fw_ldst_cmd c; 3810 3811 for (i = 0 ; i < nregs; i++) { 3812 memset(&c, 0, sizeof(c)); 3813 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) | 3814 FW_CMD_REQUEST_F | 3815 (rw ? FW_CMD_READ_F : 3816 FW_CMD_WRITE_F) | 3817 FW_LDST_CMD_ADDRSPACE_V(cmd)); 3818 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 3819 3820 c.u.addrval.addr = cpu_to_be32(start_index + i); 3821 c.u.addrval.val = rw ? 0 : cpu_to_be32(vals[i]); 3822 ret = t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), &c); 3823 if (!ret && rw) 3824 vals[i] = be32_to_cpu(c.u.addrval.val); 3825 } 3826 } 3827 3828 /** 3829 * t4_read_rss_key - read the global RSS key 3830 * @adap: the adapter 3831 * @key: 10-entry array holding the 320-bit RSS key 3832 * 3833 * Reads the global 320-bit RSS key. 3834 */ 3835 void t4_read_rss_key(struct adapter *adap, u32 *key) 3836 { 3837 if (t4_use_ldst(adap)) 3838 t4_fw_tp_pio_rw(adap, key, 10, TP_RSS_SECRET_KEY0_A, 1); 3839 else 3840 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, key, 10, 3841 TP_RSS_SECRET_KEY0_A); 3842 } 3843 3844 /** 3845 * t4_write_rss_key - program one of the RSS keys 3846 * @adap: the adapter 3847 * @key: 10-entry array holding the 320-bit RSS key 3848 * @idx: which RSS key to write 3849 * 3850 * Writes one of the RSS keys with the given 320-bit value. If @idx is 3851 * 0..15 the corresponding entry in the RSS key table is written, 3852 * otherwise the global RSS key is written. 3853 */ 3854 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx) 3855 { 3856 u8 rss_key_addr_cnt = 16; 3857 u32 vrt = t4_read_reg(adap, TP_RSS_CONFIG_VRT_A); 3858 3859 /* T6 and later: for KeyMode 3 (per-vf and per-vf scramble), 3860 * allows access to key addresses 16-63 by using KeyWrAddrX 3861 * as index[5:4](upper 2) into key table 3862 */ 3863 if ((CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) && 3864 (vrt & KEYEXTEND_F) && (KEYMODE_G(vrt) == 3)) 3865 rss_key_addr_cnt = 32; 3866 3867 if (t4_use_ldst(adap)) 3868 t4_fw_tp_pio_rw(adap, (void *)key, 10, TP_RSS_SECRET_KEY0_A, 0); 3869 else 3870 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, key, 10, 3871 TP_RSS_SECRET_KEY0_A); 3872 3873 if (idx >= 0 && idx < rss_key_addr_cnt) { 3874 if (rss_key_addr_cnt > 16) 3875 t4_write_reg(adap, TP_RSS_CONFIG_VRT_A, 3876 KEYWRADDRX_V(idx >> 4) | 3877 T6_VFWRADDR_V(idx) | KEYWREN_F); 3878 else 3879 t4_write_reg(adap, TP_RSS_CONFIG_VRT_A, 3880 KEYWRADDR_V(idx) | KEYWREN_F); 3881 } 3882 } 3883 3884 /** 3885 * t4_read_rss_pf_config - read PF RSS Configuration Table 3886 * @adapter: the adapter 3887 * @index: the entry in the PF RSS table to read 3888 * @valp: where to store the returned value 3889 * 3890 * Reads the PF RSS Configuration Table at the specified index and returns 3891 * the value found there. 3892 */ 3893 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, 3894 u32 *valp) 3895 { 3896 if (t4_use_ldst(adapter)) 3897 t4_fw_tp_pio_rw(adapter, valp, 1, 3898 TP_RSS_PF0_CONFIG_A + index, 1); 3899 else 3900 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A, 3901 valp, 1, TP_RSS_PF0_CONFIG_A + index); 3902 } 3903 3904 /** 3905 * t4_read_rss_vf_config - read VF RSS Configuration Table 3906 * @adapter: the adapter 3907 * @index: the entry in the VF RSS table to read 3908 * @vfl: where to store the returned VFL 3909 * @vfh: where to store the returned VFH 3910 * 3911 * Reads the VF RSS Configuration Table at the specified index and returns 3912 * the (VFL, VFH) values found there. 3913 */ 3914 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 3915 u32 *vfl, u32 *vfh) 3916 { 3917 u32 vrt, mask, data; 3918 3919 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) { 3920 mask = VFWRADDR_V(VFWRADDR_M); 3921 data = VFWRADDR_V(index); 3922 } else { 3923 mask = T6_VFWRADDR_V(T6_VFWRADDR_M); 3924 data = T6_VFWRADDR_V(index); 3925 } 3926 3927 /* Request that the index'th VF Table values be read into VFL/VFH. 3928 */ 3929 vrt = t4_read_reg(adapter, TP_RSS_CONFIG_VRT_A); 3930 vrt &= ~(VFRDRG_F | VFWREN_F | KEYWREN_F | mask); 3931 vrt |= data | VFRDEN_F; 3932 t4_write_reg(adapter, TP_RSS_CONFIG_VRT_A, vrt); 3933 3934 /* Grab the VFL/VFH values ... 3935 */ 3936 if (t4_use_ldst(adapter)) { 3937 t4_fw_tp_pio_rw(adapter, vfl, 1, TP_RSS_VFL_CONFIG_A, 1); 3938 t4_fw_tp_pio_rw(adapter, vfh, 1, TP_RSS_VFH_CONFIG_A, 1); 3939 } else { 3940 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A, 3941 vfl, 1, TP_RSS_VFL_CONFIG_A); 3942 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A, 3943 vfh, 1, TP_RSS_VFH_CONFIG_A); 3944 } 3945 } 3946 3947 /** 3948 * t4_read_rss_pf_map - read PF RSS Map 3949 * @adapter: the adapter 3950 * 3951 * Reads the PF RSS Map register and returns its value. 3952 */ 3953 u32 t4_read_rss_pf_map(struct adapter *adapter) 3954 { 3955 u32 pfmap; 3956 3957 if (t4_use_ldst(adapter)) 3958 t4_fw_tp_pio_rw(adapter, &pfmap, 1, TP_RSS_PF_MAP_A, 1); 3959 else 3960 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A, 3961 &pfmap, 1, TP_RSS_PF_MAP_A); 3962 return pfmap; 3963 } 3964 3965 /** 3966 * t4_read_rss_pf_mask - read PF RSS Mask 3967 * @adapter: the adapter 3968 * 3969 * Reads the PF RSS Mask register and returns its value. 3970 */ 3971 u32 t4_read_rss_pf_mask(struct adapter *adapter) 3972 { 3973 u32 pfmask; 3974 3975 if (t4_use_ldst(adapter)) 3976 t4_fw_tp_pio_rw(adapter, &pfmask, 1, TP_RSS_PF_MSK_A, 1); 3977 else 3978 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A, 3979 &pfmask, 1, TP_RSS_PF_MSK_A); 3980 return pfmask; 3981 } 3982 3983 /** 3984 * t4_tp_get_tcp_stats - read TP's TCP MIB counters 3985 * @adap: the adapter 3986 * @v4: holds the TCP/IP counter values 3987 * @v6: holds the TCP/IPv6 counter values 3988 * 3989 * Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters. 3990 * Either @v4 or @v6 may be %NULL to skip the corresponding stats. 3991 */ 3992 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 3993 struct tp_tcp_stats *v6) 3994 { 3995 u32 val[TP_MIB_TCP_RXT_SEG_LO_A - TP_MIB_TCP_OUT_RST_A + 1]; 3996 3997 #define STAT_IDX(x) ((TP_MIB_TCP_##x##_A) - TP_MIB_TCP_OUT_RST_A) 3998 #define STAT(x) val[STAT_IDX(x)] 3999 #define STAT64(x) (((u64)STAT(x##_HI) << 32) | STAT(x##_LO)) 4000 4001 if (v4) { 4002 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val, 4003 ARRAY_SIZE(val), TP_MIB_TCP_OUT_RST_A); 4004 v4->tcp_out_rsts = STAT(OUT_RST); 4005 v4->tcp_in_segs = STAT64(IN_SEG); 4006 v4->tcp_out_segs = STAT64(OUT_SEG); 4007 v4->tcp_retrans_segs = STAT64(RXT_SEG); 4008 } 4009 if (v6) { 4010 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val, 4011 ARRAY_SIZE(val), TP_MIB_TCP_V6OUT_RST_A); 4012 v6->tcp_out_rsts = STAT(OUT_RST); 4013 v6->tcp_in_segs = STAT64(IN_SEG); 4014 v6->tcp_out_segs = STAT64(OUT_SEG); 4015 v6->tcp_retrans_segs = STAT64(RXT_SEG); 4016 } 4017 #undef STAT64 4018 #undef STAT 4019 #undef STAT_IDX 4020 } 4021 4022 /** 4023 * t4_tp_get_err_stats - read TP's error MIB counters 4024 * @adap: the adapter 4025 * @st: holds the counter values 4026 * 4027 * Returns the values of TP's error counters. 4028 */ 4029 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st) 4030 { 4031 int nchan = adap->params.arch.nchan; 4032 4033 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, 4034 st->mac_in_errs, nchan, TP_MIB_MAC_IN_ERR_0_A); 4035 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, 4036 st->hdr_in_errs, nchan, TP_MIB_HDR_IN_ERR_0_A); 4037 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, 4038 st->tcp_in_errs, nchan, TP_MIB_TCP_IN_ERR_0_A); 4039 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, 4040 st->tnl_cong_drops, nchan, TP_MIB_TNL_CNG_DROP_0_A); 4041 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, 4042 st->ofld_chan_drops, nchan, TP_MIB_OFD_CHN_DROP_0_A); 4043 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, 4044 st->tnl_tx_drops, nchan, TP_MIB_TNL_DROP_0_A); 4045 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, 4046 st->ofld_vlan_drops, nchan, TP_MIB_OFD_VLN_DROP_0_A); 4047 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, 4048 st->tcp6_in_errs, nchan, TP_MIB_TCP_V6IN_ERR_0_A); 4049 4050 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, 4051 &st->ofld_no_neigh, 2, TP_MIB_OFD_ARP_DROP_A); 4052 } 4053 4054 /** 4055 * t4_tp_get_cpl_stats - read TP's CPL MIB counters 4056 * @adap: the adapter 4057 * @st: holds the counter values 4058 * 4059 * Returns the values of TP's CPL counters. 4060 */ 4061 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st) 4062 { 4063 int nchan = adap->params.arch.nchan; 4064 4065 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, st->req, 4066 nchan, TP_MIB_CPL_IN_REQ_0_A); 4067 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, st->rsp, 4068 nchan, TP_MIB_CPL_OUT_RSP_0_A); 4069 4070 } 4071 4072 /** 4073 * t4_tp_get_rdma_stats - read TP's RDMA MIB counters 4074 * @adap: the adapter 4075 * @st: holds the counter values 4076 * 4077 * Returns the values of TP's RDMA counters. 4078 */ 4079 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st) 4080 { 4081 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->rqe_dfr_pkt, 4082 2, TP_MIB_RQE_DFR_PKT_A); 4083 } 4084 4085 /** 4086 * t4_get_fcoe_stats - read TP's FCoE MIB counters for a port 4087 * @adap: the adapter 4088 * @idx: the port index 4089 * @st: holds the counter values 4090 * 4091 * Returns the values of TP's FCoE counters for the selected port. 4092 */ 4093 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 4094 struct tp_fcoe_stats *st) 4095 { 4096 u32 val[2]; 4097 4098 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->frames_ddp, 4099 1, TP_MIB_FCOE_DDP_0_A + idx); 4100 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->frames_drop, 4101 1, TP_MIB_FCOE_DROP_0_A + idx); 4102 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val, 4103 2, TP_MIB_FCOE_BYTE_0_HI_A + 2 * idx); 4104 st->octets_ddp = ((u64)val[0] << 32) | val[1]; 4105 } 4106 4107 /** 4108 * t4_get_usm_stats - read TP's non-TCP DDP MIB counters 4109 * @adap: the adapter 4110 * @st: holds the counter values 4111 * 4112 * Returns the values of TP's counters for non-TCP directly-placed packets. 4113 */ 4114 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st) 4115 { 4116 u32 val[4]; 4117 4118 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val, 4, 4119 TP_MIB_USM_PKTS_A); 4120 st->frames = val[0]; 4121 st->drops = val[1]; 4122 st->octets = ((u64)val[2] << 32) | val[3]; 4123 } 4124 4125 /** 4126 * t4_read_mtu_tbl - returns the values in the HW path MTU table 4127 * @adap: the adapter 4128 * @mtus: where to store the MTU values 4129 * @mtu_log: where to store the MTU base-2 log (may be %NULL) 4130 * 4131 * Reads the HW path MTU table. 4132 */ 4133 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log) 4134 { 4135 u32 v; 4136 int i; 4137 4138 for (i = 0; i < NMTUS; ++i) { 4139 t4_write_reg(adap, TP_MTU_TABLE_A, 4140 MTUINDEX_V(0xff) | MTUVALUE_V(i)); 4141 v = t4_read_reg(adap, TP_MTU_TABLE_A); 4142 mtus[i] = MTUVALUE_G(v); 4143 if (mtu_log) 4144 mtu_log[i] = MTUWIDTH_G(v); 4145 } 4146 } 4147 4148 /** 4149 * t4_read_cong_tbl - reads the congestion control table 4150 * @adap: the adapter 4151 * @incr: where to store the alpha values 4152 * 4153 * Reads the additive increments programmed into the HW congestion 4154 * control table. 4155 */ 4156 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]) 4157 { 4158 unsigned int mtu, w; 4159 4160 for (mtu = 0; mtu < NMTUS; ++mtu) 4161 for (w = 0; w < NCCTRL_WIN; ++w) { 4162 t4_write_reg(adap, TP_CCTRL_TABLE_A, 4163 ROWINDEX_V(0xffff) | (mtu << 5) | w); 4164 incr[mtu][w] = (u16)t4_read_reg(adap, 4165 TP_CCTRL_TABLE_A) & 0x1fff; 4166 } 4167 } 4168 4169 /** 4170 * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register 4171 * @adap: the adapter 4172 * @addr: the indirect TP register address 4173 * @mask: specifies the field within the register to modify 4174 * @val: new value for the field 4175 * 4176 * Sets a field of an indirect TP register to the given value. 4177 */ 4178 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 4179 unsigned int mask, unsigned int val) 4180 { 4181 t4_write_reg(adap, TP_PIO_ADDR_A, addr); 4182 val |= t4_read_reg(adap, TP_PIO_DATA_A) & ~mask; 4183 t4_write_reg(adap, TP_PIO_DATA_A, val); 4184 } 4185 4186 /** 4187 * init_cong_ctrl - initialize congestion control parameters 4188 * @a: the alpha values for congestion control 4189 * @b: the beta values for congestion control 4190 * 4191 * Initialize the congestion control parameters. 4192 */ 4193 static void init_cong_ctrl(unsigned short *a, unsigned short *b) 4194 { 4195 a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1; 4196 a[9] = 2; 4197 a[10] = 3; 4198 a[11] = 4; 4199 a[12] = 5; 4200 a[13] = 6; 4201 a[14] = 7; 4202 a[15] = 8; 4203 a[16] = 9; 4204 a[17] = 10; 4205 a[18] = 14; 4206 a[19] = 17; 4207 a[20] = 21; 4208 a[21] = 25; 4209 a[22] = 30; 4210 a[23] = 35; 4211 a[24] = 45; 4212 a[25] = 60; 4213 a[26] = 80; 4214 a[27] = 100; 4215 a[28] = 200; 4216 a[29] = 300; 4217 a[30] = 400; 4218 a[31] = 500; 4219 4220 b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0; 4221 b[9] = b[10] = 1; 4222 b[11] = b[12] = 2; 4223 b[13] = b[14] = b[15] = b[16] = 3; 4224 b[17] = b[18] = b[19] = b[20] = b[21] = 4; 4225 b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5; 4226 b[28] = b[29] = 6; 4227 b[30] = b[31] = 7; 4228 } 4229 4230 /* The minimum additive increment value for the congestion control table */ 4231 #define CC_MIN_INCR 2U 4232 4233 /** 4234 * t4_load_mtus - write the MTU and congestion control HW tables 4235 * @adap: the adapter 4236 * @mtus: the values for the MTU table 4237 * @alpha: the values for the congestion control alpha parameter 4238 * @beta: the values for the congestion control beta parameter 4239 * 4240 * Write the HW MTU table with the supplied MTUs and the high-speed 4241 * congestion control table with the supplied alpha, beta, and MTUs. 4242 * We write the two tables together because the additive increments 4243 * depend on the MTUs. 4244 */ 4245 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 4246 const unsigned short *alpha, const unsigned short *beta) 4247 { 4248 static const unsigned int avg_pkts[NCCTRL_WIN] = { 4249 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640, 4250 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480, 4251 28672, 40960, 57344, 81920, 114688, 163840, 229376 4252 }; 4253 4254 unsigned int i, w; 4255 4256 for (i = 0; i < NMTUS; ++i) { 4257 unsigned int mtu = mtus[i]; 4258 unsigned int log2 = fls(mtu); 4259 4260 if (!(mtu & ((1 << log2) >> 2))) /* round */ 4261 log2--; 4262 t4_write_reg(adap, TP_MTU_TABLE_A, MTUINDEX_V(i) | 4263 MTUWIDTH_V(log2) | MTUVALUE_V(mtu)); 4264 4265 for (w = 0; w < NCCTRL_WIN; ++w) { 4266 unsigned int inc; 4267 4268 inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w], 4269 CC_MIN_INCR); 4270 4271 t4_write_reg(adap, TP_CCTRL_TABLE_A, (i << 21) | 4272 (w << 16) | (beta[w] << 13) | inc); 4273 } 4274 } 4275 } 4276 4277 /* Calculates a rate in bytes/s given the number of 256-byte units per 4K core 4278 * clocks. The formula is 4279 * 4280 * bytes/s = bytes256 * 256 * ClkFreq / 4096 4281 * 4282 * which is equivalent to 4283 * 4284 * bytes/s = 62.5 * bytes256 * ClkFreq_ms 4285 */ 4286 static u64 chan_rate(struct adapter *adap, unsigned int bytes256) 4287 { 4288 u64 v = bytes256 * adap->params.vpd.cclk; 4289 4290 return v * 62 + v / 2; 4291 } 4292 4293 /** 4294 * t4_get_chan_txrate - get the current per channel Tx rates 4295 * @adap: the adapter 4296 * @nic_rate: rates for NIC traffic 4297 * @ofld_rate: rates for offloaded traffic 4298 * 4299 * Return the current Tx rates in bytes/s for NIC and offloaded traffic 4300 * for each channel. 4301 */ 4302 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate) 4303 { 4304 u32 v; 4305 4306 v = t4_read_reg(adap, TP_TX_TRATE_A); 4307 nic_rate[0] = chan_rate(adap, TNLRATE0_G(v)); 4308 nic_rate[1] = chan_rate(adap, TNLRATE1_G(v)); 4309 if (adap->params.arch.nchan == NCHAN) { 4310 nic_rate[2] = chan_rate(adap, TNLRATE2_G(v)); 4311 nic_rate[3] = chan_rate(adap, TNLRATE3_G(v)); 4312 } 4313 4314 v = t4_read_reg(adap, TP_TX_ORATE_A); 4315 ofld_rate[0] = chan_rate(adap, OFDRATE0_G(v)); 4316 ofld_rate[1] = chan_rate(adap, OFDRATE1_G(v)); 4317 if (adap->params.arch.nchan == NCHAN) { 4318 ofld_rate[2] = chan_rate(adap, OFDRATE2_G(v)); 4319 ofld_rate[3] = chan_rate(adap, OFDRATE3_G(v)); 4320 } 4321 } 4322 4323 /** 4324 * t4_set_trace_filter - configure one of the tracing filters 4325 * @adap: the adapter 4326 * @tp: the desired trace filter parameters 4327 * @idx: which filter to configure 4328 * @enable: whether to enable or disable the filter 4329 * 4330 * Configures one of the tracing filters available in HW. If @enable is 4331 * %0 @tp is not examined and may be %NULL. The user is responsible to 4332 * set the single/multiple trace mode by writing to MPS_TRC_CFG_A register 4333 */ 4334 int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp, 4335 int idx, int enable) 4336 { 4337 int i, ofst = idx * 4; 4338 u32 data_reg, mask_reg, cfg; 4339 u32 multitrc = TRCMULTIFILTER_F; 4340 4341 if (!enable) { 4342 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0); 4343 return 0; 4344 } 4345 4346 cfg = t4_read_reg(adap, MPS_TRC_CFG_A); 4347 if (cfg & TRCMULTIFILTER_F) { 4348 /* If multiple tracers are enabled, then maximum 4349 * capture size is 2.5KB (FIFO size of a single channel) 4350 * minus 2 flits for CPL_TRACE_PKT header. 4351 */ 4352 if (tp->snap_len > ((10 * 1024 / 4) - (2 * 8))) 4353 return -EINVAL; 4354 } else { 4355 /* If multiple tracers are disabled, to avoid deadlocks 4356 * maximum packet capture size of 9600 bytes is recommended. 4357 * Also in this mode, only trace0 can be enabled and running. 4358 */ 4359 multitrc = 0; 4360 if (tp->snap_len > 9600 || idx) 4361 return -EINVAL; 4362 } 4363 4364 if (tp->port > (is_t4(adap->params.chip) ? 11 : 19) || tp->invert > 1 || 4365 tp->skip_len > TFLENGTH_M || tp->skip_ofst > TFOFFSET_M || 4366 tp->min_len > TFMINPKTSIZE_M) 4367 return -EINVAL; 4368 4369 /* stop the tracer we'll be changing */ 4370 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0); 4371 4372 idx *= (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A); 4373 data_reg = MPS_TRC_FILTER0_MATCH_A + idx; 4374 mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + idx; 4375 4376 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) { 4377 t4_write_reg(adap, data_reg, tp->data[i]); 4378 t4_write_reg(adap, mask_reg, ~tp->mask[i]); 4379 } 4380 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst, 4381 TFCAPTUREMAX_V(tp->snap_len) | 4382 TFMINPKTSIZE_V(tp->min_len)); 4383 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 4384 TFOFFSET_V(tp->skip_ofst) | TFLENGTH_V(tp->skip_len) | 4385 (is_t4(adap->params.chip) ? 4386 TFPORT_V(tp->port) | TFEN_F | TFINVERTMATCH_V(tp->invert) : 4387 T5_TFPORT_V(tp->port) | T5_TFEN_F | 4388 T5_TFINVERTMATCH_V(tp->invert))); 4389 4390 return 0; 4391 } 4392 4393 /** 4394 * t4_get_trace_filter - query one of the tracing filters 4395 * @adap: the adapter 4396 * @tp: the current trace filter parameters 4397 * @idx: which trace filter to query 4398 * @enabled: non-zero if the filter is enabled 4399 * 4400 * Returns the current settings of one of the HW tracing filters. 4401 */ 4402 void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx, 4403 int *enabled) 4404 { 4405 u32 ctla, ctlb; 4406 int i, ofst = idx * 4; 4407 u32 data_reg, mask_reg; 4408 4409 ctla = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst); 4410 ctlb = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst); 4411 4412 if (is_t4(adap->params.chip)) { 4413 *enabled = !!(ctla & TFEN_F); 4414 tp->port = TFPORT_G(ctla); 4415 tp->invert = !!(ctla & TFINVERTMATCH_F); 4416 } else { 4417 *enabled = !!(ctla & T5_TFEN_F); 4418 tp->port = T5_TFPORT_G(ctla); 4419 tp->invert = !!(ctla & T5_TFINVERTMATCH_F); 4420 } 4421 tp->snap_len = TFCAPTUREMAX_G(ctlb); 4422 tp->min_len = TFMINPKTSIZE_G(ctlb); 4423 tp->skip_ofst = TFOFFSET_G(ctla); 4424 tp->skip_len = TFLENGTH_G(ctla); 4425 4426 ofst = (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A) * idx; 4427 data_reg = MPS_TRC_FILTER0_MATCH_A + ofst; 4428 mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + ofst; 4429 4430 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) { 4431 tp->mask[i] = ~t4_read_reg(adap, mask_reg); 4432 tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i]; 4433 } 4434 } 4435 4436 /** 4437 * t4_pmtx_get_stats - returns the HW stats from PMTX 4438 * @adap: the adapter 4439 * @cnt: where to store the count statistics 4440 * @cycles: where to store the cycle statistics 4441 * 4442 * Returns performance statistics from PMTX. 4443 */ 4444 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]) 4445 { 4446 int i; 4447 u32 data[2]; 4448 4449 for (i = 0; i < PM_NSTATS; i++) { 4450 t4_write_reg(adap, PM_TX_STAT_CONFIG_A, i + 1); 4451 cnt[i] = t4_read_reg(adap, PM_TX_STAT_COUNT_A); 4452 if (is_t4(adap->params.chip)) { 4453 cycles[i] = t4_read_reg64(adap, PM_TX_STAT_LSB_A); 4454 } else { 4455 t4_read_indirect(adap, PM_TX_DBG_CTRL_A, 4456 PM_TX_DBG_DATA_A, data, 2, 4457 PM_TX_DBG_STAT_MSB_A); 4458 cycles[i] = (((u64)data[0] << 32) | data[1]); 4459 } 4460 } 4461 } 4462 4463 /** 4464 * t4_pmrx_get_stats - returns the HW stats from PMRX 4465 * @adap: the adapter 4466 * @cnt: where to store the count statistics 4467 * @cycles: where to store the cycle statistics 4468 * 4469 * Returns performance statistics from PMRX. 4470 */ 4471 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]) 4472 { 4473 int i; 4474 u32 data[2]; 4475 4476 for (i = 0; i < PM_NSTATS; i++) { 4477 t4_write_reg(adap, PM_RX_STAT_CONFIG_A, i + 1); 4478 cnt[i] = t4_read_reg(adap, PM_RX_STAT_COUNT_A); 4479 if (is_t4(adap->params.chip)) { 4480 cycles[i] = t4_read_reg64(adap, PM_RX_STAT_LSB_A); 4481 } else { 4482 t4_read_indirect(adap, PM_RX_DBG_CTRL_A, 4483 PM_RX_DBG_DATA_A, data, 2, 4484 PM_RX_DBG_STAT_MSB_A); 4485 cycles[i] = (((u64)data[0] << 32) | data[1]); 4486 } 4487 } 4488 } 4489 4490 /** 4491 * t4_get_mps_bg_map - return the buffer groups associated with a port 4492 * @adap: the adapter 4493 * @idx: the port index 4494 * 4495 * Returns a bitmap indicating which MPS buffer groups are associated 4496 * with the given port. Bit i is set if buffer group i is used by the 4497 * port. 4498 */ 4499 unsigned int t4_get_mps_bg_map(struct adapter *adap, int idx) 4500 { 4501 u32 n = NUMPORTS_G(t4_read_reg(adap, MPS_CMN_CTL_A)); 4502 4503 if (n == 0) 4504 return idx == 0 ? 0xf : 0; 4505 if (n == 1) 4506 return idx < 2 ? (3 << (2 * idx)) : 0; 4507 return 1 << idx; 4508 } 4509 4510 /** 4511 * t4_get_port_type_description - return Port Type string description 4512 * @port_type: firmware Port Type enumeration 4513 */ 4514 const char *t4_get_port_type_description(enum fw_port_type port_type) 4515 { 4516 static const char *const port_type_description[] = { 4517 "R XFI", 4518 "R XAUI", 4519 "T SGMII", 4520 "T XFI", 4521 "T XAUI", 4522 "KX4", 4523 "CX4", 4524 "KX", 4525 "KR", 4526 "R SFP+", 4527 "KR/KX", 4528 "KR/KX/KX4", 4529 "R QSFP_10G", 4530 "R QSA", 4531 "R QSFP", 4532 "R BP40_BA", 4533 }; 4534 4535 if (port_type < ARRAY_SIZE(port_type_description)) 4536 return port_type_description[port_type]; 4537 return "UNKNOWN"; 4538 } 4539 4540 /** 4541 * t4_get_port_stats_offset - collect port stats relative to a previous 4542 * snapshot 4543 * @adap: The adapter 4544 * @idx: The port 4545 * @stats: Current stats to fill 4546 * @offset: Previous stats snapshot 4547 */ 4548 void t4_get_port_stats_offset(struct adapter *adap, int idx, 4549 struct port_stats *stats, 4550 struct port_stats *offset) 4551 { 4552 u64 *s, *o; 4553 int i; 4554 4555 t4_get_port_stats(adap, idx, stats); 4556 for (i = 0, s = (u64 *)stats, o = (u64 *)offset; 4557 i < (sizeof(struct port_stats) / sizeof(u64)); 4558 i++, s++, o++) 4559 *s -= *o; 4560 } 4561 4562 /** 4563 * t4_get_port_stats - collect port statistics 4564 * @adap: the adapter 4565 * @idx: the port index 4566 * @p: the stats structure to fill 4567 * 4568 * Collect statistics related to the given port from HW. 4569 */ 4570 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p) 4571 { 4572 u32 bgmap = t4_get_mps_bg_map(adap, idx); 4573 4574 #define GET_STAT(name) \ 4575 t4_read_reg64(adap, \ 4576 (is_t4(adap->params.chip) ? PORT_REG(idx, MPS_PORT_STAT_##name##_L) : \ 4577 T5_PORT_REG(idx, MPS_PORT_STAT_##name##_L))) 4578 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L) 4579 4580 p->tx_octets = GET_STAT(TX_PORT_BYTES); 4581 p->tx_frames = GET_STAT(TX_PORT_FRAMES); 4582 p->tx_bcast_frames = GET_STAT(TX_PORT_BCAST); 4583 p->tx_mcast_frames = GET_STAT(TX_PORT_MCAST); 4584 p->tx_ucast_frames = GET_STAT(TX_PORT_UCAST); 4585 p->tx_error_frames = GET_STAT(TX_PORT_ERROR); 4586 p->tx_frames_64 = GET_STAT(TX_PORT_64B); 4587 p->tx_frames_65_127 = GET_STAT(TX_PORT_65B_127B); 4588 p->tx_frames_128_255 = GET_STAT(TX_PORT_128B_255B); 4589 p->tx_frames_256_511 = GET_STAT(TX_PORT_256B_511B); 4590 p->tx_frames_512_1023 = GET_STAT(TX_PORT_512B_1023B); 4591 p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B); 4592 p->tx_frames_1519_max = GET_STAT(TX_PORT_1519B_MAX); 4593 p->tx_drop = GET_STAT(TX_PORT_DROP); 4594 p->tx_pause = GET_STAT(TX_PORT_PAUSE); 4595 p->tx_ppp0 = GET_STAT(TX_PORT_PPP0); 4596 p->tx_ppp1 = GET_STAT(TX_PORT_PPP1); 4597 p->tx_ppp2 = GET_STAT(TX_PORT_PPP2); 4598 p->tx_ppp3 = GET_STAT(TX_PORT_PPP3); 4599 p->tx_ppp4 = GET_STAT(TX_PORT_PPP4); 4600 p->tx_ppp5 = GET_STAT(TX_PORT_PPP5); 4601 p->tx_ppp6 = GET_STAT(TX_PORT_PPP6); 4602 p->tx_ppp7 = GET_STAT(TX_PORT_PPP7); 4603 4604 p->rx_octets = GET_STAT(RX_PORT_BYTES); 4605 p->rx_frames = GET_STAT(RX_PORT_FRAMES); 4606 p->rx_bcast_frames = GET_STAT(RX_PORT_BCAST); 4607 p->rx_mcast_frames = GET_STAT(RX_PORT_MCAST); 4608 p->rx_ucast_frames = GET_STAT(RX_PORT_UCAST); 4609 p->rx_too_long = GET_STAT(RX_PORT_MTU_ERROR); 4610 p->rx_jabber = GET_STAT(RX_PORT_MTU_CRC_ERROR); 4611 p->rx_fcs_err = GET_STAT(RX_PORT_CRC_ERROR); 4612 p->rx_len_err = GET_STAT(RX_PORT_LEN_ERROR); 4613 p->rx_symbol_err = GET_STAT(RX_PORT_SYM_ERROR); 4614 p->rx_runt = GET_STAT(RX_PORT_LESS_64B); 4615 p->rx_frames_64 = GET_STAT(RX_PORT_64B); 4616 p->rx_frames_65_127 = GET_STAT(RX_PORT_65B_127B); 4617 p->rx_frames_128_255 = GET_STAT(RX_PORT_128B_255B); 4618 p->rx_frames_256_511 = GET_STAT(RX_PORT_256B_511B); 4619 p->rx_frames_512_1023 = GET_STAT(RX_PORT_512B_1023B); 4620 p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B); 4621 p->rx_frames_1519_max = GET_STAT(RX_PORT_1519B_MAX); 4622 p->rx_pause = GET_STAT(RX_PORT_PAUSE); 4623 p->rx_ppp0 = GET_STAT(RX_PORT_PPP0); 4624 p->rx_ppp1 = GET_STAT(RX_PORT_PPP1); 4625 p->rx_ppp2 = GET_STAT(RX_PORT_PPP2); 4626 p->rx_ppp3 = GET_STAT(RX_PORT_PPP3); 4627 p->rx_ppp4 = GET_STAT(RX_PORT_PPP4); 4628 p->rx_ppp5 = GET_STAT(RX_PORT_PPP5); 4629 p->rx_ppp6 = GET_STAT(RX_PORT_PPP6); 4630 p->rx_ppp7 = GET_STAT(RX_PORT_PPP7); 4631 4632 p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0; 4633 p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0; 4634 p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0; 4635 p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0; 4636 p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0; 4637 p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0; 4638 p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0; 4639 p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0; 4640 4641 #undef GET_STAT 4642 #undef GET_STAT_COM 4643 } 4644 4645 /** 4646 * t4_get_lb_stats - collect loopback port statistics 4647 * @adap: the adapter 4648 * @idx: the loopback port index 4649 * @p: the stats structure to fill 4650 * 4651 * Return HW statistics for the given loopback port. 4652 */ 4653 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p) 4654 { 4655 u32 bgmap = t4_get_mps_bg_map(adap, idx); 4656 4657 #define GET_STAT(name) \ 4658 t4_read_reg64(adap, \ 4659 (is_t4(adap->params.chip) ? \ 4660 PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L) : \ 4661 T5_PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L))) 4662 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L) 4663 4664 p->octets = GET_STAT(BYTES); 4665 p->frames = GET_STAT(FRAMES); 4666 p->bcast_frames = GET_STAT(BCAST); 4667 p->mcast_frames = GET_STAT(MCAST); 4668 p->ucast_frames = GET_STAT(UCAST); 4669 p->error_frames = GET_STAT(ERROR); 4670 4671 p->frames_64 = GET_STAT(64B); 4672 p->frames_65_127 = GET_STAT(65B_127B); 4673 p->frames_128_255 = GET_STAT(128B_255B); 4674 p->frames_256_511 = GET_STAT(256B_511B); 4675 p->frames_512_1023 = GET_STAT(512B_1023B); 4676 p->frames_1024_1518 = GET_STAT(1024B_1518B); 4677 p->frames_1519_max = GET_STAT(1519B_MAX); 4678 p->drop = GET_STAT(DROP_FRAMES); 4679 4680 p->ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0; 4681 p->ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0; 4682 p->ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME) : 0; 4683 p->ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME) : 0; 4684 p->trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME) : 0; 4685 p->trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME) : 0; 4686 p->trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME) : 0; 4687 p->trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME) : 0; 4688 4689 #undef GET_STAT 4690 #undef GET_STAT_COM 4691 } 4692 4693 /* t4_mk_filtdelwr - create a delete filter WR 4694 * @ftid: the filter ID 4695 * @wr: the filter work request to populate 4696 * @qid: ingress queue to receive the delete notification 4697 * 4698 * Creates a filter work request to delete the supplied filter. If @qid is 4699 * negative the delete notification is suppressed. 4700 */ 4701 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid) 4702 { 4703 memset(wr, 0, sizeof(*wr)); 4704 wr->op_pkd = cpu_to_be32(FW_WR_OP_V(FW_FILTER_WR)); 4705 wr->len16_pkd = cpu_to_be32(FW_WR_LEN16_V(sizeof(*wr) / 16)); 4706 wr->tid_to_iq = cpu_to_be32(FW_FILTER_WR_TID_V(ftid) | 4707 FW_FILTER_WR_NOREPLY_V(qid < 0)); 4708 wr->del_filter_to_l2tix = cpu_to_be32(FW_FILTER_WR_DEL_FILTER_F); 4709 if (qid >= 0) 4710 wr->rx_chan_rx_rpl_iq = 4711 cpu_to_be16(FW_FILTER_WR_RX_RPL_IQ_V(qid)); 4712 } 4713 4714 #define INIT_CMD(var, cmd, rd_wr) do { \ 4715 (var).op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_##cmd##_CMD) | \ 4716 FW_CMD_REQUEST_F | \ 4717 FW_CMD_##rd_wr##_F); \ 4718 (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \ 4719 } while (0) 4720 4721 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, 4722 u32 addr, u32 val) 4723 { 4724 u32 ldst_addrspace; 4725 struct fw_ldst_cmd c; 4726 4727 memset(&c, 0, sizeof(c)); 4728 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FIRMWARE); 4729 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) | 4730 FW_CMD_REQUEST_F | 4731 FW_CMD_WRITE_F | 4732 ldst_addrspace); 4733 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 4734 c.u.addrval.addr = cpu_to_be32(addr); 4735 c.u.addrval.val = cpu_to_be32(val); 4736 4737 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 4738 } 4739 4740 /** 4741 * t4_mdio_rd - read a PHY register through MDIO 4742 * @adap: the adapter 4743 * @mbox: mailbox to use for the FW command 4744 * @phy_addr: the PHY address 4745 * @mmd: the PHY MMD to access (0 for clause 22 PHYs) 4746 * @reg: the register to read 4747 * @valp: where to store the value 4748 * 4749 * Issues a FW command through the given mailbox to read a PHY register. 4750 */ 4751 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 4752 unsigned int mmd, unsigned int reg, u16 *valp) 4753 { 4754 int ret; 4755 u32 ldst_addrspace; 4756 struct fw_ldst_cmd c; 4757 4758 memset(&c, 0, sizeof(c)); 4759 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO); 4760 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) | 4761 FW_CMD_REQUEST_F | FW_CMD_READ_F | 4762 ldst_addrspace); 4763 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 4764 c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) | 4765 FW_LDST_CMD_MMD_V(mmd)); 4766 c.u.mdio.raddr = cpu_to_be16(reg); 4767 4768 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 4769 if (ret == 0) 4770 *valp = be16_to_cpu(c.u.mdio.rval); 4771 return ret; 4772 } 4773 4774 /** 4775 * t4_mdio_wr - write a PHY register through MDIO 4776 * @adap: the adapter 4777 * @mbox: mailbox to use for the FW command 4778 * @phy_addr: the PHY address 4779 * @mmd: the PHY MMD to access (0 for clause 22 PHYs) 4780 * @reg: the register to write 4781 * @valp: value to write 4782 * 4783 * Issues a FW command through the given mailbox to write a PHY register. 4784 */ 4785 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 4786 unsigned int mmd, unsigned int reg, u16 val) 4787 { 4788 u32 ldst_addrspace; 4789 struct fw_ldst_cmd c; 4790 4791 memset(&c, 0, sizeof(c)); 4792 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO); 4793 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) | 4794 FW_CMD_REQUEST_F | FW_CMD_WRITE_F | 4795 ldst_addrspace); 4796 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 4797 c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) | 4798 FW_LDST_CMD_MMD_V(mmd)); 4799 c.u.mdio.raddr = cpu_to_be16(reg); 4800 c.u.mdio.rval = cpu_to_be16(val); 4801 4802 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 4803 } 4804 4805 /** 4806 * t4_sge_decode_idma_state - decode the idma state 4807 * @adap: the adapter 4808 * @state: the state idma is stuck in 4809 */ 4810 void t4_sge_decode_idma_state(struct adapter *adapter, int state) 4811 { 4812 static const char * const t4_decode[] = { 4813 "IDMA_IDLE", 4814 "IDMA_PUSH_MORE_CPL_FIFO", 4815 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO", 4816 "Not used", 4817 "IDMA_PHYSADDR_SEND_PCIEHDR", 4818 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST", 4819 "IDMA_PHYSADDR_SEND_PAYLOAD", 4820 "IDMA_SEND_FIFO_TO_IMSG", 4821 "IDMA_FL_REQ_DATA_FL_PREP", 4822 "IDMA_FL_REQ_DATA_FL", 4823 "IDMA_FL_DROP", 4824 "IDMA_FL_H_REQ_HEADER_FL", 4825 "IDMA_FL_H_SEND_PCIEHDR", 4826 "IDMA_FL_H_PUSH_CPL_FIFO", 4827 "IDMA_FL_H_SEND_CPL", 4828 "IDMA_FL_H_SEND_IP_HDR_FIRST", 4829 "IDMA_FL_H_SEND_IP_HDR", 4830 "IDMA_FL_H_REQ_NEXT_HEADER_FL", 4831 "IDMA_FL_H_SEND_NEXT_PCIEHDR", 4832 "IDMA_FL_H_SEND_IP_HDR_PADDING", 4833 "IDMA_FL_D_SEND_PCIEHDR", 4834 "IDMA_FL_D_SEND_CPL_AND_IP_HDR", 4835 "IDMA_FL_D_REQ_NEXT_DATA_FL", 4836 "IDMA_FL_SEND_PCIEHDR", 4837 "IDMA_FL_PUSH_CPL_FIFO", 4838 "IDMA_FL_SEND_CPL", 4839 "IDMA_FL_SEND_PAYLOAD_FIRST", 4840 "IDMA_FL_SEND_PAYLOAD", 4841 "IDMA_FL_REQ_NEXT_DATA_FL", 4842 "IDMA_FL_SEND_NEXT_PCIEHDR", 4843 "IDMA_FL_SEND_PADDING", 4844 "IDMA_FL_SEND_COMPLETION_TO_IMSG", 4845 "IDMA_FL_SEND_FIFO_TO_IMSG", 4846 "IDMA_FL_REQ_DATAFL_DONE", 4847 "IDMA_FL_REQ_HEADERFL_DONE", 4848 }; 4849 static const char * const t5_decode[] = { 4850 "IDMA_IDLE", 4851 "IDMA_ALMOST_IDLE", 4852 "IDMA_PUSH_MORE_CPL_FIFO", 4853 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO", 4854 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR", 4855 "IDMA_PHYSADDR_SEND_PCIEHDR", 4856 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST", 4857 "IDMA_PHYSADDR_SEND_PAYLOAD", 4858 "IDMA_SEND_FIFO_TO_IMSG", 4859 "IDMA_FL_REQ_DATA_FL", 4860 "IDMA_FL_DROP", 4861 "IDMA_FL_DROP_SEND_INC", 4862 "IDMA_FL_H_REQ_HEADER_FL", 4863 "IDMA_FL_H_SEND_PCIEHDR", 4864 "IDMA_FL_H_PUSH_CPL_FIFO", 4865 "IDMA_FL_H_SEND_CPL", 4866 "IDMA_FL_H_SEND_IP_HDR_FIRST", 4867 "IDMA_FL_H_SEND_IP_HDR", 4868 "IDMA_FL_H_REQ_NEXT_HEADER_FL", 4869 "IDMA_FL_H_SEND_NEXT_PCIEHDR", 4870 "IDMA_FL_H_SEND_IP_HDR_PADDING", 4871 "IDMA_FL_D_SEND_PCIEHDR", 4872 "IDMA_FL_D_SEND_CPL_AND_IP_HDR", 4873 "IDMA_FL_D_REQ_NEXT_DATA_FL", 4874 "IDMA_FL_SEND_PCIEHDR", 4875 "IDMA_FL_PUSH_CPL_FIFO", 4876 "IDMA_FL_SEND_CPL", 4877 "IDMA_FL_SEND_PAYLOAD_FIRST", 4878 "IDMA_FL_SEND_PAYLOAD", 4879 "IDMA_FL_REQ_NEXT_DATA_FL", 4880 "IDMA_FL_SEND_NEXT_PCIEHDR", 4881 "IDMA_FL_SEND_PADDING", 4882 "IDMA_FL_SEND_COMPLETION_TO_IMSG", 4883 }; 4884 static const u32 sge_regs[] = { 4885 SGE_DEBUG_DATA_LOW_INDEX_2_A, 4886 SGE_DEBUG_DATA_LOW_INDEX_3_A, 4887 SGE_DEBUG_DATA_HIGH_INDEX_10_A, 4888 }; 4889 const char **sge_idma_decode; 4890 int sge_idma_decode_nstates; 4891 int i; 4892 4893 if (is_t4(adapter->params.chip)) { 4894 sge_idma_decode = (const char **)t4_decode; 4895 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode); 4896 } else { 4897 sge_idma_decode = (const char **)t5_decode; 4898 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode); 4899 } 4900 4901 if (state < sge_idma_decode_nstates) 4902 CH_WARN(adapter, "idma state %s\n", sge_idma_decode[state]); 4903 else 4904 CH_WARN(adapter, "idma state %d unknown\n", state); 4905 4906 for (i = 0; i < ARRAY_SIZE(sge_regs); i++) 4907 CH_WARN(adapter, "SGE register %#x value %#x\n", 4908 sge_regs[i], t4_read_reg(adapter, sge_regs[i])); 4909 } 4910 4911 /** 4912 * t4_sge_ctxt_flush - flush the SGE context cache 4913 * @adap: the adapter 4914 * @mbox: mailbox to use for the FW command 4915 * 4916 * Issues a FW command through the given mailbox to flush the 4917 * SGE context cache. 4918 */ 4919 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox) 4920 { 4921 int ret; 4922 u32 ldst_addrspace; 4923 struct fw_ldst_cmd c; 4924 4925 memset(&c, 0, sizeof(c)); 4926 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_SGE_EGRC); 4927 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) | 4928 FW_CMD_REQUEST_F | FW_CMD_READ_F | 4929 ldst_addrspace); 4930 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 4931 c.u.idctxt.msg_ctxtflush = cpu_to_be32(FW_LDST_CMD_CTXTFLUSH_F); 4932 4933 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 4934 return ret; 4935 } 4936 4937 /** 4938 * t4_fw_hello - establish communication with FW 4939 * @adap: the adapter 4940 * @mbox: mailbox to use for the FW command 4941 * @evt_mbox: mailbox to receive async FW events 4942 * @master: specifies the caller's willingness to be the device master 4943 * @state: returns the current device state (if non-NULL) 4944 * 4945 * Issues a command to establish communication with FW. Returns either 4946 * an error (negative integer) or the mailbox of the Master PF. 4947 */ 4948 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 4949 enum dev_master master, enum dev_state *state) 4950 { 4951 int ret; 4952 struct fw_hello_cmd c; 4953 u32 v; 4954 unsigned int master_mbox; 4955 int retries = FW_CMD_HELLO_RETRIES; 4956 4957 retry: 4958 memset(&c, 0, sizeof(c)); 4959 INIT_CMD(c, HELLO, WRITE); 4960 c.err_to_clearinit = cpu_to_be32( 4961 FW_HELLO_CMD_MASTERDIS_V(master == MASTER_CANT) | 4962 FW_HELLO_CMD_MASTERFORCE_V(master == MASTER_MUST) | 4963 FW_HELLO_CMD_MBMASTER_V(master == MASTER_MUST ? 4964 mbox : FW_HELLO_CMD_MBMASTER_M) | 4965 FW_HELLO_CMD_MBASYNCNOT_V(evt_mbox) | 4966 FW_HELLO_CMD_STAGE_V(fw_hello_cmd_stage_os) | 4967 FW_HELLO_CMD_CLEARINIT_F); 4968 4969 /* 4970 * Issue the HELLO command to the firmware. If it's not successful 4971 * but indicates that we got a "busy" or "timeout" condition, retry 4972 * the HELLO until we exhaust our retry limit. If we do exceed our 4973 * retry limit, check to see if the firmware left us any error 4974 * information and report that if so. 4975 */ 4976 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 4977 if (ret < 0) { 4978 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0) 4979 goto retry; 4980 if (t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_ERR_F) 4981 t4_report_fw_error(adap); 4982 return ret; 4983 } 4984 4985 v = be32_to_cpu(c.err_to_clearinit); 4986 master_mbox = FW_HELLO_CMD_MBMASTER_G(v); 4987 if (state) { 4988 if (v & FW_HELLO_CMD_ERR_F) 4989 *state = DEV_STATE_ERR; 4990 else if (v & FW_HELLO_CMD_INIT_F) 4991 *state = DEV_STATE_INIT; 4992 else 4993 *state = DEV_STATE_UNINIT; 4994 } 4995 4996 /* 4997 * If we're not the Master PF then we need to wait around for the 4998 * Master PF Driver to finish setting up the adapter. 4999 * 5000 * Note that we also do this wait if we're a non-Master-capable PF and 5001 * there is no current Master PF; a Master PF may show up momentarily 5002 * and we wouldn't want to fail pointlessly. (This can happen when an 5003 * OS loads lots of different drivers rapidly at the same time). In 5004 * this case, the Master PF returned by the firmware will be 5005 * PCIE_FW_MASTER_M so the test below will work ... 5006 */ 5007 if ((v & (FW_HELLO_CMD_ERR_F|FW_HELLO_CMD_INIT_F)) == 0 && 5008 master_mbox != mbox) { 5009 int waiting = FW_CMD_HELLO_TIMEOUT; 5010 5011 /* 5012 * Wait for the firmware to either indicate an error or 5013 * initialized state. If we see either of these we bail out 5014 * and report the issue to the caller. If we exhaust the 5015 * "hello timeout" and we haven't exhausted our retries, try 5016 * again. Otherwise bail with a timeout error. 5017 */ 5018 for (;;) { 5019 u32 pcie_fw; 5020 5021 msleep(50); 5022 waiting -= 50; 5023 5024 /* 5025 * If neither Error nor Initialialized are indicated 5026 * by the firmware keep waiting till we exaust our 5027 * timeout ... and then retry if we haven't exhausted 5028 * our retries ... 5029 */ 5030 pcie_fw = t4_read_reg(adap, PCIE_FW_A); 5031 if (!(pcie_fw & (PCIE_FW_ERR_F|PCIE_FW_INIT_F))) { 5032 if (waiting <= 0) { 5033 if (retries-- > 0) 5034 goto retry; 5035 5036 return -ETIMEDOUT; 5037 } 5038 continue; 5039 } 5040 5041 /* 5042 * We either have an Error or Initialized condition 5043 * report errors preferentially. 5044 */ 5045 if (state) { 5046 if (pcie_fw & PCIE_FW_ERR_F) 5047 *state = DEV_STATE_ERR; 5048 else if (pcie_fw & PCIE_FW_INIT_F) 5049 *state = DEV_STATE_INIT; 5050 } 5051 5052 /* 5053 * If we arrived before a Master PF was selected and 5054 * there's not a valid Master PF, grab its identity 5055 * for our caller. 5056 */ 5057 if (master_mbox == PCIE_FW_MASTER_M && 5058 (pcie_fw & PCIE_FW_MASTER_VLD_F)) 5059 master_mbox = PCIE_FW_MASTER_G(pcie_fw); 5060 break; 5061 } 5062 } 5063 5064 return master_mbox; 5065 } 5066 5067 /** 5068 * t4_fw_bye - end communication with FW 5069 * @adap: the adapter 5070 * @mbox: mailbox to use for the FW command 5071 * 5072 * Issues a command to terminate communication with FW. 5073 */ 5074 int t4_fw_bye(struct adapter *adap, unsigned int mbox) 5075 { 5076 struct fw_bye_cmd c; 5077 5078 memset(&c, 0, sizeof(c)); 5079 INIT_CMD(c, BYE, WRITE); 5080 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 5081 } 5082 5083 /** 5084 * t4_init_cmd - ask FW to initialize the device 5085 * @adap: the adapter 5086 * @mbox: mailbox to use for the FW command 5087 * 5088 * Issues a command to FW to partially initialize the device. This 5089 * performs initialization that generally doesn't depend on user input. 5090 */ 5091 int t4_early_init(struct adapter *adap, unsigned int mbox) 5092 { 5093 struct fw_initialize_cmd c; 5094 5095 memset(&c, 0, sizeof(c)); 5096 INIT_CMD(c, INITIALIZE, WRITE); 5097 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 5098 } 5099 5100 /** 5101 * t4_fw_reset - issue a reset to FW 5102 * @adap: the adapter 5103 * @mbox: mailbox to use for the FW command 5104 * @reset: specifies the type of reset to perform 5105 * 5106 * Issues a reset command of the specified type to FW. 5107 */ 5108 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset) 5109 { 5110 struct fw_reset_cmd c; 5111 5112 memset(&c, 0, sizeof(c)); 5113 INIT_CMD(c, RESET, WRITE); 5114 c.val = cpu_to_be32(reset); 5115 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 5116 } 5117 5118 /** 5119 * t4_fw_halt - issue a reset/halt to FW and put uP into RESET 5120 * @adap: the adapter 5121 * @mbox: mailbox to use for the FW RESET command (if desired) 5122 * @force: force uP into RESET even if FW RESET command fails 5123 * 5124 * Issues a RESET command to firmware (if desired) with a HALT indication 5125 * and then puts the microprocessor into RESET state. The RESET command 5126 * will only be issued if a legitimate mailbox is provided (mbox <= 5127 * PCIE_FW_MASTER_M). 5128 * 5129 * This is generally used in order for the host to safely manipulate the 5130 * adapter without fear of conflicting with whatever the firmware might 5131 * be doing. The only way out of this state is to RESTART the firmware 5132 * ... 5133 */ 5134 static int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force) 5135 { 5136 int ret = 0; 5137 5138 /* 5139 * If a legitimate mailbox is provided, issue a RESET command 5140 * with a HALT indication. 5141 */ 5142 if (mbox <= PCIE_FW_MASTER_M) { 5143 struct fw_reset_cmd c; 5144 5145 memset(&c, 0, sizeof(c)); 5146 INIT_CMD(c, RESET, WRITE); 5147 c.val = cpu_to_be32(PIORST_F | PIORSTMODE_F); 5148 c.halt_pkd = cpu_to_be32(FW_RESET_CMD_HALT_F); 5149 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 5150 } 5151 5152 /* 5153 * Normally we won't complete the operation if the firmware RESET 5154 * command fails but if our caller insists we'll go ahead and put the 5155 * uP into RESET. This can be useful if the firmware is hung or even 5156 * missing ... We'll have to take the risk of putting the uP into 5157 * RESET without the cooperation of firmware in that case. 5158 * 5159 * We also force the firmware's HALT flag to be on in case we bypassed 5160 * the firmware RESET command above or we're dealing with old firmware 5161 * which doesn't have the HALT capability. This will serve as a flag 5162 * for the incoming firmware to know that it's coming out of a HALT 5163 * rather than a RESET ... if it's new enough to understand that ... 5164 */ 5165 if (ret == 0 || force) { 5166 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, UPCRST_F); 5167 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F, 5168 PCIE_FW_HALT_F); 5169 } 5170 5171 /* 5172 * And we always return the result of the firmware RESET command 5173 * even when we force the uP into RESET ... 5174 */ 5175 return ret; 5176 } 5177 5178 /** 5179 * t4_fw_restart - restart the firmware by taking the uP out of RESET 5180 * @adap: the adapter 5181 * @reset: if we want to do a RESET to restart things 5182 * 5183 * Restart firmware previously halted by t4_fw_halt(). On successful 5184 * return the previous PF Master remains as the new PF Master and there 5185 * is no need to issue a new HELLO command, etc. 5186 * 5187 * We do this in two ways: 5188 * 5189 * 1. If we're dealing with newer firmware we'll simply want to take 5190 * the chip's microprocessor out of RESET. This will cause the 5191 * firmware to start up from its start vector. And then we'll loop 5192 * until the firmware indicates it's started again (PCIE_FW.HALT 5193 * reset to 0) or we timeout. 5194 * 5195 * 2. If we're dealing with older firmware then we'll need to RESET 5196 * the chip since older firmware won't recognize the PCIE_FW.HALT 5197 * flag and automatically RESET itself on startup. 5198 */ 5199 static int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset) 5200 { 5201 if (reset) { 5202 /* 5203 * Since we're directing the RESET instead of the firmware 5204 * doing it automatically, we need to clear the PCIE_FW.HALT 5205 * bit. 5206 */ 5207 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F, 0); 5208 5209 /* 5210 * If we've been given a valid mailbox, first try to get the 5211 * firmware to do the RESET. If that works, great and we can 5212 * return success. Otherwise, if we haven't been given a 5213 * valid mailbox or the RESET command failed, fall back to 5214 * hitting the chip with a hammer. 5215 */ 5216 if (mbox <= PCIE_FW_MASTER_M) { 5217 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0); 5218 msleep(100); 5219 if (t4_fw_reset(adap, mbox, 5220 PIORST_F | PIORSTMODE_F) == 0) 5221 return 0; 5222 } 5223 5224 t4_write_reg(adap, PL_RST_A, PIORST_F | PIORSTMODE_F); 5225 msleep(2000); 5226 } else { 5227 int ms; 5228 5229 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0); 5230 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) { 5231 if (!(t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_HALT_F)) 5232 return 0; 5233 msleep(100); 5234 ms += 100; 5235 } 5236 return -ETIMEDOUT; 5237 } 5238 return 0; 5239 } 5240 5241 /** 5242 * t4_fw_upgrade - perform all of the steps necessary to upgrade FW 5243 * @adap: the adapter 5244 * @mbox: mailbox to use for the FW RESET command (if desired) 5245 * @fw_data: the firmware image to write 5246 * @size: image size 5247 * @force: force upgrade even if firmware doesn't cooperate 5248 * 5249 * Perform all of the steps necessary for upgrading an adapter's 5250 * firmware image. Normally this requires the cooperation of the 5251 * existing firmware in order to halt all existing activities 5252 * but if an invalid mailbox token is passed in we skip that step 5253 * (though we'll still put the adapter microprocessor into RESET in 5254 * that case). 5255 * 5256 * On successful return the new firmware will have been loaded and 5257 * the adapter will have been fully RESET losing all previous setup 5258 * state. On unsuccessful return the adapter may be completely hosed ... 5259 * positive errno indicates that the adapter is ~probably~ intact, a 5260 * negative errno indicates that things are looking bad ... 5261 */ 5262 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 5263 const u8 *fw_data, unsigned int size, int force) 5264 { 5265 const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data; 5266 int reset, ret; 5267 5268 if (!t4_fw_matches_chip(adap, fw_hdr)) 5269 return -EINVAL; 5270 5271 ret = t4_fw_halt(adap, mbox, force); 5272 if (ret < 0 && !force) 5273 return ret; 5274 5275 ret = t4_load_fw(adap, fw_data, size); 5276 if (ret < 0) 5277 return ret; 5278 5279 /* 5280 * Older versions of the firmware don't understand the new 5281 * PCIE_FW.HALT flag and so won't know to perform a RESET when they 5282 * restart. So for newly loaded older firmware we'll have to do the 5283 * RESET for it so it starts up on a clean slate. We can tell if 5284 * the newly loaded firmware will handle this right by checking 5285 * its header flags to see if it advertises the capability. 5286 */ 5287 reset = ((be32_to_cpu(fw_hdr->flags) & FW_HDR_FLAGS_RESET_HALT) == 0); 5288 return t4_fw_restart(adap, mbox, reset); 5289 } 5290 5291 /** 5292 * t4_fixup_host_params - fix up host-dependent parameters 5293 * @adap: the adapter 5294 * @page_size: the host's Base Page Size 5295 * @cache_line_size: the host's Cache Line Size 5296 * 5297 * Various registers in T4 contain values which are dependent on the 5298 * host's Base Page and Cache Line Sizes. This function will fix all of 5299 * those registers with the appropriate values as passed in ... 5300 */ 5301 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, 5302 unsigned int cache_line_size) 5303 { 5304 unsigned int page_shift = fls(page_size) - 1; 5305 unsigned int sge_hps = page_shift - 10; 5306 unsigned int stat_len = cache_line_size > 64 ? 128 : 64; 5307 unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size; 5308 unsigned int fl_align_log = fls(fl_align) - 1; 5309 5310 t4_write_reg(adap, SGE_HOST_PAGE_SIZE_A, 5311 HOSTPAGESIZEPF0_V(sge_hps) | 5312 HOSTPAGESIZEPF1_V(sge_hps) | 5313 HOSTPAGESIZEPF2_V(sge_hps) | 5314 HOSTPAGESIZEPF3_V(sge_hps) | 5315 HOSTPAGESIZEPF4_V(sge_hps) | 5316 HOSTPAGESIZEPF5_V(sge_hps) | 5317 HOSTPAGESIZEPF6_V(sge_hps) | 5318 HOSTPAGESIZEPF7_V(sge_hps)); 5319 5320 if (is_t4(adap->params.chip)) { 5321 t4_set_reg_field(adap, SGE_CONTROL_A, 5322 INGPADBOUNDARY_V(INGPADBOUNDARY_M) | 5323 EGRSTATUSPAGESIZE_F, 5324 INGPADBOUNDARY_V(fl_align_log - 5325 INGPADBOUNDARY_SHIFT_X) | 5326 EGRSTATUSPAGESIZE_V(stat_len != 64)); 5327 } else { 5328 /* T5 introduced the separation of the Free List Padding and 5329 * Packing Boundaries. Thus, we can select a smaller Padding 5330 * Boundary to avoid uselessly chewing up PCIe Link and Memory 5331 * Bandwidth, and use a Packing Boundary which is large enough 5332 * to avoid false sharing between CPUs, etc. 5333 * 5334 * For the PCI Link, the smaller the Padding Boundary the 5335 * better. For the Memory Controller, a smaller Padding 5336 * Boundary is better until we cross under the Memory Line 5337 * Size (the minimum unit of transfer to/from Memory). If we 5338 * have a Padding Boundary which is smaller than the Memory 5339 * Line Size, that'll involve a Read-Modify-Write cycle on the 5340 * Memory Controller which is never good. For T5 the smallest 5341 * Padding Boundary which we can select is 32 bytes which is 5342 * larger than any known Memory Controller Line Size so we'll 5343 * use that. 5344 * 5345 * T5 has a different interpretation of the "0" value for the 5346 * Packing Boundary. This corresponds to 16 bytes instead of 5347 * the expected 32 bytes. We never have a Packing Boundary 5348 * less than 32 bytes so we can't use that special value but 5349 * on the other hand, if we wanted 32 bytes, the best we can 5350 * really do is 64 bytes. 5351 */ 5352 if (fl_align <= 32) { 5353 fl_align = 64; 5354 fl_align_log = 6; 5355 } 5356 t4_set_reg_field(adap, SGE_CONTROL_A, 5357 INGPADBOUNDARY_V(INGPADBOUNDARY_M) | 5358 EGRSTATUSPAGESIZE_F, 5359 INGPADBOUNDARY_V(INGPCIEBOUNDARY_32B_X) | 5360 EGRSTATUSPAGESIZE_V(stat_len != 64)); 5361 t4_set_reg_field(adap, SGE_CONTROL2_A, 5362 INGPACKBOUNDARY_V(INGPACKBOUNDARY_M), 5363 INGPACKBOUNDARY_V(fl_align_log - 5364 INGPACKBOUNDARY_SHIFT_X)); 5365 } 5366 /* 5367 * Adjust various SGE Free List Host Buffer Sizes. 5368 * 5369 * This is something of a crock since we're using fixed indices into 5370 * the array which are also known by the sge.c code and the T4 5371 * Firmware Configuration File. We need to come up with a much better 5372 * approach to managing this array. For now, the first four entries 5373 * are: 5374 * 5375 * 0: Host Page Size 5376 * 1: 64KB 5377 * 2: Buffer size corresponding to 1500 byte MTU (unpacked mode) 5378 * 3: Buffer size corresponding to 9000 byte MTU (unpacked mode) 5379 * 5380 * For the single-MTU buffers in unpacked mode we need to include 5381 * space for the SGE Control Packet Shift, 14 byte Ethernet header, 5382 * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet 5383 * Padding boundary. All of these are accommodated in the Factory 5384 * Default Firmware Configuration File but we need to adjust it for 5385 * this host's cache line size. 5386 */ 5387 t4_write_reg(adap, SGE_FL_BUFFER_SIZE0_A, page_size); 5388 t4_write_reg(adap, SGE_FL_BUFFER_SIZE2_A, 5389 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE2_A) + fl_align-1) 5390 & ~(fl_align-1)); 5391 t4_write_reg(adap, SGE_FL_BUFFER_SIZE3_A, 5392 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE3_A) + fl_align-1) 5393 & ~(fl_align-1)); 5394 5395 t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(page_shift - 12)); 5396 5397 return 0; 5398 } 5399 5400 /** 5401 * t4_fw_initialize - ask FW to initialize the device 5402 * @adap: the adapter 5403 * @mbox: mailbox to use for the FW command 5404 * 5405 * Issues a command to FW to partially initialize the device. This 5406 * performs initialization that generally doesn't depend on user input. 5407 */ 5408 int t4_fw_initialize(struct adapter *adap, unsigned int mbox) 5409 { 5410 struct fw_initialize_cmd c; 5411 5412 memset(&c, 0, sizeof(c)); 5413 INIT_CMD(c, INITIALIZE, WRITE); 5414 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 5415 } 5416 5417 /** 5418 * t4_query_params_rw - query FW or device parameters 5419 * @adap: the adapter 5420 * @mbox: mailbox to use for the FW command 5421 * @pf: the PF 5422 * @vf: the VF 5423 * @nparams: the number of parameters 5424 * @params: the parameter names 5425 * @val: the parameter values 5426 * @rw: Write and read flag 5427 * 5428 * Reads the value of FW or device parameters. Up to 7 parameters can be 5429 * queried at once. 5430 */ 5431 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, 5432 unsigned int vf, unsigned int nparams, const u32 *params, 5433 u32 *val, int rw) 5434 { 5435 int i, ret; 5436 struct fw_params_cmd c; 5437 __be32 *p = &c.param[0].mnem; 5438 5439 if (nparams > 7) 5440 return -EINVAL; 5441 5442 memset(&c, 0, sizeof(c)); 5443 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) | 5444 FW_CMD_REQUEST_F | FW_CMD_READ_F | 5445 FW_PARAMS_CMD_PFN_V(pf) | 5446 FW_PARAMS_CMD_VFN_V(vf)); 5447 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 5448 5449 for (i = 0; i < nparams; i++) { 5450 *p++ = cpu_to_be32(*params++); 5451 if (rw) 5452 *p = cpu_to_be32(*(val + i)); 5453 p++; 5454 } 5455 5456 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 5457 if (ret == 0) 5458 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2) 5459 *val++ = be32_to_cpu(*p); 5460 return ret; 5461 } 5462 5463 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 5464 unsigned int vf, unsigned int nparams, const u32 *params, 5465 u32 *val) 5466 { 5467 return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0); 5468 } 5469 5470 /** 5471 * t4_set_params_timeout - sets FW or device parameters 5472 * @adap: the adapter 5473 * @mbox: mailbox to use for the FW command 5474 * @pf: the PF 5475 * @vf: the VF 5476 * @nparams: the number of parameters 5477 * @params: the parameter names 5478 * @val: the parameter values 5479 * @timeout: the timeout time 5480 * 5481 * Sets the value of FW or device parameters. Up to 7 parameters can be 5482 * specified at once. 5483 */ 5484 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 5485 unsigned int pf, unsigned int vf, 5486 unsigned int nparams, const u32 *params, 5487 const u32 *val, int timeout) 5488 { 5489 struct fw_params_cmd c; 5490 __be32 *p = &c.param[0].mnem; 5491 5492 if (nparams > 7) 5493 return -EINVAL; 5494 5495 memset(&c, 0, sizeof(c)); 5496 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) | 5497 FW_CMD_REQUEST_F | FW_CMD_WRITE_F | 5498 FW_PARAMS_CMD_PFN_V(pf) | 5499 FW_PARAMS_CMD_VFN_V(vf)); 5500 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 5501 5502 while (nparams--) { 5503 *p++ = cpu_to_be32(*params++); 5504 *p++ = cpu_to_be32(*val++); 5505 } 5506 5507 return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout); 5508 } 5509 5510 /** 5511 * t4_set_params - sets FW or device parameters 5512 * @adap: the adapter 5513 * @mbox: mailbox to use for the FW command 5514 * @pf: the PF 5515 * @vf: the VF 5516 * @nparams: the number of parameters 5517 * @params: the parameter names 5518 * @val: the parameter values 5519 * 5520 * Sets the value of FW or device parameters. Up to 7 parameters can be 5521 * specified at once. 5522 */ 5523 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 5524 unsigned int vf, unsigned int nparams, const u32 *params, 5525 const u32 *val) 5526 { 5527 return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val, 5528 FW_CMD_MAX_TIMEOUT); 5529 } 5530 5531 /** 5532 * t4_cfg_pfvf - configure PF/VF resource limits 5533 * @adap: the adapter 5534 * @mbox: mailbox to use for the FW command 5535 * @pf: the PF being configured 5536 * @vf: the VF being configured 5537 * @txq: the max number of egress queues 5538 * @txq_eth_ctrl: the max number of egress Ethernet or control queues 5539 * @rxqi: the max number of interrupt-capable ingress queues 5540 * @rxq: the max number of interruptless ingress queues 5541 * @tc: the PCI traffic class 5542 * @vi: the max number of virtual interfaces 5543 * @cmask: the channel access rights mask for the PF/VF 5544 * @pmask: the port access rights mask for the PF/VF 5545 * @nexact: the maximum number of exact MPS filters 5546 * @rcaps: read capabilities 5547 * @wxcaps: write/execute capabilities 5548 * 5549 * Configures resource limits and capabilities for a physical or virtual 5550 * function. 5551 */ 5552 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 5553 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 5554 unsigned int rxqi, unsigned int rxq, unsigned int tc, 5555 unsigned int vi, unsigned int cmask, unsigned int pmask, 5556 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps) 5557 { 5558 struct fw_pfvf_cmd c; 5559 5560 memset(&c, 0, sizeof(c)); 5561 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PFVF_CMD) | FW_CMD_REQUEST_F | 5562 FW_CMD_WRITE_F | FW_PFVF_CMD_PFN_V(pf) | 5563 FW_PFVF_CMD_VFN_V(vf)); 5564 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 5565 c.niqflint_niq = cpu_to_be32(FW_PFVF_CMD_NIQFLINT_V(rxqi) | 5566 FW_PFVF_CMD_NIQ_V(rxq)); 5567 c.type_to_neq = cpu_to_be32(FW_PFVF_CMD_CMASK_V(cmask) | 5568 FW_PFVF_CMD_PMASK_V(pmask) | 5569 FW_PFVF_CMD_NEQ_V(txq)); 5570 c.tc_to_nexactf = cpu_to_be32(FW_PFVF_CMD_TC_V(tc) | 5571 FW_PFVF_CMD_NVI_V(vi) | 5572 FW_PFVF_CMD_NEXACTF_V(nexact)); 5573 c.r_caps_to_nethctrl = cpu_to_be32(FW_PFVF_CMD_R_CAPS_V(rcaps) | 5574 FW_PFVF_CMD_WX_CAPS_V(wxcaps) | 5575 FW_PFVF_CMD_NETHCTRL_V(txq_eth_ctrl)); 5576 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 5577 } 5578 5579 /** 5580 * t4_alloc_vi - allocate a virtual interface 5581 * @adap: the adapter 5582 * @mbox: mailbox to use for the FW command 5583 * @port: physical port associated with the VI 5584 * @pf: the PF owning the VI 5585 * @vf: the VF owning the VI 5586 * @nmac: number of MAC addresses needed (1 to 5) 5587 * @mac: the MAC addresses of the VI 5588 * @rss_size: size of RSS table slice associated with this VI 5589 * 5590 * Allocates a virtual interface for the given physical port. If @mac is 5591 * not %NULL it contains the MAC addresses of the VI as assigned by FW. 5592 * @mac should be large enough to hold @nmac Ethernet addresses, they are 5593 * stored consecutively so the space needed is @nmac * 6 bytes. 5594 * Returns a negative error number or the non-negative VI id. 5595 */ 5596 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 5597 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 5598 unsigned int *rss_size) 5599 { 5600 int ret; 5601 struct fw_vi_cmd c; 5602 5603 memset(&c, 0, sizeof(c)); 5604 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) | FW_CMD_REQUEST_F | 5605 FW_CMD_WRITE_F | FW_CMD_EXEC_F | 5606 FW_VI_CMD_PFN_V(pf) | FW_VI_CMD_VFN_V(vf)); 5607 c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_ALLOC_F | FW_LEN16(c)); 5608 c.portid_pkd = FW_VI_CMD_PORTID_V(port); 5609 c.nmac = nmac - 1; 5610 5611 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 5612 if (ret) 5613 return ret; 5614 5615 if (mac) { 5616 memcpy(mac, c.mac, sizeof(c.mac)); 5617 switch (nmac) { 5618 case 5: 5619 memcpy(mac + 24, c.nmac3, sizeof(c.nmac3)); 5620 case 4: 5621 memcpy(mac + 18, c.nmac2, sizeof(c.nmac2)); 5622 case 3: 5623 memcpy(mac + 12, c.nmac1, sizeof(c.nmac1)); 5624 case 2: 5625 memcpy(mac + 6, c.nmac0, sizeof(c.nmac0)); 5626 } 5627 } 5628 if (rss_size) 5629 *rss_size = FW_VI_CMD_RSSSIZE_G(be16_to_cpu(c.rsssize_pkd)); 5630 return FW_VI_CMD_VIID_G(be16_to_cpu(c.type_viid)); 5631 } 5632 5633 /** 5634 * t4_free_vi - free a virtual interface 5635 * @adap: the adapter 5636 * @mbox: mailbox to use for the FW command 5637 * @pf: the PF owning the VI 5638 * @vf: the VF owning the VI 5639 * @viid: virtual interface identifiler 5640 * 5641 * Free a previously allocated virtual interface. 5642 */ 5643 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf, 5644 unsigned int vf, unsigned int viid) 5645 { 5646 struct fw_vi_cmd c; 5647 5648 memset(&c, 0, sizeof(c)); 5649 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) | 5650 FW_CMD_REQUEST_F | 5651 FW_CMD_EXEC_F | 5652 FW_VI_CMD_PFN_V(pf) | 5653 FW_VI_CMD_VFN_V(vf)); 5654 c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_FREE_F | FW_LEN16(c)); 5655 c.type_viid = cpu_to_be16(FW_VI_CMD_VIID_V(viid)); 5656 5657 return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 5658 } 5659 5660 /** 5661 * t4_set_rxmode - set Rx properties of a virtual interface 5662 * @adap: the adapter 5663 * @mbox: mailbox to use for the FW command 5664 * @viid: the VI id 5665 * @mtu: the new MTU or -1 5666 * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change 5667 * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change 5668 * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change 5669 * @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change 5670 * @sleep_ok: if true we may sleep while awaiting command completion 5671 * 5672 * Sets Rx properties of a virtual interface. 5673 */ 5674 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 5675 int mtu, int promisc, int all_multi, int bcast, int vlanex, 5676 bool sleep_ok) 5677 { 5678 struct fw_vi_rxmode_cmd c; 5679 5680 /* convert to FW values */ 5681 if (mtu < 0) 5682 mtu = FW_RXMODE_MTU_NO_CHG; 5683 if (promisc < 0) 5684 promisc = FW_VI_RXMODE_CMD_PROMISCEN_M; 5685 if (all_multi < 0) 5686 all_multi = FW_VI_RXMODE_CMD_ALLMULTIEN_M; 5687 if (bcast < 0) 5688 bcast = FW_VI_RXMODE_CMD_BROADCASTEN_M; 5689 if (vlanex < 0) 5690 vlanex = FW_VI_RXMODE_CMD_VLANEXEN_M; 5691 5692 memset(&c, 0, sizeof(c)); 5693 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_RXMODE_CMD) | 5694 FW_CMD_REQUEST_F | FW_CMD_WRITE_F | 5695 FW_VI_RXMODE_CMD_VIID_V(viid)); 5696 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 5697 c.mtu_to_vlanexen = 5698 cpu_to_be32(FW_VI_RXMODE_CMD_MTU_V(mtu) | 5699 FW_VI_RXMODE_CMD_PROMISCEN_V(promisc) | 5700 FW_VI_RXMODE_CMD_ALLMULTIEN_V(all_multi) | 5701 FW_VI_RXMODE_CMD_BROADCASTEN_V(bcast) | 5702 FW_VI_RXMODE_CMD_VLANEXEN_V(vlanex)); 5703 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok); 5704 } 5705 5706 /** 5707 * t4_alloc_mac_filt - allocates exact-match filters for MAC addresses 5708 * @adap: the adapter 5709 * @mbox: mailbox to use for the FW command 5710 * @viid: the VI id 5711 * @free: if true any existing filters for this VI id are first removed 5712 * @naddr: the number of MAC addresses to allocate filters for (up to 7) 5713 * @addr: the MAC address(es) 5714 * @idx: where to store the index of each allocated filter 5715 * @hash: pointer to hash address filter bitmap 5716 * @sleep_ok: call is allowed to sleep 5717 * 5718 * Allocates an exact-match filter for each of the supplied addresses and 5719 * sets it to the corresponding address. If @idx is not %NULL it should 5720 * have at least @naddr entries, each of which will be set to the index of 5721 * the filter allocated for the corresponding MAC address. If a filter 5722 * could not be allocated for an address its index is set to 0xffff. 5723 * If @hash is not %NULL addresses that fail to allocate an exact filter 5724 * are hashed and update the hash filter bitmap pointed at by @hash. 5725 * 5726 * Returns a negative error number or the number of filters allocated. 5727 */ 5728 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, 5729 unsigned int viid, bool free, unsigned int naddr, 5730 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok) 5731 { 5732 int offset, ret = 0; 5733 struct fw_vi_mac_cmd c; 5734 unsigned int nfilters = 0; 5735 unsigned int max_naddr = adap->params.arch.mps_tcam_size; 5736 unsigned int rem = naddr; 5737 5738 if (naddr > max_naddr) 5739 return -EINVAL; 5740 5741 for (offset = 0; offset < naddr ; /**/) { 5742 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact) ? 5743 rem : ARRAY_SIZE(c.u.exact)); 5744 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd, 5745 u.exact[fw_naddr]), 16); 5746 struct fw_vi_mac_exact *p; 5747 int i; 5748 5749 memset(&c, 0, sizeof(c)); 5750 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) | 5751 FW_CMD_REQUEST_F | 5752 FW_CMD_WRITE_F | 5753 FW_CMD_EXEC_V(free) | 5754 FW_VI_MAC_CMD_VIID_V(viid)); 5755 c.freemacs_to_len16 = 5756 cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(free) | 5757 FW_CMD_LEN16_V(len16)); 5758 5759 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) { 5760 p->valid_to_idx = 5761 cpu_to_be16(FW_VI_MAC_CMD_VALID_F | 5762 FW_VI_MAC_CMD_IDX_V( 5763 FW_VI_MAC_ADD_MAC)); 5764 memcpy(p->macaddr, addr[offset + i], 5765 sizeof(p->macaddr)); 5766 } 5767 5768 /* It's okay if we run out of space in our MAC address arena. 5769 * Some of the addresses we submit may get stored so we need 5770 * to run through the reply to see what the results were ... 5771 */ 5772 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok); 5773 if (ret && ret != -FW_ENOMEM) 5774 break; 5775 5776 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) { 5777 u16 index = FW_VI_MAC_CMD_IDX_G( 5778 be16_to_cpu(p->valid_to_idx)); 5779 5780 if (idx) 5781 idx[offset + i] = (index >= max_naddr ? 5782 0xffff : index); 5783 if (index < max_naddr) 5784 nfilters++; 5785 else if (hash) 5786 *hash |= (1ULL << 5787 hash_mac_addr(addr[offset + i])); 5788 } 5789 5790 free = false; 5791 offset += fw_naddr; 5792 rem -= fw_naddr; 5793 } 5794 5795 if (ret == 0 || ret == -FW_ENOMEM) 5796 ret = nfilters; 5797 return ret; 5798 } 5799 5800 /** 5801 * t4_change_mac - modifies the exact-match filter for a MAC address 5802 * @adap: the adapter 5803 * @mbox: mailbox to use for the FW command 5804 * @viid: the VI id 5805 * @idx: index of existing filter for old value of MAC address, or -1 5806 * @addr: the new MAC address value 5807 * @persist: whether a new MAC allocation should be persistent 5808 * @add_smt: if true also add the address to the HW SMT 5809 * 5810 * Modifies an exact-match filter and sets it to the new MAC address. 5811 * Note that in general it is not possible to modify the value of a given 5812 * filter so the generic way to modify an address filter is to free the one 5813 * being used by the old address value and allocate a new filter for the 5814 * new address value. @idx can be -1 if the address is a new addition. 5815 * 5816 * Returns a negative error number or the index of the filter with the new 5817 * MAC value. 5818 */ 5819 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 5820 int idx, const u8 *addr, bool persist, bool add_smt) 5821 { 5822 int ret, mode; 5823 struct fw_vi_mac_cmd c; 5824 struct fw_vi_mac_exact *p = c.u.exact; 5825 unsigned int max_mac_addr = adap->params.arch.mps_tcam_size; 5826 5827 if (idx < 0) /* new allocation */ 5828 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC; 5829 mode = add_smt ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY; 5830 5831 memset(&c, 0, sizeof(c)); 5832 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) | 5833 FW_CMD_REQUEST_F | FW_CMD_WRITE_F | 5834 FW_VI_MAC_CMD_VIID_V(viid)); 5835 c.freemacs_to_len16 = cpu_to_be32(FW_CMD_LEN16_V(1)); 5836 p->valid_to_idx = cpu_to_be16(FW_VI_MAC_CMD_VALID_F | 5837 FW_VI_MAC_CMD_SMAC_RESULT_V(mode) | 5838 FW_VI_MAC_CMD_IDX_V(idx)); 5839 memcpy(p->macaddr, addr, sizeof(p->macaddr)); 5840 5841 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 5842 if (ret == 0) { 5843 ret = FW_VI_MAC_CMD_IDX_G(be16_to_cpu(p->valid_to_idx)); 5844 if (ret >= max_mac_addr) 5845 ret = -ENOMEM; 5846 } 5847 return ret; 5848 } 5849 5850 /** 5851 * t4_set_addr_hash - program the MAC inexact-match hash filter 5852 * @adap: the adapter 5853 * @mbox: mailbox to use for the FW command 5854 * @viid: the VI id 5855 * @ucast: whether the hash filter should also match unicast addresses 5856 * @vec: the value to be written to the hash filter 5857 * @sleep_ok: call is allowed to sleep 5858 * 5859 * Sets the 64-bit inexact-match hash filter for a virtual interface. 5860 */ 5861 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 5862 bool ucast, u64 vec, bool sleep_ok) 5863 { 5864 struct fw_vi_mac_cmd c; 5865 5866 memset(&c, 0, sizeof(c)); 5867 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) | 5868 FW_CMD_REQUEST_F | FW_CMD_WRITE_F | 5869 FW_VI_ENABLE_CMD_VIID_V(viid)); 5870 c.freemacs_to_len16 = cpu_to_be32(FW_VI_MAC_CMD_HASHVECEN_F | 5871 FW_VI_MAC_CMD_HASHUNIEN_V(ucast) | 5872 FW_CMD_LEN16_V(1)); 5873 c.u.hash.hashvec = cpu_to_be64(vec); 5874 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok); 5875 } 5876 5877 /** 5878 * t4_enable_vi_params - enable/disable a virtual interface 5879 * @adap: the adapter 5880 * @mbox: mailbox to use for the FW command 5881 * @viid: the VI id 5882 * @rx_en: 1=enable Rx, 0=disable Rx 5883 * @tx_en: 1=enable Tx, 0=disable Tx 5884 * @dcb_en: 1=enable delivery of Data Center Bridging messages. 5885 * 5886 * Enables/disables a virtual interface. Note that setting DCB Enable 5887 * only makes sense when enabling a Virtual Interface ... 5888 */ 5889 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 5890 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en) 5891 { 5892 struct fw_vi_enable_cmd c; 5893 5894 memset(&c, 0, sizeof(c)); 5895 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) | 5896 FW_CMD_REQUEST_F | FW_CMD_EXEC_F | 5897 FW_VI_ENABLE_CMD_VIID_V(viid)); 5898 c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_IEN_V(rx_en) | 5899 FW_VI_ENABLE_CMD_EEN_V(tx_en) | 5900 FW_VI_ENABLE_CMD_DCB_INFO_V(dcb_en) | 5901 FW_LEN16(c)); 5902 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL); 5903 } 5904 5905 /** 5906 * t4_enable_vi - enable/disable a virtual interface 5907 * @adap: the adapter 5908 * @mbox: mailbox to use for the FW command 5909 * @viid: the VI id 5910 * @rx_en: 1=enable Rx, 0=disable Rx 5911 * @tx_en: 1=enable Tx, 0=disable Tx 5912 * 5913 * Enables/disables a virtual interface. 5914 */ 5915 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 5916 bool rx_en, bool tx_en) 5917 { 5918 return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0); 5919 } 5920 5921 /** 5922 * t4_identify_port - identify a VI's port by blinking its LED 5923 * @adap: the adapter 5924 * @mbox: mailbox to use for the FW command 5925 * @viid: the VI id 5926 * @nblinks: how many times to blink LED at 2.5 Hz 5927 * 5928 * Identifies a VI's port by blinking its LED. 5929 */ 5930 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 5931 unsigned int nblinks) 5932 { 5933 struct fw_vi_enable_cmd c; 5934 5935 memset(&c, 0, sizeof(c)); 5936 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) | 5937 FW_CMD_REQUEST_F | FW_CMD_EXEC_F | 5938 FW_VI_ENABLE_CMD_VIID_V(viid)); 5939 c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_LED_F | FW_LEN16(c)); 5940 c.blinkdur = cpu_to_be16(nblinks); 5941 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 5942 } 5943 5944 /** 5945 * t4_iq_free - free an ingress queue and its FLs 5946 * @adap: the adapter 5947 * @mbox: mailbox to use for the FW command 5948 * @pf: the PF owning the queues 5949 * @vf: the VF owning the queues 5950 * @iqtype: the ingress queue type 5951 * @iqid: ingress queue id 5952 * @fl0id: FL0 queue id or 0xffff if no attached FL0 5953 * @fl1id: FL1 queue id or 0xffff if no attached FL1 5954 * 5955 * Frees an ingress queue and its associated FLs, if any. 5956 */ 5957 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 5958 unsigned int vf, unsigned int iqtype, unsigned int iqid, 5959 unsigned int fl0id, unsigned int fl1id) 5960 { 5961 struct fw_iq_cmd c; 5962 5963 memset(&c, 0, sizeof(c)); 5964 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F | 5965 FW_CMD_EXEC_F | FW_IQ_CMD_PFN_V(pf) | 5966 FW_IQ_CMD_VFN_V(vf)); 5967 c.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_FREE_F | FW_LEN16(c)); 5968 c.type_to_iqandstindex = cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype)); 5969 c.iqid = cpu_to_be16(iqid); 5970 c.fl0id = cpu_to_be16(fl0id); 5971 c.fl1id = cpu_to_be16(fl1id); 5972 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 5973 } 5974 5975 /** 5976 * t4_eth_eq_free - free an Ethernet egress queue 5977 * @adap: the adapter 5978 * @mbox: mailbox to use for the FW command 5979 * @pf: the PF owning the queue 5980 * @vf: the VF owning the queue 5981 * @eqid: egress queue id 5982 * 5983 * Frees an Ethernet egress queue. 5984 */ 5985 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 5986 unsigned int vf, unsigned int eqid) 5987 { 5988 struct fw_eq_eth_cmd c; 5989 5990 memset(&c, 0, sizeof(c)); 5991 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_ETH_CMD) | 5992 FW_CMD_REQUEST_F | FW_CMD_EXEC_F | 5993 FW_EQ_ETH_CMD_PFN_V(pf) | 5994 FW_EQ_ETH_CMD_VFN_V(vf)); 5995 c.alloc_to_len16 = cpu_to_be32(FW_EQ_ETH_CMD_FREE_F | FW_LEN16(c)); 5996 c.eqid_pkd = cpu_to_be32(FW_EQ_ETH_CMD_EQID_V(eqid)); 5997 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 5998 } 5999 6000 /** 6001 * t4_ctrl_eq_free - free a control egress queue 6002 * @adap: the adapter 6003 * @mbox: mailbox to use for the FW command 6004 * @pf: the PF owning the queue 6005 * @vf: the VF owning the queue 6006 * @eqid: egress queue id 6007 * 6008 * Frees a control egress queue. 6009 */ 6010 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 6011 unsigned int vf, unsigned int eqid) 6012 { 6013 struct fw_eq_ctrl_cmd c; 6014 6015 memset(&c, 0, sizeof(c)); 6016 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_CTRL_CMD) | 6017 FW_CMD_REQUEST_F | FW_CMD_EXEC_F | 6018 FW_EQ_CTRL_CMD_PFN_V(pf) | 6019 FW_EQ_CTRL_CMD_VFN_V(vf)); 6020 c.alloc_to_len16 = cpu_to_be32(FW_EQ_CTRL_CMD_FREE_F | FW_LEN16(c)); 6021 c.cmpliqid_eqid = cpu_to_be32(FW_EQ_CTRL_CMD_EQID_V(eqid)); 6022 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 6023 } 6024 6025 /** 6026 * t4_ofld_eq_free - free an offload egress queue 6027 * @adap: the adapter 6028 * @mbox: mailbox to use for the FW command 6029 * @pf: the PF owning the queue 6030 * @vf: the VF owning the queue 6031 * @eqid: egress queue id 6032 * 6033 * Frees a control egress queue. 6034 */ 6035 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 6036 unsigned int vf, unsigned int eqid) 6037 { 6038 struct fw_eq_ofld_cmd c; 6039 6040 memset(&c, 0, sizeof(c)); 6041 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_OFLD_CMD) | 6042 FW_CMD_REQUEST_F | FW_CMD_EXEC_F | 6043 FW_EQ_OFLD_CMD_PFN_V(pf) | 6044 FW_EQ_OFLD_CMD_VFN_V(vf)); 6045 c.alloc_to_len16 = cpu_to_be32(FW_EQ_OFLD_CMD_FREE_F | FW_LEN16(c)); 6046 c.eqid_pkd = cpu_to_be32(FW_EQ_OFLD_CMD_EQID_V(eqid)); 6047 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 6048 } 6049 6050 /** 6051 * t4_handle_fw_rpl - process a FW reply message 6052 * @adap: the adapter 6053 * @rpl: start of the FW message 6054 * 6055 * Processes a FW message, such as link state change messages. 6056 */ 6057 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl) 6058 { 6059 u8 opcode = *(const u8 *)rpl; 6060 6061 if (opcode == FW_PORT_CMD) { /* link/module state change message */ 6062 int speed = 0, fc = 0; 6063 const struct fw_port_cmd *p = (void *)rpl; 6064 int chan = FW_PORT_CMD_PORTID_G(be32_to_cpu(p->op_to_portid)); 6065 int port = adap->chan_map[chan]; 6066 struct port_info *pi = adap2pinfo(adap, port); 6067 struct link_config *lc = &pi->link_cfg; 6068 u32 stat = be32_to_cpu(p->u.info.lstatus_to_modtype); 6069 int link_ok = (stat & FW_PORT_CMD_LSTATUS_F) != 0; 6070 u32 mod = FW_PORT_CMD_MODTYPE_G(stat); 6071 6072 if (stat & FW_PORT_CMD_RXPAUSE_F) 6073 fc |= PAUSE_RX; 6074 if (stat & FW_PORT_CMD_TXPAUSE_F) 6075 fc |= PAUSE_TX; 6076 if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100M)) 6077 speed = 100; 6078 else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_1G)) 6079 speed = 1000; 6080 else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_10G)) 6081 speed = 10000; 6082 else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_40G)) 6083 speed = 40000; 6084 6085 if (link_ok != lc->link_ok || speed != lc->speed || 6086 fc != lc->fc) { /* something changed */ 6087 lc->link_ok = link_ok; 6088 lc->speed = speed; 6089 lc->fc = fc; 6090 lc->supported = be16_to_cpu(p->u.info.pcap); 6091 t4_os_link_changed(adap, port, link_ok); 6092 } 6093 if (mod != pi->mod_type) { 6094 pi->mod_type = mod; 6095 t4_os_portmod_changed(adap, port); 6096 } 6097 } 6098 return 0; 6099 } 6100 6101 static void get_pci_mode(struct adapter *adapter, struct pci_params *p) 6102 { 6103 u16 val; 6104 6105 if (pci_is_pcie(adapter->pdev)) { 6106 pcie_capability_read_word(adapter->pdev, PCI_EXP_LNKSTA, &val); 6107 p->speed = val & PCI_EXP_LNKSTA_CLS; 6108 p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4; 6109 } 6110 } 6111 6112 /** 6113 * init_link_config - initialize a link's SW state 6114 * @lc: structure holding the link state 6115 * @caps: link capabilities 6116 * 6117 * Initializes the SW state maintained for each link, including the link's 6118 * capabilities and default speed/flow-control/autonegotiation settings. 6119 */ 6120 static void init_link_config(struct link_config *lc, unsigned int caps) 6121 { 6122 lc->supported = caps; 6123 lc->requested_speed = 0; 6124 lc->speed = 0; 6125 lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX; 6126 if (lc->supported & FW_PORT_CAP_ANEG) { 6127 lc->advertising = lc->supported & ADVERT_MASK; 6128 lc->autoneg = AUTONEG_ENABLE; 6129 lc->requested_fc |= PAUSE_AUTONEG; 6130 } else { 6131 lc->advertising = 0; 6132 lc->autoneg = AUTONEG_DISABLE; 6133 } 6134 } 6135 6136 #define CIM_PF_NOACCESS 0xeeeeeeee 6137 6138 int t4_wait_dev_ready(void __iomem *regs) 6139 { 6140 u32 whoami; 6141 6142 whoami = readl(regs + PL_WHOAMI_A); 6143 if (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS) 6144 return 0; 6145 6146 msleep(500); 6147 whoami = readl(regs + PL_WHOAMI_A); 6148 return (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS ? 0 : -EIO); 6149 } 6150 6151 struct flash_desc { 6152 u32 vendor_and_model_id; 6153 u32 size_mb; 6154 }; 6155 6156 static int get_flash_params(struct adapter *adap) 6157 { 6158 /* Table for non-Numonix supported flash parts. Numonix parts are left 6159 * to the preexisting code. All flash parts have 64KB sectors. 6160 */ 6161 static struct flash_desc supported_flash[] = { 6162 { 0x150201, 4 << 20 }, /* Spansion 4MB S25FL032P */ 6163 }; 6164 6165 int ret; 6166 u32 info; 6167 6168 ret = sf1_write(adap, 1, 1, 0, SF_RD_ID); 6169 if (!ret) 6170 ret = sf1_read(adap, 3, 0, 1, &info); 6171 t4_write_reg(adap, SF_OP_A, 0); /* unlock SF */ 6172 if (ret) 6173 return ret; 6174 6175 for (ret = 0; ret < ARRAY_SIZE(supported_flash); ++ret) 6176 if (supported_flash[ret].vendor_and_model_id == info) { 6177 adap->params.sf_size = supported_flash[ret].size_mb; 6178 adap->params.sf_nsec = 6179 adap->params.sf_size / SF_SEC_SIZE; 6180 return 0; 6181 } 6182 6183 if ((info & 0xff) != 0x20) /* not a Numonix flash */ 6184 return -EINVAL; 6185 info >>= 16; /* log2 of size */ 6186 if (info >= 0x14 && info < 0x18) 6187 adap->params.sf_nsec = 1 << (info - 16); 6188 else if (info == 0x18) 6189 adap->params.sf_nsec = 64; 6190 else 6191 return -EINVAL; 6192 adap->params.sf_size = 1 << info; 6193 adap->params.sf_fw_start = 6194 t4_read_reg(adap, CIM_BOOT_CFG_A) & BOOTADDR_M; 6195 6196 if (adap->params.sf_size < FLASH_MIN_SIZE) 6197 dev_warn(adap->pdev_dev, "WARNING!!! FLASH size %#x < %#x!!!\n", 6198 adap->params.sf_size, FLASH_MIN_SIZE); 6199 return 0; 6200 } 6201 6202 static void set_pcie_completion_timeout(struct adapter *adapter, u8 range) 6203 { 6204 u16 val; 6205 u32 pcie_cap; 6206 6207 pcie_cap = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP); 6208 if (pcie_cap) { 6209 pci_read_config_word(adapter->pdev, 6210 pcie_cap + PCI_EXP_DEVCTL2, &val); 6211 val &= ~PCI_EXP_DEVCTL2_COMP_TIMEOUT; 6212 val |= range; 6213 pci_write_config_word(adapter->pdev, 6214 pcie_cap + PCI_EXP_DEVCTL2, val); 6215 } 6216 } 6217 6218 /** 6219 * t4_prep_adapter - prepare SW and HW for operation 6220 * @adapter: the adapter 6221 * @reset: if true perform a HW reset 6222 * 6223 * Initialize adapter SW state for the various HW modules, set initial 6224 * values for some adapter tunables, take PHYs out of reset, and 6225 * initialize the MDIO interface. 6226 */ 6227 int t4_prep_adapter(struct adapter *adapter) 6228 { 6229 int ret, ver; 6230 uint16_t device_id; 6231 u32 pl_rev; 6232 6233 get_pci_mode(adapter, &adapter->params.pci); 6234 pl_rev = REV_G(t4_read_reg(adapter, PL_REV_A)); 6235 6236 ret = get_flash_params(adapter); 6237 if (ret < 0) { 6238 dev_err(adapter->pdev_dev, "error %d identifying flash\n", ret); 6239 return ret; 6240 } 6241 6242 /* Retrieve adapter's device ID 6243 */ 6244 pci_read_config_word(adapter->pdev, PCI_DEVICE_ID, &device_id); 6245 ver = device_id >> 12; 6246 adapter->params.chip = 0; 6247 switch (ver) { 6248 case CHELSIO_T4: 6249 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev); 6250 adapter->params.arch.sge_fl_db = DBPRIO_F; 6251 adapter->params.arch.mps_tcam_size = 6252 NUM_MPS_CLS_SRAM_L_INSTANCES; 6253 adapter->params.arch.mps_rplc_size = 128; 6254 adapter->params.arch.nchan = NCHAN; 6255 adapter->params.arch.vfcount = 128; 6256 break; 6257 case CHELSIO_T5: 6258 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev); 6259 adapter->params.arch.sge_fl_db = DBPRIO_F | DBTYPE_F; 6260 adapter->params.arch.mps_tcam_size = 6261 NUM_MPS_T5_CLS_SRAM_L_INSTANCES; 6262 adapter->params.arch.mps_rplc_size = 128; 6263 adapter->params.arch.nchan = NCHAN; 6264 adapter->params.arch.vfcount = 128; 6265 break; 6266 case CHELSIO_T6: 6267 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev); 6268 adapter->params.arch.sge_fl_db = 0; 6269 adapter->params.arch.mps_tcam_size = 6270 NUM_MPS_T5_CLS_SRAM_L_INSTANCES; 6271 adapter->params.arch.mps_rplc_size = 256; 6272 adapter->params.arch.nchan = 2; 6273 adapter->params.arch.vfcount = 256; 6274 break; 6275 default: 6276 dev_err(adapter->pdev_dev, "Device %d is not supported\n", 6277 device_id); 6278 return -EINVAL; 6279 } 6280 6281 adapter->params.cim_la_size = CIMLA_SIZE; 6282 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd); 6283 6284 /* 6285 * Default port for debugging in case we can't reach FW. 6286 */ 6287 adapter->params.nports = 1; 6288 adapter->params.portvec = 1; 6289 adapter->params.vpd.cclk = 50000; 6290 6291 /* Set pci completion timeout value to 4 seconds. */ 6292 set_pcie_completion_timeout(adapter, 0xd); 6293 return 0; 6294 } 6295 6296 /** 6297 * t4_bar2_sge_qregs - return BAR2 SGE Queue register information 6298 * @adapter: the adapter 6299 * @qid: the Queue ID 6300 * @qtype: the Ingress or Egress type for @qid 6301 * @user: true if this request is for a user mode queue 6302 * @pbar2_qoffset: BAR2 Queue Offset 6303 * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues 6304 * 6305 * Returns the BAR2 SGE Queue Registers information associated with the 6306 * indicated Absolute Queue ID. These are passed back in return value 6307 * pointers. @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue 6308 * and T4_BAR2_QTYPE_INGRESS for Ingress Queues. 6309 * 6310 * This may return an error which indicates that BAR2 SGE Queue 6311 * registers aren't available. If an error is not returned, then the 6312 * following values are returned: 6313 * 6314 * *@pbar2_qoffset: the BAR2 Offset of the @qid Registers 6315 * *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid 6316 * 6317 * If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which 6318 * require the "Inferred Queue ID" ability may be used. E.g. the 6319 * Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0, 6320 * then these "Inferred Queue ID" register may not be used. 6321 */ 6322 int t4_bar2_sge_qregs(struct adapter *adapter, 6323 unsigned int qid, 6324 enum t4_bar2_qtype qtype, 6325 int user, 6326 u64 *pbar2_qoffset, 6327 unsigned int *pbar2_qid) 6328 { 6329 unsigned int page_shift, page_size, qpp_shift, qpp_mask; 6330 u64 bar2_page_offset, bar2_qoffset; 6331 unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred; 6332 6333 /* T4 doesn't support BAR2 SGE Queue registers for kernel mode queues */ 6334 if (!user && is_t4(adapter->params.chip)) 6335 return -EINVAL; 6336 6337 /* Get our SGE Page Size parameters. 6338 */ 6339 page_shift = adapter->params.sge.hps + 10; 6340 page_size = 1 << page_shift; 6341 6342 /* Get the right Queues per Page parameters for our Queue. 6343 */ 6344 qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS 6345 ? adapter->params.sge.eq_qpp 6346 : adapter->params.sge.iq_qpp); 6347 qpp_mask = (1 << qpp_shift) - 1; 6348 6349 /* Calculate the basics of the BAR2 SGE Queue register area: 6350 * o The BAR2 page the Queue registers will be in. 6351 * o The BAR2 Queue ID. 6352 * o The BAR2 Queue ID Offset into the BAR2 page. 6353 */ 6354 bar2_page_offset = ((u64)(qid >> qpp_shift) << page_shift); 6355 bar2_qid = qid & qpp_mask; 6356 bar2_qid_offset = bar2_qid * SGE_UDB_SIZE; 6357 6358 /* If the BAR2 Queue ID Offset is less than the Page Size, then the 6359 * hardware will infer the Absolute Queue ID simply from the writes to 6360 * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a 6361 * BAR2 Queue ID of 0 for those writes). Otherwise, we'll simply 6362 * write to the first BAR2 SGE Queue Area within the BAR2 Page with 6363 * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID 6364 * from the BAR2 Page and BAR2 Queue ID. 6365 * 6366 * One important censequence of this is that some BAR2 SGE registers 6367 * have a "Queue ID" field and we can write the BAR2 SGE Queue ID 6368 * there. But other registers synthesize the SGE Queue ID purely 6369 * from the writes to the registers -- the Write Combined Doorbell 6370 * Buffer is a good example. These BAR2 SGE Registers are only 6371 * available for those BAR2 SGE Register areas where the SGE Absolute 6372 * Queue ID can be inferred from simple writes. 6373 */ 6374 bar2_qoffset = bar2_page_offset; 6375 bar2_qinferred = (bar2_qid_offset < page_size); 6376 if (bar2_qinferred) { 6377 bar2_qoffset += bar2_qid_offset; 6378 bar2_qid = 0; 6379 } 6380 6381 *pbar2_qoffset = bar2_qoffset; 6382 *pbar2_qid = bar2_qid; 6383 return 0; 6384 } 6385 6386 /** 6387 * t4_init_devlog_params - initialize adapter->params.devlog 6388 * @adap: the adapter 6389 * 6390 * Initialize various fields of the adapter's Firmware Device Log 6391 * Parameters structure. 6392 */ 6393 int t4_init_devlog_params(struct adapter *adap) 6394 { 6395 struct devlog_params *dparams = &adap->params.devlog; 6396 u32 pf_dparams; 6397 unsigned int devlog_meminfo; 6398 struct fw_devlog_cmd devlog_cmd; 6399 int ret; 6400 6401 /* If we're dealing with newer firmware, the Device Log Paramerters 6402 * are stored in a designated register which allows us to access the 6403 * Device Log even if we can't talk to the firmware. 6404 */ 6405 pf_dparams = 6406 t4_read_reg(adap, PCIE_FW_REG(PCIE_FW_PF_A, PCIE_FW_PF_DEVLOG)); 6407 if (pf_dparams) { 6408 unsigned int nentries, nentries128; 6409 6410 dparams->memtype = PCIE_FW_PF_DEVLOG_MEMTYPE_G(pf_dparams); 6411 dparams->start = PCIE_FW_PF_DEVLOG_ADDR16_G(pf_dparams) << 4; 6412 6413 nentries128 = PCIE_FW_PF_DEVLOG_NENTRIES128_G(pf_dparams); 6414 nentries = (nentries128 + 1) * 128; 6415 dparams->size = nentries * sizeof(struct fw_devlog_e); 6416 6417 return 0; 6418 } 6419 6420 /* Otherwise, ask the firmware for it's Device Log Parameters. 6421 */ 6422 memset(&devlog_cmd, 0, sizeof(devlog_cmd)); 6423 devlog_cmd.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_DEVLOG_CMD) | 6424 FW_CMD_REQUEST_F | FW_CMD_READ_F); 6425 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd)); 6426 ret = t4_wr_mbox(adap, adap->mbox, &devlog_cmd, sizeof(devlog_cmd), 6427 &devlog_cmd); 6428 if (ret) 6429 return ret; 6430 6431 devlog_meminfo = 6432 be32_to_cpu(devlog_cmd.memtype_devlog_memaddr16_devlog); 6433 dparams->memtype = FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(devlog_meminfo); 6434 dparams->start = FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(devlog_meminfo) << 4; 6435 dparams->size = be32_to_cpu(devlog_cmd.memsize_devlog); 6436 6437 return 0; 6438 } 6439 6440 /** 6441 * t4_init_sge_params - initialize adap->params.sge 6442 * @adapter: the adapter 6443 * 6444 * Initialize various fields of the adapter's SGE Parameters structure. 6445 */ 6446 int t4_init_sge_params(struct adapter *adapter) 6447 { 6448 struct sge_params *sge_params = &adapter->params.sge; 6449 u32 hps, qpp; 6450 unsigned int s_hps, s_qpp; 6451 6452 /* Extract the SGE Page Size for our PF. 6453 */ 6454 hps = t4_read_reg(adapter, SGE_HOST_PAGE_SIZE_A); 6455 s_hps = (HOSTPAGESIZEPF0_S + 6456 (HOSTPAGESIZEPF1_S - HOSTPAGESIZEPF0_S) * adapter->pf); 6457 sge_params->hps = ((hps >> s_hps) & HOSTPAGESIZEPF0_M); 6458 6459 /* Extract the SGE Egress and Ingess Queues Per Page for our PF. 6460 */ 6461 s_qpp = (QUEUESPERPAGEPF0_S + 6462 (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) * adapter->pf); 6463 qpp = t4_read_reg(adapter, SGE_EGRESS_QUEUES_PER_PAGE_PF_A); 6464 sge_params->eq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M); 6465 qpp = t4_read_reg(adapter, SGE_INGRESS_QUEUES_PER_PAGE_PF_A); 6466 sge_params->iq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M); 6467 6468 return 0; 6469 } 6470 6471 /** 6472 * t4_init_tp_params - initialize adap->params.tp 6473 * @adap: the adapter 6474 * 6475 * Initialize various fields of the adapter's TP Parameters structure. 6476 */ 6477 int t4_init_tp_params(struct adapter *adap) 6478 { 6479 int chan; 6480 u32 v; 6481 6482 v = t4_read_reg(adap, TP_TIMER_RESOLUTION_A); 6483 adap->params.tp.tre = TIMERRESOLUTION_G(v); 6484 adap->params.tp.dack_re = DELAYEDACKRESOLUTION_G(v); 6485 6486 /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */ 6487 for (chan = 0; chan < NCHAN; chan++) 6488 adap->params.tp.tx_modq[chan] = chan; 6489 6490 /* Cache the adapter's Compressed Filter Mode and global Incress 6491 * Configuration. 6492 */ 6493 if (t4_use_ldst(adap)) { 6494 t4_fw_tp_pio_rw(adap, &adap->params.tp.vlan_pri_map, 1, 6495 TP_VLAN_PRI_MAP_A, 1); 6496 t4_fw_tp_pio_rw(adap, &adap->params.tp.ingress_config, 1, 6497 TP_INGRESS_CONFIG_A, 1); 6498 } else { 6499 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, 6500 &adap->params.tp.vlan_pri_map, 1, 6501 TP_VLAN_PRI_MAP_A); 6502 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, 6503 &adap->params.tp.ingress_config, 1, 6504 TP_INGRESS_CONFIG_A); 6505 } 6506 6507 /* Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field 6508 * shift positions of several elements of the Compressed Filter Tuple 6509 * for this adapter which we need frequently ... 6510 */ 6511 adap->params.tp.vlan_shift = t4_filter_field_shift(adap, VLAN_F); 6512 adap->params.tp.vnic_shift = t4_filter_field_shift(adap, VNIC_ID_F); 6513 adap->params.tp.port_shift = t4_filter_field_shift(adap, PORT_F); 6514 adap->params.tp.protocol_shift = t4_filter_field_shift(adap, 6515 PROTOCOL_F); 6516 6517 /* If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID 6518 * represents the presence of an Outer VLAN instead of a VNIC ID. 6519 */ 6520 if ((adap->params.tp.ingress_config & VNIC_F) == 0) 6521 adap->params.tp.vnic_shift = -1; 6522 6523 return 0; 6524 } 6525 6526 /** 6527 * t4_filter_field_shift - calculate filter field shift 6528 * @adap: the adapter 6529 * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits) 6530 * 6531 * Return the shift position of a filter field within the Compressed 6532 * Filter Tuple. The filter field is specified via its selection bit 6533 * within TP_VLAN_PRI_MAL (filter mode). E.g. F_VLAN. 6534 */ 6535 int t4_filter_field_shift(const struct adapter *adap, int filter_sel) 6536 { 6537 unsigned int filter_mode = adap->params.tp.vlan_pri_map; 6538 unsigned int sel; 6539 int field_shift; 6540 6541 if ((filter_mode & filter_sel) == 0) 6542 return -1; 6543 6544 for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) { 6545 switch (filter_mode & sel) { 6546 case FCOE_F: 6547 field_shift += FT_FCOE_W; 6548 break; 6549 case PORT_F: 6550 field_shift += FT_PORT_W; 6551 break; 6552 case VNIC_ID_F: 6553 field_shift += FT_VNIC_ID_W; 6554 break; 6555 case VLAN_F: 6556 field_shift += FT_VLAN_W; 6557 break; 6558 case TOS_F: 6559 field_shift += FT_TOS_W; 6560 break; 6561 case PROTOCOL_F: 6562 field_shift += FT_PROTOCOL_W; 6563 break; 6564 case ETHERTYPE_F: 6565 field_shift += FT_ETHERTYPE_W; 6566 break; 6567 case MACMATCH_F: 6568 field_shift += FT_MACMATCH_W; 6569 break; 6570 case MPSHITTYPE_F: 6571 field_shift += FT_MPSHITTYPE_W; 6572 break; 6573 case FRAGMENTATION_F: 6574 field_shift += FT_FRAGMENTATION_W; 6575 break; 6576 } 6577 } 6578 return field_shift; 6579 } 6580 6581 int t4_init_rss_mode(struct adapter *adap, int mbox) 6582 { 6583 int i, ret; 6584 struct fw_rss_vi_config_cmd rvc; 6585 6586 memset(&rvc, 0, sizeof(rvc)); 6587 6588 for_each_port(adap, i) { 6589 struct port_info *p = adap2pinfo(adap, i); 6590 6591 rvc.op_to_viid = 6592 cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) | 6593 FW_CMD_REQUEST_F | FW_CMD_READ_F | 6594 FW_RSS_VI_CONFIG_CMD_VIID_V(p->viid)); 6595 rvc.retval_len16 = cpu_to_be32(FW_LEN16(rvc)); 6596 ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc); 6597 if (ret) 6598 return ret; 6599 p->rss_mode = be32_to_cpu(rvc.u.basicvirtual.defaultq_to_udpen); 6600 } 6601 return 0; 6602 } 6603 6604 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf) 6605 { 6606 u8 addr[6]; 6607 int ret, i, j = 0; 6608 struct fw_port_cmd c; 6609 struct fw_rss_vi_config_cmd rvc; 6610 6611 memset(&c, 0, sizeof(c)); 6612 memset(&rvc, 0, sizeof(rvc)); 6613 6614 for_each_port(adap, i) { 6615 unsigned int rss_size; 6616 struct port_info *p = adap2pinfo(adap, i); 6617 6618 while ((adap->params.portvec & (1 << j)) == 0) 6619 j++; 6620 6621 c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) | 6622 FW_CMD_REQUEST_F | FW_CMD_READ_F | 6623 FW_PORT_CMD_PORTID_V(j)); 6624 c.action_to_len16 = cpu_to_be32( 6625 FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_GET_PORT_INFO) | 6626 FW_LEN16(c)); 6627 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 6628 if (ret) 6629 return ret; 6630 6631 ret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &rss_size); 6632 if (ret < 0) 6633 return ret; 6634 6635 p->viid = ret; 6636 p->tx_chan = j; 6637 p->lport = j; 6638 p->rss_size = rss_size; 6639 memcpy(adap->port[i]->dev_addr, addr, ETH_ALEN); 6640 adap->port[i]->dev_port = j; 6641 6642 ret = be32_to_cpu(c.u.info.lstatus_to_modtype); 6643 p->mdio_addr = (ret & FW_PORT_CMD_MDIOCAP_F) ? 6644 FW_PORT_CMD_MDIOADDR_G(ret) : -1; 6645 p->port_type = FW_PORT_CMD_PTYPE_G(ret); 6646 p->mod_type = FW_PORT_MOD_TYPE_NA; 6647 6648 rvc.op_to_viid = 6649 cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) | 6650 FW_CMD_REQUEST_F | FW_CMD_READ_F | 6651 FW_RSS_VI_CONFIG_CMD_VIID(p->viid)); 6652 rvc.retval_len16 = cpu_to_be32(FW_LEN16(rvc)); 6653 ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc); 6654 if (ret) 6655 return ret; 6656 p->rss_mode = be32_to_cpu(rvc.u.basicvirtual.defaultq_to_udpen); 6657 6658 init_link_config(&p->link_cfg, be16_to_cpu(c.u.info.pcap)); 6659 j++; 6660 } 6661 return 0; 6662 } 6663 6664 /** 6665 * t4_read_cimq_cfg - read CIM queue configuration 6666 * @adap: the adapter 6667 * @base: holds the queue base addresses in bytes 6668 * @size: holds the queue sizes in bytes 6669 * @thres: holds the queue full thresholds in bytes 6670 * 6671 * Returns the current configuration of the CIM queues, starting with 6672 * the IBQs, then the OBQs. 6673 */ 6674 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres) 6675 { 6676 unsigned int i, v; 6677 int cim_num_obq = is_t4(adap->params.chip) ? 6678 CIM_NUM_OBQ : CIM_NUM_OBQ_T5; 6679 6680 for (i = 0; i < CIM_NUM_IBQ; i++) { 6681 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, IBQSELECT_F | 6682 QUENUMSELECT_V(i)); 6683 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A); 6684 /* value is in 256-byte units */ 6685 *base++ = CIMQBASE_G(v) * 256; 6686 *size++ = CIMQSIZE_G(v) * 256; 6687 *thres++ = QUEFULLTHRSH_G(v) * 8; /* 8-byte unit */ 6688 } 6689 for (i = 0; i < cim_num_obq; i++) { 6690 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F | 6691 QUENUMSELECT_V(i)); 6692 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A); 6693 /* value is in 256-byte units */ 6694 *base++ = CIMQBASE_G(v) * 256; 6695 *size++ = CIMQSIZE_G(v) * 256; 6696 } 6697 } 6698 6699 /** 6700 * t4_read_cim_ibq - read the contents of a CIM inbound queue 6701 * @adap: the adapter 6702 * @qid: the queue index 6703 * @data: where to store the queue contents 6704 * @n: capacity of @data in 32-bit words 6705 * 6706 * Reads the contents of the selected CIM queue starting at address 0 up 6707 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on 6708 * error and the number of 32-bit words actually read on success. 6709 */ 6710 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n) 6711 { 6712 int i, err, attempts; 6713 unsigned int addr; 6714 const unsigned int nwords = CIM_IBQ_SIZE * 4; 6715 6716 if (qid > 5 || (n & 3)) 6717 return -EINVAL; 6718 6719 addr = qid * nwords; 6720 if (n > nwords) 6721 n = nwords; 6722 6723 /* It might take 3-10ms before the IBQ debug read access is allowed. 6724 * Wait for 1 Sec with a delay of 1 usec. 6725 */ 6726 attempts = 1000000; 6727 6728 for (i = 0; i < n; i++, addr++) { 6729 t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, IBQDBGADDR_V(addr) | 6730 IBQDBGEN_F); 6731 err = t4_wait_op_done(adap, CIM_IBQ_DBG_CFG_A, IBQDBGBUSY_F, 0, 6732 attempts, 1); 6733 if (err) 6734 return err; 6735 *data++ = t4_read_reg(adap, CIM_IBQ_DBG_DATA_A); 6736 } 6737 t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, 0); 6738 return i; 6739 } 6740 6741 /** 6742 * t4_read_cim_obq - read the contents of a CIM outbound queue 6743 * @adap: the adapter 6744 * @qid: the queue index 6745 * @data: where to store the queue contents 6746 * @n: capacity of @data in 32-bit words 6747 * 6748 * Reads the contents of the selected CIM queue starting at address 0 up 6749 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on 6750 * error and the number of 32-bit words actually read on success. 6751 */ 6752 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n) 6753 { 6754 int i, err; 6755 unsigned int addr, v, nwords; 6756 int cim_num_obq = is_t4(adap->params.chip) ? 6757 CIM_NUM_OBQ : CIM_NUM_OBQ_T5; 6758 6759 if ((qid > (cim_num_obq - 1)) || (n & 3)) 6760 return -EINVAL; 6761 6762 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F | 6763 QUENUMSELECT_V(qid)); 6764 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A); 6765 6766 addr = CIMQBASE_G(v) * 64; /* muliple of 256 -> muliple of 4 */ 6767 nwords = CIMQSIZE_G(v) * 64; /* same */ 6768 if (n > nwords) 6769 n = nwords; 6770 6771 for (i = 0; i < n; i++, addr++) { 6772 t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, OBQDBGADDR_V(addr) | 6773 OBQDBGEN_F); 6774 err = t4_wait_op_done(adap, CIM_OBQ_DBG_CFG_A, OBQDBGBUSY_F, 0, 6775 2, 1); 6776 if (err) 6777 return err; 6778 *data++ = t4_read_reg(adap, CIM_OBQ_DBG_DATA_A); 6779 } 6780 t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, 0); 6781 return i; 6782 } 6783 6784 /** 6785 * t4_cim_read - read a block from CIM internal address space 6786 * @adap: the adapter 6787 * @addr: the start address within the CIM address space 6788 * @n: number of words to read 6789 * @valp: where to store the result 6790 * 6791 * Reads a block of 4-byte words from the CIM intenal address space. 6792 */ 6793 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 6794 unsigned int *valp) 6795 { 6796 int ret = 0; 6797 6798 if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F) 6799 return -EBUSY; 6800 6801 for ( ; !ret && n--; addr += 4) { 6802 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr); 6803 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F, 6804 0, 5, 2); 6805 if (!ret) 6806 *valp++ = t4_read_reg(adap, CIM_HOST_ACC_DATA_A); 6807 } 6808 return ret; 6809 } 6810 6811 /** 6812 * t4_cim_write - write a block into CIM internal address space 6813 * @adap: the adapter 6814 * @addr: the start address within the CIM address space 6815 * @n: number of words to write 6816 * @valp: set of values to write 6817 * 6818 * Writes a block of 4-byte words into the CIM intenal address space. 6819 */ 6820 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 6821 const unsigned int *valp) 6822 { 6823 int ret = 0; 6824 6825 if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F) 6826 return -EBUSY; 6827 6828 for ( ; !ret && n--; addr += 4) { 6829 t4_write_reg(adap, CIM_HOST_ACC_DATA_A, *valp++); 6830 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr | HOSTWRITE_F); 6831 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F, 6832 0, 5, 2); 6833 } 6834 return ret; 6835 } 6836 6837 static int t4_cim_write1(struct adapter *adap, unsigned int addr, 6838 unsigned int val) 6839 { 6840 return t4_cim_write(adap, addr, 1, &val); 6841 } 6842 6843 /** 6844 * t4_cim_read_la - read CIM LA capture buffer 6845 * @adap: the adapter 6846 * @la_buf: where to store the LA data 6847 * @wrptr: the HW write pointer within the capture buffer 6848 * 6849 * Reads the contents of the CIM LA buffer with the most recent entry at 6850 * the end of the returned data and with the entry at @wrptr first. 6851 * We try to leave the LA in the running state we find it in. 6852 */ 6853 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr) 6854 { 6855 int i, ret; 6856 unsigned int cfg, val, idx; 6857 6858 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &cfg); 6859 if (ret) 6860 return ret; 6861 6862 if (cfg & UPDBGLAEN_F) { /* LA is running, freeze it */ 6863 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A, 0); 6864 if (ret) 6865 return ret; 6866 } 6867 6868 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val); 6869 if (ret) 6870 goto restart; 6871 6872 idx = UPDBGLAWRPTR_G(val); 6873 if (wrptr) 6874 *wrptr = idx; 6875 6876 for (i = 0; i < adap->params.cim_la_size; i++) { 6877 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A, 6878 UPDBGLARDPTR_V(idx) | UPDBGLARDEN_F); 6879 if (ret) 6880 break; 6881 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val); 6882 if (ret) 6883 break; 6884 if (val & UPDBGLARDEN_F) { 6885 ret = -ETIMEDOUT; 6886 break; 6887 } 6888 ret = t4_cim_read(adap, UP_UP_DBG_LA_DATA_A, 1, &la_buf[i]); 6889 if (ret) 6890 break; 6891 idx = (idx + 1) & UPDBGLARDPTR_M; 6892 } 6893 restart: 6894 if (cfg & UPDBGLAEN_F) { 6895 int r = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A, 6896 cfg & ~UPDBGLARDEN_F); 6897 if (!ret) 6898 ret = r; 6899 } 6900 return ret; 6901 } 6902 6903 /** 6904 * t4_tp_read_la - read TP LA capture buffer 6905 * @adap: the adapter 6906 * @la_buf: where to store the LA data 6907 * @wrptr: the HW write pointer within the capture buffer 6908 * 6909 * Reads the contents of the TP LA buffer with the most recent entry at 6910 * the end of the returned data and with the entry at @wrptr first. 6911 * We leave the LA in the running state we find it in. 6912 */ 6913 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr) 6914 { 6915 bool last_incomplete; 6916 unsigned int i, cfg, val, idx; 6917 6918 cfg = t4_read_reg(adap, TP_DBG_LA_CONFIG_A) & 0xffff; 6919 if (cfg & DBGLAENABLE_F) /* freeze LA */ 6920 t4_write_reg(adap, TP_DBG_LA_CONFIG_A, 6921 adap->params.tp.la_mask | (cfg ^ DBGLAENABLE_F)); 6922 6923 val = t4_read_reg(adap, TP_DBG_LA_CONFIG_A); 6924 idx = DBGLAWPTR_G(val); 6925 last_incomplete = DBGLAMODE_G(val) >= 2 && (val & DBGLAWHLF_F) == 0; 6926 if (last_incomplete) 6927 idx = (idx + 1) & DBGLARPTR_M; 6928 if (wrptr) 6929 *wrptr = idx; 6930 6931 val &= 0xffff; 6932 val &= ~DBGLARPTR_V(DBGLARPTR_M); 6933 val |= adap->params.tp.la_mask; 6934 6935 for (i = 0; i < TPLA_SIZE; i++) { 6936 t4_write_reg(adap, TP_DBG_LA_CONFIG_A, DBGLARPTR_V(idx) | val); 6937 la_buf[i] = t4_read_reg64(adap, TP_DBG_LA_DATAL_A); 6938 idx = (idx + 1) & DBGLARPTR_M; 6939 } 6940 6941 /* Wipe out last entry if it isn't valid */ 6942 if (last_incomplete) 6943 la_buf[TPLA_SIZE - 1] = ~0ULL; 6944 6945 if (cfg & DBGLAENABLE_F) /* restore running state */ 6946 t4_write_reg(adap, TP_DBG_LA_CONFIG_A, 6947 cfg | adap->params.tp.la_mask); 6948 } 6949 6950 /* SGE Hung Ingress DMA Warning Threshold time and Warning Repeat Rate (in 6951 * seconds). If we find one of the SGE Ingress DMA State Machines in the same 6952 * state for more than the Warning Threshold then we'll issue a warning about 6953 * a potential hang. We'll repeat the warning as the SGE Ingress DMA Channel 6954 * appears to be hung every Warning Repeat second till the situation clears. 6955 * If the situation clears, we'll note that as well. 6956 */ 6957 #define SGE_IDMA_WARN_THRESH 1 6958 #define SGE_IDMA_WARN_REPEAT 300 6959 6960 /** 6961 * t4_idma_monitor_init - initialize SGE Ingress DMA Monitor 6962 * @adapter: the adapter 6963 * @idma: the adapter IDMA Monitor state 6964 * 6965 * Initialize the state of an SGE Ingress DMA Monitor. 6966 */ 6967 void t4_idma_monitor_init(struct adapter *adapter, 6968 struct sge_idma_monitor_state *idma) 6969 { 6970 /* Initialize the state variables for detecting an SGE Ingress DMA 6971 * hang. The SGE has internal counters which count up on each clock 6972 * tick whenever the SGE finds its Ingress DMA State Engines in the 6973 * same state they were on the previous clock tick. The clock used is 6974 * the Core Clock so we have a limit on the maximum "time" they can 6975 * record; typically a very small number of seconds. For instance, 6976 * with a 600MHz Core Clock, we can only count up to a bit more than 6977 * 7s. So we'll synthesize a larger counter in order to not run the 6978 * risk of having the "timers" overflow and give us the flexibility to 6979 * maintain a Hung SGE State Machine of our own which operates across 6980 * a longer time frame. 6981 */ 6982 idma->idma_1s_thresh = core_ticks_per_usec(adapter) * 1000000; /* 1s */ 6983 idma->idma_stalled[0] = 0; 6984 idma->idma_stalled[1] = 0; 6985 } 6986 6987 /** 6988 * t4_idma_monitor - monitor SGE Ingress DMA state 6989 * @adapter: the adapter 6990 * @idma: the adapter IDMA Monitor state 6991 * @hz: number of ticks/second 6992 * @ticks: number of ticks since the last IDMA Monitor call 6993 */ 6994 void t4_idma_monitor(struct adapter *adapter, 6995 struct sge_idma_monitor_state *idma, 6996 int hz, int ticks) 6997 { 6998 int i, idma_same_state_cnt[2]; 6999 7000 /* Read the SGE Debug Ingress DMA Same State Count registers. These 7001 * are counters inside the SGE which count up on each clock when the 7002 * SGE finds its Ingress DMA State Engines in the same states they 7003 * were in the previous clock. The counters will peg out at 7004 * 0xffffffff without wrapping around so once they pass the 1s 7005 * threshold they'll stay above that till the IDMA state changes. 7006 */ 7007 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 13); 7008 idma_same_state_cnt[0] = t4_read_reg(adapter, SGE_DEBUG_DATA_HIGH_A); 7009 idma_same_state_cnt[1] = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A); 7010 7011 for (i = 0; i < 2; i++) { 7012 u32 debug0, debug11; 7013 7014 /* If the Ingress DMA Same State Counter ("timer") is less 7015 * than 1s, then we can reset our synthesized Stall Timer and 7016 * continue. If we have previously emitted warnings about a 7017 * potential stalled Ingress Queue, issue a note indicating 7018 * that the Ingress Queue has resumed forward progress. 7019 */ 7020 if (idma_same_state_cnt[i] < idma->idma_1s_thresh) { 7021 if (idma->idma_stalled[i] >= SGE_IDMA_WARN_THRESH * hz) 7022 dev_warn(adapter->pdev_dev, "SGE idma%d, queue %u, " 7023 "resumed after %d seconds\n", 7024 i, idma->idma_qid[i], 7025 idma->idma_stalled[i] / hz); 7026 idma->idma_stalled[i] = 0; 7027 continue; 7028 } 7029 7030 /* Synthesize an SGE Ingress DMA Same State Timer in the Hz 7031 * domain. The first time we get here it'll be because we 7032 * passed the 1s Threshold; each additional time it'll be 7033 * because the RX Timer Callback is being fired on its regular 7034 * schedule. 7035 * 7036 * If the stall is below our Potential Hung Ingress Queue 7037 * Warning Threshold, continue. 7038 */ 7039 if (idma->idma_stalled[i] == 0) { 7040 idma->idma_stalled[i] = hz; 7041 idma->idma_warn[i] = 0; 7042 } else { 7043 idma->idma_stalled[i] += ticks; 7044 idma->idma_warn[i] -= ticks; 7045 } 7046 7047 if (idma->idma_stalled[i] < SGE_IDMA_WARN_THRESH * hz) 7048 continue; 7049 7050 /* We'll issue a warning every SGE_IDMA_WARN_REPEAT seconds. 7051 */ 7052 if (idma->idma_warn[i] > 0) 7053 continue; 7054 idma->idma_warn[i] = SGE_IDMA_WARN_REPEAT * hz; 7055 7056 /* Read and save the SGE IDMA State and Queue ID information. 7057 * We do this every time in case it changes across time ... 7058 * can't be too careful ... 7059 */ 7060 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 0); 7061 debug0 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A); 7062 idma->idma_state[i] = (debug0 >> (i * 9)) & 0x3f; 7063 7064 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 11); 7065 debug11 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A); 7066 idma->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff; 7067 7068 dev_warn(adapter->pdev_dev, "SGE idma%u, queue %u, potentially stuck in " 7069 "state %u for %d seconds (debug0=%#x, debug11=%#x)\n", 7070 i, idma->idma_qid[i], idma->idma_state[i], 7071 idma->idma_stalled[i] / hz, 7072 debug0, debug11); 7073 t4_sge_decode_idma_state(adapter, idma->idma_state[i]); 7074 } 7075 } 7076