1 /* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #ifndef __CXGB4_H__ 36 #define __CXGB4_H__ 37 38 #include "t4_hw.h" 39 40 #include <linux/bitops.h> 41 #include <linux/cache.h> 42 #include <linux/interrupt.h> 43 #include <linux/list.h> 44 #include <linux/netdevice.h> 45 #include <linux/pci.h> 46 #include <linux/spinlock.h> 47 #include <linux/timer.h> 48 #include <linux/vmalloc.h> 49 #include <linux/rhashtable.h> 50 #include <linux/etherdevice.h> 51 #include <linux/net_tstamp.h> 52 #include <linux/ptp_clock_kernel.h> 53 #include <linux/ptp_classify.h> 54 #include <linux/crash_dump.h> 55 #include <asm/io.h> 56 #include "t4_chip_type.h" 57 #include "cxgb4_uld.h" 58 59 #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__) 60 extern struct list_head adapter_list; 61 extern struct mutex uld_mutex; 62 63 /* Suspend an Ethernet Tx queue with fewer available descriptors than this. 64 * This is the same as calc_tx_descs() for a TSO packet with 65 * nr_frags == MAX_SKB_FRAGS. 66 */ 67 #define ETHTXQ_STOP_THRES \ 68 (1 + DIV_ROUND_UP((3 * MAX_SKB_FRAGS) / 2 + (MAX_SKB_FRAGS & 1), 8)) 69 70 enum { 71 MAX_NPORTS = 4, /* max # of ports */ 72 SERNUM_LEN = 24, /* Serial # length */ 73 EC_LEN = 16, /* E/C length */ 74 ID_LEN = 16, /* ID length */ 75 PN_LEN = 16, /* Part Number length */ 76 MACADDR_LEN = 12, /* MAC Address length */ 77 }; 78 79 enum { 80 T4_REGMAP_SIZE = (160 * 1024), 81 T5_REGMAP_SIZE = (332 * 1024), 82 }; 83 84 enum { 85 MEM_EDC0, 86 MEM_EDC1, 87 MEM_MC, 88 MEM_MC0 = MEM_MC, 89 MEM_MC1, 90 MEM_HMA, 91 }; 92 93 enum { 94 MEMWIN0_APERTURE = 2048, 95 MEMWIN0_BASE = 0x1b800, 96 MEMWIN1_APERTURE = 32768, 97 MEMWIN1_BASE = 0x28000, 98 MEMWIN1_BASE_T5 = 0x52000, 99 MEMWIN2_APERTURE = 65536, 100 MEMWIN2_BASE = 0x30000, 101 MEMWIN2_APERTURE_T5 = 131072, 102 MEMWIN2_BASE_T5 = 0x60000, 103 }; 104 105 enum dev_master { 106 MASTER_CANT, 107 MASTER_MAY, 108 MASTER_MUST 109 }; 110 111 enum dev_state { 112 DEV_STATE_UNINIT, 113 DEV_STATE_INIT, 114 DEV_STATE_ERR 115 }; 116 117 enum cc_pause { 118 PAUSE_RX = 1 << 0, 119 PAUSE_TX = 1 << 1, 120 PAUSE_AUTONEG = 1 << 2 121 }; 122 123 enum cc_fec { 124 FEC_AUTO = 1 << 0, /* IEEE 802.3 "automatic" */ 125 FEC_RS = 1 << 1, /* Reed-Solomon */ 126 FEC_BASER_RS = 1 << 2 /* BaseR/Reed-Solomon */ 127 }; 128 129 struct port_stats { 130 u64 tx_octets; /* total # of octets in good frames */ 131 u64 tx_frames; /* all good frames */ 132 u64 tx_bcast_frames; /* all broadcast frames */ 133 u64 tx_mcast_frames; /* all multicast frames */ 134 u64 tx_ucast_frames; /* all unicast frames */ 135 u64 tx_error_frames; /* all error frames */ 136 137 u64 tx_frames_64; /* # of Tx frames in a particular range */ 138 u64 tx_frames_65_127; 139 u64 tx_frames_128_255; 140 u64 tx_frames_256_511; 141 u64 tx_frames_512_1023; 142 u64 tx_frames_1024_1518; 143 u64 tx_frames_1519_max; 144 145 u64 tx_drop; /* # of dropped Tx frames */ 146 u64 tx_pause; /* # of transmitted pause frames */ 147 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ 148 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ 149 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ 150 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ 151 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ 152 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ 153 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ 154 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ 155 156 u64 rx_octets; /* total # of octets in good frames */ 157 u64 rx_frames; /* all good frames */ 158 u64 rx_bcast_frames; /* all broadcast frames */ 159 u64 rx_mcast_frames; /* all multicast frames */ 160 u64 rx_ucast_frames; /* all unicast frames */ 161 u64 rx_too_long; /* # of frames exceeding MTU */ 162 u64 rx_jabber; /* # of jabber frames */ 163 u64 rx_fcs_err; /* # of received frames with bad FCS */ 164 u64 rx_len_err; /* # of received frames with length error */ 165 u64 rx_symbol_err; /* symbol errors */ 166 u64 rx_runt; /* # of short frames */ 167 168 u64 rx_frames_64; /* # of Rx frames in a particular range */ 169 u64 rx_frames_65_127; 170 u64 rx_frames_128_255; 171 u64 rx_frames_256_511; 172 u64 rx_frames_512_1023; 173 u64 rx_frames_1024_1518; 174 u64 rx_frames_1519_max; 175 176 u64 rx_pause; /* # of received pause frames */ 177 u64 rx_ppp0; /* # of received PPP prio 0 frames */ 178 u64 rx_ppp1; /* # of received PPP prio 1 frames */ 179 u64 rx_ppp2; /* # of received PPP prio 2 frames */ 180 u64 rx_ppp3; /* # of received PPP prio 3 frames */ 181 u64 rx_ppp4; /* # of received PPP prio 4 frames */ 182 u64 rx_ppp5; /* # of received PPP prio 5 frames */ 183 u64 rx_ppp6; /* # of received PPP prio 6 frames */ 184 u64 rx_ppp7; /* # of received PPP prio 7 frames */ 185 186 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ 187 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ 188 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ 189 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ 190 u64 rx_trunc0; /* buffer-group 0 truncated packets */ 191 u64 rx_trunc1; /* buffer-group 1 truncated packets */ 192 u64 rx_trunc2; /* buffer-group 2 truncated packets */ 193 u64 rx_trunc3; /* buffer-group 3 truncated packets */ 194 }; 195 196 struct lb_port_stats { 197 u64 octets; 198 u64 frames; 199 u64 bcast_frames; 200 u64 mcast_frames; 201 u64 ucast_frames; 202 u64 error_frames; 203 204 u64 frames_64; 205 u64 frames_65_127; 206 u64 frames_128_255; 207 u64 frames_256_511; 208 u64 frames_512_1023; 209 u64 frames_1024_1518; 210 u64 frames_1519_max; 211 212 u64 drop; 213 214 u64 ovflow0; 215 u64 ovflow1; 216 u64 ovflow2; 217 u64 ovflow3; 218 u64 trunc0; 219 u64 trunc1; 220 u64 trunc2; 221 u64 trunc3; 222 }; 223 224 struct tp_tcp_stats { 225 u32 tcp_out_rsts; 226 u64 tcp_in_segs; 227 u64 tcp_out_segs; 228 u64 tcp_retrans_segs; 229 }; 230 231 struct tp_usm_stats { 232 u32 frames; 233 u32 drops; 234 u64 octets; 235 }; 236 237 struct tp_fcoe_stats { 238 u32 frames_ddp; 239 u32 frames_drop; 240 u64 octets_ddp; 241 }; 242 243 struct tp_err_stats { 244 u32 mac_in_errs[4]; 245 u32 hdr_in_errs[4]; 246 u32 tcp_in_errs[4]; 247 u32 tnl_cong_drops[4]; 248 u32 ofld_chan_drops[4]; 249 u32 tnl_tx_drops[4]; 250 u32 ofld_vlan_drops[4]; 251 u32 tcp6_in_errs[4]; 252 u32 ofld_no_neigh; 253 u32 ofld_cong_defer; 254 }; 255 256 struct tp_cpl_stats { 257 u32 req[4]; 258 u32 rsp[4]; 259 }; 260 261 struct tp_rdma_stats { 262 u32 rqe_dfr_pkt; 263 u32 rqe_dfr_mod; 264 }; 265 266 struct sge_params { 267 u32 hps; /* host page size for our PF/VF */ 268 u32 eq_qpp; /* egress queues/page for our PF/VF */ 269 u32 iq_qpp; /* egress queues/page for our PF/VF */ 270 }; 271 272 struct tp_params { 273 unsigned int tre; /* log2 of core clocks per TP tick */ 274 unsigned int la_mask; /* what events are recorded by TP LA */ 275 unsigned short tx_modq_map; /* TX modulation scheduler queue to */ 276 /* channel map */ 277 278 uint32_t dack_re; /* DACK timer resolution */ 279 unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */ 280 281 u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */ 282 u32 ingress_config; /* cached TP_INGRESS_CONFIG */ 283 284 /* cached TP_OUT_CONFIG compressed error vector 285 * and passing outer header info for encapsulated packets. 286 */ 287 int rx_pkt_encap; 288 289 /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a 290 * subset of the set of fields which may be present in the Compressed 291 * Filter Tuple portion of filters and TCP TCB connections. The 292 * fields which are present are controlled by the TP_VLAN_PRI_MAP. 293 * Since a variable number of fields may or may not be present, their 294 * shifted field positions within the Compressed Filter Tuple may 295 * vary, or not even be present if the field isn't selected in 296 * TP_VLAN_PRI_MAP. Since some of these fields are needed in various 297 * places we store their offsets here, or a -1 if the field isn't 298 * present. 299 */ 300 int fcoe_shift; 301 int port_shift; 302 int vnic_shift; 303 int vlan_shift; 304 int tos_shift; 305 int protocol_shift; 306 int ethertype_shift; 307 int macmatch_shift; 308 int matchtype_shift; 309 int frag_shift; 310 311 u64 hash_filter_mask; 312 }; 313 314 struct vpd_params { 315 unsigned int cclk; 316 u8 ec[EC_LEN + 1]; 317 u8 sn[SERNUM_LEN + 1]; 318 u8 id[ID_LEN + 1]; 319 u8 pn[PN_LEN + 1]; 320 u8 na[MACADDR_LEN + 1]; 321 }; 322 323 /* Maximum resources provisioned for a PCI PF. 324 */ 325 struct pf_resources { 326 unsigned int nvi; /* N virtual interfaces */ 327 unsigned int neq; /* N egress Qs */ 328 unsigned int nethctrl; /* N egress ETH or CTRL Qs */ 329 unsigned int niqflint; /* N ingress Qs/w free list(s) & intr */ 330 unsigned int niq; /* N ingress Qs */ 331 unsigned int tc; /* PCI-E traffic class */ 332 unsigned int pmask; /* port access rights mask */ 333 unsigned int nexactf; /* N exact MPS filters */ 334 unsigned int r_caps; /* read capabilities */ 335 unsigned int wx_caps; /* write/execute capabilities */ 336 }; 337 338 struct pci_params { 339 unsigned int vpd_cap_addr; 340 unsigned char speed; 341 unsigned char width; 342 }; 343 344 struct devlog_params { 345 u32 memtype; /* which memory (EDC0, EDC1, MC) */ 346 u32 start; /* start of log in firmware memory */ 347 u32 size; /* size of log */ 348 }; 349 350 /* Stores chip specific parameters */ 351 struct arch_specific_params { 352 u8 nchan; 353 u8 pm_stats_cnt; 354 u8 cng_ch_bits_log; /* congestion channel map bits width */ 355 u16 mps_rplc_size; 356 u16 vfcount; 357 u32 sge_fl_db; 358 u16 mps_tcam_size; 359 }; 360 361 struct adapter_params { 362 struct sge_params sge; 363 struct tp_params tp; 364 struct vpd_params vpd; 365 struct pf_resources pfres; 366 struct pci_params pci; 367 struct devlog_params devlog; 368 enum pcie_memwin drv_memwin; 369 370 unsigned int cim_la_size; 371 372 unsigned int sf_size; /* serial flash size in bytes */ 373 unsigned int sf_nsec; /* # of flash sectors */ 374 375 unsigned int fw_vers; /* firmware version */ 376 unsigned int bs_vers; /* bootstrap version */ 377 unsigned int tp_vers; /* TP microcode version */ 378 unsigned int er_vers; /* expansion ROM version */ 379 unsigned int scfg_vers; /* Serial Configuration version */ 380 unsigned int vpd_vers; /* VPD Version */ 381 u8 api_vers[7]; 382 383 unsigned short mtus[NMTUS]; 384 unsigned short a_wnd[NCCTRL_WIN]; 385 unsigned short b_wnd[NCCTRL_WIN]; 386 387 unsigned char nports; /* # of ethernet ports */ 388 unsigned char portvec; 389 enum chip_type chip; /* chip code */ 390 struct arch_specific_params arch; /* chip specific params */ 391 unsigned char offload; 392 unsigned char crypto; /* HW capability for crypto */ 393 394 unsigned char bypass; 395 unsigned char hash_filter; 396 397 unsigned int ofldq_wr_cred; 398 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ 399 400 unsigned int nsched_cls; /* number of traffic classes */ 401 unsigned int max_ordird_qp; /* Max read depth per RDMA QP */ 402 unsigned int max_ird_adapter; /* Max read depth per adapter */ 403 bool fr_nsmr_tpte_wr_support; /* FW support for FR_NSMR_TPTE_WR */ 404 u8 fw_caps_support; /* 32-bit Port Capabilities */ 405 bool filter2_wr_support; /* FW support for FILTER2_WR */ 406 407 /* MPS Buffer Group Map[per Port]. Bit i is set if buffer group i is 408 * used by the Port 409 */ 410 u8 mps_bg_map[MAX_NPORTS]; /* MPS Buffer Group Map */ 411 bool write_w_imm_support; /* FW supports WRITE_WITH_IMMEDIATE */ 412 bool write_cmpl_support; /* FW supports WRITE_CMPL */ 413 }; 414 415 /* State needed to monitor the forward progress of SGE Ingress DMA activities 416 * and possible hangs. 417 */ 418 struct sge_idma_monitor_state { 419 unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */ 420 unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */ 421 unsigned int idma_state[2]; /* IDMA Hang detect state */ 422 unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */ 423 unsigned int idma_warn[2]; /* time to warning in HZ */ 424 }; 425 426 /* Firmware Mailbox Command/Reply log. All values are in Host-Endian format. 427 * The access and execute times are signed in order to accommodate negative 428 * error returns. 429 */ 430 struct mbox_cmd { 431 u64 cmd[MBOX_LEN / 8]; /* a Firmware Mailbox Command/Reply */ 432 u64 timestamp; /* OS-dependent timestamp */ 433 u32 seqno; /* sequence number */ 434 s16 access; /* time (ms) to access mailbox */ 435 s16 execute; /* time (ms) to execute */ 436 }; 437 438 struct mbox_cmd_log { 439 unsigned int size; /* number of entries in the log */ 440 unsigned int cursor; /* next position in the log to write */ 441 u32 seqno; /* next sequence number */ 442 /* variable length mailbox command log starts here */ 443 }; 444 445 /* Given a pointer to a Firmware Mailbox Command Log and a log entry index, 446 * return a pointer to the specified entry. 447 */ 448 static inline struct mbox_cmd *mbox_cmd_log_entry(struct mbox_cmd_log *log, 449 unsigned int entry_idx) 450 { 451 return &((struct mbox_cmd *)&(log)[1])[entry_idx]; 452 } 453 454 #include "t4fw_api.h" 455 456 #define FW_VERSION(chip) ( \ 457 FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \ 458 FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \ 459 FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \ 460 FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD)) 461 #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf) 462 463 struct fw_info { 464 u8 chip; 465 char *fs_name; 466 char *fw_mod_name; 467 struct fw_hdr fw_hdr; 468 }; 469 470 struct trace_params { 471 u32 data[TRACE_LEN / 4]; 472 u32 mask[TRACE_LEN / 4]; 473 unsigned short snap_len; 474 unsigned short min_len; 475 unsigned char skip_ofst; 476 unsigned char skip_len; 477 unsigned char invert; 478 unsigned char port; 479 }; 480 481 /* Firmware Port Capabilities types. */ 482 483 typedef u16 fw_port_cap16_t; /* 16-bit Port Capabilities integral value */ 484 typedef u32 fw_port_cap32_t; /* 32-bit Port Capabilities integral value */ 485 486 enum fw_caps { 487 FW_CAPS_UNKNOWN = 0, /* 0'ed out initial state */ 488 FW_CAPS16 = 1, /* old Firmware: 16-bit Port Capabilities */ 489 FW_CAPS32 = 2, /* new Firmware: 32-bit Port Capabilities */ 490 }; 491 492 struct link_config { 493 fw_port_cap32_t pcaps; /* link capabilities */ 494 fw_port_cap32_t def_acaps; /* default advertised capabilities */ 495 fw_port_cap32_t acaps; /* advertised capabilities */ 496 fw_port_cap32_t lpacaps; /* peer advertised capabilities */ 497 498 fw_port_cap32_t speed_caps; /* speed(s) user has requested */ 499 unsigned int speed; /* actual link speed (Mb/s) */ 500 501 enum cc_pause requested_fc; /* flow control user has requested */ 502 enum cc_pause fc; /* actual link flow control */ 503 504 enum cc_fec requested_fec; /* Forward Error Correction: */ 505 enum cc_fec fec; /* requested and actual in use */ 506 507 unsigned char autoneg; /* autonegotiating? */ 508 509 unsigned char link_ok; /* link up? */ 510 unsigned char link_down_rc; /* link down reason */ 511 512 bool new_module; /* ->OS Transceiver Module inserted */ 513 bool redo_l1cfg; /* ->CC redo current "sticky" L1 CFG */ 514 }; 515 516 #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16) 517 518 enum { 519 MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */ 520 MAX_OFLD_QSETS = 16, /* # of offload Tx, iscsi Rx queue sets */ 521 MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */ 522 }; 523 524 enum { 525 MAX_TXQ_ENTRIES = 16384, 526 MAX_CTRL_TXQ_ENTRIES = 1024, 527 MAX_RSPQ_ENTRIES = 16384, 528 MAX_RX_BUFFERS = 16384, 529 MIN_TXQ_ENTRIES = 32, 530 MIN_CTRL_TXQ_ENTRIES = 32, 531 MIN_RSPQ_ENTRIES = 128, 532 MIN_FL_ENTRIES = 16 533 }; 534 535 enum { 536 MAX_TXQ_DESC_SIZE = 64, 537 MAX_RXQ_DESC_SIZE = 128, 538 MAX_FL_DESC_SIZE = 8, 539 MAX_CTRL_TXQ_DESC_SIZE = 64, 540 }; 541 542 enum { 543 INGQ_EXTRAS = 2, /* firmware event queue and */ 544 /* forwarded interrupts */ 545 MAX_INGQ = MAX_ETH_QSETS + INGQ_EXTRAS, 546 }; 547 548 enum { 549 PRIV_FLAG_PORT_TX_VM_BIT, 550 }; 551 552 #define PRIV_FLAG_PORT_TX_VM BIT(PRIV_FLAG_PORT_TX_VM_BIT) 553 554 #define PRIV_FLAGS_ADAP 0 555 #define PRIV_FLAGS_PORT PRIV_FLAG_PORT_TX_VM 556 557 struct adapter; 558 struct sge_rspq; 559 560 #include "cxgb4_dcb.h" 561 562 #ifdef CONFIG_CHELSIO_T4_FCOE 563 #include "cxgb4_fcoe.h" 564 #endif /* CONFIG_CHELSIO_T4_FCOE */ 565 566 struct port_info { 567 struct adapter *adapter; 568 u16 viid; 569 s16 xact_addr_filt; /* index of exact MAC address filter */ 570 u16 rss_size; /* size of VI's RSS table slice */ 571 s8 mdio_addr; 572 enum fw_port_type port_type; 573 u8 mod_type; 574 u8 port_id; 575 u8 tx_chan; 576 u8 lport; /* associated offload logical port */ 577 u8 nqsets; /* # of qsets */ 578 u8 first_qset; /* index of first qset */ 579 u8 rss_mode; 580 struct link_config link_cfg; 581 u16 *rss; 582 struct port_stats stats_base; 583 #ifdef CONFIG_CHELSIO_T4_DCB 584 struct port_dcb_info dcb; /* Data Center Bridging support */ 585 #endif 586 #ifdef CONFIG_CHELSIO_T4_FCOE 587 struct cxgb_fcoe fcoe; 588 #endif /* CONFIG_CHELSIO_T4_FCOE */ 589 bool rxtstamp; /* Enable TS */ 590 struct hwtstamp_config tstamp_config; 591 bool ptp_enable; 592 struct sched_table *sched_tbl; 593 u32 eth_flags; 594 }; 595 596 struct dentry; 597 struct work_struct; 598 599 enum { /* adapter flags */ 600 FULL_INIT_DONE = (1 << 0), 601 DEV_ENABLED = (1 << 1), 602 USING_MSI = (1 << 2), 603 USING_MSIX = (1 << 3), 604 FW_OK = (1 << 4), 605 RSS_TNLALLLOOKUP = (1 << 5), 606 USING_SOFT_PARAMS = (1 << 6), 607 MASTER_PF = (1 << 7), 608 FW_OFLD_CONN = (1 << 9), 609 ROOT_NO_RELAXED_ORDERING = (1 << 10), 610 SHUTTING_DOWN = (1 << 11), 611 }; 612 613 enum { 614 ULP_CRYPTO_LOOKASIDE = 1 << 0, 615 ULP_CRYPTO_IPSEC_INLINE = 1 << 1, 616 }; 617 618 struct rx_sw_desc; 619 620 struct sge_fl { /* SGE free-buffer queue state */ 621 unsigned int avail; /* # of available Rx buffers */ 622 unsigned int pend_cred; /* new buffers since last FL DB ring */ 623 unsigned int cidx; /* consumer index */ 624 unsigned int pidx; /* producer index */ 625 unsigned long alloc_failed; /* # of times buffer allocation failed */ 626 unsigned long large_alloc_failed; 627 unsigned long mapping_err; /* # of RX Buffer DMA Mapping failures */ 628 unsigned long low; /* # of times momentarily starving */ 629 unsigned long starving; 630 /* RO fields */ 631 unsigned int cntxt_id; /* SGE context id for the free list */ 632 unsigned int size; /* capacity of free list */ 633 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */ 634 __be64 *desc; /* address of HW Rx descriptor ring */ 635 dma_addr_t addr; /* bus address of HW ring start */ 636 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 637 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 638 }; 639 640 /* A packet gather list */ 641 struct pkt_gl { 642 u64 sgetstamp; /* SGE Time Stamp for Ingress Packet */ 643 struct page_frag frags[MAX_SKB_FRAGS]; 644 void *va; /* virtual address of first byte */ 645 unsigned int nfrags; /* # of fragments */ 646 unsigned int tot_len; /* total length of fragments */ 647 }; 648 649 typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp, 650 const struct pkt_gl *gl); 651 typedef void (*rspq_flush_handler_t)(struct sge_rspq *q); 652 /* LRO related declarations for ULD */ 653 struct t4_lro_mgr { 654 #define MAX_LRO_SESSIONS 64 655 u8 lro_session_cnt; /* # of sessions to aggregate */ 656 unsigned long lro_pkts; /* # of LRO super packets */ 657 unsigned long lro_merged; /* # of wire packets merged by LRO */ 658 struct sk_buff_head lroq; /* list of aggregated sessions */ 659 }; 660 661 struct sge_rspq { /* state for an SGE response queue */ 662 struct napi_struct napi; 663 const __be64 *cur_desc; /* current descriptor in queue */ 664 unsigned int cidx; /* consumer index */ 665 u8 gen; /* current generation bit */ 666 u8 intr_params; /* interrupt holdoff parameters */ 667 u8 next_intr_params; /* holdoff params for next interrupt */ 668 u8 adaptive_rx; 669 u8 pktcnt_idx; /* interrupt packet threshold */ 670 u8 uld; /* ULD handling this queue */ 671 u8 idx; /* queue index within its group */ 672 int offset; /* offset into current Rx buffer */ 673 u16 cntxt_id; /* SGE context id for the response q */ 674 u16 abs_id; /* absolute SGE id for the response q */ 675 __be64 *desc; /* address of HW response ring */ 676 dma_addr_t phys_addr; /* physical address of the ring */ 677 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 678 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 679 unsigned int iqe_len; /* entry size */ 680 unsigned int size; /* capacity of response queue */ 681 struct adapter *adap; 682 struct net_device *netdev; /* associated net device */ 683 rspq_handler_t handler; 684 rspq_flush_handler_t flush_handler; 685 struct t4_lro_mgr lro_mgr; 686 }; 687 688 struct sge_eth_stats { /* Ethernet queue statistics */ 689 unsigned long pkts; /* # of ethernet packets */ 690 unsigned long lro_pkts; /* # of LRO super packets */ 691 unsigned long lro_merged; /* # of wire packets merged by LRO */ 692 unsigned long rx_cso; /* # of Rx checksum offloads */ 693 unsigned long vlan_ex; /* # of Rx VLAN extractions */ 694 unsigned long rx_drops; /* # of packets dropped due to no mem */ 695 }; 696 697 struct sge_eth_rxq { /* SW Ethernet Rx queue */ 698 struct sge_rspq rspq; 699 struct sge_fl fl; 700 struct sge_eth_stats stats; 701 } ____cacheline_aligned_in_smp; 702 703 struct sge_ofld_stats { /* offload queue statistics */ 704 unsigned long pkts; /* # of packets */ 705 unsigned long imm; /* # of immediate-data packets */ 706 unsigned long an; /* # of asynchronous notifications */ 707 unsigned long nomem; /* # of responses deferred due to no mem */ 708 }; 709 710 struct sge_ofld_rxq { /* SW offload Rx queue */ 711 struct sge_rspq rspq; 712 struct sge_fl fl; 713 struct sge_ofld_stats stats; 714 } ____cacheline_aligned_in_smp; 715 716 struct tx_desc { 717 __be64 flit[8]; 718 }; 719 720 struct tx_sw_desc; 721 722 struct sge_txq { 723 unsigned int in_use; /* # of in-use Tx descriptors */ 724 unsigned int q_type; /* Q type Eth/Ctrl/Ofld */ 725 unsigned int size; /* # of descriptors */ 726 unsigned int cidx; /* SW consumer index */ 727 unsigned int pidx; /* producer index */ 728 unsigned long stops; /* # of times q has been stopped */ 729 unsigned long restarts; /* # of queue restarts */ 730 unsigned int cntxt_id; /* SGE context id for the Tx q */ 731 struct tx_desc *desc; /* address of HW Tx descriptor ring */ 732 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */ 733 struct sge_qstat *stat; /* queue status entry */ 734 dma_addr_t phys_addr; /* physical address of the ring */ 735 spinlock_t db_lock; 736 int db_disabled; 737 unsigned short db_pidx; 738 unsigned short db_pidx_inc; 739 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 740 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 741 }; 742 743 struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */ 744 struct sge_txq q; 745 struct netdev_queue *txq; /* associated netdev TX queue */ 746 #ifdef CONFIG_CHELSIO_T4_DCB 747 u8 dcb_prio; /* DCB Priority bound to queue */ 748 #endif 749 unsigned long tso; /* # of TSO requests */ 750 unsigned long tx_cso; /* # of Tx checksum offloads */ 751 unsigned long vlan_ins; /* # of Tx VLAN insertions */ 752 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 753 } ____cacheline_aligned_in_smp; 754 755 struct sge_uld_txq { /* state for an SGE offload Tx queue */ 756 struct sge_txq q; 757 struct adapter *adap; 758 struct sk_buff_head sendq; /* list of backpressured packets */ 759 struct tasklet_struct qresume_tsk; /* restarts the queue */ 760 bool service_ofldq_running; /* service_ofldq() is processing sendq */ 761 u8 full; /* the Tx ring is full */ 762 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 763 } ____cacheline_aligned_in_smp; 764 765 struct sge_ctrl_txq { /* state for an SGE control Tx queue */ 766 struct sge_txq q; 767 struct adapter *adap; 768 struct sk_buff_head sendq; /* list of backpressured packets */ 769 struct tasklet_struct qresume_tsk; /* restarts the queue */ 770 u8 full; /* the Tx ring is full */ 771 } ____cacheline_aligned_in_smp; 772 773 struct sge_uld_rxq_info { 774 char name[IFNAMSIZ]; /* name of ULD driver */ 775 struct sge_ofld_rxq *uldrxq; /* Rxq's for ULD */ 776 u16 *msix_tbl; /* msix_tbl for uld */ 777 u16 *rspq_id; /* response queue id's of rxq */ 778 u16 nrxq; /* # of ingress uld queues */ 779 u16 nciq; /* # of completion queues */ 780 u8 uld; /* uld type */ 781 }; 782 783 struct sge_uld_txq_info { 784 struct sge_uld_txq *uldtxq; /* Txq's for ULD */ 785 atomic_t users; /* num users */ 786 u16 ntxq; /* # of egress uld queues */ 787 }; 788 789 struct sge { 790 struct sge_eth_txq ethtxq[MAX_ETH_QSETS]; 791 struct sge_eth_txq ptptxq; 792 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES]; 793 794 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS]; 795 struct sge_rspq fw_evtq ____cacheline_aligned_in_smp; 796 struct sge_uld_rxq_info **uld_rxq_info; 797 struct sge_uld_txq_info **uld_txq_info; 798 799 struct sge_rspq intrq ____cacheline_aligned_in_smp; 800 spinlock_t intrq_lock; 801 802 u16 max_ethqsets; /* # of available Ethernet queue sets */ 803 u16 ethqsets; /* # of active Ethernet queue sets */ 804 u16 ethtxq_rover; /* Tx queue to clean up next */ 805 u16 ofldqsets; /* # of active ofld queue sets */ 806 u16 nqs_per_uld; /* # of Rx queues per ULD */ 807 u16 timer_val[SGE_NTIMERS]; 808 u8 counter_val[SGE_NCOUNTERS]; 809 u32 fl_pg_order; /* large page allocation size */ 810 u32 stat_len; /* length of status page at ring end */ 811 u32 pktshift; /* padding between CPL & packet data */ 812 u32 fl_align; /* response queue message alignment */ 813 u32 fl_starve_thres; /* Free List starvation threshold */ 814 815 struct sge_idma_monitor_state idma_monitor; 816 unsigned int egr_start; 817 unsigned int egr_sz; 818 unsigned int ingr_start; 819 unsigned int ingr_sz; 820 void **egr_map; /* qid->queue egress queue map */ 821 struct sge_rspq **ingr_map; /* qid->queue ingress queue map */ 822 unsigned long *starving_fl; 823 unsigned long *txq_maperr; 824 unsigned long *blocked_fl; 825 struct timer_list rx_timer; /* refills starving FLs */ 826 struct timer_list tx_timer; /* checks Tx queues */ 827 }; 828 829 #define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++) 830 #define for_each_ofldtxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++) 831 832 struct l2t_data; 833 834 #ifdef CONFIG_PCI_IOV 835 836 /* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial 837 * Configuration initialization for T5 only has SR-IOV functionality enabled 838 * on PF0-3 in order to simplify everything. 839 */ 840 #define NUM_OF_PF_WITH_SRIOV 4 841 842 #endif 843 844 struct doorbell_stats { 845 u32 db_drop; 846 u32 db_empty; 847 u32 db_full; 848 }; 849 850 struct hash_mac_addr { 851 struct list_head list; 852 u8 addr[ETH_ALEN]; 853 }; 854 855 struct uld_msix_bmap { 856 unsigned long *msix_bmap; 857 unsigned int mapsize; 858 spinlock_t lock; /* lock for acquiring bitmap */ 859 }; 860 861 struct uld_msix_info { 862 unsigned short vec; 863 char desc[IFNAMSIZ + 10]; 864 unsigned int idx; 865 }; 866 867 struct vf_info { 868 unsigned char vf_mac_addr[ETH_ALEN]; 869 unsigned int tx_rate; 870 bool pf_set_mac; 871 u16 vlan; 872 }; 873 874 enum { 875 HMA_DMA_MAPPED_FLAG = 1 876 }; 877 878 struct hma_data { 879 unsigned char flags; 880 struct sg_table *sgt; 881 dma_addr_t *phy_addr; /* physical address of the page */ 882 }; 883 884 struct mbox_list { 885 struct list_head list; 886 }; 887 888 struct mps_encap_entry { 889 atomic_t refcnt; 890 }; 891 892 struct adapter { 893 void __iomem *regs; 894 void __iomem *bar2; 895 u32 t4_bar0; 896 struct pci_dev *pdev; 897 struct device *pdev_dev; 898 const char *name; 899 unsigned int mbox; 900 unsigned int pf; 901 unsigned int flags; 902 unsigned int adap_idx; 903 enum chip_type chip; 904 u32 eth_flags; 905 906 int msg_enable; 907 __be16 vxlan_port; 908 u8 vxlan_port_cnt; 909 __be16 geneve_port; 910 u8 geneve_port_cnt; 911 912 struct adapter_params params; 913 struct cxgb4_virt_res vres; 914 unsigned int swintr; 915 916 struct { 917 unsigned short vec; 918 char desc[IFNAMSIZ + 10]; 919 } msix_info[MAX_INGQ + 1]; 920 struct uld_msix_info *msix_info_ulds; /* msix info for uld's */ 921 struct uld_msix_bmap msix_bmap_ulds; /* msix bitmap for all uld */ 922 int msi_idx; 923 924 struct doorbell_stats db_stats; 925 struct sge sge; 926 927 struct net_device *port[MAX_NPORTS]; 928 u8 chan_map[NCHAN]; /* channel -> port map */ 929 930 struct vf_info *vfinfo; 931 u8 num_vfs; 932 933 u32 filter_mode; 934 unsigned int l2t_start; 935 unsigned int l2t_end; 936 struct l2t_data *l2t; 937 unsigned int clipt_start; 938 unsigned int clipt_end; 939 struct clip_tbl *clipt; 940 unsigned int rawf_start; 941 unsigned int rawf_cnt; 942 struct smt_data *smt; 943 struct mps_encap_entry *mps_encap; 944 struct cxgb4_uld_info *uld; 945 void *uld_handle[CXGB4_ULD_MAX]; 946 unsigned int num_uld; 947 unsigned int num_ofld_uld; 948 struct list_head list_node; 949 struct list_head rcu_node; 950 struct list_head mac_hlist; /* list of MAC addresses in MPS Hash */ 951 952 void *iscsi_ppm; 953 954 struct tid_info tids; 955 void **tid_release_head; 956 spinlock_t tid_release_lock; 957 struct workqueue_struct *workq; 958 struct work_struct tid_release_task; 959 struct work_struct db_full_task; 960 struct work_struct db_drop_task; 961 struct work_struct fatal_err_notify_task; 962 bool tid_release_task_busy; 963 964 /* lock for mailbox cmd list */ 965 spinlock_t mbox_lock; 966 struct mbox_list mlist; 967 968 /* support for mailbox command/reply logging */ 969 #define T4_OS_LOG_MBOX_CMDS 256 970 struct mbox_cmd_log *mbox_log; 971 972 struct mutex uld_mutex; 973 974 struct dentry *debugfs_root; 975 bool use_bd; /* Use SGE Back Door intfc for reading SGE Contexts */ 976 bool trace_rss; /* 1 implies that different RSS flit per filter is 977 * used per filter else if 0 default RSS flit is 978 * used for all 4 filters. 979 */ 980 981 struct ptp_clock *ptp_clock; 982 struct ptp_clock_info ptp_clock_info; 983 struct sk_buff *ptp_tx_skb; 984 /* ptp lock */ 985 spinlock_t ptp_lock; 986 spinlock_t stats_lock; 987 spinlock_t win0_lock ____cacheline_aligned_in_smp; 988 989 /* TC u32 offload */ 990 struct cxgb4_tc_u32_table *tc_u32; 991 struct chcr_stats_debug chcr_stats; 992 993 /* TC flower offload */ 994 bool tc_flower_initialized; 995 struct rhashtable flower_tbl; 996 struct rhashtable_params flower_ht_params; 997 struct timer_list flower_stats_timer; 998 struct work_struct flower_stats_work; 999 1000 /* Ethtool Dump */ 1001 struct ethtool_dump eth_dump; 1002 1003 /* HMA */ 1004 struct hma_data hma; 1005 1006 struct srq_data *srq; 1007 1008 /* Dump buffer for collecting logs in kdump kernel */ 1009 struct vmcoredd_data vmcoredd; 1010 }; 1011 1012 /* Support for "sched-class" command to allow a TX Scheduling Class to be 1013 * programmed with various parameters. 1014 */ 1015 struct ch_sched_params { 1016 s8 type; /* packet or flow */ 1017 union { 1018 struct { 1019 s8 level; /* scheduler hierarchy level */ 1020 s8 mode; /* per-class or per-flow */ 1021 s8 rateunit; /* bit or packet rate */ 1022 s8 ratemode; /* %port relative or kbps absolute */ 1023 s8 channel; /* scheduler channel [0..N] */ 1024 s8 class; /* scheduler class [0..N] */ 1025 s32 minrate; /* minimum rate */ 1026 s32 maxrate; /* maximum rate */ 1027 s16 weight; /* percent weight */ 1028 s16 pktsize; /* average packet size */ 1029 } params; 1030 } u; 1031 }; 1032 1033 enum { 1034 SCHED_CLASS_TYPE_PACKET = 0, /* class type */ 1035 }; 1036 1037 enum { 1038 SCHED_CLASS_LEVEL_CL_RL = 0, /* class rate limiter */ 1039 }; 1040 1041 enum { 1042 SCHED_CLASS_MODE_CLASS = 0, /* per-class scheduling */ 1043 }; 1044 1045 enum { 1046 SCHED_CLASS_RATEUNIT_BITS = 0, /* bit rate scheduling */ 1047 }; 1048 1049 enum { 1050 SCHED_CLASS_RATEMODE_ABS = 1, /* Kb/s */ 1051 }; 1052 1053 struct tx_sw_desc { /* SW state per Tx descriptor */ 1054 struct sk_buff *skb; 1055 struct ulptx_sgl *sgl; 1056 }; 1057 1058 /* Support for "sched_queue" command to allow one or more NIC TX Queues 1059 * to be bound to a TX Scheduling Class. 1060 */ 1061 struct ch_sched_queue { 1062 s8 queue; /* queue index */ 1063 s8 class; /* class index */ 1064 }; 1065 1066 /* Defined bit width of user definable filter tuples 1067 */ 1068 #define ETHTYPE_BITWIDTH 16 1069 #define FRAG_BITWIDTH 1 1070 #define MACIDX_BITWIDTH 9 1071 #define FCOE_BITWIDTH 1 1072 #define IPORT_BITWIDTH 3 1073 #define MATCHTYPE_BITWIDTH 3 1074 #define PROTO_BITWIDTH 8 1075 #define TOS_BITWIDTH 8 1076 #define PF_BITWIDTH 8 1077 #define VF_BITWIDTH 8 1078 #define IVLAN_BITWIDTH 16 1079 #define OVLAN_BITWIDTH 16 1080 #define ENCAP_VNI_BITWIDTH 24 1081 1082 /* Filter matching rules. These consist of a set of ingress packet field 1083 * (value, mask) tuples. The associated ingress packet field matches the 1084 * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field 1085 * rule can be constructed by specifying a tuple of (0, 0).) A filter rule 1086 * matches an ingress packet when all of the individual individual field 1087 * matching rules are true. 1088 * 1089 * Partial field masks are always valid, however, while it may be easy to 1090 * understand their meanings for some fields (e.g. IP address to match a 1091 * subnet), for others making sensible partial masks is less intuitive (e.g. 1092 * MPS match type) ... 1093 * 1094 * Most of the following data structures are modeled on T4 capabilities. 1095 * Drivers for earlier chips use the subsets which make sense for those chips. 1096 * We really need to come up with a hardware-independent mechanism to 1097 * represent hardware filter capabilities ... 1098 */ 1099 struct ch_filter_tuple { 1100 /* Compressed header matching field rules. The TP_VLAN_PRI_MAP 1101 * register selects which of these fields will participate in the 1102 * filter match rules -- up to a maximum of 36 bits. Because 1103 * TP_VLAN_PRI_MAP is a global register, all filters must use the same 1104 * set of fields. 1105 */ 1106 uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */ 1107 uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */ 1108 uint32_t ivlan_vld:1; /* inner VLAN valid */ 1109 uint32_t ovlan_vld:1; /* outer VLAN valid */ 1110 uint32_t pfvf_vld:1; /* PF/VF valid */ 1111 uint32_t encap_vld:1; /* Encapsulation valid */ 1112 uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */ 1113 uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */ 1114 uint32_t iport:IPORT_BITWIDTH; /* ingress port */ 1115 uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */ 1116 uint32_t proto:PROTO_BITWIDTH; /* protocol type */ 1117 uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */ 1118 uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */ 1119 uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */ 1120 uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */ 1121 uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */ 1122 uint32_t vni:ENCAP_VNI_BITWIDTH; /* VNI of tunnel */ 1123 1124 /* Uncompressed header matching field rules. These are always 1125 * available for field rules. 1126 */ 1127 uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */ 1128 uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */ 1129 uint16_t lport; /* local port */ 1130 uint16_t fport; /* foreign port */ 1131 }; 1132 1133 /* A filter ioctl command. 1134 */ 1135 struct ch_filter_specification { 1136 /* Administrative fields for filter. 1137 */ 1138 uint32_t hitcnts:1; /* count filter hits in TCB */ 1139 uint32_t prio:1; /* filter has priority over active/server */ 1140 1141 /* Fundamental filter typing. This is the one element of filter 1142 * matching that doesn't exist as a (value, mask) tuple. 1143 */ 1144 uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */ 1145 u32 hash:1; /* 0 => wild-card, 1 => exact-match */ 1146 1147 /* Packet dispatch information. Ingress packets which match the 1148 * filter rules will be dropped, passed to the host or switched back 1149 * out as egress packets. 1150 */ 1151 uint32_t action:2; /* drop, pass, switch */ 1152 1153 uint32_t rpttid:1; /* report TID in RSS hash field */ 1154 1155 uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */ 1156 uint32_t iq:10; /* ingress queue */ 1157 1158 uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */ 1159 uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */ 1160 /* 1 => TCB contains IQ ID */ 1161 1162 /* Switch proxy/rewrite fields. An ingress packet which matches a 1163 * filter with "switch" set will be looped back out as an egress 1164 * packet -- potentially with some Ethernet header rewriting. 1165 */ 1166 uint32_t eport:2; /* egress port to switch packet out */ 1167 uint32_t newdmac:1; /* rewrite destination MAC address */ 1168 uint32_t newsmac:1; /* rewrite source MAC address */ 1169 uint32_t newvlan:2; /* rewrite VLAN Tag */ 1170 uint32_t nat_mode:3; /* specify NAT operation mode */ 1171 uint8_t dmac[ETH_ALEN]; /* new destination MAC address */ 1172 uint8_t smac[ETH_ALEN]; /* new source MAC address */ 1173 uint16_t vlan; /* VLAN Tag to insert */ 1174 1175 u8 nat_lip[16]; /* local IP to use after NAT'ing */ 1176 u8 nat_fip[16]; /* foreign IP to use after NAT'ing */ 1177 u16 nat_lport; /* local port to use after NAT'ing */ 1178 u16 nat_fport; /* foreign port to use after NAT'ing */ 1179 1180 /* reservation for future additions */ 1181 u8 rsvd[24]; 1182 1183 /* Filter rule value/mask pairs. 1184 */ 1185 struct ch_filter_tuple val; 1186 struct ch_filter_tuple mask; 1187 }; 1188 1189 enum { 1190 FILTER_PASS = 0, /* default */ 1191 FILTER_DROP, 1192 FILTER_SWITCH 1193 }; 1194 1195 enum { 1196 VLAN_NOCHANGE = 0, /* default */ 1197 VLAN_REMOVE, 1198 VLAN_INSERT, 1199 VLAN_REWRITE 1200 }; 1201 1202 enum { 1203 NAT_MODE_NONE = 0, /* No NAT performed */ 1204 NAT_MODE_DIP, /* NAT on Dst IP */ 1205 NAT_MODE_DIP_DP, /* NAT on Dst IP, Dst Port */ 1206 NAT_MODE_DIP_DP_SIP, /* NAT on Dst IP, Dst Port and Src IP */ 1207 NAT_MODE_DIP_DP_SP, /* NAT on Dst IP, Dst Port and Src Port */ 1208 NAT_MODE_SIP_SP, /* NAT on Src IP and Src Port */ 1209 NAT_MODE_DIP_SIP_SP, /* NAT on Dst IP, Src IP and Src Port */ 1210 NAT_MODE_ALL /* NAT on entire 4-tuple */ 1211 }; 1212 1213 /* Host shadow copy of ingress filter entry. This is in host native format 1214 * and doesn't match the ordering or bit order, etc. of the hardware of the 1215 * firmware command. The use of bit-field structure elements is purely to 1216 * remind ourselves of the field size limitations and save memory in the case 1217 * where the filter table is large. 1218 */ 1219 struct filter_entry { 1220 /* Administrative fields for filter. */ 1221 u32 valid:1; /* filter allocated and valid */ 1222 u32 locked:1; /* filter is administratively locked */ 1223 1224 u32 pending:1; /* filter action is pending firmware reply */ 1225 struct filter_ctx *ctx; /* Caller's completion hook */ 1226 struct l2t_entry *l2t; /* Layer Two Table entry for dmac */ 1227 struct smt_entry *smt; /* Source Mac Table entry for smac */ 1228 struct net_device *dev; /* Associated net device */ 1229 u32 tid; /* This will store the actual tid */ 1230 1231 /* The filter itself. Most of this is a straight copy of information 1232 * provided by the extended ioctl(). Some fields are translated to 1233 * internal forms -- for instance the Ingress Queue ID passed in from 1234 * the ioctl() is translated into the Absolute Ingress Queue ID. 1235 */ 1236 struct ch_filter_specification fs; 1237 }; 1238 1239 static inline int is_offload(const struct adapter *adap) 1240 { 1241 return adap->params.offload; 1242 } 1243 1244 static inline int is_hashfilter(const struct adapter *adap) 1245 { 1246 return adap->params.hash_filter; 1247 } 1248 1249 static inline int is_pci_uld(const struct adapter *adap) 1250 { 1251 return adap->params.crypto; 1252 } 1253 1254 static inline int is_uld(const struct adapter *adap) 1255 { 1256 return (adap->params.offload || adap->params.crypto); 1257 } 1258 1259 static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr) 1260 { 1261 return readl(adap->regs + reg_addr); 1262 } 1263 1264 static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val) 1265 { 1266 writel(val, adap->regs + reg_addr); 1267 } 1268 1269 #ifndef readq 1270 static inline u64 readq(const volatile void __iomem *addr) 1271 { 1272 return readl(addr) + ((u64)readl(addr + 4) << 32); 1273 } 1274 1275 static inline void writeq(u64 val, volatile void __iomem *addr) 1276 { 1277 writel(val, addr); 1278 writel(val >> 32, addr + 4); 1279 } 1280 #endif 1281 1282 static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr) 1283 { 1284 return readq(adap->regs + reg_addr); 1285 } 1286 1287 static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val) 1288 { 1289 writeq(val, adap->regs + reg_addr); 1290 } 1291 1292 /** 1293 * t4_set_hw_addr - store a port's MAC address in SW 1294 * @adapter: the adapter 1295 * @port_idx: the port index 1296 * @hw_addr: the Ethernet address 1297 * 1298 * Store the Ethernet address of the given port in SW. Called by the common 1299 * code when it retrieves a port's Ethernet address from EEPROM. 1300 */ 1301 static inline void t4_set_hw_addr(struct adapter *adapter, int port_idx, 1302 u8 hw_addr[]) 1303 { 1304 ether_addr_copy(adapter->port[port_idx]->dev_addr, hw_addr); 1305 ether_addr_copy(adapter->port[port_idx]->perm_addr, hw_addr); 1306 } 1307 1308 /** 1309 * netdev2pinfo - return the port_info structure associated with a net_device 1310 * @dev: the netdev 1311 * 1312 * Return the struct port_info associated with a net_device 1313 */ 1314 static inline struct port_info *netdev2pinfo(const struct net_device *dev) 1315 { 1316 return netdev_priv(dev); 1317 } 1318 1319 /** 1320 * adap2pinfo - return the port_info of a port 1321 * @adap: the adapter 1322 * @idx: the port index 1323 * 1324 * Return the port_info structure for the port of the given index. 1325 */ 1326 static inline struct port_info *adap2pinfo(struct adapter *adap, int idx) 1327 { 1328 return netdev_priv(adap->port[idx]); 1329 } 1330 1331 /** 1332 * netdev2adap - return the adapter structure associated with a net_device 1333 * @dev: the netdev 1334 * 1335 * Return the struct adapter associated with a net_device 1336 */ 1337 static inline struct adapter *netdev2adap(const struct net_device *dev) 1338 { 1339 return netdev2pinfo(dev)->adapter; 1340 } 1341 1342 /* Return a version number to identify the type of adapter. The scheme is: 1343 * - bits 0..9: chip version 1344 * - bits 10..15: chip revision 1345 * - bits 16..23: register dump version 1346 */ 1347 static inline unsigned int mk_adap_vers(struct adapter *ap) 1348 { 1349 return CHELSIO_CHIP_VERSION(ap->params.chip) | 1350 (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16); 1351 } 1352 1353 /* Return a queue's interrupt hold-off time in us. 0 means no timer. */ 1354 static inline unsigned int qtimer_val(const struct adapter *adap, 1355 const struct sge_rspq *q) 1356 { 1357 unsigned int idx = q->intr_params >> 1; 1358 1359 return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0; 1360 } 1361 1362 /* driver version & name used for ethtool_drvinfo */ 1363 extern char cxgb4_driver_name[]; 1364 extern const char cxgb4_driver_version[]; 1365 1366 void t4_os_portmod_changed(struct adapter *adap, int port_id); 1367 void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat); 1368 1369 void t4_free_sge_resources(struct adapter *adap); 1370 void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q); 1371 irq_handler_t t4_intr_handler(struct adapter *adap); 1372 netdev_tx_t t4_start_xmit(struct sk_buff *skb, struct net_device *dev); 1373 int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp, 1374 const struct pkt_gl *gl); 1375 int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb); 1376 int t4_ofld_send(struct adapter *adap, struct sk_buff *skb); 1377 int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, 1378 struct net_device *dev, int intr_idx, 1379 struct sge_fl *fl, rspq_handler_t hnd, 1380 rspq_flush_handler_t flush_handler, int cong); 1381 int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq, 1382 struct net_device *dev, struct netdev_queue *netdevq, 1383 unsigned int iqid); 1384 int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq, 1385 struct net_device *dev, unsigned int iqid, 1386 unsigned int cmplqid); 1387 int t4_sge_mod_ctrl_txq(struct adapter *adap, unsigned int eqid, 1388 unsigned int cmplqid); 1389 int t4_sge_alloc_uld_txq(struct adapter *adap, struct sge_uld_txq *txq, 1390 struct net_device *dev, unsigned int iqid, 1391 unsigned int uld_type); 1392 irqreturn_t t4_sge_intr_msix(int irq, void *cookie); 1393 int t4_sge_init(struct adapter *adap); 1394 void t4_sge_start(struct adapter *adap); 1395 void t4_sge_stop(struct adapter *adap); 1396 void cxgb4_set_ethtool_ops(struct net_device *netdev); 1397 int cxgb4_write_rss(const struct port_info *pi, const u16 *queues); 1398 enum cpl_tx_tnl_lso_type cxgb_encap_offload_supported(struct sk_buff *skb); 1399 extern int dbfifo_int_thresh; 1400 1401 #define for_each_port(adapter, iter) \ 1402 for (iter = 0; iter < (adapter)->params.nports; ++iter) 1403 1404 static inline int is_bypass(struct adapter *adap) 1405 { 1406 return adap->params.bypass; 1407 } 1408 1409 static inline int is_bypass_device(int device) 1410 { 1411 /* this should be set based upon device capabilities */ 1412 switch (device) { 1413 case 0x440b: 1414 case 0x440c: 1415 return 1; 1416 default: 1417 return 0; 1418 } 1419 } 1420 1421 static inline int is_10gbt_device(int device) 1422 { 1423 /* this should be set based upon device capabilities */ 1424 switch (device) { 1425 case 0x4409: 1426 case 0x4486: 1427 return 1; 1428 1429 default: 1430 return 0; 1431 } 1432 } 1433 1434 static inline unsigned int core_ticks_per_usec(const struct adapter *adap) 1435 { 1436 return adap->params.vpd.cclk / 1000; 1437 } 1438 1439 static inline unsigned int us_to_core_ticks(const struct adapter *adap, 1440 unsigned int us) 1441 { 1442 return (us * adap->params.vpd.cclk) / 1000; 1443 } 1444 1445 static inline unsigned int core_ticks_to_us(const struct adapter *adapter, 1446 unsigned int ticks) 1447 { 1448 /* add Core Clock / 2 to round ticks to nearest uS */ 1449 return ((ticks * 1000 + adapter->params.vpd.cclk/2) / 1450 adapter->params.vpd.cclk); 1451 } 1452 1453 static inline unsigned int dack_ticks_to_usec(const struct adapter *adap, 1454 unsigned int ticks) 1455 { 1456 return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap); 1457 } 1458 1459 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, 1460 u32 val); 1461 1462 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 1463 int size, void *rpl, bool sleep_ok, int timeout); 1464 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 1465 void *rpl, bool sleep_ok); 1466 1467 static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox, 1468 const void *cmd, int size, void *rpl, 1469 int timeout) 1470 { 1471 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true, 1472 timeout); 1473 } 1474 1475 static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, 1476 int size, void *rpl) 1477 { 1478 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true); 1479 } 1480 1481 static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, 1482 int size, void *rpl) 1483 { 1484 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false); 1485 } 1486 1487 /** 1488 * hash_mac_addr - return the hash value of a MAC address 1489 * @addr: the 48-bit Ethernet MAC address 1490 * 1491 * Hashes a MAC address according to the hash function used by HW inexact 1492 * (hash) address matching. 1493 */ 1494 static inline int hash_mac_addr(const u8 *addr) 1495 { 1496 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2]; 1497 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5]; 1498 1499 a ^= b; 1500 a ^= (a >> 12); 1501 a ^= (a >> 6); 1502 return a & 0x3f; 1503 } 1504 1505 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us, 1506 unsigned int cnt); 1507 static inline void init_rspq(struct adapter *adap, struct sge_rspq *q, 1508 unsigned int us, unsigned int cnt, 1509 unsigned int size, unsigned int iqe_size) 1510 { 1511 q->adap = adap; 1512 cxgb4_set_rspq_intr_params(q, us, cnt); 1513 q->iqe_len = iqe_size; 1514 q->size = size; 1515 } 1516 1517 /** 1518 * t4_is_inserted_mod_type - is a plugged in Firmware Module Type 1519 * @fw_mod_type: the Firmware Mofule Type 1520 * 1521 * Return whether the Firmware Module Type represents a real Transceiver 1522 * Module/Cable Module Type which has been inserted. 1523 */ 1524 static inline bool t4_is_inserted_mod_type(unsigned int fw_mod_type) 1525 { 1526 return (fw_mod_type != FW_PORT_MOD_TYPE_NONE && 1527 fw_mod_type != FW_PORT_MOD_TYPE_NOTSUPPORTED && 1528 fw_mod_type != FW_PORT_MOD_TYPE_UNKNOWN && 1529 fw_mod_type != FW_PORT_MOD_TYPE_ERROR); 1530 } 1531 1532 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 1533 unsigned int data_reg, const u32 *vals, 1534 unsigned int nregs, unsigned int start_idx); 1535 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 1536 unsigned int data_reg, u32 *vals, unsigned int nregs, 1537 unsigned int start_idx); 1538 void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val); 1539 1540 struct fw_filter_wr; 1541 1542 void t4_intr_enable(struct adapter *adapter); 1543 void t4_intr_disable(struct adapter *adapter); 1544 int t4_slow_intr_handler(struct adapter *adapter); 1545 1546 int t4_wait_dev_ready(void __iomem *regs); 1547 1548 int t4_link_l1cfg_core(struct adapter *adap, unsigned int mbox, 1549 unsigned int port, struct link_config *lc, 1550 bool sleep_ok, int timeout); 1551 1552 static inline int t4_link_l1cfg(struct adapter *adapter, unsigned int mbox, 1553 unsigned int port, struct link_config *lc) 1554 { 1555 return t4_link_l1cfg_core(adapter, mbox, port, lc, 1556 true, FW_CMD_MAX_TIMEOUT); 1557 } 1558 1559 static inline int t4_link_l1cfg_ns(struct adapter *adapter, unsigned int mbox, 1560 unsigned int port, struct link_config *lc) 1561 { 1562 return t4_link_l1cfg_core(adapter, mbox, port, lc, 1563 false, FW_CMD_MAX_TIMEOUT); 1564 } 1565 1566 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port); 1567 1568 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg); 1569 u32 t4_get_util_window(struct adapter *adap); 1570 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window); 1571 1572 int t4_memory_rw_init(struct adapter *adap, int win, int mtype, u32 *mem_off, 1573 u32 *mem_base, u32 *mem_aperture); 1574 void t4_memory_update_win(struct adapter *adap, int win, u32 addr); 1575 void t4_memory_rw_residual(struct adapter *adap, u32 off, u32 addr, u8 *buf, 1576 int dir); 1577 #define T4_MEMORY_WRITE 0 1578 #define T4_MEMORY_READ 1 1579 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len, 1580 void *buf, int dir); 1581 static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr, 1582 u32 len, __be32 *buf) 1583 { 1584 return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0); 1585 } 1586 1587 unsigned int t4_get_regs_len(struct adapter *adapter); 1588 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size); 1589 1590 int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz); 1591 int t4_seeprom_wp(struct adapter *adapter, bool enable); 1592 int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p); 1593 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p); 1594 int t4_get_pfres(struct adapter *adapter); 1595 int t4_read_flash(struct adapter *adapter, unsigned int addr, 1596 unsigned int nwords, u32 *data, int byte_oriented); 1597 int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size); 1598 int t4_load_phy_fw(struct adapter *adap, 1599 int win, spinlock_t *lock, 1600 int (*phy_fw_version)(const u8 *, size_t), 1601 const u8 *phy_fw_data, size_t phy_fw_size); 1602 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver); 1603 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op); 1604 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 1605 const u8 *fw_data, unsigned int size, int force); 1606 int t4_fl_pkt_align(struct adapter *adap); 1607 unsigned int t4_flash_cfg_addr(struct adapter *adapter); 1608 int t4_check_fw_version(struct adapter *adap); 1609 int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size); 1610 int t4_get_fw_version(struct adapter *adapter, u32 *vers); 1611 int t4_get_bs_version(struct adapter *adapter, u32 *vers); 1612 int t4_get_tp_version(struct adapter *adapter, u32 *vers); 1613 int t4_get_exprom_version(struct adapter *adapter, u32 *vers); 1614 int t4_get_scfg_version(struct adapter *adapter, u32 *vers); 1615 int t4_get_vpd_version(struct adapter *adapter, u32 *vers); 1616 int t4_get_version_info(struct adapter *adapter); 1617 void t4_dump_version_info(struct adapter *adapter); 1618 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info, 1619 const u8 *fw_data, unsigned int fw_size, 1620 struct fw_hdr *card_fw, enum dev_state state, int *reset); 1621 int t4_prep_adapter(struct adapter *adapter); 1622 int t4_shutdown_adapter(struct adapter *adapter); 1623 1624 enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS }; 1625 int t4_bar2_sge_qregs(struct adapter *adapter, 1626 unsigned int qid, 1627 enum t4_bar2_qtype qtype, 1628 int user, 1629 u64 *pbar2_qoffset, 1630 unsigned int *pbar2_qid); 1631 1632 unsigned int qtimer_val(const struct adapter *adap, 1633 const struct sge_rspq *q); 1634 1635 int t4_init_devlog_params(struct adapter *adapter); 1636 int t4_init_sge_params(struct adapter *adapter); 1637 int t4_init_tp_params(struct adapter *adap, bool sleep_ok); 1638 int t4_filter_field_shift(const struct adapter *adap, int filter_sel); 1639 int t4_init_rss_mode(struct adapter *adap, int mbox); 1640 int t4_init_portinfo(struct port_info *pi, int mbox, 1641 int port, int pf, int vf, u8 mac[]); 1642 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf); 1643 void t4_fatal_err(struct adapter *adapter); 1644 unsigned int t4_chip_rss_size(struct adapter *adapter); 1645 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 1646 int start, int n, const u16 *rspq, unsigned int nrspq); 1647 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 1648 unsigned int flags); 1649 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 1650 unsigned int flags, unsigned int defq); 1651 int t4_read_rss(struct adapter *adapter, u16 *entries); 1652 void t4_read_rss_key(struct adapter *adapter, u32 *key, bool sleep_ok); 1653 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx, 1654 bool sleep_ok); 1655 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, 1656 u32 *valp, bool sleep_ok); 1657 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 1658 u32 *vfl, u32 *vfh, bool sleep_ok); 1659 u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok); 1660 u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok); 1661 1662 unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx); 1663 unsigned int t4_get_tp_ch_map(struct adapter *adapter, int pidx); 1664 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1665 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1666 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, 1667 size_t n); 1668 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, 1669 size_t n); 1670 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 1671 unsigned int *valp); 1672 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 1673 const unsigned int *valp); 1674 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr); 1675 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, 1676 unsigned int *pif_req_wrptr, 1677 unsigned int *pif_rsp_wrptr); 1678 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp); 1679 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres); 1680 const char *t4_get_port_type_description(enum fw_port_type port_type); 1681 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); 1682 void t4_get_port_stats_offset(struct adapter *adap, int idx, 1683 struct port_stats *stats, 1684 struct port_stats *offset); 1685 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p); 1686 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); 1687 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]); 1688 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 1689 unsigned int mask, unsigned int val); 1690 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr); 1691 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st, 1692 bool sleep_ok); 1693 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st, 1694 bool sleep_ok); 1695 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st, 1696 bool sleep_ok); 1697 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st, 1698 bool sleep_ok); 1699 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 1700 struct tp_tcp_stats *v6, bool sleep_ok); 1701 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 1702 struct tp_fcoe_stats *st, bool sleep_ok); 1703 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 1704 const unsigned short *alpha, const unsigned short *beta); 1705 1706 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf); 1707 1708 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate); 1709 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid); 1710 1711 void t4_wol_magic_enable(struct adapter *adap, unsigned int port, 1712 const u8 *addr); 1713 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 1714 u64 mask0, u64 mask1, unsigned int crc, bool enable); 1715 1716 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 1717 enum dev_master master, enum dev_state *state); 1718 int t4_fw_bye(struct adapter *adap, unsigned int mbox); 1719 int t4_early_init(struct adapter *adap, unsigned int mbox); 1720 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); 1721 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, 1722 unsigned int cache_line_size); 1723 int t4_fw_initialize(struct adapter *adap, unsigned int mbox); 1724 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1725 unsigned int vf, unsigned int nparams, const u32 *params, 1726 u32 *val); 1727 int t4_query_params_ns(struct adapter *adap, unsigned int mbox, unsigned int pf, 1728 unsigned int vf, unsigned int nparams, const u32 *params, 1729 u32 *val); 1730 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, 1731 unsigned int vf, unsigned int nparams, const u32 *params, 1732 u32 *val, int rw, bool sleep_ok); 1733 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 1734 unsigned int pf, unsigned int vf, 1735 unsigned int nparams, const u32 *params, 1736 const u32 *val, int timeout); 1737 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1738 unsigned int vf, unsigned int nparams, const u32 *params, 1739 const u32 *val); 1740 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 1741 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 1742 unsigned int rxqi, unsigned int rxq, unsigned int tc, 1743 unsigned int vi, unsigned int cmask, unsigned int pmask, 1744 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps); 1745 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 1746 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 1747 unsigned int *rss_size); 1748 int t4_free_vi(struct adapter *adap, unsigned int mbox, 1749 unsigned int pf, unsigned int vf, 1750 unsigned int viid); 1751 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 1752 int mtu, int promisc, int all_multi, int bcast, int vlanex, 1753 bool sleep_ok); 1754 int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid, 1755 const u8 *addr, const u8 *mask, unsigned int idx, 1756 u8 lookup_type, u8 port_id, bool sleep_ok); 1757 int t4_free_encap_mac_filt(struct adapter *adap, unsigned int viid, int idx, 1758 bool sleep_ok); 1759 int t4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid, 1760 const u8 *addr, const u8 *mask, unsigned int vni, 1761 unsigned int vni_mask, u8 dip_hit, u8 lookup_type, 1762 bool sleep_ok); 1763 int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid, 1764 const u8 *addr, const u8 *mask, unsigned int idx, 1765 u8 lookup_type, u8 port_id, bool sleep_ok); 1766 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, 1767 unsigned int viid, bool free, unsigned int naddr, 1768 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok); 1769 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox, 1770 unsigned int viid, unsigned int naddr, 1771 const u8 **addr, bool sleep_ok); 1772 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 1773 int idx, const u8 *addr, bool persist, bool add_smt); 1774 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 1775 bool ucast, u64 vec, bool sleep_ok); 1776 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 1777 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en); 1778 int t4_enable_pi_params(struct adapter *adap, unsigned int mbox, 1779 struct port_info *pi, 1780 bool rx_en, bool tx_en, bool dcb_en); 1781 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 1782 bool rx_en, bool tx_en); 1783 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 1784 unsigned int nblinks); 1785 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1786 unsigned int mmd, unsigned int reg, u16 *valp); 1787 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1788 unsigned int mmd, unsigned int reg, u16 val); 1789 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, 1790 unsigned int vf, unsigned int iqtype, unsigned int iqid, 1791 unsigned int fl0id, unsigned int fl1id); 1792 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1793 unsigned int vf, unsigned int iqtype, unsigned int iqid, 1794 unsigned int fl0id, unsigned int fl1id); 1795 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1796 unsigned int vf, unsigned int eqid); 1797 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1798 unsigned int vf, unsigned int eqid); 1799 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1800 unsigned int vf, unsigned int eqid); 1801 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox, int ctxt_type); 1802 void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl); 1803 int t4_update_port_info(struct port_info *pi); 1804 int t4_get_link_params(struct port_info *pi, unsigned int *link_okp, 1805 unsigned int *speedp, unsigned int *mtup); 1806 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); 1807 void t4_db_full(struct adapter *adapter); 1808 void t4_db_dropped(struct adapter *adapter); 1809 int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp, 1810 int filter_index, int enable); 1811 void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp, 1812 int filter_index, int *enabled); 1813 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, 1814 u32 addr, u32 val); 1815 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]); 1816 void t4_get_tx_sched(struct adapter *adap, unsigned int sched, 1817 unsigned int *kbps, unsigned int *ipg, bool sleep_ok); 1818 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid, 1819 enum ctxt_type ctype, u32 *data); 1820 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, 1821 enum ctxt_type ctype, u32 *data); 1822 int t4_sched_params(struct adapter *adapter, int type, int level, int mode, 1823 int rateunit, int ratemode, int channel, int class, 1824 int minrate, int maxrate, int weight, int pktsize); 1825 void t4_sge_decode_idma_state(struct adapter *adapter, int state); 1826 void t4_idma_monitor_init(struct adapter *adapter, 1827 struct sge_idma_monitor_state *idma); 1828 void t4_idma_monitor(struct adapter *adapter, 1829 struct sge_idma_monitor_state *idma, 1830 int hz, int ticks); 1831 int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf, 1832 unsigned int naddr, u8 *addr); 1833 void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 1834 u32 start_index, bool sleep_ok); 1835 void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 1836 u32 start_index, bool sleep_ok); 1837 void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, 1838 u32 start_index, bool sleep_ok); 1839 1840 void t4_uld_mem_free(struct adapter *adap); 1841 int t4_uld_mem_alloc(struct adapter *adap); 1842 void t4_uld_clean_up(struct adapter *adap); 1843 void t4_register_netevent_notifier(void); 1844 int t4_i2c_rd(struct adapter *adap, unsigned int mbox, int port, 1845 unsigned int devid, unsigned int offset, 1846 unsigned int len, u8 *buf); 1847 void free_rspq_fl(struct adapter *adap, struct sge_rspq *rq, struct sge_fl *fl); 1848 void free_tx_desc(struct adapter *adap, struct sge_txq *q, 1849 unsigned int n, bool unmap); 1850 void free_txq(struct adapter *adap, struct sge_txq *q); 1851 void cxgb4_reclaim_completed_tx(struct adapter *adap, 1852 struct sge_txq *q, bool unmap); 1853 int cxgb4_map_skb(struct device *dev, const struct sk_buff *skb, 1854 dma_addr_t *addr); 1855 void cxgb4_inline_tx_skb(const struct sk_buff *skb, const struct sge_txq *q, 1856 void *pos); 1857 void cxgb4_write_sgl(const struct sk_buff *skb, struct sge_txq *q, 1858 struct ulptx_sgl *sgl, u64 *end, unsigned int start, 1859 const dma_addr_t *addr); 1860 void cxgb4_ring_tx_db(struct adapter *adap, struct sge_txq *q, int n); 1861 int t4_set_vlan_acl(struct adapter *adap, unsigned int mbox, unsigned int vf, 1862 u16 vlan); 1863 int cxgb4_dcb_enabled(const struct net_device *dev); 1864 #endif /* __CXGB4_H__ */ 1865