1 /* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #ifndef __CXGB4_H__ 36 #define __CXGB4_H__ 37 38 #include "t4_hw.h" 39 40 #include <linux/bitops.h> 41 #include <linux/cache.h> 42 #include <linux/interrupt.h> 43 #include <linux/list.h> 44 #include <linux/netdevice.h> 45 #include <linux/pci.h> 46 #include <linux/spinlock.h> 47 #include <linux/timer.h> 48 #include <linux/vmalloc.h> 49 #include <linux/rhashtable.h> 50 #include <linux/etherdevice.h> 51 #include <linux/net_tstamp.h> 52 #include <linux/ptp_clock_kernel.h> 53 #include <linux/ptp_classify.h> 54 #include <linux/crash_dump.h> 55 #include <asm/io.h> 56 #include "t4_chip_type.h" 57 #include "cxgb4_uld.h" 58 59 #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__) 60 extern struct list_head adapter_list; 61 extern struct mutex uld_mutex; 62 63 /* Suspend an Ethernet Tx queue with fewer available descriptors than this. 64 * This is the same as calc_tx_descs() for a TSO packet with 65 * nr_frags == MAX_SKB_FRAGS. 66 */ 67 #define ETHTXQ_STOP_THRES \ 68 (1 + DIV_ROUND_UP((3 * MAX_SKB_FRAGS) / 2 + (MAX_SKB_FRAGS & 1), 8)) 69 70 enum { 71 MAX_NPORTS = 4, /* max # of ports */ 72 SERNUM_LEN = 24, /* Serial # length */ 73 EC_LEN = 16, /* E/C length */ 74 ID_LEN = 16, /* ID length */ 75 PN_LEN = 16, /* Part Number length */ 76 MACADDR_LEN = 12, /* MAC Address length */ 77 }; 78 79 enum { 80 T4_REGMAP_SIZE = (160 * 1024), 81 T5_REGMAP_SIZE = (332 * 1024), 82 }; 83 84 enum { 85 MEM_EDC0, 86 MEM_EDC1, 87 MEM_MC, 88 MEM_MC0 = MEM_MC, 89 MEM_MC1, 90 MEM_HMA, 91 }; 92 93 enum { 94 MEMWIN0_APERTURE = 2048, 95 MEMWIN0_BASE = 0x1b800, 96 MEMWIN1_APERTURE = 32768, 97 MEMWIN1_BASE = 0x28000, 98 MEMWIN1_BASE_T5 = 0x52000, 99 MEMWIN2_APERTURE = 65536, 100 MEMWIN2_BASE = 0x30000, 101 MEMWIN2_APERTURE_T5 = 131072, 102 MEMWIN2_BASE_T5 = 0x60000, 103 }; 104 105 enum dev_master { 106 MASTER_CANT, 107 MASTER_MAY, 108 MASTER_MUST 109 }; 110 111 enum dev_state { 112 DEV_STATE_UNINIT, 113 DEV_STATE_INIT, 114 DEV_STATE_ERR 115 }; 116 117 enum cc_pause { 118 PAUSE_RX = 1 << 0, 119 PAUSE_TX = 1 << 1, 120 PAUSE_AUTONEG = 1 << 2 121 }; 122 123 enum cc_fec { 124 FEC_AUTO = 1 << 0, /* IEEE 802.3 "automatic" */ 125 FEC_RS = 1 << 1, /* Reed-Solomon */ 126 FEC_BASER_RS = 1 << 2 /* BaseR/Reed-Solomon */ 127 }; 128 129 struct port_stats { 130 u64 tx_octets; /* total # of octets in good frames */ 131 u64 tx_frames; /* all good frames */ 132 u64 tx_bcast_frames; /* all broadcast frames */ 133 u64 tx_mcast_frames; /* all multicast frames */ 134 u64 tx_ucast_frames; /* all unicast frames */ 135 u64 tx_error_frames; /* all error frames */ 136 137 u64 tx_frames_64; /* # of Tx frames in a particular range */ 138 u64 tx_frames_65_127; 139 u64 tx_frames_128_255; 140 u64 tx_frames_256_511; 141 u64 tx_frames_512_1023; 142 u64 tx_frames_1024_1518; 143 u64 tx_frames_1519_max; 144 145 u64 tx_drop; /* # of dropped Tx frames */ 146 u64 tx_pause; /* # of transmitted pause frames */ 147 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ 148 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ 149 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ 150 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ 151 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ 152 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ 153 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ 154 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ 155 156 u64 rx_octets; /* total # of octets in good frames */ 157 u64 rx_frames; /* all good frames */ 158 u64 rx_bcast_frames; /* all broadcast frames */ 159 u64 rx_mcast_frames; /* all multicast frames */ 160 u64 rx_ucast_frames; /* all unicast frames */ 161 u64 rx_too_long; /* # of frames exceeding MTU */ 162 u64 rx_jabber; /* # of jabber frames */ 163 u64 rx_fcs_err; /* # of received frames with bad FCS */ 164 u64 rx_len_err; /* # of received frames with length error */ 165 u64 rx_symbol_err; /* symbol errors */ 166 u64 rx_runt; /* # of short frames */ 167 168 u64 rx_frames_64; /* # of Rx frames in a particular range */ 169 u64 rx_frames_65_127; 170 u64 rx_frames_128_255; 171 u64 rx_frames_256_511; 172 u64 rx_frames_512_1023; 173 u64 rx_frames_1024_1518; 174 u64 rx_frames_1519_max; 175 176 u64 rx_pause; /* # of received pause frames */ 177 u64 rx_ppp0; /* # of received PPP prio 0 frames */ 178 u64 rx_ppp1; /* # of received PPP prio 1 frames */ 179 u64 rx_ppp2; /* # of received PPP prio 2 frames */ 180 u64 rx_ppp3; /* # of received PPP prio 3 frames */ 181 u64 rx_ppp4; /* # of received PPP prio 4 frames */ 182 u64 rx_ppp5; /* # of received PPP prio 5 frames */ 183 u64 rx_ppp6; /* # of received PPP prio 6 frames */ 184 u64 rx_ppp7; /* # of received PPP prio 7 frames */ 185 186 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ 187 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ 188 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ 189 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ 190 u64 rx_trunc0; /* buffer-group 0 truncated packets */ 191 u64 rx_trunc1; /* buffer-group 1 truncated packets */ 192 u64 rx_trunc2; /* buffer-group 2 truncated packets */ 193 u64 rx_trunc3; /* buffer-group 3 truncated packets */ 194 }; 195 196 struct lb_port_stats { 197 u64 octets; 198 u64 frames; 199 u64 bcast_frames; 200 u64 mcast_frames; 201 u64 ucast_frames; 202 u64 error_frames; 203 204 u64 frames_64; 205 u64 frames_65_127; 206 u64 frames_128_255; 207 u64 frames_256_511; 208 u64 frames_512_1023; 209 u64 frames_1024_1518; 210 u64 frames_1519_max; 211 212 u64 drop; 213 214 u64 ovflow0; 215 u64 ovflow1; 216 u64 ovflow2; 217 u64 ovflow3; 218 u64 trunc0; 219 u64 trunc1; 220 u64 trunc2; 221 u64 trunc3; 222 }; 223 224 struct tp_tcp_stats { 225 u32 tcp_out_rsts; 226 u64 tcp_in_segs; 227 u64 tcp_out_segs; 228 u64 tcp_retrans_segs; 229 }; 230 231 struct tp_usm_stats { 232 u32 frames; 233 u32 drops; 234 u64 octets; 235 }; 236 237 struct tp_fcoe_stats { 238 u32 frames_ddp; 239 u32 frames_drop; 240 u64 octets_ddp; 241 }; 242 243 struct tp_err_stats { 244 u32 mac_in_errs[4]; 245 u32 hdr_in_errs[4]; 246 u32 tcp_in_errs[4]; 247 u32 tnl_cong_drops[4]; 248 u32 ofld_chan_drops[4]; 249 u32 tnl_tx_drops[4]; 250 u32 ofld_vlan_drops[4]; 251 u32 tcp6_in_errs[4]; 252 u32 ofld_no_neigh; 253 u32 ofld_cong_defer; 254 }; 255 256 struct tp_cpl_stats { 257 u32 req[4]; 258 u32 rsp[4]; 259 }; 260 261 struct tp_rdma_stats { 262 u32 rqe_dfr_pkt; 263 u32 rqe_dfr_mod; 264 }; 265 266 struct sge_params { 267 u32 hps; /* host page size for our PF/VF */ 268 u32 eq_qpp; /* egress queues/page for our PF/VF */ 269 u32 iq_qpp; /* egress queues/page for our PF/VF */ 270 }; 271 272 struct tp_params { 273 unsigned int tre; /* log2 of core clocks per TP tick */ 274 unsigned int la_mask; /* what events are recorded by TP LA */ 275 unsigned short tx_modq_map; /* TX modulation scheduler queue to */ 276 /* channel map */ 277 278 uint32_t dack_re; /* DACK timer resolution */ 279 unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */ 280 281 u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */ 282 u32 ingress_config; /* cached TP_INGRESS_CONFIG */ 283 284 /* cached TP_OUT_CONFIG compressed error vector 285 * and passing outer header info for encapsulated packets. 286 */ 287 int rx_pkt_encap; 288 289 /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a 290 * subset of the set of fields which may be present in the Compressed 291 * Filter Tuple portion of filters and TCP TCB connections. The 292 * fields which are present are controlled by the TP_VLAN_PRI_MAP. 293 * Since a variable number of fields may or may not be present, their 294 * shifted field positions within the Compressed Filter Tuple may 295 * vary, or not even be present if the field isn't selected in 296 * TP_VLAN_PRI_MAP. Since some of these fields are needed in various 297 * places we store their offsets here, or a -1 if the field isn't 298 * present. 299 */ 300 int fcoe_shift; 301 int port_shift; 302 int vnic_shift; 303 int vlan_shift; 304 int tos_shift; 305 int protocol_shift; 306 int ethertype_shift; 307 int macmatch_shift; 308 int matchtype_shift; 309 int frag_shift; 310 311 u64 hash_filter_mask; 312 }; 313 314 struct vpd_params { 315 unsigned int cclk; 316 u8 ec[EC_LEN + 1]; 317 u8 sn[SERNUM_LEN + 1]; 318 u8 id[ID_LEN + 1]; 319 u8 pn[PN_LEN + 1]; 320 u8 na[MACADDR_LEN + 1]; 321 }; 322 323 struct pci_params { 324 unsigned int vpd_cap_addr; 325 unsigned char speed; 326 unsigned char width; 327 }; 328 329 struct devlog_params { 330 u32 memtype; /* which memory (EDC0, EDC1, MC) */ 331 u32 start; /* start of log in firmware memory */ 332 u32 size; /* size of log */ 333 }; 334 335 /* Stores chip specific parameters */ 336 struct arch_specific_params { 337 u8 nchan; 338 u8 pm_stats_cnt; 339 u8 cng_ch_bits_log; /* congestion channel map bits width */ 340 u16 mps_rplc_size; 341 u16 vfcount; 342 u32 sge_fl_db; 343 u16 mps_tcam_size; 344 }; 345 346 struct adapter_params { 347 struct sge_params sge; 348 struct tp_params tp; 349 struct vpd_params vpd; 350 struct pci_params pci; 351 struct devlog_params devlog; 352 enum pcie_memwin drv_memwin; 353 354 unsigned int cim_la_size; 355 356 unsigned int sf_size; /* serial flash size in bytes */ 357 unsigned int sf_nsec; /* # of flash sectors */ 358 359 unsigned int fw_vers; /* firmware version */ 360 unsigned int bs_vers; /* bootstrap version */ 361 unsigned int tp_vers; /* TP microcode version */ 362 unsigned int er_vers; /* expansion ROM version */ 363 unsigned int scfg_vers; /* Serial Configuration version */ 364 unsigned int vpd_vers; /* VPD Version */ 365 u8 api_vers[7]; 366 367 unsigned short mtus[NMTUS]; 368 unsigned short a_wnd[NCCTRL_WIN]; 369 unsigned short b_wnd[NCCTRL_WIN]; 370 371 unsigned char nports; /* # of ethernet ports */ 372 unsigned char portvec; 373 enum chip_type chip; /* chip code */ 374 struct arch_specific_params arch; /* chip specific params */ 375 unsigned char offload; 376 unsigned char crypto; /* HW capability for crypto */ 377 378 unsigned char bypass; 379 unsigned char hash_filter; 380 381 unsigned int ofldq_wr_cred; 382 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ 383 384 unsigned int nsched_cls; /* number of traffic classes */ 385 unsigned int max_ordird_qp; /* Max read depth per RDMA QP */ 386 unsigned int max_ird_adapter; /* Max read depth per adapter */ 387 bool fr_nsmr_tpte_wr_support; /* FW support for FR_NSMR_TPTE_WR */ 388 u8 fw_caps_support; /* 32-bit Port Capabilities */ 389 bool filter2_wr_support; /* FW support for FILTER2_WR */ 390 391 /* MPS Buffer Group Map[per Port]. Bit i is set if buffer group i is 392 * used by the Port 393 */ 394 u8 mps_bg_map[MAX_NPORTS]; /* MPS Buffer Group Map */ 395 bool write_w_imm_support; /* FW supports WRITE_WITH_IMMEDIATE */ 396 bool write_cmpl_support; /* FW supports WRITE_CMPL */ 397 }; 398 399 /* State needed to monitor the forward progress of SGE Ingress DMA activities 400 * and possible hangs. 401 */ 402 struct sge_idma_monitor_state { 403 unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */ 404 unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */ 405 unsigned int idma_state[2]; /* IDMA Hang detect state */ 406 unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */ 407 unsigned int idma_warn[2]; /* time to warning in HZ */ 408 }; 409 410 /* Firmware Mailbox Command/Reply log. All values are in Host-Endian format. 411 * The access and execute times are signed in order to accommodate negative 412 * error returns. 413 */ 414 struct mbox_cmd { 415 u64 cmd[MBOX_LEN / 8]; /* a Firmware Mailbox Command/Reply */ 416 u64 timestamp; /* OS-dependent timestamp */ 417 u32 seqno; /* sequence number */ 418 s16 access; /* time (ms) to access mailbox */ 419 s16 execute; /* time (ms) to execute */ 420 }; 421 422 struct mbox_cmd_log { 423 unsigned int size; /* number of entries in the log */ 424 unsigned int cursor; /* next position in the log to write */ 425 u32 seqno; /* next sequence number */ 426 /* variable length mailbox command log starts here */ 427 }; 428 429 /* Given a pointer to a Firmware Mailbox Command Log and a log entry index, 430 * return a pointer to the specified entry. 431 */ 432 static inline struct mbox_cmd *mbox_cmd_log_entry(struct mbox_cmd_log *log, 433 unsigned int entry_idx) 434 { 435 return &((struct mbox_cmd *)&(log)[1])[entry_idx]; 436 } 437 438 #include "t4fw_api.h" 439 440 #define FW_VERSION(chip) ( \ 441 FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \ 442 FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \ 443 FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \ 444 FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD)) 445 #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf) 446 447 struct fw_info { 448 u8 chip; 449 char *fs_name; 450 char *fw_mod_name; 451 struct fw_hdr fw_hdr; 452 }; 453 454 struct trace_params { 455 u32 data[TRACE_LEN / 4]; 456 u32 mask[TRACE_LEN / 4]; 457 unsigned short snap_len; 458 unsigned short min_len; 459 unsigned char skip_ofst; 460 unsigned char skip_len; 461 unsigned char invert; 462 unsigned char port; 463 }; 464 465 /* Firmware Port Capabilities types. */ 466 467 typedef u16 fw_port_cap16_t; /* 16-bit Port Capabilities integral value */ 468 typedef u32 fw_port_cap32_t; /* 32-bit Port Capabilities integral value */ 469 470 enum fw_caps { 471 FW_CAPS_UNKNOWN = 0, /* 0'ed out initial state */ 472 FW_CAPS16 = 1, /* old Firmware: 16-bit Port Capabilities */ 473 FW_CAPS32 = 2, /* new Firmware: 32-bit Port Capabilities */ 474 }; 475 476 struct link_config { 477 fw_port_cap32_t pcaps; /* link capabilities */ 478 fw_port_cap32_t def_acaps; /* default advertised capabilities */ 479 fw_port_cap32_t acaps; /* advertised capabilities */ 480 fw_port_cap32_t lpacaps; /* peer advertised capabilities */ 481 482 fw_port_cap32_t speed_caps; /* speed(s) user has requested */ 483 unsigned int speed; /* actual link speed (Mb/s) */ 484 485 enum cc_pause requested_fc; /* flow control user has requested */ 486 enum cc_pause fc; /* actual link flow control */ 487 488 enum cc_fec requested_fec; /* Forward Error Correction: */ 489 enum cc_fec fec; /* requested and actual in use */ 490 491 unsigned char autoneg; /* autonegotiating? */ 492 493 unsigned char link_ok; /* link up? */ 494 unsigned char link_down_rc; /* link down reason */ 495 496 bool new_module; /* ->OS Transceiver Module inserted */ 497 bool redo_l1cfg; /* ->CC redo current "sticky" L1 CFG */ 498 }; 499 500 #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16) 501 502 enum { 503 MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */ 504 MAX_OFLD_QSETS = 16, /* # of offload Tx, iscsi Rx queue sets */ 505 MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */ 506 }; 507 508 enum { 509 MAX_TXQ_ENTRIES = 16384, 510 MAX_CTRL_TXQ_ENTRIES = 1024, 511 MAX_RSPQ_ENTRIES = 16384, 512 MAX_RX_BUFFERS = 16384, 513 MIN_TXQ_ENTRIES = 32, 514 MIN_CTRL_TXQ_ENTRIES = 32, 515 MIN_RSPQ_ENTRIES = 128, 516 MIN_FL_ENTRIES = 16 517 }; 518 519 enum { 520 INGQ_EXTRAS = 2, /* firmware event queue and */ 521 /* forwarded interrupts */ 522 MAX_INGQ = MAX_ETH_QSETS + INGQ_EXTRAS, 523 }; 524 525 struct adapter; 526 struct sge_rspq; 527 528 #include "cxgb4_dcb.h" 529 530 #ifdef CONFIG_CHELSIO_T4_FCOE 531 #include "cxgb4_fcoe.h" 532 #endif /* CONFIG_CHELSIO_T4_FCOE */ 533 534 struct port_info { 535 struct adapter *adapter; 536 u16 viid; 537 s16 xact_addr_filt; /* index of exact MAC address filter */ 538 u16 rss_size; /* size of VI's RSS table slice */ 539 s8 mdio_addr; 540 enum fw_port_type port_type; 541 u8 mod_type; 542 u8 port_id; 543 u8 tx_chan; 544 u8 lport; /* associated offload logical port */ 545 u8 nqsets; /* # of qsets */ 546 u8 first_qset; /* index of first qset */ 547 u8 rss_mode; 548 struct link_config link_cfg; 549 u16 *rss; 550 struct port_stats stats_base; 551 #ifdef CONFIG_CHELSIO_T4_DCB 552 struct port_dcb_info dcb; /* Data Center Bridging support */ 553 #endif 554 #ifdef CONFIG_CHELSIO_T4_FCOE 555 struct cxgb_fcoe fcoe; 556 #endif /* CONFIG_CHELSIO_T4_FCOE */ 557 bool rxtstamp; /* Enable TS */ 558 struct hwtstamp_config tstamp_config; 559 bool ptp_enable; 560 struct sched_table *sched_tbl; 561 }; 562 563 struct dentry; 564 struct work_struct; 565 566 enum { /* adapter flags */ 567 FULL_INIT_DONE = (1 << 0), 568 DEV_ENABLED = (1 << 1), 569 USING_MSI = (1 << 2), 570 USING_MSIX = (1 << 3), 571 FW_OK = (1 << 4), 572 RSS_TNLALLLOOKUP = (1 << 5), 573 USING_SOFT_PARAMS = (1 << 6), 574 MASTER_PF = (1 << 7), 575 FW_OFLD_CONN = (1 << 9), 576 ROOT_NO_RELAXED_ORDERING = (1 << 10), 577 SHUTTING_DOWN = (1 << 11), 578 }; 579 580 enum { 581 ULP_CRYPTO_LOOKASIDE = 1 << 0, 582 ULP_CRYPTO_IPSEC_INLINE = 1 << 1, 583 }; 584 585 struct rx_sw_desc; 586 587 struct sge_fl { /* SGE free-buffer queue state */ 588 unsigned int avail; /* # of available Rx buffers */ 589 unsigned int pend_cred; /* new buffers since last FL DB ring */ 590 unsigned int cidx; /* consumer index */ 591 unsigned int pidx; /* producer index */ 592 unsigned long alloc_failed; /* # of times buffer allocation failed */ 593 unsigned long large_alloc_failed; 594 unsigned long mapping_err; /* # of RX Buffer DMA Mapping failures */ 595 unsigned long low; /* # of times momentarily starving */ 596 unsigned long starving; 597 /* RO fields */ 598 unsigned int cntxt_id; /* SGE context id for the free list */ 599 unsigned int size; /* capacity of free list */ 600 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */ 601 __be64 *desc; /* address of HW Rx descriptor ring */ 602 dma_addr_t addr; /* bus address of HW ring start */ 603 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 604 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 605 }; 606 607 /* A packet gather list */ 608 struct pkt_gl { 609 u64 sgetstamp; /* SGE Time Stamp for Ingress Packet */ 610 struct page_frag frags[MAX_SKB_FRAGS]; 611 void *va; /* virtual address of first byte */ 612 unsigned int nfrags; /* # of fragments */ 613 unsigned int tot_len; /* total length of fragments */ 614 }; 615 616 typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp, 617 const struct pkt_gl *gl); 618 typedef void (*rspq_flush_handler_t)(struct sge_rspq *q); 619 /* LRO related declarations for ULD */ 620 struct t4_lro_mgr { 621 #define MAX_LRO_SESSIONS 64 622 u8 lro_session_cnt; /* # of sessions to aggregate */ 623 unsigned long lro_pkts; /* # of LRO super packets */ 624 unsigned long lro_merged; /* # of wire packets merged by LRO */ 625 struct sk_buff_head lroq; /* list of aggregated sessions */ 626 }; 627 628 struct sge_rspq { /* state for an SGE response queue */ 629 struct napi_struct napi; 630 const __be64 *cur_desc; /* current descriptor in queue */ 631 unsigned int cidx; /* consumer index */ 632 u8 gen; /* current generation bit */ 633 u8 intr_params; /* interrupt holdoff parameters */ 634 u8 next_intr_params; /* holdoff params for next interrupt */ 635 u8 adaptive_rx; 636 u8 pktcnt_idx; /* interrupt packet threshold */ 637 u8 uld; /* ULD handling this queue */ 638 u8 idx; /* queue index within its group */ 639 int offset; /* offset into current Rx buffer */ 640 u16 cntxt_id; /* SGE context id for the response q */ 641 u16 abs_id; /* absolute SGE id for the response q */ 642 __be64 *desc; /* address of HW response ring */ 643 dma_addr_t phys_addr; /* physical address of the ring */ 644 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 645 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 646 unsigned int iqe_len; /* entry size */ 647 unsigned int size; /* capacity of response queue */ 648 struct adapter *adap; 649 struct net_device *netdev; /* associated net device */ 650 rspq_handler_t handler; 651 rspq_flush_handler_t flush_handler; 652 struct t4_lro_mgr lro_mgr; 653 }; 654 655 struct sge_eth_stats { /* Ethernet queue statistics */ 656 unsigned long pkts; /* # of ethernet packets */ 657 unsigned long lro_pkts; /* # of LRO super packets */ 658 unsigned long lro_merged; /* # of wire packets merged by LRO */ 659 unsigned long rx_cso; /* # of Rx checksum offloads */ 660 unsigned long vlan_ex; /* # of Rx VLAN extractions */ 661 unsigned long rx_drops; /* # of packets dropped due to no mem */ 662 }; 663 664 struct sge_eth_rxq { /* SW Ethernet Rx queue */ 665 struct sge_rspq rspq; 666 struct sge_fl fl; 667 struct sge_eth_stats stats; 668 } ____cacheline_aligned_in_smp; 669 670 struct sge_ofld_stats { /* offload queue statistics */ 671 unsigned long pkts; /* # of packets */ 672 unsigned long imm; /* # of immediate-data packets */ 673 unsigned long an; /* # of asynchronous notifications */ 674 unsigned long nomem; /* # of responses deferred due to no mem */ 675 }; 676 677 struct sge_ofld_rxq { /* SW offload Rx queue */ 678 struct sge_rspq rspq; 679 struct sge_fl fl; 680 struct sge_ofld_stats stats; 681 } ____cacheline_aligned_in_smp; 682 683 struct tx_desc { 684 __be64 flit[8]; 685 }; 686 687 struct tx_sw_desc; 688 689 struct sge_txq { 690 unsigned int in_use; /* # of in-use Tx descriptors */ 691 unsigned int q_type; /* Q type Eth/Ctrl/Ofld */ 692 unsigned int size; /* # of descriptors */ 693 unsigned int cidx; /* SW consumer index */ 694 unsigned int pidx; /* producer index */ 695 unsigned long stops; /* # of times q has been stopped */ 696 unsigned long restarts; /* # of queue restarts */ 697 unsigned int cntxt_id; /* SGE context id for the Tx q */ 698 struct tx_desc *desc; /* address of HW Tx descriptor ring */ 699 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */ 700 struct sge_qstat *stat; /* queue status entry */ 701 dma_addr_t phys_addr; /* physical address of the ring */ 702 spinlock_t db_lock; 703 int db_disabled; 704 unsigned short db_pidx; 705 unsigned short db_pidx_inc; 706 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 707 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 708 }; 709 710 struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */ 711 struct sge_txq q; 712 struct netdev_queue *txq; /* associated netdev TX queue */ 713 #ifdef CONFIG_CHELSIO_T4_DCB 714 u8 dcb_prio; /* DCB Priority bound to queue */ 715 #endif 716 unsigned long tso; /* # of TSO requests */ 717 unsigned long tx_cso; /* # of Tx checksum offloads */ 718 unsigned long vlan_ins; /* # of Tx VLAN insertions */ 719 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 720 } ____cacheline_aligned_in_smp; 721 722 struct sge_uld_txq { /* state for an SGE offload Tx queue */ 723 struct sge_txq q; 724 struct adapter *adap; 725 struct sk_buff_head sendq; /* list of backpressured packets */ 726 struct tasklet_struct qresume_tsk; /* restarts the queue */ 727 bool service_ofldq_running; /* service_ofldq() is processing sendq */ 728 u8 full; /* the Tx ring is full */ 729 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 730 } ____cacheline_aligned_in_smp; 731 732 struct sge_ctrl_txq { /* state for an SGE control Tx queue */ 733 struct sge_txq q; 734 struct adapter *adap; 735 struct sk_buff_head sendq; /* list of backpressured packets */ 736 struct tasklet_struct qresume_tsk; /* restarts the queue */ 737 u8 full; /* the Tx ring is full */ 738 } ____cacheline_aligned_in_smp; 739 740 struct sge_uld_rxq_info { 741 char name[IFNAMSIZ]; /* name of ULD driver */ 742 struct sge_ofld_rxq *uldrxq; /* Rxq's for ULD */ 743 u16 *msix_tbl; /* msix_tbl for uld */ 744 u16 *rspq_id; /* response queue id's of rxq */ 745 u16 nrxq; /* # of ingress uld queues */ 746 u16 nciq; /* # of completion queues */ 747 u8 uld; /* uld type */ 748 }; 749 750 struct sge_uld_txq_info { 751 struct sge_uld_txq *uldtxq; /* Txq's for ULD */ 752 atomic_t users; /* num users */ 753 u16 ntxq; /* # of egress uld queues */ 754 }; 755 756 struct sge { 757 struct sge_eth_txq ethtxq[MAX_ETH_QSETS]; 758 struct sge_eth_txq ptptxq; 759 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES]; 760 761 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS]; 762 struct sge_rspq fw_evtq ____cacheline_aligned_in_smp; 763 struct sge_uld_rxq_info **uld_rxq_info; 764 struct sge_uld_txq_info **uld_txq_info; 765 766 struct sge_rspq intrq ____cacheline_aligned_in_smp; 767 spinlock_t intrq_lock; 768 769 u16 max_ethqsets; /* # of available Ethernet queue sets */ 770 u16 ethqsets; /* # of active Ethernet queue sets */ 771 u16 ethtxq_rover; /* Tx queue to clean up next */ 772 u16 ofldqsets; /* # of active ofld queue sets */ 773 u16 nqs_per_uld; /* # of Rx queues per ULD */ 774 u16 timer_val[SGE_NTIMERS]; 775 u8 counter_val[SGE_NCOUNTERS]; 776 u32 fl_pg_order; /* large page allocation size */ 777 u32 stat_len; /* length of status page at ring end */ 778 u32 pktshift; /* padding between CPL & packet data */ 779 u32 fl_align; /* response queue message alignment */ 780 u32 fl_starve_thres; /* Free List starvation threshold */ 781 782 struct sge_idma_monitor_state idma_monitor; 783 unsigned int egr_start; 784 unsigned int egr_sz; 785 unsigned int ingr_start; 786 unsigned int ingr_sz; 787 void **egr_map; /* qid->queue egress queue map */ 788 struct sge_rspq **ingr_map; /* qid->queue ingress queue map */ 789 unsigned long *starving_fl; 790 unsigned long *txq_maperr; 791 unsigned long *blocked_fl; 792 struct timer_list rx_timer; /* refills starving FLs */ 793 struct timer_list tx_timer; /* checks Tx queues */ 794 }; 795 796 #define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++) 797 #define for_each_ofldtxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++) 798 799 struct l2t_data; 800 801 #ifdef CONFIG_PCI_IOV 802 803 /* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial 804 * Configuration initialization for T5 only has SR-IOV functionality enabled 805 * on PF0-3 in order to simplify everything. 806 */ 807 #define NUM_OF_PF_WITH_SRIOV 4 808 809 #endif 810 811 struct doorbell_stats { 812 u32 db_drop; 813 u32 db_empty; 814 u32 db_full; 815 }; 816 817 struct hash_mac_addr { 818 struct list_head list; 819 u8 addr[ETH_ALEN]; 820 }; 821 822 struct uld_msix_bmap { 823 unsigned long *msix_bmap; 824 unsigned int mapsize; 825 spinlock_t lock; /* lock for acquiring bitmap */ 826 }; 827 828 struct uld_msix_info { 829 unsigned short vec; 830 char desc[IFNAMSIZ + 10]; 831 unsigned int idx; 832 }; 833 834 struct vf_info { 835 unsigned char vf_mac_addr[ETH_ALEN]; 836 unsigned int tx_rate; 837 bool pf_set_mac; 838 u16 vlan; 839 }; 840 841 enum { 842 HMA_DMA_MAPPED_FLAG = 1 843 }; 844 845 struct hma_data { 846 unsigned char flags; 847 struct sg_table *sgt; 848 dma_addr_t *phy_addr; /* physical address of the page */ 849 }; 850 851 struct mbox_list { 852 struct list_head list; 853 }; 854 855 struct mps_encap_entry { 856 atomic_t refcnt; 857 }; 858 859 struct adapter { 860 void __iomem *regs; 861 void __iomem *bar2; 862 u32 t4_bar0; 863 struct pci_dev *pdev; 864 struct device *pdev_dev; 865 const char *name; 866 unsigned int mbox; 867 unsigned int pf; 868 unsigned int flags; 869 unsigned int adap_idx; 870 enum chip_type chip; 871 872 int msg_enable; 873 __be16 vxlan_port; 874 u8 vxlan_port_cnt; 875 __be16 geneve_port; 876 u8 geneve_port_cnt; 877 878 struct adapter_params params; 879 struct cxgb4_virt_res vres; 880 unsigned int swintr; 881 882 struct { 883 unsigned short vec; 884 char desc[IFNAMSIZ + 10]; 885 } msix_info[MAX_INGQ + 1]; 886 struct uld_msix_info *msix_info_ulds; /* msix info for uld's */ 887 struct uld_msix_bmap msix_bmap_ulds; /* msix bitmap for all uld */ 888 int msi_idx; 889 890 struct doorbell_stats db_stats; 891 struct sge sge; 892 893 struct net_device *port[MAX_NPORTS]; 894 u8 chan_map[NCHAN]; /* channel -> port map */ 895 896 struct vf_info *vfinfo; 897 u8 num_vfs; 898 899 u32 filter_mode; 900 unsigned int l2t_start; 901 unsigned int l2t_end; 902 struct l2t_data *l2t; 903 unsigned int clipt_start; 904 unsigned int clipt_end; 905 struct clip_tbl *clipt; 906 unsigned int rawf_start; 907 unsigned int rawf_cnt; 908 struct smt_data *smt; 909 struct mps_encap_entry *mps_encap; 910 struct cxgb4_uld_info *uld; 911 void *uld_handle[CXGB4_ULD_MAX]; 912 unsigned int num_uld; 913 unsigned int num_ofld_uld; 914 struct list_head list_node; 915 struct list_head rcu_node; 916 struct list_head mac_hlist; /* list of MAC addresses in MPS Hash */ 917 918 void *iscsi_ppm; 919 920 struct tid_info tids; 921 void **tid_release_head; 922 spinlock_t tid_release_lock; 923 struct workqueue_struct *workq; 924 struct work_struct tid_release_task; 925 struct work_struct db_full_task; 926 struct work_struct db_drop_task; 927 struct work_struct fatal_err_notify_task; 928 bool tid_release_task_busy; 929 930 /* lock for mailbox cmd list */ 931 spinlock_t mbox_lock; 932 struct mbox_list mlist; 933 934 /* support for mailbox command/reply logging */ 935 #define T4_OS_LOG_MBOX_CMDS 256 936 struct mbox_cmd_log *mbox_log; 937 938 struct mutex uld_mutex; 939 940 struct dentry *debugfs_root; 941 bool use_bd; /* Use SGE Back Door intfc for reading SGE Contexts */ 942 bool trace_rss; /* 1 implies that different RSS flit per filter is 943 * used per filter else if 0 default RSS flit is 944 * used for all 4 filters. 945 */ 946 947 struct ptp_clock *ptp_clock; 948 struct ptp_clock_info ptp_clock_info; 949 struct sk_buff *ptp_tx_skb; 950 /* ptp lock */ 951 spinlock_t ptp_lock; 952 spinlock_t stats_lock; 953 spinlock_t win0_lock ____cacheline_aligned_in_smp; 954 955 /* TC u32 offload */ 956 struct cxgb4_tc_u32_table *tc_u32; 957 struct chcr_stats_debug chcr_stats; 958 959 /* TC flower offload */ 960 struct rhashtable flower_tbl; 961 struct rhashtable_params flower_ht_params; 962 struct timer_list flower_stats_timer; 963 struct work_struct flower_stats_work; 964 965 /* Ethtool Dump */ 966 struct ethtool_dump eth_dump; 967 968 /* HMA */ 969 struct hma_data hma; 970 971 struct srq_data *srq; 972 973 /* Dump buffer for collecting logs in kdump kernel */ 974 struct vmcoredd_data vmcoredd; 975 }; 976 977 /* Support for "sched-class" command to allow a TX Scheduling Class to be 978 * programmed with various parameters. 979 */ 980 struct ch_sched_params { 981 s8 type; /* packet or flow */ 982 union { 983 struct { 984 s8 level; /* scheduler hierarchy level */ 985 s8 mode; /* per-class or per-flow */ 986 s8 rateunit; /* bit or packet rate */ 987 s8 ratemode; /* %port relative or kbps absolute */ 988 s8 channel; /* scheduler channel [0..N] */ 989 s8 class; /* scheduler class [0..N] */ 990 s32 minrate; /* minimum rate */ 991 s32 maxrate; /* maximum rate */ 992 s16 weight; /* percent weight */ 993 s16 pktsize; /* average packet size */ 994 } params; 995 } u; 996 }; 997 998 enum { 999 SCHED_CLASS_TYPE_PACKET = 0, /* class type */ 1000 }; 1001 1002 enum { 1003 SCHED_CLASS_LEVEL_CL_RL = 0, /* class rate limiter */ 1004 }; 1005 1006 enum { 1007 SCHED_CLASS_MODE_CLASS = 0, /* per-class scheduling */ 1008 }; 1009 1010 enum { 1011 SCHED_CLASS_RATEUNIT_BITS = 0, /* bit rate scheduling */ 1012 }; 1013 1014 enum { 1015 SCHED_CLASS_RATEMODE_ABS = 1, /* Kb/s */ 1016 }; 1017 1018 struct tx_sw_desc { /* SW state per Tx descriptor */ 1019 struct sk_buff *skb; 1020 struct ulptx_sgl *sgl; 1021 }; 1022 1023 /* Support for "sched_queue" command to allow one or more NIC TX Queues 1024 * to be bound to a TX Scheduling Class. 1025 */ 1026 struct ch_sched_queue { 1027 s8 queue; /* queue index */ 1028 s8 class; /* class index */ 1029 }; 1030 1031 /* Defined bit width of user definable filter tuples 1032 */ 1033 #define ETHTYPE_BITWIDTH 16 1034 #define FRAG_BITWIDTH 1 1035 #define MACIDX_BITWIDTH 9 1036 #define FCOE_BITWIDTH 1 1037 #define IPORT_BITWIDTH 3 1038 #define MATCHTYPE_BITWIDTH 3 1039 #define PROTO_BITWIDTH 8 1040 #define TOS_BITWIDTH 8 1041 #define PF_BITWIDTH 8 1042 #define VF_BITWIDTH 8 1043 #define IVLAN_BITWIDTH 16 1044 #define OVLAN_BITWIDTH 16 1045 #define ENCAP_VNI_BITWIDTH 24 1046 1047 /* Filter matching rules. These consist of a set of ingress packet field 1048 * (value, mask) tuples. The associated ingress packet field matches the 1049 * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field 1050 * rule can be constructed by specifying a tuple of (0, 0).) A filter rule 1051 * matches an ingress packet when all of the individual individual field 1052 * matching rules are true. 1053 * 1054 * Partial field masks are always valid, however, while it may be easy to 1055 * understand their meanings for some fields (e.g. IP address to match a 1056 * subnet), for others making sensible partial masks is less intuitive (e.g. 1057 * MPS match type) ... 1058 * 1059 * Most of the following data structures are modeled on T4 capabilities. 1060 * Drivers for earlier chips use the subsets which make sense for those chips. 1061 * We really need to come up with a hardware-independent mechanism to 1062 * represent hardware filter capabilities ... 1063 */ 1064 struct ch_filter_tuple { 1065 /* Compressed header matching field rules. The TP_VLAN_PRI_MAP 1066 * register selects which of these fields will participate in the 1067 * filter match rules -- up to a maximum of 36 bits. Because 1068 * TP_VLAN_PRI_MAP is a global register, all filters must use the same 1069 * set of fields. 1070 */ 1071 uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */ 1072 uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */ 1073 uint32_t ivlan_vld:1; /* inner VLAN valid */ 1074 uint32_t ovlan_vld:1; /* outer VLAN valid */ 1075 uint32_t pfvf_vld:1; /* PF/VF valid */ 1076 uint32_t encap_vld:1; /* Encapsulation valid */ 1077 uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */ 1078 uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */ 1079 uint32_t iport:IPORT_BITWIDTH; /* ingress port */ 1080 uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */ 1081 uint32_t proto:PROTO_BITWIDTH; /* protocol type */ 1082 uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */ 1083 uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */ 1084 uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */ 1085 uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */ 1086 uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */ 1087 uint32_t vni:ENCAP_VNI_BITWIDTH; /* VNI of tunnel */ 1088 1089 /* Uncompressed header matching field rules. These are always 1090 * available for field rules. 1091 */ 1092 uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */ 1093 uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */ 1094 uint16_t lport; /* local port */ 1095 uint16_t fport; /* foreign port */ 1096 }; 1097 1098 /* A filter ioctl command. 1099 */ 1100 struct ch_filter_specification { 1101 /* Administrative fields for filter. 1102 */ 1103 uint32_t hitcnts:1; /* count filter hits in TCB */ 1104 uint32_t prio:1; /* filter has priority over active/server */ 1105 1106 /* Fundamental filter typing. This is the one element of filter 1107 * matching that doesn't exist as a (value, mask) tuple. 1108 */ 1109 uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */ 1110 u32 hash:1; /* 0 => wild-card, 1 => exact-match */ 1111 1112 /* Packet dispatch information. Ingress packets which match the 1113 * filter rules will be dropped, passed to the host or switched back 1114 * out as egress packets. 1115 */ 1116 uint32_t action:2; /* drop, pass, switch */ 1117 1118 uint32_t rpttid:1; /* report TID in RSS hash field */ 1119 1120 uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */ 1121 uint32_t iq:10; /* ingress queue */ 1122 1123 uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */ 1124 uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */ 1125 /* 1 => TCB contains IQ ID */ 1126 1127 /* Switch proxy/rewrite fields. An ingress packet which matches a 1128 * filter with "switch" set will be looped back out as an egress 1129 * packet -- potentially with some Ethernet header rewriting. 1130 */ 1131 uint32_t eport:2; /* egress port to switch packet out */ 1132 uint32_t newdmac:1; /* rewrite destination MAC address */ 1133 uint32_t newsmac:1; /* rewrite source MAC address */ 1134 uint32_t newvlan:2; /* rewrite VLAN Tag */ 1135 uint32_t nat_mode:3; /* specify NAT operation mode */ 1136 uint8_t dmac[ETH_ALEN]; /* new destination MAC address */ 1137 uint8_t smac[ETH_ALEN]; /* new source MAC address */ 1138 uint16_t vlan; /* VLAN Tag to insert */ 1139 1140 u8 nat_lip[16]; /* local IP to use after NAT'ing */ 1141 u8 nat_fip[16]; /* foreign IP to use after NAT'ing */ 1142 u16 nat_lport; /* local port to use after NAT'ing */ 1143 u16 nat_fport; /* foreign port to use after NAT'ing */ 1144 1145 /* reservation for future additions */ 1146 u8 rsvd[24]; 1147 1148 /* Filter rule value/mask pairs. 1149 */ 1150 struct ch_filter_tuple val; 1151 struct ch_filter_tuple mask; 1152 }; 1153 1154 enum { 1155 FILTER_PASS = 0, /* default */ 1156 FILTER_DROP, 1157 FILTER_SWITCH 1158 }; 1159 1160 enum { 1161 VLAN_NOCHANGE = 0, /* default */ 1162 VLAN_REMOVE, 1163 VLAN_INSERT, 1164 VLAN_REWRITE 1165 }; 1166 1167 enum { 1168 NAT_MODE_NONE = 0, /* No NAT performed */ 1169 NAT_MODE_DIP, /* NAT on Dst IP */ 1170 NAT_MODE_DIP_DP, /* NAT on Dst IP, Dst Port */ 1171 NAT_MODE_DIP_DP_SIP, /* NAT on Dst IP, Dst Port and Src IP */ 1172 NAT_MODE_DIP_DP_SP, /* NAT on Dst IP, Dst Port and Src Port */ 1173 NAT_MODE_SIP_SP, /* NAT on Src IP and Src Port */ 1174 NAT_MODE_DIP_SIP_SP, /* NAT on Dst IP, Src IP and Src Port */ 1175 NAT_MODE_ALL /* NAT on entire 4-tuple */ 1176 }; 1177 1178 /* Host shadow copy of ingress filter entry. This is in host native format 1179 * and doesn't match the ordering or bit order, etc. of the hardware of the 1180 * firmware command. The use of bit-field structure elements is purely to 1181 * remind ourselves of the field size limitations and save memory in the case 1182 * where the filter table is large. 1183 */ 1184 struct filter_entry { 1185 /* Administrative fields for filter. */ 1186 u32 valid:1; /* filter allocated and valid */ 1187 u32 locked:1; /* filter is administratively locked */ 1188 1189 u32 pending:1; /* filter action is pending firmware reply */ 1190 struct filter_ctx *ctx; /* Caller's completion hook */ 1191 struct l2t_entry *l2t; /* Layer Two Table entry for dmac */ 1192 struct smt_entry *smt; /* Source Mac Table entry for smac */ 1193 struct net_device *dev; /* Associated net device */ 1194 u32 tid; /* This will store the actual tid */ 1195 1196 /* The filter itself. Most of this is a straight copy of information 1197 * provided by the extended ioctl(). Some fields are translated to 1198 * internal forms -- for instance the Ingress Queue ID passed in from 1199 * the ioctl() is translated into the Absolute Ingress Queue ID. 1200 */ 1201 struct ch_filter_specification fs; 1202 }; 1203 1204 static inline int is_offload(const struct adapter *adap) 1205 { 1206 return adap->params.offload; 1207 } 1208 1209 static inline int is_hashfilter(const struct adapter *adap) 1210 { 1211 return adap->params.hash_filter; 1212 } 1213 1214 static inline int is_pci_uld(const struct adapter *adap) 1215 { 1216 return adap->params.crypto; 1217 } 1218 1219 static inline int is_uld(const struct adapter *adap) 1220 { 1221 return (adap->params.offload || adap->params.crypto); 1222 } 1223 1224 static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr) 1225 { 1226 return readl(adap->regs + reg_addr); 1227 } 1228 1229 static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val) 1230 { 1231 writel(val, adap->regs + reg_addr); 1232 } 1233 1234 #ifndef readq 1235 static inline u64 readq(const volatile void __iomem *addr) 1236 { 1237 return readl(addr) + ((u64)readl(addr + 4) << 32); 1238 } 1239 1240 static inline void writeq(u64 val, volatile void __iomem *addr) 1241 { 1242 writel(val, addr); 1243 writel(val >> 32, addr + 4); 1244 } 1245 #endif 1246 1247 static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr) 1248 { 1249 return readq(adap->regs + reg_addr); 1250 } 1251 1252 static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val) 1253 { 1254 writeq(val, adap->regs + reg_addr); 1255 } 1256 1257 /** 1258 * t4_set_hw_addr - store a port's MAC address in SW 1259 * @adapter: the adapter 1260 * @port_idx: the port index 1261 * @hw_addr: the Ethernet address 1262 * 1263 * Store the Ethernet address of the given port in SW. Called by the common 1264 * code when it retrieves a port's Ethernet address from EEPROM. 1265 */ 1266 static inline void t4_set_hw_addr(struct adapter *adapter, int port_idx, 1267 u8 hw_addr[]) 1268 { 1269 ether_addr_copy(adapter->port[port_idx]->dev_addr, hw_addr); 1270 ether_addr_copy(adapter->port[port_idx]->perm_addr, hw_addr); 1271 } 1272 1273 /** 1274 * netdev2pinfo - return the port_info structure associated with a net_device 1275 * @dev: the netdev 1276 * 1277 * Return the struct port_info associated with a net_device 1278 */ 1279 static inline struct port_info *netdev2pinfo(const struct net_device *dev) 1280 { 1281 return netdev_priv(dev); 1282 } 1283 1284 /** 1285 * adap2pinfo - return the port_info of a port 1286 * @adap: the adapter 1287 * @idx: the port index 1288 * 1289 * Return the port_info structure for the port of the given index. 1290 */ 1291 static inline struct port_info *adap2pinfo(struct adapter *adap, int idx) 1292 { 1293 return netdev_priv(adap->port[idx]); 1294 } 1295 1296 /** 1297 * netdev2adap - return the adapter structure associated with a net_device 1298 * @dev: the netdev 1299 * 1300 * Return the struct adapter associated with a net_device 1301 */ 1302 static inline struct adapter *netdev2adap(const struct net_device *dev) 1303 { 1304 return netdev2pinfo(dev)->adapter; 1305 } 1306 1307 /* Return a version number to identify the type of adapter. The scheme is: 1308 * - bits 0..9: chip version 1309 * - bits 10..15: chip revision 1310 * - bits 16..23: register dump version 1311 */ 1312 static inline unsigned int mk_adap_vers(struct adapter *ap) 1313 { 1314 return CHELSIO_CHIP_VERSION(ap->params.chip) | 1315 (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16); 1316 } 1317 1318 /* Return a queue's interrupt hold-off time in us. 0 means no timer. */ 1319 static inline unsigned int qtimer_val(const struct adapter *adap, 1320 const struct sge_rspq *q) 1321 { 1322 unsigned int idx = q->intr_params >> 1; 1323 1324 return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0; 1325 } 1326 1327 /* driver version & name used for ethtool_drvinfo */ 1328 extern char cxgb4_driver_name[]; 1329 extern const char cxgb4_driver_version[]; 1330 1331 void t4_os_portmod_changed(struct adapter *adap, int port_id); 1332 void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat); 1333 1334 void t4_free_sge_resources(struct adapter *adap); 1335 void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q); 1336 irq_handler_t t4_intr_handler(struct adapter *adap); 1337 netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev); 1338 int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp, 1339 const struct pkt_gl *gl); 1340 int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb); 1341 int t4_ofld_send(struct adapter *adap, struct sk_buff *skb); 1342 int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, 1343 struct net_device *dev, int intr_idx, 1344 struct sge_fl *fl, rspq_handler_t hnd, 1345 rspq_flush_handler_t flush_handler, int cong); 1346 int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq, 1347 struct net_device *dev, struct netdev_queue *netdevq, 1348 unsigned int iqid); 1349 int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq, 1350 struct net_device *dev, unsigned int iqid, 1351 unsigned int cmplqid); 1352 int t4_sge_mod_ctrl_txq(struct adapter *adap, unsigned int eqid, 1353 unsigned int cmplqid); 1354 int t4_sge_alloc_uld_txq(struct adapter *adap, struct sge_uld_txq *txq, 1355 struct net_device *dev, unsigned int iqid, 1356 unsigned int uld_type); 1357 irqreturn_t t4_sge_intr_msix(int irq, void *cookie); 1358 int t4_sge_init(struct adapter *adap); 1359 void t4_sge_start(struct adapter *adap); 1360 void t4_sge_stop(struct adapter *adap); 1361 void cxgb4_set_ethtool_ops(struct net_device *netdev); 1362 int cxgb4_write_rss(const struct port_info *pi, const u16 *queues); 1363 enum cpl_tx_tnl_lso_type cxgb_encap_offload_supported(struct sk_buff *skb); 1364 extern int dbfifo_int_thresh; 1365 1366 #define for_each_port(adapter, iter) \ 1367 for (iter = 0; iter < (adapter)->params.nports; ++iter) 1368 1369 static inline int is_bypass(struct adapter *adap) 1370 { 1371 return adap->params.bypass; 1372 } 1373 1374 static inline int is_bypass_device(int device) 1375 { 1376 /* this should be set based upon device capabilities */ 1377 switch (device) { 1378 case 0x440b: 1379 case 0x440c: 1380 return 1; 1381 default: 1382 return 0; 1383 } 1384 } 1385 1386 static inline int is_10gbt_device(int device) 1387 { 1388 /* this should be set based upon device capabilities */ 1389 switch (device) { 1390 case 0x4409: 1391 case 0x4486: 1392 return 1; 1393 1394 default: 1395 return 0; 1396 } 1397 } 1398 1399 static inline unsigned int core_ticks_per_usec(const struct adapter *adap) 1400 { 1401 return adap->params.vpd.cclk / 1000; 1402 } 1403 1404 static inline unsigned int us_to_core_ticks(const struct adapter *adap, 1405 unsigned int us) 1406 { 1407 return (us * adap->params.vpd.cclk) / 1000; 1408 } 1409 1410 static inline unsigned int core_ticks_to_us(const struct adapter *adapter, 1411 unsigned int ticks) 1412 { 1413 /* add Core Clock / 2 to round ticks to nearest uS */ 1414 return ((ticks * 1000 + adapter->params.vpd.cclk/2) / 1415 adapter->params.vpd.cclk); 1416 } 1417 1418 static inline unsigned int dack_ticks_to_usec(const struct adapter *adap, 1419 unsigned int ticks) 1420 { 1421 return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap); 1422 } 1423 1424 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, 1425 u32 val); 1426 1427 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 1428 int size, void *rpl, bool sleep_ok, int timeout); 1429 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 1430 void *rpl, bool sleep_ok); 1431 1432 static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox, 1433 const void *cmd, int size, void *rpl, 1434 int timeout) 1435 { 1436 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true, 1437 timeout); 1438 } 1439 1440 static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, 1441 int size, void *rpl) 1442 { 1443 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true); 1444 } 1445 1446 static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, 1447 int size, void *rpl) 1448 { 1449 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false); 1450 } 1451 1452 /** 1453 * hash_mac_addr - return the hash value of a MAC address 1454 * @addr: the 48-bit Ethernet MAC address 1455 * 1456 * Hashes a MAC address according to the hash function used by HW inexact 1457 * (hash) address matching. 1458 */ 1459 static inline int hash_mac_addr(const u8 *addr) 1460 { 1461 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2]; 1462 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5]; 1463 1464 a ^= b; 1465 a ^= (a >> 12); 1466 a ^= (a >> 6); 1467 return a & 0x3f; 1468 } 1469 1470 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us, 1471 unsigned int cnt); 1472 static inline void init_rspq(struct adapter *adap, struct sge_rspq *q, 1473 unsigned int us, unsigned int cnt, 1474 unsigned int size, unsigned int iqe_size) 1475 { 1476 q->adap = adap; 1477 cxgb4_set_rspq_intr_params(q, us, cnt); 1478 q->iqe_len = iqe_size; 1479 q->size = size; 1480 } 1481 1482 /** 1483 * t4_is_inserted_mod_type - is a plugged in Firmware Module Type 1484 * @fw_mod_type: the Firmware Mofule Type 1485 * 1486 * Return whether the Firmware Module Type represents a real Transceiver 1487 * Module/Cable Module Type which has been inserted. 1488 */ 1489 static inline bool t4_is_inserted_mod_type(unsigned int fw_mod_type) 1490 { 1491 return (fw_mod_type != FW_PORT_MOD_TYPE_NONE && 1492 fw_mod_type != FW_PORT_MOD_TYPE_NOTSUPPORTED && 1493 fw_mod_type != FW_PORT_MOD_TYPE_UNKNOWN && 1494 fw_mod_type != FW_PORT_MOD_TYPE_ERROR); 1495 } 1496 1497 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 1498 unsigned int data_reg, const u32 *vals, 1499 unsigned int nregs, unsigned int start_idx); 1500 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 1501 unsigned int data_reg, u32 *vals, unsigned int nregs, 1502 unsigned int start_idx); 1503 void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val); 1504 1505 struct fw_filter_wr; 1506 1507 void t4_intr_enable(struct adapter *adapter); 1508 void t4_intr_disable(struct adapter *adapter); 1509 int t4_slow_intr_handler(struct adapter *adapter); 1510 1511 int t4_wait_dev_ready(void __iomem *regs); 1512 1513 int t4_link_l1cfg_core(struct adapter *adap, unsigned int mbox, 1514 unsigned int port, struct link_config *lc, 1515 bool sleep_ok, int timeout); 1516 1517 static inline int t4_link_l1cfg(struct adapter *adapter, unsigned int mbox, 1518 unsigned int port, struct link_config *lc) 1519 { 1520 return t4_link_l1cfg_core(adapter, mbox, port, lc, 1521 true, FW_CMD_MAX_TIMEOUT); 1522 } 1523 1524 static inline int t4_link_l1cfg_ns(struct adapter *adapter, unsigned int mbox, 1525 unsigned int port, struct link_config *lc) 1526 { 1527 return t4_link_l1cfg_core(adapter, mbox, port, lc, 1528 false, FW_CMD_MAX_TIMEOUT); 1529 } 1530 1531 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port); 1532 1533 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg); 1534 u32 t4_get_util_window(struct adapter *adap); 1535 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window); 1536 1537 int t4_memory_rw_init(struct adapter *adap, int win, int mtype, u32 *mem_off, 1538 u32 *mem_base, u32 *mem_aperture); 1539 void t4_memory_update_win(struct adapter *adap, int win, u32 addr); 1540 void t4_memory_rw_residual(struct adapter *adap, u32 off, u32 addr, u8 *buf, 1541 int dir); 1542 #define T4_MEMORY_WRITE 0 1543 #define T4_MEMORY_READ 1 1544 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len, 1545 void *buf, int dir); 1546 static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr, 1547 u32 len, __be32 *buf) 1548 { 1549 return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0); 1550 } 1551 1552 unsigned int t4_get_regs_len(struct adapter *adapter); 1553 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size); 1554 1555 int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz); 1556 int t4_seeprom_wp(struct adapter *adapter, bool enable); 1557 int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p); 1558 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p); 1559 int t4_read_flash(struct adapter *adapter, unsigned int addr, 1560 unsigned int nwords, u32 *data, int byte_oriented); 1561 int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size); 1562 int t4_load_phy_fw(struct adapter *adap, 1563 int win, spinlock_t *lock, 1564 int (*phy_fw_version)(const u8 *, size_t), 1565 const u8 *phy_fw_data, size_t phy_fw_size); 1566 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver); 1567 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op); 1568 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 1569 const u8 *fw_data, unsigned int size, int force); 1570 int t4_fl_pkt_align(struct adapter *adap); 1571 unsigned int t4_flash_cfg_addr(struct adapter *adapter); 1572 int t4_check_fw_version(struct adapter *adap); 1573 int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size); 1574 int t4_get_fw_version(struct adapter *adapter, u32 *vers); 1575 int t4_get_bs_version(struct adapter *adapter, u32 *vers); 1576 int t4_get_tp_version(struct adapter *adapter, u32 *vers); 1577 int t4_get_exprom_version(struct adapter *adapter, u32 *vers); 1578 int t4_get_scfg_version(struct adapter *adapter, u32 *vers); 1579 int t4_get_vpd_version(struct adapter *adapter, u32 *vers); 1580 int t4_get_version_info(struct adapter *adapter); 1581 void t4_dump_version_info(struct adapter *adapter); 1582 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info, 1583 const u8 *fw_data, unsigned int fw_size, 1584 struct fw_hdr *card_fw, enum dev_state state, int *reset); 1585 int t4_prep_adapter(struct adapter *adapter); 1586 int t4_shutdown_adapter(struct adapter *adapter); 1587 1588 enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS }; 1589 int t4_bar2_sge_qregs(struct adapter *adapter, 1590 unsigned int qid, 1591 enum t4_bar2_qtype qtype, 1592 int user, 1593 u64 *pbar2_qoffset, 1594 unsigned int *pbar2_qid); 1595 1596 unsigned int qtimer_val(const struct adapter *adap, 1597 const struct sge_rspq *q); 1598 1599 int t4_init_devlog_params(struct adapter *adapter); 1600 int t4_init_sge_params(struct adapter *adapter); 1601 int t4_init_tp_params(struct adapter *adap, bool sleep_ok); 1602 int t4_filter_field_shift(const struct adapter *adap, int filter_sel); 1603 int t4_init_rss_mode(struct adapter *adap, int mbox); 1604 int t4_init_portinfo(struct port_info *pi, int mbox, 1605 int port, int pf, int vf, u8 mac[]); 1606 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf); 1607 void t4_fatal_err(struct adapter *adapter); 1608 unsigned int t4_chip_rss_size(struct adapter *adapter); 1609 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 1610 int start, int n, const u16 *rspq, unsigned int nrspq); 1611 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 1612 unsigned int flags); 1613 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 1614 unsigned int flags, unsigned int defq); 1615 int t4_read_rss(struct adapter *adapter, u16 *entries); 1616 void t4_read_rss_key(struct adapter *adapter, u32 *key, bool sleep_ok); 1617 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx, 1618 bool sleep_ok); 1619 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, 1620 u32 *valp, bool sleep_ok); 1621 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 1622 u32 *vfl, u32 *vfh, bool sleep_ok); 1623 u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok); 1624 u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok); 1625 1626 unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx); 1627 unsigned int t4_get_tp_ch_map(struct adapter *adapter, int pidx); 1628 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1629 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1630 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, 1631 size_t n); 1632 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, 1633 size_t n); 1634 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 1635 unsigned int *valp); 1636 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 1637 const unsigned int *valp); 1638 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr); 1639 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, 1640 unsigned int *pif_req_wrptr, 1641 unsigned int *pif_rsp_wrptr); 1642 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp); 1643 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres); 1644 const char *t4_get_port_type_description(enum fw_port_type port_type); 1645 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); 1646 void t4_get_port_stats_offset(struct adapter *adap, int idx, 1647 struct port_stats *stats, 1648 struct port_stats *offset); 1649 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p); 1650 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); 1651 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]); 1652 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 1653 unsigned int mask, unsigned int val); 1654 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr); 1655 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st, 1656 bool sleep_ok); 1657 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st, 1658 bool sleep_ok); 1659 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st, 1660 bool sleep_ok); 1661 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st, 1662 bool sleep_ok); 1663 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 1664 struct tp_tcp_stats *v6, bool sleep_ok); 1665 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 1666 struct tp_fcoe_stats *st, bool sleep_ok); 1667 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 1668 const unsigned short *alpha, const unsigned short *beta); 1669 1670 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf); 1671 1672 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate); 1673 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid); 1674 1675 void t4_wol_magic_enable(struct adapter *adap, unsigned int port, 1676 const u8 *addr); 1677 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 1678 u64 mask0, u64 mask1, unsigned int crc, bool enable); 1679 1680 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 1681 enum dev_master master, enum dev_state *state); 1682 int t4_fw_bye(struct adapter *adap, unsigned int mbox); 1683 int t4_early_init(struct adapter *adap, unsigned int mbox); 1684 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); 1685 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, 1686 unsigned int cache_line_size); 1687 int t4_fw_initialize(struct adapter *adap, unsigned int mbox); 1688 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1689 unsigned int vf, unsigned int nparams, const u32 *params, 1690 u32 *val); 1691 int t4_query_params_ns(struct adapter *adap, unsigned int mbox, unsigned int pf, 1692 unsigned int vf, unsigned int nparams, const u32 *params, 1693 u32 *val); 1694 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, 1695 unsigned int vf, unsigned int nparams, const u32 *params, 1696 u32 *val, int rw, bool sleep_ok); 1697 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 1698 unsigned int pf, unsigned int vf, 1699 unsigned int nparams, const u32 *params, 1700 const u32 *val, int timeout); 1701 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1702 unsigned int vf, unsigned int nparams, const u32 *params, 1703 const u32 *val); 1704 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 1705 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 1706 unsigned int rxqi, unsigned int rxq, unsigned int tc, 1707 unsigned int vi, unsigned int cmask, unsigned int pmask, 1708 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps); 1709 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 1710 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 1711 unsigned int *rss_size); 1712 int t4_free_vi(struct adapter *adap, unsigned int mbox, 1713 unsigned int pf, unsigned int vf, 1714 unsigned int viid); 1715 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 1716 int mtu, int promisc, int all_multi, int bcast, int vlanex, 1717 bool sleep_ok); 1718 int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid, 1719 const u8 *addr, const u8 *mask, unsigned int idx, 1720 u8 lookup_type, u8 port_id, bool sleep_ok); 1721 int t4_free_encap_mac_filt(struct adapter *adap, unsigned int viid, int idx, 1722 bool sleep_ok); 1723 int t4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid, 1724 const u8 *addr, const u8 *mask, unsigned int vni, 1725 unsigned int vni_mask, u8 dip_hit, u8 lookup_type, 1726 bool sleep_ok); 1727 int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid, 1728 const u8 *addr, const u8 *mask, unsigned int idx, 1729 u8 lookup_type, u8 port_id, bool sleep_ok); 1730 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, 1731 unsigned int viid, bool free, unsigned int naddr, 1732 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok); 1733 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox, 1734 unsigned int viid, unsigned int naddr, 1735 const u8 **addr, bool sleep_ok); 1736 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 1737 int idx, const u8 *addr, bool persist, bool add_smt); 1738 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 1739 bool ucast, u64 vec, bool sleep_ok); 1740 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 1741 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en); 1742 int t4_enable_pi_params(struct adapter *adap, unsigned int mbox, 1743 struct port_info *pi, 1744 bool rx_en, bool tx_en, bool dcb_en); 1745 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 1746 bool rx_en, bool tx_en); 1747 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 1748 unsigned int nblinks); 1749 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1750 unsigned int mmd, unsigned int reg, u16 *valp); 1751 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1752 unsigned int mmd, unsigned int reg, u16 val); 1753 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, 1754 unsigned int vf, unsigned int iqtype, unsigned int iqid, 1755 unsigned int fl0id, unsigned int fl1id); 1756 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1757 unsigned int vf, unsigned int iqtype, unsigned int iqid, 1758 unsigned int fl0id, unsigned int fl1id); 1759 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1760 unsigned int vf, unsigned int eqid); 1761 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1762 unsigned int vf, unsigned int eqid); 1763 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1764 unsigned int vf, unsigned int eqid); 1765 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox, int ctxt_type); 1766 void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl); 1767 int t4_update_port_info(struct port_info *pi); 1768 int t4_get_link_params(struct port_info *pi, unsigned int *link_okp, 1769 unsigned int *speedp, unsigned int *mtup); 1770 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); 1771 void t4_db_full(struct adapter *adapter); 1772 void t4_db_dropped(struct adapter *adapter); 1773 int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp, 1774 int filter_index, int enable); 1775 void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp, 1776 int filter_index, int *enabled); 1777 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, 1778 u32 addr, u32 val); 1779 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]); 1780 void t4_get_tx_sched(struct adapter *adap, unsigned int sched, 1781 unsigned int *kbps, unsigned int *ipg, bool sleep_ok); 1782 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid, 1783 enum ctxt_type ctype, u32 *data); 1784 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, 1785 enum ctxt_type ctype, u32 *data); 1786 int t4_sched_params(struct adapter *adapter, int type, int level, int mode, 1787 int rateunit, int ratemode, int channel, int class, 1788 int minrate, int maxrate, int weight, int pktsize); 1789 void t4_sge_decode_idma_state(struct adapter *adapter, int state); 1790 void t4_idma_monitor_init(struct adapter *adapter, 1791 struct sge_idma_monitor_state *idma); 1792 void t4_idma_monitor(struct adapter *adapter, 1793 struct sge_idma_monitor_state *idma, 1794 int hz, int ticks); 1795 int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf, 1796 unsigned int naddr, u8 *addr); 1797 void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 1798 u32 start_index, bool sleep_ok); 1799 void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 1800 u32 start_index, bool sleep_ok); 1801 void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, 1802 u32 start_index, bool sleep_ok); 1803 1804 void t4_uld_mem_free(struct adapter *adap); 1805 int t4_uld_mem_alloc(struct adapter *adap); 1806 void t4_uld_clean_up(struct adapter *adap); 1807 void t4_register_netevent_notifier(void); 1808 int t4_i2c_rd(struct adapter *adap, unsigned int mbox, int port, 1809 unsigned int devid, unsigned int offset, 1810 unsigned int len, u8 *buf); 1811 void free_rspq_fl(struct adapter *adap, struct sge_rspq *rq, struct sge_fl *fl); 1812 void free_tx_desc(struct adapter *adap, struct sge_txq *q, 1813 unsigned int n, bool unmap); 1814 void free_txq(struct adapter *adap, struct sge_txq *q); 1815 void cxgb4_reclaim_completed_tx(struct adapter *adap, 1816 struct sge_txq *q, bool unmap); 1817 int cxgb4_map_skb(struct device *dev, const struct sk_buff *skb, 1818 dma_addr_t *addr); 1819 void cxgb4_inline_tx_skb(const struct sk_buff *skb, const struct sge_txq *q, 1820 void *pos); 1821 void cxgb4_write_sgl(const struct sk_buff *skb, struct sge_txq *q, 1822 struct ulptx_sgl *sgl, u64 *end, unsigned int start, 1823 const dma_addr_t *addr); 1824 void cxgb4_ring_tx_db(struct adapter *adap, struct sge_txq *q, int n); 1825 int t4_set_vlan_acl(struct adapter *adap, unsigned int mbox, unsigned int vf, 1826 u16 vlan); 1827 #endif /* __CXGB4_H__ */ 1828