1 /* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #ifndef __CXGB4_H__ 36 #define __CXGB4_H__ 37 38 #include "t4_hw.h" 39 40 #include <linux/bitops.h> 41 #include <linux/cache.h> 42 #include <linux/interrupt.h> 43 #include <linux/list.h> 44 #include <linux/netdevice.h> 45 #include <linux/pci.h> 46 #include <linux/spinlock.h> 47 #include <linux/timer.h> 48 #include <linux/vmalloc.h> 49 #include <linux/etherdevice.h> 50 #include <linux/net_tstamp.h> 51 #include <asm/io.h> 52 #include "t4_chip_type.h" 53 #include "cxgb4_uld.h" 54 55 #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__) 56 57 enum { 58 MAX_NPORTS = 4, /* max # of ports */ 59 SERNUM_LEN = 24, /* Serial # length */ 60 EC_LEN = 16, /* E/C length */ 61 ID_LEN = 16, /* ID length */ 62 PN_LEN = 16, /* Part Number length */ 63 MACADDR_LEN = 12, /* MAC Address length */ 64 }; 65 66 enum { 67 T4_REGMAP_SIZE = (160 * 1024), 68 T5_REGMAP_SIZE = (332 * 1024), 69 }; 70 71 enum { 72 MEM_EDC0, 73 MEM_EDC1, 74 MEM_MC, 75 MEM_MC0 = MEM_MC, 76 MEM_MC1 77 }; 78 79 enum { 80 MEMWIN0_APERTURE = 2048, 81 MEMWIN0_BASE = 0x1b800, 82 MEMWIN1_APERTURE = 32768, 83 MEMWIN1_BASE = 0x28000, 84 MEMWIN1_BASE_T5 = 0x52000, 85 MEMWIN2_APERTURE = 65536, 86 MEMWIN2_BASE = 0x30000, 87 MEMWIN2_APERTURE_T5 = 131072, 88 MEMWIN2_BASE_T5 = 0x60000, 89 }; 90 91 enum dev_master { 92 MASTER_CANT, 93 MASTER_MAY, 94 MASTER_MUST 95 }; 96 97 enum dev_state { 98 DEV_STATE_UNINIT, 99 DEV_STATE_INIT, 100 DEV_STATE_ERR 101 }; 102 103 enum { 104 PAUSE_RX = 1 << 0, 105 PAUSE_TX = 1 << 1, 106 PAUSE_AUTONEG = 1 << 2 107 }; 108 109 struct port_stats { 110 u64 tx_octets; /* total # of octets in good frames */ 111 u64 tx_frames; /* all good frames */ 112 u64 tx_bcast_frames; /* all broadcast frames */ 113 u64 tx_mcast_frames; /* all multicast frames */ 114 u64 tx_ucast_frames; /* all unicast frames */ 115 u64 tx_error_frames; /* all error frames */ 116 117 u64 tx_frames_64; /* # of Tx frames in a particular range */ 118 u64 tx_frames_65_127; 119 u64 tx_frames_128_255; 120 u64 tx_frames_256_511; 121 u64 tx_frames_512_1023; 122 u64 tx_frames_1024_1518; 123 u64 tx_frames_1519_max; 124 125 u64 tx_drop; /* # of dropped Tx frames */ 126 u64 tx_pause; /* # of transmitted pause frames */ 127 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ 128 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ 129 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ 130 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ 131 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ 132 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ 133 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ 134 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ 135 136 u64 rx_octets; /* total # of octets in good frames */ 137 u64 rx_frames; /* all good frames */ 138 u64 rx_bcast_frames; /* all broadcast frames */ 139 u64 rx_mcast_frames; /* all multicast frames */ 140 u64 rx_ucast_frames; /* all unicast frames */ 141 u64 rx_too_long; /* # of frames exceeding MTU */ 142 u64 rx_jabber; /* # of jabber frames */ 143 u64 rx_fcs_err; /* # of received frames with bad FCS */ 144 u64 rx_len_err; /* # of received frames with length error */ 145 u64 rx_symbol_err; /* symbol errors */ 146 u64 rx_runt; /* # of short frames */ 147 148 u64 rx_frames_64; /* # of Rx frames in a particular range */ 149 u64 rx_frames_65_127; 150 u64 rx_frames_128_255; 151 u64 rx_frames_256_511; 152 u64 rx_frames_512_1023; 153 u64 rx_frames_1024_1518; 154 u64 rx_frames_1519_max; 155 156 u64 rx_pause; /* # of received pause frames */ 157 u64 rx_ppp0; /* # of received PPP prio 0 frames */ 158 u64 rx_ppp1; /* # of received PPP prio 1 frames */ 159 u64 rx_ppp2; /* # of received PPP prio 2 frames */ 160 u64 rx_ppp3; /* # of received PPP prio 3 frames */ 161 u64 rx_ppp4; /* # of received PPP prio 4 frames */ 162 u64 rx_ppp5; /* # of received PPP prio 5 frames */ 163 u64 rx_ppp6; /* # of received PPP prio 6 frames */ 164 u64 rx_ppp7; /* # of received PPP prio 7 frames */ 165 166 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ 167 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ 168 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ 169 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ 170 u64 rx_trunc0; /* buffer-group 0 truncated packets */ 171 u64 rx_trunc1; /* buffer-group 1 truncated packets */ 172 u64 rx_trunc2; /* buffer-group 2 truncated packets */ 173 u64 rx_trunc3; /* buffer-group 3 truncated packets */ 174 }; 175 176 struct lb_port_stats { 177 u64 octets; 178 u64 frames; 179 u64 bcast_frames; 180 u64 mcast_frames; 181 u64 ucast_frames; 182 u64 error_frames; 183 184 u64 frames_64; 185 u64 frames_65_127; 186 u64 frames_128_255; 187 u64 frames_256_511; 188 u64 frames_512_1023; 189 u64 frames_1024_1518; 190 u64 frames_1519_max; 191 192 u64 drop; 193 194 u64 ovflow0; 195 u64 ovflow1; 196 u64 ovflow2; 197 u64 ovflow3; 198 u64 trunc0; 199 u64 trunc1; 200 u64 trunc2; 201 u64 trunc3; 202 }; 203 204 struct tp_tcp_stats { 205 u32 tcp_out_rsts; 206 u64 tcp_in_segs; 207 u64 tcp_out_segs; 208 u64 tcp_retrans_segs; 209 }; 210 211 struct tp_usm_stats { 212 u32 frames; 213 u32 drops; 214 u64 octets; 215 }; 216 217 struct tp_fcoe_stats { 218 u32 frames_ddp; 219 u32 frames_drop; 220 u64 octets_ddp; 221 }; 222 223 struct tp_err_stats { 224 u32 mac_in_errs[4]; 225 u32 hdr_in_errs[4]; 226 u32 tcp_in_errs[4]; 227 u32 tnl_cong_drops[4]; 228 u32 ofld_chan_drops[4]; 229 u32 tnl_tx_drops[4]; 230 u32 ofld_vlan_drops[4]; 231 u32 tcp6_in_errs[4]; 232 u32 ofld_no_neigh; 233 u32 ofld_cong_defer; 234 }; 235 236 struct tp_cpl_stats { 237 u32 req[4]; 238 u32 rsp[4]; 239 }; 240 241 struct tp_rdma_stats { 242 u32 rqe_dfr_pkt; 243 u32 rqe_dfr_mod; 244 }; 245 246 struct sge_params { 247 u32 hps; /* host page size for our PF/VF */ 248 u32 eq_qpp; /* egress queues/page for our PF/VF */ 249 u32 iq_qpp; /* egress queues/page for our PF/VF */ 250 }; 251 252 struct tp_params { 253 unsigned int tre; /* log2 of core clocks per TP tick */ 254 unsigned int la_mask; /* what events are recorded by TP LA */ 255 unsigned short tx_modq_map; /* TX modulation scheduler queue to */ 256 /* channel map */ 257 258 uint32_t dack_re; /* DACK timer resolution */ 259 unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */ 260 261 u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */ 262 u32 ingress_config; /* cached TP_INGRESS_CONFIG */ 263 264 /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a 265 * subset of the set of fields which may be present in the Compressed 266 * Filter Tuple portion of filters and TCP TCB connections. The 267 * fields which are present are controlled by the TP_VLAN_PRI_MAP. 268 * Since a variable number of fields may or may not be present, their 269 * shifted field positions within the Compressed Filter Tuple may 270 * vary, or not even be present if the field isn't selected in 271 * TP_VLAN_PRI_MAP. Since some of these fields are needed in various 272 * places we store their offsets here, or a -1 if the field isn't 273 * present. 274 */ 275 int vlan_shift; 276 int vnic_shift; 277 int port_shift; 278 int protocol_shift; 279 }; 280 281 struct vpd_params { 282 unsigned int cclk; 283 u8 ec[EC_LEN + 1]; 284 u8 sn[SERNUM_LEN + 1]; 285 u8 id[ID_LEN + 1]; 286 u8 pn[PN_LEN + 1]; 287 u8 na[MACADDR_LEN + 1]; 288 }; 289 290 struct pci_params { 291 unsigned char speed; 292 unsigned char width; 293 }; 294 295 struct devlog_params { 296 u32 memtype; /* which memory (EDC0, EDC1, MC) */ 297 u32 start; /* start of log in firmware memory */ 298 u32 size; /* size of log */ 299 }; 300 301 /* Stores chip specific parameters */ 302 struct arch_specific_params { 303 u8 nchan; 304 u8 pm_stats_cnt; 305 u8 cng_ch_bits_log; /* congestion channel map bits width */ 306 u16 mps_rplc_size; 307 u16 vfcount; 308 u32 sge_fl_db; 309 u16 mps_tcam_size; 310 }; 311 312 struct adapter_params { 313 struct sge_params sge; 314 struct tp_params tp; 315 struct vpd_params vpd; 316 struct pci_params pci; 317 struct devlog_params devlog; 318 enum pcie_memwin drv_memwin; 319 320 unsigned int cim_la_size; 321 322 unsigned int sf_size; /* serial flash size in bytes */ 323 unsigned int sf_nsec; /* # of flash sectors */ 324 unsigned int sf_fw_start; /* start of FW image in flash */ 325 326 unsigned int fw_vers; 327 unsigned int tp_vers; 328 u8 api_vers[7]; 329 330 unsigned short mtus[NMTUS]; 331 unsigned short a_wnd[NCCTRL_WIN]; 332 unsigned short b_wnd[NCCTRL_WIN]; 333 334 unsigned char nports; /* # of ethernet ports */ 335 unsigned char portvec; 336 enum chip_type chip; /* chip code */ 337 struct arch_specific_params arch; /* chip specific params */ 338 unsigned char offload; 339 340 unsigned char bypass; 341 342 unsigned int ofldq_wr_cred; 343 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ 344 345 unsigned int max_ordird_qp; /* Max read depth per RDMA QP */ 346 unsigned int max_ird_adapter; /* Max read depth per adapter */ 347 }; 348 349 /* State needed to monitor the forward progress of SGE Ingress DMA activities 350 * and possible hangs. 351 */ 352 struct sge_idma_monitor_state { 353 unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */ 354 unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */ 355 unsigned int idma_state[2]; /* IDMA Hang detect state */ 356 unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */ 357 unsigned int idma_warn[2]; /* time to warning in HZ */ 358 }; 359 360 #include "t4fw_api.h" 361 362 #define FW_VERSION(chip) ( \ 363 FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \ 364 FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \ 365 FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \ 366 FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD)) 367 #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf) 368 369 struct fw_info { 370 u8 chip; 371 char *fs_name; 372 char *fw_mod_name; 373 struct fw_hdr fw_hdr; 374 }; 375 376 377 struct trace_params { 378 u32 data[TRACE_LEN / 4]; 379 u32 mask[TRACE_LEN / 4]; 380 unsigned short snap_len; 381 unsigned short min_len; 382 unsigned char skip_ofst; 383 unsigned char skip_len; 384 unsigned char invert; 385 unsigned char port; 386 }; 387 388 struct link_config { 389 unsigned short supported; /* link capabilities */ 390 unsigned short advertising; /* advertised capabilities */ 391 unsigned short requested_speed; /* speed user has requested */ 392 unsigned short speed; /* actual link speed */ 393 unsigned char requested_fc; /* flow control user has requested */ 394 unsigned char fc; /* actual link flow control */ 395 unsigned char autoneg; /* autonegotiating? */ 396 unsigned char link_ok; /* link up? */ 397 }; 398 399 #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16) 400 401 enum { 402 MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */ 403 MAX_OFLD_QSETS = 16, /* # of offload Tx, iscsi Rx queue sets */ 404 MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */ 405 MAX_RDMA_QUEUES = NCHAN, /* # of streaming RDMA Rx queues */ 406 MAX_RDMA_CIQS = 32, /* # of RDMA concentrator IQs */ 407 }; 408 409 enum { 410 MAX_TXQ_ENTRIES = 16384, 411 MAX_CTRL_TXQ_ENTRIES = 1024, 412 MAX_RSPQ_ENTRIES = 16384, 413 MAX_RX_BUFFERS = 16384, 414 MIN_TXQ_ENTRIES = 32, 415 MIN_CTRL_TXQ_ENTRIES = 32, 416 MIN_RSPQ_ENTRIES = 128, 417 MIN_FL_ENTRIES = 16 418 }; 419 420 enum { 421 INGQ_EXTRAS = 2, /* firmware event queue and */ 422 /* forwarded interrupts */ 423 MAX_INGQ = MAX_ETH_QSETS + MAX_OFLD_QSETS + MAX_RDMA_QUEUES 424 + MAX_RDMA_CIQS + INGQ_EXTRAS, 425 }; 426 427 struct adapter; 428 struct sge_rspq; 429 430 #include "cxgb4_dcb.h" 431 432 #ifdef CONFIG_CHELSIO_T4_FCOE 433 #include "cxgb4_fcoe.h" 434 #endif /* CONFIG_CHELSIO_T4_FCOE */ 435 436 struct port_info { 437 struct adapter *adapter; 438 u16 viid; 439 s16 xact_addr_filt; /* index of exact MAC address filter */ 440 u16 rss_size; /* size of VI's RSS table slice */ 441 s8 mdio_addr; 442 enum fw_port_type port_type; 443 u8 mod_type; 444 u8 port_id; 445 u8 tx_chan; 446 u8 lport; /* associated offload logical port */ 447 u8 nqsets; /* # of qsets */ 448 u8 first_qset; /* index of first qset */ 449 u8 rss_mode; 450 struct link_config link_cfg; 451 u16 *rss; 452 struct port_stats stats_base; 453 #ifdef CONFIG_CHELSIO_T4_DCB 454 struct port_dcb_info dcb; /* Data Center Bridging support */ 455 #endif 456 #ifdef CONFIG_CHELSIO_T4_FCOE 457 struct cxgb_fcoe fcoe; 458 #endif /* CONFIG_CHELSIO_T4_FCOE */ 459 bool rxtstamp; /* Enable TS */ 460 struct hwtstamp_config tstamp_config; 461 }; 462 463 struct dentry; 464 struct work_struct; 465 466 enum { /* adapter flags */ 467 FULL_INIT_DONE = (1 << 0), 468 DEV_ENABLED = (1 << 1), 469 USING_MSI = (1 << 2), 470 USING_MSIX = (1 << 3), 471 FW_OK = (1 << 4), 472 RSS_TNLALLLOOKUP = (1 << 5), 473 USING_SOFT_PARAMS = (1 << 6), 474 MASTER_PF = (1 << 7), 475 FW_OFLD_CONN = (1 << 9), 476 }; 477 478 struct rx_sw_desc; 479 480 struct sge_fl { /* SGE free-buffer queue state */ 481 unsigned int avail; /* # of available Rx buffers */ 482 unsigned int pend_cred; /* new buffers since last FL DB ring */ 483 unsigned int cidx; /* consumer index */ 484 unsigned int pidx; /* producer index */ 485 unsigned long alloc_failed; /* # of times buffer allocation failed */ 486 unsigned long large_alloc_failed; 487 unsigned long mapping_err; /* # of RX Buffer DMA Mapping failures */ 488 unsigned long low; /* # of times momentarily starving */ 489 unsigned long starving; 490 /* RO fields */ 491 unsigned int cntxt_id; /* SGE context id for the free list */ 492 unsigned int size; /* capacity of free list */ 493 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */ 494 __be64 *desc; /* address of HW Rx descriptor ring */ 495 dma_addr_t addr; /* bus address of HW ring start */ 496 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 497 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 498 }; 499 500 /* A packet gather list */ 501 struct pkt_gl { 502 u64 sgetstamp; /* SGE Time Stamp for Ingress Packet */ 503 struct page_frag frags[MAX_SKB_FRAGS]; 504 void *va; /* virtual address of first byte */ 505 unsigned int nfrags; /* # of fragments */ 506 unsigned int tot_len; /* total length of fragments */ 507 }; 508 509 typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp, 510 const struct pkt_gl *gl); 511 512 struct sge_rspq { /* state for an SGE response queue */ 513 struct napi_struct napi; 514 const __be64 *cur_desc; /* current descriptor in queue */ 515 unsigned int cidx; /* consumer index */ 516 u8 gen; /* current generation bit */ 517 u8 intr_params; /* interrupt holdoff parameters */ 518 u8 next_intr_params; /* holdoff params for next interrupt */ 519 u8 adaptive_rx; 520 u8 pktcnt_idx; /* interrupt packet threshold */ 521 u8 uld; /* ULD handling this queue */ 522 u8 idx; /* queue index within its group */ 523 int offset; /* offset into current Rx buffer */ 524 u16 cntxt_id; /* SGE context id for the response q */ 525 u16 abs_id; /* absolute SGE id for the response q */ 526 __be64 *desc; /* address of HW response ring */ 527 dma_addr_t phys_addr; /* physical address of the ring */ 528 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 529 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 530 unsigned int iqe_len; /* entry size */ 531 unsigned int size; /* capacity of response queue */ 532 struct adapter *adap; 533 struct net_device *netdev; /* associated net device */ 534 rspq_handler_t handler; 535 #ifdef CONFIG_NET_RX_BUSY_POLL 536 #define CXGB_POLL_STATE_IDLE 0 537 #define CXGB_POLL_STATE_NAPI BIT(0) /* NAPI owns this poll */ 538 #define CXGB_POLL_STATE_POLL BIT(1) /* poll owns this poll */ 539 #define CXGB_POLL_STATE_NAPI_YIELD BIT(2) /* NAPI yielded this poll */ 540 #define CXGB_POLL_STATE_POLL_YIELD BIT(3) /* poll yielded this poll */ 541 #define CXGB_POLL_YIELD (CXGB_POLL_STATE_NAPI_YIELD | \ 542 CXGB_POLL_STATE_POLL_YIELD) 543 #define CXGB_POLL_LOCKED (CXGB_POLL_STATE_NAPI | \ 544 CXGB_POLL_STATE_POLL) 545 #define CXGB_POLL_USER_PEND (CXGB_POLL_STATE_POLL | \ 546 CXGB_POLL_STATE_POLL_YIELD) 547 unsigned int bpoll_state; 548 spinlock_t bpoll_lock; /* lock for busy poll */ 549 #endif /* CONFIG_NET_RX_BUSY_POLL */ 550 551 }; 552 553 struct sge_eth_stats { /* Ethernet queue statistics */ 554 unsigned long pkts; /* # of ethernet packets */ 555 unsigned long lro_pkts; /* # of LRO super packets */ 556 unsigned long lro_merged; /* # of wire packets merged by LRO */ 557 unsigned long rx_cso; /* # of Rx checksum offloads */ 558 unsigned long vlan_ex; /* # of Rx VLAN extractions */ 559 unsigned long rx_drops; /* # of packets dropped due to no mem */ 560 }; 561 562 struct sge_eth_rxq { /* SW Ethernet Rx queue */ 563 struct sge_rspq rspq; 564 struct sge_fl fl; 565 struct sge_eth_stats stats; 566 } ____cacheline_aligned_in_smp; 567 568 struct sge_ofld_stats { /* offload queue statistics */ 569 unsigned long pkts; /* # of packets */ 570 unsigned long imm; /* # of immediate-data packets */ 571 unsigned long an; /* # of asynchronous notifications */ 572 unsigned long nomem; /* # of responses deferred due to no mem */ 573 }; 574 575 struct sge_ofld_rxq { /* SW offload Rx queue */ 576 struct sge_rspq rspq; 577 struct sge_fl fl; 578 struct sge_ofld_stats stats; 579 } ____cacheline_aligned_in_smp; 580 581 struct tx_desc { 582 __be64 flit[8]; 583 }; 584 585 struct tx_sw_desc; 586 587 struct sge_txq { 588 unsigned int in_use; /* # of in-use Tx descriptors */ 589 unsigned int size; /* # of descriptors */ 590 unsigned int cidx; /* SW consumer index */ 591 unsigned int pidx; /* producer index */ 592 unsigned long stops; /* # of times q has been stopped */ 593 unsigned long restarts; /* # of queue restarts */ 594 unsigned int cntxt_id; /* SGE context id for the Tx q */ 595 struct tx_desc *desc; /* address of HW Tx descriptor ring */ 596 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */ 597 struct sge_qstat *stat; /* queue status entry */ 598 dma_addr_t phys_addr; /* physical address of the ring */ 599 spinlock_t db_lock; 600 int db_disabled; 601 unsigned short db_pidx; 602 unsigned short db_pidx_inc; 603 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 604 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 605 }; 606 607 struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */ 608 struct sge_txq q; 609 struct netdev_queue *txq; /* associated netdev TX queue */ 610 #ifdef CONFIG_CHELSIO_T4_DCB 611 u8 dcb_prio; /* DCB Priority bound to queue */ 612 #endif 613 unsigned long tso; /* # of TSO requests */ 614 unsigned long tx_cso; /* # of Tx checksum offloads */ 615 unsigned long vlan_ins; /* # of Tx VLAN insertions */ 616 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 617 } ____cacheline_aligned_in_smp; 618 619 struct sge_ofld_txq { /* state for an SGE offload Tx queue */ 620 struct sge_txq q; 621 struct adapter *adap; 622 struct sk_buff_head sendq; /* list of backpressured packets */ 623 struct tasklet_struct qresume_tsk; /* restarts the queue */ 624 bool service_ofldq_running; /* service_ofldq() is processing sendq */ 625 u8 full; /* the Tx ring is full */ 626 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 627 } ____cacheline_aligned_in_smp; 628 629 struct sge_ctrl_txq { /* state for an SGE control Tx queue */ 630 struct sge_txq q; 631 struct adapter *adap; 632 struct sk_buff_head sendq; /* list of backpressured packets */ 633 struct tasklet_struct qresume_tsk; /* restarts the queue */ 634 u8 full; /* the Tx ring is full */ 635 } ____cacheline_aligned_in_smp; 636 637 struct sge { 638 struct sge_eth_txq ethtxq[MAX_ETH_QSETS]; 639 struct sge_ofld_txq ofldtxq[MAX_OFLD_QSETS]; 640 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES]; 641 642 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS]; 643 struct sge_ofld_rxq iscsirxq[MAX_OFLD_QSETS]; 644 struct sge_ofld_rxq rdmarxq[MAX_RDMA_QUEUES]; 645 struct sge_ofld_rxq rdmaciq[MAX_RDMA_CIQS]; 646 struct sge_rspq fw_evtq ____cacheline_aligned_in_smp; 647 648 struct sge_rspq intrq ____cacheline_aligned_in_smp; 649 spinlock_t intrq_lock; 650 651 u16 max_ethqsets; /* # of available Ethernet queue sets */ 652 u16 ethqsets; /* # of active Ethernet queue sets */ 653 u16 ethtxq_rover; /* Tx queue to clean up next */ 654 u16 iscsiqsets; /* # of active iSCSI queue sets */ 655 u16 rdmaqs; /* # of available RDMA Rx queues */ 656 u16 rdmaciqs; /* # of available RDMA concentrator IQs */ 657 u16 iscsi_rxq[MAX_OFLD_QSETS]; 658 u16 rdma_rxq[MAX_RDMA_QUEUES]; 659 u16 rdma_ciq[MAX_RDMA_CIQS]; 660 u16 timer_val[SGE_NTIMERS]; 661 u8 counter_val[SGE_NCOUNTERS]; 662 u32 fl_pg_order; /* large page allocation size */ 663 u32 stat_len; /* length of status page at ring end */ 664 u32 pktshift; /* padding between CPL & packet data */ 665 u32 fl_align; /* response queue message alignment */ 666 u32 fl_starve_thres; /* Free List starvation threshold */ 667 668 struct sge_idma_monitor_state idma_monitor; 669 unsigned int egr_start; 670 unsigned int egr_sz; 671 unsigned int ingr_start; 672 unsigned int ingr_sz; 673 void **egr_map; /* qid->queue egress queue map */ 674 struct sge_rspq **ingr_map; /* qid->queue ingress queue map */ 675 unsigned long *starving_fl; 676 unsigned long *txq_maperr; 677 unsigned long *blocked_fl; 678 struct timer_list rx_timer; /* refills starving FLs */ 679 struct timer_list tx_timer; /* checks Tx queues */ 680 }; 681 682 #define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++) 683 #define for_each_iscsirxq(sge, i) for (i = 0; i < (sge)->iscsiqsets; i++) 684 #define for_each_rdmarxq(sge, i) for (i = 0; i < (sge)->rdmaqs; i++) 685 #define for_each_rdmaciq(sge, i) for (i = 0; i < (sge)->rdmaciqs; i++) 686 687 struct l2t_data; 688 689 #ifdef CONFIG_PCI_IOV 690 691 /* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial 692 * Configuration initialization for T5 only has SR-IOV functionality enabled 693 * on PF0-3 in order to simplify everything. 694 */ 695 #define NUM_OF_PF_WITH_SRIOV 4 696 697 #endif 698 699 struct doorbell_stats { 700 u32 db_drop; 701 u32 db_empty; 702 u32 db_full; 703 }; 704 705 struct adapter { 706 void __iomem *regs; 707 void __iomem *bar2; 708 u32 t4_bar0; 709 struct pci_dev *pdev; 710 struct device *pdev_dev; 711 unsigned int mbox; 712 unsigned int pf; 713 unsigned int flags; 714 enum chip_type chip; 715 716 int msg_enable; 717 718 struct adapter_params params; 719 struct cxgb4_virt_res vres; 720 unsigned int swintr; 721 722 struct { 723 unsigned short vec; 724 char desc[IFNAMSIZ + 10]; 725 } msix_info[MAX_INGQ + 1]; 726 727 struct doorbell_stats db_stats; 728 struct sge sge; 729 730 struct net_device *port[MAX_NPORTS]; 731 u8 chan_map[NCHAN]; /* channel -> port map */ 732 733 u32 filter_mode; 734 unsigned int l2t_start; 735 unsigned int l2t_end; 736 struct l2t_data *l2t; 737 unsigned int clipt_start; 738 unsigned int clipt_end; 739 struct clip_tbl *clipt; 740 void *uld_handle[CXGB4_ULD_MAX]; 741 struct list_head list_node; 742 struct list_head rcu_node; 743 744 struct tid_info tids; 745 void **tid_release_head; 746 spinlock_t tid_release_lock; 747 struct workqueue_struct *workq; 748 struct work_struct tid_release_task; 749 struct work_struct db_full_task; 750 struct work_struct db_drop_task; 751 bool tid_release_task_busy; 752 753 struct dentry *debugfs_root; 754 bool use_bd; /* Use SGE Back Door intfc for reading SGE Contexts */ 755 bool trace_rss; /* 1 implies that different RSS flit per filter is 756 * used per filter else if 0 default RSS flit is 757 * used for all 4 filters. 758 */ 759 760 spinlock_t stats_lock; 761 spinlock_t win0_lock ____cacheline_aligned_in_smp; 762 }; 763 764 /* Defined bit width of user definable filter tuples 765 */ 766 #define ETHTYPE_BITWIDTH 16 767 #define FRAG_BITWIDTH 1 768 #define MACIDX_BITWIDTH 9 769 #define FCOE_BITWIDTH 1 770 #define IPORT_BITWIDTH 3 771 #define MATCHTYPE_BITWIDTH 3 772 #define PROTO_BITWIDTH 8 773 #define TOS_BITWIDTH 8 774 #define PF_BITWIDTH 8 775 #define VF_BITWIDTH 8 776 #define IVLAN_BITWIDTH 16 777 #define OVLAN_BITWIDTH 16 778 779 /* Filter matching rules. These consist of a set of ingress packet field 780 * (value, mask) tuples. The associated ingress packet field matches the 781 * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field 782 * rule can be constructed by specifying a tuple of (0, 0).) A filter rule 783 * matches an ingress packet when all of the individual individual field 784 * matching rules are true. 785 * 786 * Partial field masks are always valid, however, while it may be easy to 787 * understand their meanings for some fields (e.g. IP address to match a 788 * subnet), for others making sensible partial masks is less intuitive (e.g. 789 * MPS match type) ... 790 * 791 * Most of the following data structures are modeled on T4 capabilities. 792 * Drivers for earlier chips use the subsets which make sense for those chips. 793 * We really need to come up with a hardware-independent mechanism to 794 * represent hardware filter capabilities ... 795 */ 796 struct ch_filter_tuple { 797 /* Compressed header matching field rules. The TP_VLAN_PRI_MAP 798 * register selects which of these fields will participate in the 799 * filter match rules -- up to a maximum of 36 bits. Because 800 * TP_VLAN_PRI_MAP is a global register, all filters must use the same 801 * set of fields. 802 */ 803 uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */ 804 uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */ 805 uint32_t ivlan_vld:1; /* inner VLAN valid */ 806 uint32_t ovlan_vld:1; /* outer VLAN valid */ 807 uint32_t pfvf_vld:1; /* PF/VF valid */ 808 uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */ 809 uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */ 810 uint32_t iport:IPORT_BITWIDTH; /* ingress port */ 811 uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */ 812 uint32_t proto:PROTO_BITWIDTH; /* protocol type */ 813 uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */ 814 uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */ 815 uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */ 816 uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */ 817 uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */ 818 819 /* Uncompressed header matching field rules. These are always 820 * available for field rules. 821 */ 822 uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */ 823 uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */ 824 uint16_t lport; /* local port */ 825 uint16_t fport; /* foreign port */ 826 }; 827 828 /* A filter ioctl command. 829 */ 830 struct ch_filter_specification { 831 /* Administrative fields for filter. 832 */ 833 uint32_t hitcnts:1; /* count filter hits in TCB */ 834 uint32_t prio:1; /* filter has priority over active/server */ 835 836 /* Fundamental filter typing. This is the one element of filter 837 * matching that doesn't exist as a (value, mask) tuple. 838 */ 839 uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */ 840 841 /* Packet dispatch information. Ingress packets which match the 842 * filter rules will be dropped, passed to the host or switched back 843 * out as egress packets. 844 */ 845 uint32_t action:2; /* drop, pass, switch */ 846 847 uint32_t rpttid:1; /* report TID in RSS hash field */ 848 849 uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */ 850 uint32_t iq:10; /* ingress queue */ 851 852 uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */ 853 uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */ 854 /* 1 => TCB contains IQ ID */ 855 856 /* Switch proxy/rewrite fields. An ingress packet which matches a 857 * filter with "switch" set will be looped back out as an egress 858 * packet -- potentially with some Ethernet header rewriting. 859 */ 860 uint32_t eport:2; /* egress port to switch packet out */ 861 uint32_t newdmac:1; /* rewrite destination MAC address */ 862 uint32_t newsmac:1; /* rewrite source MAC address */ 863 uint32_t newvlan:2; /* rewrite VLAN Tag */ 864 uint8_t dmac[ETH_ALEN]; /* new destination MAC address */ 865 uint8_t smac[ETH_ALEN]; /* new source MAC address */ 866 uint16_t vlan; /* VLAN Tag to insert */ 867 868 /* Filter rule value/mask pairs. 869 */ 870 struct ch_filter_tuple val; 871 struct ch_filter_tuple mask; 872 }; 873 874 enum { 875 FILTER_PASS = 0, /* default */ 876 FILTER_DROP, 877 FILTER_SWITCH 878 }; 879 880 enum { 881 VLAN_NOCHANGE = 0, /* default */ 882 VLAN_REMOVE, 883 VLAN_INSERT, 884 VLAN_REWRITE 885 }; 886 887 static inline int is_offload(const struct adapter *adap) 888 { 889 return adap->params.offload; 890 } 891 892 static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr) 893 { 894 return readl(adap->regs + reg_addr); 895 } 896 897 static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val) 898 { 899 writel(val, adap->regs + reg_addr); 900 } 901 902 #ifndef readq 903 static inline u64 readq(const volatile void __iomem *addr) 904 { 905 return readl(addr) + ((u64)readl(addr + 4) << 32); 906 } 907 908 static inline void writeq(u64 val, volatile void __iomem *addr) 909 { 910 writel(val, addr); 911 writel(val >> 32, addr + 4); 912 } 913 #endif 914 915 static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr) 916 { 917 return readq(adap->regs + reg_addr); 918 } 919 920 static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val) 921 { 922 writeq(val, adap->regs + reg_addr); 923 } 924 925 /** 926 * t4_set_hw_addr - store a port's MAC address in SW 927 * @adapter: the adapter 928 * @port_idx: the port index 929 * @hw_addr: the Ethernet address 930 * 931 * Store the Ethernet address of the given port in SW. Called by the common 932 * code when it retrieves a port's Ethernet address from EEPROM. 933 */ 934 static inline void t4_set_hw_addr(struct adapter *adapter, int port_idx, 935 u8 hw_addr[]) 936 { 937 ether_addr_copy(adapter->port[port_idx]->dev_addr, hw_addr); 938 ether_addr_copy(adapter->port[port_idx]->perm_addr, hw_addr); 939 } 940 941 /** 942 * netdev2pinfo - return the port_info structure associated with a net_device 943 * @dev: the netdev 944 * 945 * Return the struct port_info associated with a net_device 946 */ 947 static inline struct port_info *netdev2pinfo(const struct net_device *dev) 948 { 949 return netdev_priv(dev); 950 } 951 952 /** 953 * adap2pinfo - return the port_info of a port 954 * @adap: the adapter 955 * @idx: the port index 956 * 957 * Return the port_info structure for the port of the given index. 958 */ 959 static inline struct port_info *adap2pinfo(struct adapter *adap, int idx) 960 { 961 return netdev_priv(adap->port[idx]); 962 } 963 964 /** 965 * netdev2adap - return the adapter structure associated with a net_device 966 * @dev: the netdev 967 * 968 * Return the struct adapter associated with a net_device 969 */ 970 static inline struct adapter *netdev2adap(const struct net_device *dev) 971 { 972 return netdev2pinfo(dev)->adapter; 973 } 974 975 #ifdef CONFIG_NET_RX_BUSY_POLL 976 static inline void cxgb_busy_poll_init_lock(struct sge_rspq *q) 977 { 978 spin_lock_init(&q->bpoll_lock); 979 q->bpoll_state = CXGB_POLL_STATE_IDLE; 980 } 981 982 static inline bool cxgb_poll_lock_napi(struct sge_rspq *q) 983 { 984 bool rc = true; 985 986 spin_lock(&q->bpoll_lock); 987 if (q->bpoll_state & CXGB_POLL_LOCKED) { 988 q->bpoll_state |= CXGB_POLL_STATE_NAPI_YIELD; 989 rc = false; 990 } else { 991 q->bpoll_state = CXGB_POLL_STATE_NAPI; 992 } 993 spin_unlock(&q->bpoll_lock); 994 return rc; 995 } 996 997 static inline bool cxgb_poll_unlock_napi(struct sge_rspq *q) 998 { 999 bool rc = false; 1000 1001 spin_lock(&q->bpoll_lock); 1002 if (q->bpoll_state & CXGB_POLL_STATE_POLL_YIELD) 1003 rc = true; 1004 q->bpoll_state = CXGB_POLL_STATE_IDLE; 1005 spin_unlock(&q->bpoll_lock); 1006 return rc; 1007 } 1008 1009 static inline bool cxgb_poll_lock_poll(struct sge_rspq *q) 1010 { 1011 bool rc = true; 1012 1013 spin_lock_bh(&q->bpoll_lock); 1014 if (q->bpoll_state & CXGB_POLL_LOCKED) { 1015 q->bpoll_state |= CXGB_POLL_STATE_POLL_YIELD; 1016 rc = false; 1017 } else { 1018 q->bpoll_state |= CXGB_POLL_STATE_POLL; 1019 } 1020 spin_unlock_bh(&q->bpoll_lock); 1021 return rc; 1022 } 1023 1024 static inline bool cxgb_poll_unlock_poll(struct sge_rspq *q) 1025 { 1026 bool rc = false; 1027 1028 spin_lock_bh(&q->bpoll_lock); 1029 if (q->bpoll_state & CXGB_POLL_STATE_POLL_YIELD) 1030 rc = true; 1031 q->bpoll_state = CXGB_POLL_STATE_IDLE; 1032 spin_unlock_bh(&q->bpoll_lock); 1033 return rc; 1034 } 1035 1036 static inline bool cxgb_poll_busy_polling(struct sge_rspq *q) 1037 { 1038 return q->bpoll_state & CXGB_POLL_USER_PEND; 1039 } 1040 #else 1041 static inline void cxgb_busy_poll_init_lock(struct sge_rspq *q) 1042 { 1043 } 1044 1045 static inline bool cxgb_poll_lock_napi(struct sge_rspq *q) 1046 { 1047 return true; 1048 } 1049 1050 static inline bool cxgb_poll_unlock_napi(struct sge_rspq *q) 1051 { 1052 return false; 1053 } 1054 1055 static inline bool cxgb_poll_lock_poll(struct sge_rspq *q) 1056 { 1057 return false; 1058 } 1059 1060 static inline bool cxgb_poll_unlock_poll(struct sge_rspq *q) 1061 { 1062 return false; 1063 } 1064 1065 static inline bool cxgb_poll_busy_polling(struct sge_rspq *q) 1066 { 1067 return false; 1068 } 1069 #endif /* CONFIG_NET_RX_BUSY_POLL */ 1070 1071 /* Return a version number to identify the type of adapter. The scheme is: 1072 * - bits 0..9: chip version 1073 * - bits 10..15: chip revision 1074 * - bits 16..23: register dump version 1075 */ 1076 static inline unsigned int mk_adap_vers(struct adapter *ap) 1077 { 1078 return CHELSIO_CHIP_VERSION(ap->params.chip) | 1079 (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16); 1080 } 1081 1082 /* Return a queue's interrupt hold-off time in us. 0 means no timer. */ 1083 static inline unsigned int qtimer_val(const struct adapter *adap, 1084 const struct sge_rspq *q) 1085 { 1086 unsigned int idx = q->intr_params >> 1; 1087 1088 return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0; 1089 } 1090 1091 /* driver version & name used for ethtool_drvinfo */ 1092 extern char cxgb4_driver_name[]; 1093 extern const char cxgb4_driver_version[]; 1094 1095 void t4_os_portmod_changed(const struct adapter *adap, int port_id); 1096 void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat); 1097 1098 void *t4_alloc_mem(size_t size); 1099 1100 void t4_free_sge_resources(struct adapter *adap); 1101 void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q); 1102 irq_handler_t t4_intr_handler(struct adapter *adap); 1103 netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev); 1104 int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp, 1105 const struct pkt_gl *gl); 1106 int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb); 1107 int t4_ofld_send(struct adapter *adap, struct sk_buff *skb); 1108 int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, 1109 struct net_device *dev, int intr_idx, 1110 struct sge_fl *fl, rspq_handler_t hnd, int cong); 1111 int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq, 1112 struct net_device *dev, struct netdev_queue *netdevq, 1113 unsigned int iqid); 1114 int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq, 1115 struct net_device *dev, unsigned int iqid, 1116 unsigned int cmplqid); 1117 int t4_sge_alloc_ofld_txq(struct adapter *adap, struct sge_ofld_txq *txq, 1118 struct net_device *dev, unsigned int iqid); 1119 irqreturn_t t4_sge_intr_msix(int irq, void *cookie); 1120 int t4_sge_init(struct adapter *adap); 1121 void t4_sge_start(struct adapter *adap); 1122 void t4_sge_stop(struct adapter *adap); 1123 int cxgb_busy_poll(struct napi_struct *napi); 1124 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us, 1125 unsigned int cnt); 1126 void cxgb4_set_ethtool_ops(struct net_device *netdev); 1127 int cxgb4_write_rss(const struct port_info *pi, const u16 *queues); 1128 extern int dbfifo_int_thresh; 1129 1130 #define for_each_port(adapter, iter) \ 1131 for (iter = 0; iter < (adapter)->params.nports; ++iter) 1132 1133 static inline int is_bypass(struct adapter *adap) 1134 { 1135 return adap->params.bypass; 1136 } 1137 1138 static inline int is_bypass_device(int device) 1139 { 1140 /* this should be set based upon device capabilities */ 1141 switch (device) { 1142 case 0x440b: 1143 case 0x440c: 1144 return 1; 1145 default: 1146 return 0; 1147 } 1148 } 1149 1150 static inline int is_10gbt_device(int device) 1151 { 1152 /* this should be set based upon device capabilities */ 1153 switch (device) { 1154 case 0x4409: 1155 case 0x4486: 1156 return 1; 1157 1158 default: 1159 return 0; 1160 } 1161 } 1162 1163 static inline unsigned int core_ticks_per_usec(const struct adapter *adap) 1164 { 1165 return adap->params.vpd.cclk / 1000; 1166 } 1167 1168 static inline unsigned int us_to_core_ticks(const struct adapter *adap, 1169 unsigned int us) 1170 { 1171 return (us * adap->params.vpd.cclk) / 1000; 1172 } 1173 1174 static inline unsigned int core_ticks_to_us(const struct adapter *adapter, 1175 unsigned int ticks) 1176 { 1177 /* add Core Clock / 2 to round ticks to nearest uS */ 1178 return ((ticks * 1000 + adapter->params.vpd.cclk/2) / 1179 adapter->params.vpd.cclk); 1180 } 1181 1182 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, 1183 u32 val); 1184 1185 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 1186 int size, void *rpl, bool sleep_ok, int timeout); 1187 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 1188 void *rpl, bool sleep_ok); 1189 1190 static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox, 1191 const void *cmd, int size, void *rpl, 1192 int timeout) 1193 { 1194 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true, 1195 timeout); 1196 } 1197 1198 static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, 1199 int size, void *rpl) 1200 { 1201 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true); 1202 } 1203 1204 static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, 1205 int size, void *rpl) 1206 { 1207 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false); 1208 } 1209 1210 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 1211 unsigned int data_reg, const u32 *vals, 1212 unsigned int nregs, unsigned int start_idx); 1213 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 1214 unsigned int data_reg, u32 *vals, unsigned int nregs, 1215 unsigned int start_idx); 1216 void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val); 1217 1218 struct fw_filter_wr; 1219 1220 void t4_intr_enable(struct adapter *adapter); 1221 void t4_intr_disable(struct adapter *adapter); 1222 int t4_slow_intr_handler(struct adapter *adapter); 1223 1224 int t4_wait_dev_ready(void __iomem *regs); 1225 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port, 1226 struct link_config *lc); 1227 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port); 1228 1229 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg); 1230 u32 t4_get_util_window(struct adapter *adap); 1231 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window); 1232 1233 #define T4_MEMORY_WRITE 0 1234 #define T4_MEMORY_READ 1 1235 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len, 1236 void *buf, int dir); 1237 static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr, 1238 u32 len, __be32 *buf) 1239 { 1240 return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0); 1241 } 1242 1243 unsigned int t4_get_regs_len(struct adapter *adapter); 1244 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size); 1245 1246 int t4_seeprom_wp(struct adapter *adapter, bool enable); 1247 int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p); 1248 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p); 1249 int t4_read_flash(struct adapter *adapter, unsigned int addr, 1250 unsigned int nwords, u32 *data, int byte_oriented); 1251 int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size); 1252 int t4_load_phy_fw(struct adapter *adap, 1253 int win, spinlock_t *lock, 1254 int (*phy_fw_version)(const u8 *, size_t), 1255 const u8 *phy_fw_data, size_t phy_fw_size); 1256 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver); 1257 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op); 1258 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 1259 const u8 *fw_data, unsigned int size, int force); 1260 int t4_fl_pkt_align(struct adapter *adap); 1261 unsigned int t4_flash_cfg_addr(struct adapter *adapter); 1262 int t4_check_fw_version(struct adapter *adap); 1263 int t4_get_fw_version(struct adapter *adapter, u32 *vers); 1264 int t4_get_tp_version(struct adapter *adapter, u32 *vers); 1265 int t4_get_exprom_version(struct adapter *adapter, u32 *vers); 1266 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info, 1267 const u8 *fw_data, unsigned int fw_size, 1268 struct fw_hdr *card_fw, enum dev_state state, int *reset); 1269 int t4_prep_adapter(struct adapter *adapter); 1270 1271 enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS }; 1272 int t4_bar2_sge_qregs(struct adapter *adapter, 1273 unsigned int qid, 1274 enum t4_bar2_qtype qtype, 1275 int user, 1276 u64 *pbar2_qoffset, 1277 unsigned int *pbar2_qid); 1278 1279 unsigned int qtimer_val(const struct adapter *adap, 1280 const struct sge_rspq *q); 1281 1282 int t4_init_devlog_params(struct adapter *adapter); 1283 int t4_init_sge_params(struct adapter *adapter); 1284 int t4_init_tp_params(struct adapter *adap); 1285 int t4_filter_field_shift(const struct adapter *adap, int filter_sel); 1286 int t4_init_rss_mode(struct adapter *adap, int mbox); 1287 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf); 1288 void t4_fatal_err(struct adapter *adapter); 1289 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 1290 int start, int n, const u16 *rspq, unsigned int nrspq); 1291 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 1292 unsigned int flags); 1293 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 1294 unsigned int flags, unsigned int defq); 1295 int t4_read_rss(struct adapter *adapter, u16 *entries); 1296 void t4_read_rss_key(struct adapter *adapter, u32 *key); 1297 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx); 1298 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, 1299 u32 *valp); 1300 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 1301 u32 *vfl, u32 *vfh); 1302 u32 t4_read_rss_pf_map(struct adapter *adapter); 1303 u32 t4_read_rss_pf_mask(struct adapter *adapter); 1304 1305 unsigned int t4_get_mps_bg_map(struct adapter *adapter, int idx); 1306 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1307 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1308 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, 1309 size_t n); 1310 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, 1311 size_t n); 1312 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 1313 unsigned int *valp); 1314 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 1315 const unsigned int *valp); 1316 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr); 1317 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, 1318 unsigned int *pif_req_wrptr, 1319 unsigned int *pif_rsp_wrptr); 1320 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp); 1321 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres); 1322 const char *t4_get_port_type_description(enum fw_port_type port_type); 1323 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); 1324 void t4_get_port_stats_offset(struct adapter *adap, int idx, 1325 struct port_stats *stats, 1326 struct port_stats *offset); 1327 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p); 1328 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); 1329 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]); 1330 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 1331 unsigned int mask, unsigned int val); 1332 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr); 1333 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st); 1334 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st); 1335 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st); 1336 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st); 1337 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 1338 struct tp_tcp_stats *v6); 1339 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 1340 struct tp_fcoe_stats *st); 1341 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 1342 const unsigned short *alpha, const unsigned short *beta); 1343 1344 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf); 1345 1346 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate); 1347 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid); 1348 1349 void t4_wol_magic_enable(struct adapter *adap, unsigned int port, 1350 const u8 *addr); 1351 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 1352 u64 mask0, u64 mask1, unsigned int crc, bool enable); 1353 1354 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 1355 enum dev_master master, enum dev_state *state); 1356 int t4_fw_bye(struct adapter *adap, unsigned int mbox); 1357 int t4_early_init(struct adapter *adap, unsigned int mbox); 1358 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); 1359 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, 1360 unsigned int cache_line_size); 1361 int t4_fw_initialize(struct adapter *adap, unsigned int mbox); 1362 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1363 unsigned int vf, unsigned int nparams, const u32 *params, 1364 u32 *val); 1365 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, 1366 unsigned int vf, unsigned int nparams, const u32 *params, 1367 u32 *val, int rw); 1368 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 1369 unsigned int pf, unsigned int vf, 1370 unsigned int nparams, const u32 *params, 1371 const u32 *val, int timeout); 1372 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1373 unsigned int vf, unsigned int nparams, const u32 *params, 1374 const u32 *val); 1375 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 1376 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 1377 unsigned int rxqi, unsigned int rxq, unsigned int tc, 1378 unsigned int vi, unsigned int cmask, unsigned int pmask, 1379 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps); 1380 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 1381 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 1382 unsigned int *rss_size); 1383 int t4_free_vi(struct adapter *adap, unsigned int mbox, 1384 unsigned int pf, unsigned int vf, 1385 unsigned int viid); 1386 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 1387 int mtu, int promisc, int all_multi, int bcast, int vlanex, 1388 bool sleep_ok); 1389 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, 1390 unsigned int viid, bool free, unsigned int naddr, 1391 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok); 1392 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 1393 int idx, const u8 *addr, bool persist, bool add_smt); 1394 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 1395 bool ucast, u64 vec, bool sleep_ok); 1396 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 1397 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en); 1398 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 1399 bool rx_en, bool tx_en); 1400 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 1401 unsigned int nblinks); 1402 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1403 unsigned int mmd, unsigned int reg, u16 *valp); 1404 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1405 unsigned int mmd, unsigned int reg, u16 val); 1406 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1407 unsigned int vf, unsigned int iqtype, unsigned int iqid, 1408 unsigned int fl0id, unsigned int fl1id); 1409 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1410 unsigned int vf, unsigned int eqid); 1411 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1412 unsigned int vf, unsigned int eqid); 1413 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1414 unsigned int vf, unsigned int eqid); 1415 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox); 1416 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); 1417 void t4_db_full(struct adapter *adapter); 1418 void t4_db_dropped(struct adapter *adapter); 1419 int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp, 1420 int filter_index, int enable); 1421 void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp, 1422 int filter_index, int *enabled); 1423 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, 1424 u32 addr, u32 val); 1425 void t4_sge_decode_idma_state(struct adapter *adapter, int state); 1426 void t4_free_mem(void *addr); 1427 void t4_idma_monitor_init(struct adapter *adapter, 1428 struct sge_idma_monitor_state *idma); 1429 void t4_idma_monitor(struct adapter *adapter, 1430 struct sge_idma_monitor_state *idma, 1431 int hz, int ticks); 1432 #endif /* __CXGB4_H__ */ 1433