1 /* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #ifndef __CXGB4_H__ 36 #define __CXGB4_H__ 37 38 #include "t4_hw.h" 39 40 #include <linux/bitops.h> 41 #include <linux/cache.h> 42 #include <linux/interrupt.h> 43 #include <linux/list.h> 44 #include <linux/netdevice.h> 45 #include <linux/pci.h> 46 #include <linux/spinlock.h> 47 #include <linux/timer.h> 48 #include <linux/vmalloc.h> 49 #include <linux/etherdevice.h> 50 #include <linux/net_tstamp.h> 51 #include <linux/ptp_clock_kernel.h> 52 #include <linux/ptp_classify.h> 53 #include <asm/io.h> 54 #include "t4_chip_type.h" 55 #include "cxgb4_uld.h" 56 57 #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__) 58 extern struct list_head adapter_list; 59 extern struct mutex uld_mutex; 60 61 enum { 62 MAX_NPORTS = 4, /* max # of ports */ 63 SERNUM_LEN = 24, /* Serial # length */ 64 EC_LEN = 16, /* E/C length */ 65 ID_LEN = 16, /* ID length */ 66 PN_LEN = 16, /* Part Number length */ 67 MACADDR_LEN = 12, /* MAC Address length */ 68 }; 69 70 enum { 71 T4_REGMAP_SIZE = (160 * 1024), 72 T5_REGMAP_SIZE = (332 * 1024), 73 }; 74 75 enum { 76 MEM_EDC0, 77 MEM_EDC1, 78 MEM_MC, 79 MEM_MC0 = MEM_MC, 80 MEM_MC1 81 }; 82 83 enum { 84 MEMWIN0_APERTURE = 2048, 85 MEMWIN0_BASE = 0x1b800, 86 MEMWIN1_APERTURE = 32768, 87 MEMWIN1_BASE = 0x28000, 88 MEMWIN1_BASE_T5 = 0x52000, 89 MEMWIN2_APERTURE = 65536, 90 MEMWIN2_BASE = 0x30000, 91 MEMWIN2_APERTURE_T5 = 131072, 92 MEMWIN2_BASE_T5 = 0x60000, 93 }; 94 95 enum dev_master { 96 MASTER_CANT, 97 MASTER_MAY, 98 MASTER_MUST 99 }; 100 101 enum dev_state { 102 DEV_STATE_UNINIT, 103 DEV_STATE_INIT, 104 DEV_STATE_ERR 105 }; 106 107 enum cc_pause { 108 PAUSE_RX = 1 << 0, 109 PAUSE_TX = 1 << 1, 110 PAUSE_AUTONEG = 1 << 2 111 }; 112 113 enum cc_fec { 114 FEC_AUTO = 1 << 0, /* IEEE 802.3 "automatic" */ 115 FEC_RS = 1 << 1, /* Reed-Solomon */ 116 FEC_BASER_RS = 1 << 2 /* BaseR/Reed-Solomon */ 117 }; 118 119 struct port_stats { 120 u64 tx_octets; /* total # of octets in good frames */ 121 u64 tx_frames; /* all good frames */ 122 u64 tx_bcast_frames; /* all broadcast frames */ 123 u64 tx_mcast_frames; /* all multicast frames */ 124 u64 tx_ucast_frames; /* all unicast frames */ 125 u64 tx_error_frames; /* all error frames */ 126 127 u64 tx_frames_64; /* # of Tx frames in a particular range */ 128 u64 tx_frames_65_127; 129 u64 tx_frames_128_255; 130 u64 tx_frames_256_511; 131 u64 tx_frames_512_1023; 132 u64 tx_frames_1024_1518; 133 u64 tx_frames_1519_max; 134 135 u64 tx_drop; /* # of dropped Tx frames */ 136 u64 tx_pause; /* # of transmitted pause frames */ 137 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ 138 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ 139 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ 140 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ 141 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ 142 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ 143 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ 144 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ 145 146 u64 rx_octets; /* total # of octets in good frames */ 147 u64 rx_frames; /* all good frames */ 148 u64 rx_bcast_frames; /* all broadcast frames */ 149 u64 rx_mcast_frames; /* all multicast frames */ 150 u64 rx_ucast_frames; /* all unicast frames */ 151 u64 rx_too_long; /* # of frames exceeding MTU */ 152 u64 rx_jabber; /* # of jabber frames */ 153 u64 rx_fcs_err; /* # of received frames with bad FCS */ 154 u64 rx_len_err; /* # of received frames with length error */ 155 u64 rx_symbol_err; /* symbol errors */ 156 u64 rx_runt; /* # of short frames */ 157 158 u64 rx_frames_64; /* # of Rx frames in a particular range */ 159 u64 rx_frames_65_127; 160 u64 rx_frames_128_255; 161 u64 rx_frames_256_511; 162 u64 rx_frames_512_1023; 163 u64 rx_frames_1024_1518; 164 u64 rx_frames_1519_max; 165 166 u64 rx_pause; /* # of received pause frames */ 167 u64 rx_ppp0; /* # of received PPP prio 0 frames */ 168 u64 rx_ppp1; /* # of received PPP prio 1 frames */ 169 u64 rx_ppp2; /* # of received PPP prio 2 frames */ 170 u64 rx_ppp3; /* # of received PPP prio 3 frames */ 171 u64 rx_ppp4; /* # of received PPP prio 4 frames */ 172 u64 rx_ppp5; /* # of received PPP prio 5 frames */ 173 u64 rx_ppp6; /* # of received PPP prio 6 frames */ 174 u64 rx_ppp7; /* # of received PPP prio 7 frames */ 175 176 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ 177 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ 178 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ 179 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ 180 u64 rx_trunc0; /* buffer-group 0 truncated packets */ 181 u64 rx_trunc1; /* buffer-group 1 truncated packets */ 182 u64 rx_trunc2; /* buffer-group 2 truncated packets */ 183 u64 rx_trunc3; /* buffer-group 3 truncated packets */ 184 }; 185 186 struct lb_port_stats { 187 u64 octets; 188 u64 frames; 189 u64 bcast_frames; 190 u64 mcast_frames; 191 u64 ucast_frames; 192 u64 error_frames; 193 194 u64 frames_64; 195 u64 frames_65_127; 196 u64 frames_128_255; 197 u64 frames_256_511; 198 u64 frames_512_1023; 199 u64 frames_1024_1518; 200 u64 frames_1519_max; 201 202 u64 drop; 203 204 u64 ovflow0; 205 u64 ovflow1; 206 u64 ovflow2; 207 u64 ovflow3; 208 u64 trunc0; 209 u64 trunc1; 210 u64 trunc2; 211 u64 trunc3; 212 }; 213 214 struct tp_tcp_stats { 215 u32 tcp_out_rsts; 216 u64 tcp_in_segs; 217 u64 tcp_out_segs; 218 u64 tcp_retrans_segs; 219 }; 220 221 struct tp_usm_stats { 222 u32 frames; 223 u32 drops; 224 u64 octets; 225 }; 226 227 struct tp_fcoe_stats { 228 u32 frames_ddp; 229 u32 frames_drop; 230 u64 octets_ddp; 231 }; 232 233 struct tp_err_stats { 234 u32 mac_in_errs[4]; 235 u32 hdr_in_errs[4]; 236 u32 tcp_in_errs[4]; 237 u32 tnl_cong_drops[4]; 238 u32 ofld_chan_drops[4]; 239 u32 tnl_tx_drops[4]; 240 u32 ofld_vlan_drops[4]; 241 u32 tcp6_in_errs[4]; 242 u32 ofld_no_neigh; 243 u32 ofld_cong_defer; 244 }; 245 246 struct tp_cpl_stats { 247 u32 req[4]; 248 u32 rsp[4]; 249 }; 250 251 struct tp_rdma_stats { 252 u32 rqe_dfr_pkt; 253 u32 rqe_dfr_mod; 254 }; 255 256 struct sge_params { 257 u32 hps; /* host page size for our PF/VF */ 258 u32 eq_qpp; /* egress queues/page for our PF/VF */ 259 u32 iq_qpp; /* egress queues/page for our PF/VF */ 260 }; 261 262 struct tp_params { 263 unsigned int tre; /* log2 of core clocks per TP tick */ 264 unsigned int la_mask; /* what events are recorded by TP LA */ 265 unsigned short tx_modq_map; /* TX modulation scheduler queue to */ 266 /* channel map */ 267 268 uint32_t dack_re; /* DACK timer resolution */ 269 unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */ 270 271 u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */ 272 u32 ingress_config; /* cached TP_INGRESS_CONFIG */ 273 274 /* cached TP_OUT_CONFIG compressed error vector 275 * and passing outer header info for encapsulated packets. 276 */ 277 int rx_pkt_encap; 278 279 /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a 280 * subset of the set of fields which may be present in the Compressed 281 * Filter Tuple portion of filters and TCP TCB connections. The 282 * fields which are present are controlled by the TP_VLAN_PRI_MAP. 283 * Since a variable number of fields may or may not be present, their 284 * shifted field positions within the Compressed Filter Tuple may 285 * vary, or not even be present if the field isn't selected in 286 * TP_VLAN_PRI_MAP. Since some of these fields are needed in various 287 * places we store their offsets here, or a -1 if the field isn't 288 * present. 289 */ 290 int vlan_shift; 291 int vnic_shift; 292 int port_shift; 293 int protocol_shift; 294 }; 295 296 struct vpd_params { 297 unsigned int cclk; 298 u8 ec[EC_LEN + 1]; 299 u8 sn[SERNUM_LEN + 1]; 300 u8 id[ID_LEN + 1]; 301 u8 pn[PN_LEN + 1]; 302 u8 na[MACADDR_LEN + 1]; 303 }; 304 305 struct pci_params { 306 unsigned char speed; 307 unsigned char width; 308 }; 309 310 struct devlog_params { 311 u32 memtype; /* which memory (EDC0, EDC1, MC) */ 312 u32 start; /* start of log in firmware memory */ 313 u32 size; /* size of log */ 314 }; 315 316 /* Stores chip specific parameters */ 317 struct arch_specific_params { 318 u8 nchan; 319 u8 pm_stats_cnt; 320 u8 cng_ch_bits_log; /* congestion channel map bits width */ 321 u16 mps_rplc_size; 322 u16 vfcount; 323 u32 sge_fl_db; 324 u16 mps_tcam_size; 325 }; 326 327 struct adapter_params { 328 struct sge_params sge; 329 struct tp_params tp; 330 struct vpd_params vpd; 331 struct pci_params pci; 332 struct devlog_params devlog; 333 enum pcie_memwin drv_memwin; 334 335 unsigned int cim_la_size; 336 337 unsigned int sf_size; /* serial flash size in bytes */ 338 unsigned int sf_nsec; /* # of flash sectors */ 339 unsigned int sf_fw_start; /* start of FW image in flash */ 340 341 unsigned int fw_vers; /* firmware version */ 342 unsigned int bs_vers; /* bootstrap version */ 343 unsigned int tp_vers; /* TP microcode version */ 344 unsigned int er_vers; /* expansion ROM version */ 345 unsigned int scfg_vers; /* Serial Configuration version */ 346 unsigned int vpd_vers; /* VPD Version */ 347 u8 api_vers[7]; 348 349 unsigned short mtus[NMTUS]; 350 unsigned short a_wnd[NCCTRL_WIN]; 351 unsigned short b_wnd[NCCTRL_WIN]; 352 353 unsigned char nports; /* # of ethernet ports */ 354 unsigned char portvec; 355 enum chip_type chip; /* chip code */ 356 struct arch_specific_params arch; /* chip specific params */ 357 unsigned char offload; 358 unsigned char crypto; /* HW capability for crypto */ 359 360 unsigned char bypass; 361 362 unsigned int ofldq_wr_cred; 363 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ 364 365 unsigned int nsched_cls; /* number of traffic classes */ 366 unsigned int max_ordird_qp; /* Max read depth per RDMA QP */ 367 unsigned int max_ird_adapter; /* Max read depth per adapter */ 368 bool fr_nsmr_tpte_wr_support; /* FW support for FR_NSMR_TPTE_WR */ 369 u8 fw_caps_support; /* 32-bit Port Capabilities */ 370 371 /* MPS Buffer Group Map[per Port]. Bit i is set if buffer group i is 372 * used by the Port 373 */ 374 u8 mps_bg_map[MAX_NPORTS]; /* MPS Buffer Group Map */ 375 }; 376 377 /* State needed to monitor the forward progress of SGE Ingress DMA activities 378 * and possible hangs. 379 */ 380 struct sge_idma_monitor_state { 381 unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */ 382 unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */ 383 unsigned int idma_state[2]; /* IDMA Hang detect state */ 384 unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */ 385 unsigned int idma_warn[2]; /* time to warning in HZ */ 386 }; 387 388 /* Firmware Mailbox Command/Reply log. All values are in Host-Endian format. 389 * The access and execute times are signed in order to accommodate negative 390 * error returns. 391 */ 392 struct mbox_cmd { 393 u64 cmd[MBOX_LEN / 8]; /* a Firmware Mailbox Command/Reply */ 394 u64 timestamp; /* OS-dependent timestamp */ 395 u32 seqno; /* sequence number */ 396 s16 access; /* time (ms) to access mailbox */ 397 s16 execute; /* time (ms) to execute */ 398 }; 399 400 struct mbox_cmd_log { 401 unsigned int size; /* number of entries in the log */ 402 unsigned int cursor; /* next position in the log to write */ 403 u32 seqno; /* next sequence number */ 404 /* variable length mailbox command log starts here */ 405 }; 406 407 /* Given a pointer to a Firmware Mailbox Command Log and a log entry index, 408 * return a pointer to the specified entry. 409 */ 410 static inline struct mbox_cmd *mbox_cmd_log_entry(struct mbox_cmd_log *log, 411 unsigned int entry_idx) 412 { 413 return &((struct mbox_cmd *)&(log)[1])[entry_idx]; 414 } 415 416 #include "t4fw_api.h" 417 418 #define FW_VERSION(chip) ( \ 419 FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \ 420 FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \ 421 FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \ 422 FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD)) 423 #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf) 424 425 struct fw_info { 426 u8 chip; 427 char *fs_name; 428 char *fw_mod_name; 429 struct fw_hdr fw_hdr; 430 }; 431 432 struct trace_params { 433 u32 data[TRACE_LEN / 4]; 434 u32 mask[TRACE_LEN / 4]; 435 unsigned short snap_len; 436 unsigned short min_len; 437 unsigned char skip_ofst; 438 unsigned char skip_len; 439 unsigned char invert; 440 unsigned char port; 441 }; 442 443 /* Firmware Port Capabilities types. */ 444 445 typedef u16 fw_port_cap16_t; /* 16-bit Port Capabilities integral value */ 446 typedef u32 fw_port_cap32_t; /* 32-bit Port Capabilities integral value */ 447 448 enum fw_caps { 449 FW_CAPS_UNKNOWN = 0, /* 0'ed out initial state */ 450 FW_CAPS16 = 1, /* old Firmware: 16-bit Port Capabilities */ 451 FW_CAPS32 = 2, /* new Firmware: 32-bit Port Capabilities */ 452 }; 453 454 struct link_config { 455 fw_port_cap32_t pcaps; /* link capabilities */ 456 fw_port_cap32_t def_acaps; /* default advertised capabilities */ 457 fw_port_cap32_t acaps; /* advertised capabilities */ 458 fw_port_cap32_t lpacaps; /* peer advertised capabilities */ 459 460 fw_port_cap32_t speed_caps; /* speed(s) user has requested */ 461 unsigned int speed; /* actual link speed (Mb/s) */ 462 463 enum cc_pause requested_fc; /* flow control user has requested */ 464 enum cc_pause fc; /* actual link flow control */ 465 466 enum cc_fec requested_fec; /* Forward Error Correction: */ 467 enum cc_fec fec; /* requested and actual in use */ 468 469 unsigned char autoneg; /* autonegotiating? */ 470 471 unsigned char link_ok; /* link up? */ 472 unsigned char link_down_rc; /* link down reason */ 473 }; 474 475 #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16) 476 477 enum { 478 MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */ 479 MAX_OFLD_QSETS = 16, /* # of offload Tx, iscsi Rx queue sets */ 480 MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */ 481 }; 482 483 enum { 484 MAX_TXQ_ENTRIES = 16384, 485 MAX_CTRL_TXQ_ENTRIES = 1024, 486 MAX_RSPQ_ENTRIES = 16384, 487 MAX_RX_BUFFERS = 16384, 488 MIN_TXQ_ENTRIES = 32, 489 MIN_CTRL_TXQ_ENTRIES = 32, 490 MIN_RSPQ_ENTRIES = 128, 491 MIN_FL_ENTRIES = 16 492 }; 493 494 enum { 495 INGQ_EXTRAS = 2, /* firmware event queue and */ 496 /* forwarded interrupts */ 497 MAX_INGQ = MAX_ETH_QSETS + INGQ_EXTRAS, 498 }; 499 500 struct adapter; 501 struct sge_rspq; 502 503 #include "cxgb4_dcb.h" 504 505 #ifdef CONFIG_CHELSIO_T4_FCOE 506 #include "cxgb4_fcoe.h" 507 #endif /* CONFIG_CHELSIO_T4_FCOE */ 508 509 struct port_info { 510 struct adapter *adapter; 511 u16 viid; 512 s16 xact_addr_filt; /* index of exact MAC address filter */ 513 u16 rss_size; /* size of VI's RSS table slice */ 514 s8 mdio_addr; 515 enum fw_port_type port_type; 516 u8 mod_type; 517 u8 port_id; 518 u8 tx_chan; 519 u8 lport; /* associated offload logical port */ 520 u8 nqsets; /* # of qsets */ 521 u8 first_qset; /* index of first qset */ 522 u8 rss_mode; 523 struct link_config link_cfg; 524 u16 *rss; 525 struct port_stats stats_base; 526 #ifdef CONFIG_CHELSIO_T4_DCB 527 struct port_dcb_info dcb; /* Data Center Bridging support */ 528 #endif 529 #ifdef CONFIG_CHELSIO_T4_FCOE 530 struct cxgb_fcoe fcoe; 531 #endif /* CONFIG_CHELSIO_T4_FCOE */ 532 bool rxtstamp; /* Enable TS */ 533 struct hwtstamp_config tstamp_config; 534 bool ptp_enable; 535 struct sched_table *sched_tbl; 536 }; 537 538 struct dentry; 539 struct work_struct; 540 541 enum { /* adapter flags */ 542 FULL_INIT_DONE = (1 << 0), 543 DEV_ENABLED = (1 << 1), 544 USING_MSI = (1 << 2), 545 USING_MSIX = (1 << 3), 546 FW_OK = (1 << 4), 547 RSS_TNLALLLOOKUP = (1 << 5), 548 USING_SOFT_PARAMS = (1 << 6), 549 MASTER_PF = (1 << 7), 550 FW_OFLD_CONN = (1 << 9), 551 ROOT_NO_RELAXED_ORDERING = (1 << 10), 552 SHUTTING_DOWN = (1 << 11), 553 }; 554 555 enum { 556 ULP_CRYPTO_LOOKASIDE = 1 << 0, 557 }; 558 559 struct rx_sw_desc; 560 561 struct sge_fl { /* SGE free-buffer queue state */ 562 unsigned int avail; /* # of available Rx buffers */ 563 unsigned int pend_cred; /* new buffers since last FL DB ring */ 564 unsigned int cidx; /* consumer index */ 565 unsigned int pidx; /* producer index */ 566 unsigned long alloc_failed; /* # of times buffer allocation failed */ 567 unsigned long large_alloc_failed; 568 unsigned long mapping_err; /* # of RX Buffer DMA Mapping failures */ 569 unsigned long low; /* # of times momentarily starving */ 570 unsigned long starving; 571 /* RO fields */ 572 unsigned int cntxt_id; /* SGE context id for the free list */ 573 unsigned int size; /* capacity of free list */ 574 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */ 575 __be64 *desc; /* address of HW Rx descriptor ring */ 576 dma_addr_t addr; /* bus address of HW ring start */ 577 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 578 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 579 }; 580 581 /* A packet gather list */ 582 struct pkt_gl { 583 u64 sgetstamp; /* SGE Time Stamp for Ingress Packet */ 584 struct page_frag frags[MAX_SKB_FRAGS]; 585 void *va; /* virtual address of first byte */ 586 unsigned int nfrags; /* # of fragments */ 587 unsigned int tot_len; /* total length of fragments */ 588 }; 589 590 typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp, 591 const struct pkt_gl *gl); 592 typedef void (*rspq_flush_handler_t)(struct sge_rspq *q); 593 /* LRO related declarations for ULD */ 594 struct t4_lro_mgr { 595 #define MAX_LRO_SESSIONS 64 596 u8 lro_session_cnt; /* # of sessions to aggregate */ 597 unsigned long lro_pkts; /* # of LRO super packets */ 598 unsigned long lro_merged; /* # of wire packets merged by LRO */ 599 struct sk_buff_head lroq; /* list of aggregated sessions */ 600 }; 601 602 struct sge_rspq { /* state for an SGE response queue */ 603 struct napi_struct napi; 604 const __be64 *cur_desc; /* current descriptor in queue */ 605 unsigned int cidx; /* consumer index */ 606 u8 gen; /* current generation bit */ 607 u8 intr_params; /* interrupt holdoff parameters */ 608 u8 next_intr_params; /* holdoff params for next interrupt */ 609 u8 adaptive_rx; 610 u8 pktcnt_idx; /* interrupt packet threshold */ 611 u8 uld; /* ULD handling this queue */ 612 u8 idx; /* queue index within its group */ 613 int offset; /* offset into current Rx buffer */ 614 u16 cntxt_id; /* SGE context id for the response q */ 615 u16 abs_id; /* absolute SGE id for the response q */ 616 __be64 *desc; /* address of HW response ring */ 617 dma_addr_t phys_addr; /* physical address of the ring */ 618 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 619 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 620 unsigned int iqe_len; /* entry size */ 621 unsigned int size; /* capacity of response queue */ 622 struct adapter *adap; 623 struct net_device *netdev; /* associated net device */ 624 rspq_handler_t handler; 625 rspq_flush_handler_t flush_handler; 626 struct t4_lro_mgr lro_mgr; 627 }; 628 629 struct sge_eth_stats { /* Ethernet queue statistics */ 630 unsigned long pkts; /* # of ethernet packets */ 631 unsigned long lro_pkts; /* # of LRO super packets */ 632 unsigned long lro_merged; /* # of wire packets merged by LRO */ 633 unsigned long rx_cso; /* # of Rx checksum offloads */ 634 unsigned long vlan_ex; /* # of Rx VLAN extractions */ 635 unsigned long rx_drops; /* # of packets dropped due to no mem */ 636 }; 637 638 struct sge_eth_rxq { /* SW Ethernet Rx queue */ 639 struct sge_rspq rspq; 640 struct sge_fl fl; 641 struct sge_eth_stats stats; 642 } ____cacheline_aligned_in_smp; 643 644 struct sge_ofld_stats { /* offload queue statistics */ 645 unsigned long pkts; /* # of packets */ 646 unsigned long imm; /* # of immediate-data packets */ 647 unsigned long an; /* # of asynchronous notifications */ 648 unsigned long nomem; /* # of responses deferred due to no mem */ 649 }; 650 651 struct sge_ofld_rxq { /* SW offload Rx queue */ 652 struct sge_rspq rspq; 653 struct sge_fl fl; 654 struct sge_ofld_stats stats; 655 } ____cacheline_aligned_in_smp; 656 657 struct tx_desc { 658 __be64 flit[8]; 659 }; 660 661 struct tx_sw_desc; 662 663 struct sge_txq { 664 unsigned int in_use; /* # of in-use Tx descriptors */ 665 unsigned int q_type; /* Q type Eth/Ctrl/Ofld */ 666 unsigned int size; /* # of descriptors */ 667 unsigned int cidx; /* SW consumer index */ 668 unsigned int pidx; /* producer index */ 669 unsigned long stops; /* # of times q has been stopped */ 670 unsigned long restarts; /* # of queue restarts */ 671 unsigned int cntxt_id; /* SGE context id for the Tx q */ 672 struct tx_desc *desc; /* address of HW Tx descriptor ring */ 673 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */ 674 struct sge_qstat *stat; /* queue status entry */ 675 dma_addr_t phys_addr; /* physical address of the ring */ 676 spinlock_t db_lock; 677 int db_disabled; 678 unsigned short db_pidx; 679 unsigned short db_pidx_inc; 680 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 681 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 682 }; 683 684 struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */ 685 struct sge_txq q; 686 struct netdev_queue *txq; /* associated netdev TX queue */ 687 #ifdef CONFIG_CHELSIO_T4_DCB 688 u8 dcb_prio; /* DCB Priority bound to queue */ 689 #endif 690 unsigned long tso; /* # of TSO requests */ 691 unsigned long tx_cso; /* # of Tx checksum offloads */ 692 unsigned long vlan_ins; /* # of Tx VLAN insertions */ 693 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 694 } ____cacheline_aligned_in_smp; 695 696 struct sge_uld_txq { /* state for an SGE offload Tx queue */ 697 struct sge_txq q; 698 struct adapter *adap; 699 struct sk_buff_head sendq; /* list of backpressured packets */ 700 struct tasklet_struct qresume_tsk; /* restarts the queue */ 701 bool service_ofldq_running; /* service_ofldq() is processing sendq */ 702 u8 full; /* the Tx ring is full */ 703 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 704 } ____cacheline_aligned_in_smp; 705 706 struct sge_ctrl_txq { /* state for an SGE control Tx queue */ 707 struct sge_txq q; 708 struct adapter *adap; 709 struct sk_buff_head sendq; /* list of backpressured packets */ 710 struct tasklet_struct qresume_tsk; /* restarts the queue */ 711 u8 full; /* the Tx ring is full */ 712 } ____cacheline_aligned_in_smp; 713 714 struct sge_uld_rxq_info { 715 char name[IFNAMSIZ]; /* name of ULD driver */ 716 struct sge_ofld_rxq *uldrxq; /* Rxq's for ULD */ 717 u16 *msix_tbl; /* msix_tbl for uld */ 718 u16 *rspq_id; /* response queue id's of rxq */ 719 u16 nrxq; /* # of ingress uld queues */ 720 u16 nciq; /* # of completion queues */ 721 u8 uld; /* uld type */ 722 }; 723 724 struct sge_uld_txq_info { 725 struct sge_uld_txq *uldtxq; /* Txq's for ULD */ 726 atomic_t users; /* num users */ 727 u16 ntxq; /* # of egress uld queues */ 728 }; 729 730 struct sge { 731 struct sge_eth_txq ethtxq[MAX_ETH_QSETS]; 732 struct sge_eth_txq ptptxq; 733 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES]; 734 735 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS]; 736 struct sge_rspq fw_evtq ____cacheline_aligned_in_smp; 737 struct sge_uld_rxq_info **uld_rxq_info; 738 struct sge_uld_txq_info **uld_txq_info; 739 740 struct sge_rspq intrq ____cacheline_aligned_in_smp; 741 spinlock_t intrq_lock; 742 743 u16 max_ethqsets; /* # of available Ethernet queue sets */ 744 u16 ethqsets; /* # of active Ethernet queue sets */ 745 u16 ethtxq_rover; /* Tx queue to clean up next */ 746 u16 ofldqsets; /* # of active ofld queue sets */ 747 u16 nqs_per_uld; /* # of Rx queues per ULD */ 748 u16 timer_val[SGE_NTIMERS]; 749 u8 counter_val[SGE_NCOUNTERS]; 750 u32 fl_pg_order; /* large page allocation size */ 751 u32 stat_len; /* length of status page at ring end */ 752 u32 pktshift; /* padding between CPL & packet data */ 753 u32 fl_align; /* response queue message alignment */ 754 u32 fl_starve_thres; /* Free List starvation threshold */ 755 756 struct sge_idma_monitor_state idma_monitor; 757 unsigned int egr_start; 758 unsigned int egr_sz; 759 unsigned int ingr_start; 760 unsigned int ingr_sz; 761 void **egr_map; /* qid->queue egress queue map */ 762 struct sge_rspq **ingr_map; /* qid->queue ingress queue map */ 763 unsigned long *starving_fl; 764 unsigned long *txq_maperr; 765 unsigned long *blocked_fl; 766 struct timer_list rx_timer; /* refills starving FLs */ 767 struct timer_list tx_timer; /* checks Tx queues */ 768 }; 769 770 #define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++) 771 #define for_each_ofldtxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++) 772 773 struct l2t_data; 774 775 #ifdef CONFIG_PCI_IOV 776 777 /* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial 778 * Configuration initialization for T5 only has SR-IOV functionality enabled 779 * on PF0-3 in order to simplify everything. 780 */ 781 #define NUM_OF_PF_WITH_SRIOV 4 782 783 #endif 784 785 struct doorbell_stats { 786 u32 db_drop; 787 u32 db_empty; 788 u32 db_full; 789 }; 790 791 struct hash_mac_addr { 792 struct list_head list; 793 u8 addr[ETH_ALEN]; 794 }; 795 796 struct uld_msix_bmap { 797 unsigned long *msix_bmap; 798 unsigned int mapsize; 799 spinlock_t lock; /* lock for acquiring bitmap */ 800 }; 801 802 struct uld_msix_info { 803 unsigned short vec; 804 char desc[IFNAMSIZ + 10]; 805 unsigned int idx; 806 }; 807 808 struct vf_info { 809 unsigned char vf_mac_addr[ETH_ALEN]; 810 unsigned int tx_rate; 811 bool pf_set_mac; 812 }; 813 814 struct mbox_list { 815 struct list_head list; 816 }; 817 818 struct adapter { 819 void __iomem *regs; 820 void __iomem *bar2; 821 u32 t4_bar0; 822 struct pci_dev *pdev; 823 struct device *pdev_dev; 824 const char *name; 825 unsigned int mbox; 826 unsigned int pf; 827 unsigned int flags; 828 unsigned int adap_idx; 829 enum chip_type chip; 830 831 int msg_enable; 832 833 struct adapter_params params; 834 struct cxgb4_virt_res vres; 835 unsigned int swintr; 836 837 struct { 838 unsigned short vec; 839 char desc[IFNAMSIZ + 10]; 840 } msix_info[MAX_INGQ + 1]; 841 struct uld_msix_info *msix_info_ulds; /* msix info for uld's */ 842 struct uld_msix_bmap msix_bmap_ulds; /* msix bitmap for all uld */ 843 int msi_idx; 844 845 struct doorbell_stats db_stats; 846 struct sge sge; 847 848 struct net_device *port[MAX_NPORTS]; 849 u8 chan_map[NCHAN]; /* channel -> port map */ 850 851 struct vf_info *vfinfo; 852 u8 num_vfs; 853 854 u32 filter_mode; 855 unsigned int l2t_start; 856 unsigned int l2t_end; 857 struct l2t_data *l2t; 858 unsigned int clipt_start; 859 unsigned int clipt_end; 860 struct clip_tbl *clipt; 861 struct cxgb4_uld_info *uld; 862 void *uld_handle[CXGB4_ULD_MAX]; 863 unsigned int num_uld; 864 unsigned int num_ofld_uld; 865 struct list_head list_node; 866 struct list_head rcu_node; 867 struct list_head mac_hlist; /* list of MAC addresses in MPS Hash */ 868 869 void *iscsi_ppm; 870 871 struct tid_info tids; 872 void **tid_release_head; 873 spinlock_t tid_release_lock; 874 struct workqueue_struct *workq; 875 struct work_struct tid_release_task; 876 struct work_struct db_full_task; 877 struct work_struct db_drop_task; 878 bool tid_release_task_busy; 879 880 /* lock for mailbox cmd list */ 881 spinlock_t mbox_lock; 882 struct mbox_list mlist; 883 884 /* support for mailbox command/reply logging */ 885 #define T4_OS_LOG_MBOX_CMDS 256 886 struct mbox_cmd_log *mbox_log; 887 888 struct mutex uld_mutex; 889 890 struct dentry *debugfs_root; 891 bool use_bd; /* Use SGE Back Door intfc for reading SGE Contexts */ 892 bool trace_rss; /* 1 implies that different RSS flit per filter is 893 * used per filter else if 0 default RSS flit is 894 * used for all 4 filters. 895 */ 896 897 struct ptp_clock *ptp_clock; 898 struct ptp_clock_info ptp_clock_info; 899 struct sk_buff *ptp_tx_skb; 900 /* ptp lock */ 901 spinlock_t ptp_lock; 902 spinlock_t stats_lock; 903 spinlock_t win0_lock ____cacheline_aligned_in_smp; 904 905 /* TC u32 offload */ 906 struct cxgb4_tc_u32_table *tc_u32; 907 struct chcr_stats_debug chcr_stats; 908 909 /* TC flower offload */ 910 DECLARE_HASHTABLE(flower_anymatch_tbl, 9); 911 struct timer_list flower_stats_timer; 912 913 /* Ethtool Dump */ 914 struct ethtool_dump eth_dump; 915 }; 916 917 /* Support for "sched-class" command to allow a TX Scheduling Class to be 918 * programmed with various parameters. 919 */ 920 struct ch_sched_params { 921 s8 type; /* packet or flow */ 922 union { 923 struct { 924 s8 level; /* scheduler hierarchy level */ 925 s8 mode; /* per-class or per-flow */ 926 s8 rateunit; /* bit or packet rate */ 927 s8 ratemode; /* %port relative or kbps absolute */ 928 s8 channel; /* scheduler channel [0..N] */ 929 s8 class; /* scheduler class [0..N] */ 930 s32 minrate; /* minimum rate */ 931 s32 maxrate; /* maximum rate */ 932 s16 weight; /* percent weight */ 933 s16 pktsize; /* average packet size */ 934 } params; 935 } u; 936 }; 937 938 enum { 939 SCHED_CLASS_TYPE_PACKET = 0, /* class type */ 940 }; 941 942 enum { 943 SCHED_CLASS_LEVEL_CL_RL = 0, /* class rate limiter */ 944 }; 945 946 enum { 947 SCHED_CLASS_MODE_CLASS = 0, /* per-class scheduling */ 948 }; 949 950 enum { 951 SCHED_CLASS_RATEUNIT_BITS = 0, /* bit rate scheduling */ 952 }; 953 954 enum { 955 SCHED_CLASS_RATEMODE_ABS = 1, /* Kb/s */ 956 }; 957 958 /* Support for "sched_queue" command to allow one or more NIC TX Queues 959 * to be bound to a TX Scheduling Class. 960 */ 961 struct ch_sched_queue { 962 s8 queue; /* queue index */ 963 s8 class; /* class index */ 964 }; 965 966 /* Defined bit width of user definable filter tuples 967 */ 968 #define ETHTYPE_BITWIDTH 16 969 #define FRAG_BITWIDTH 1 970 #define MACIDX_BITWIDTH 9 971 #define FCOE_BITWIDTH 1 972 #define IPORT_BITWIDTH 3 973 #define MATCHTYPE_BITWIDTH 3 974 #define PROTO_BITWIDTH 8 975 #define TOS_BITWIDTH 8 976 #define PF_BITWIDTH 8 977 #define VF_BITWIDTH 8 978 #define IVLAN_BITWIDTH 16 979 #define OVLAN_BITWIDTH 16 980 981 /* Filter matching rules. These consist of a set of ingress packet field 982 * (value, mask) tuples. The associated ingress packet field matches the 983 * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field 984 * rule can be constructed by specifying a tuple of (0, 0).) A filter rule 985 * matches an ingress packet when all of the individual individual field 986 * matching rules are true. 987 * 988 * Partial field masks are always valid, however, while it may be easy to 989 * understand their meanings for some fields (e.g. IP address to match a 990 * subnet), for others making sensible partial masks is less intuitive (e.g. 991 * MPS match type) ... 992 * 993 * Most of the following data structures are modeled on T4 capabilities. 994 * Drivers for earlier chips use the subsets which make sense for those chips. 995 * We really need to come up with a hardware-independent mechanism to 996 * represent hardware filter capabilities ... 997 */ 998 struct ch_filter_tuple { 999 /* Compressed header matching field rules. The TP_VLAN_PRI_MAP 1000 * register selects which of these fields will participate in the 1001 * filter match rules -- up to a maximum of 36 bits. Because 1002 * TP_VLAN_PRI_MAP is a global register, all filters must use the same 1003 * set of fields. 1004 */ 1005 uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */ 1006 uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */ 1007 uint32_t ivlan_vld:1; /* inner VLAN valid */ 1008 uint32_t ovlan_vld:1; /* outer VLAN valid */ 1009 uint32_t pfvf_vld:1; /* PF/VF valid */ 1010 uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */ 1011 uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */ 1012 uint32_t iport:IPORT_BITWIDTH; /* ingress port */ 1013 uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */ 1014 uint32_t proto:PROTO_BITWIDTH; /* protocol type */ 1015 uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */ 1016 uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */ 1017 uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */ 1018 uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */ 1019 uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */ 1020 1021 /* Uncompressed header matching field rules. These are always 1022 * available for field rules. 1023 */ 1024 uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */ 1025 uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */ 1026 uint16_t lport; /* local port */ 1027 uint16_t fport; /* foreign port */ 1028 }; 1029 1030 /* A filter ioctl command. 1031 */ 1032 struct ch_filter_specification { 1033 /* Administrative fields for filter. 1034 */ 1035 uint32_t hitcnts:1; /* count filter hits in TCB */ 1036 uint32_t prio:1; /* filter has priority over active/server */ 1037 1038 /* Fundamental filter typing. This is the one element of filter 1039 * matching that doesn't exist as a (value, mask) tuple. 1040 */ 1041 uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */ 1042 1043 /* Packet dispatch information. Ingress packets which match the 1044 * filter rules will be dropped, passed to the host or switched back 1045 * out as egress packets. 1046 */ 1047 uint32_t action:2; /* drop, pass, switch */ 1048 1049 uint32_t rpttid:1; /* report TID in RSS hash field */ 1050 1051 uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */ 1052 uint32_t iq:10; /* ingress queue */ 1053 1054 uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */ 1055 uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */ 1056 /* 1 => TCB contains IQ ID */ 1057 1058 /* Switch proxy/rewrite fields. An ingress packet which matches a 1059 * filter with "switch" set will be looped back out as an egress 1060 * packet -- potentially with some Ethernet header rewriting. 1061 */ 1062 uint32_t eport:2; /* egress port to switch packet out */ 1063 uint32_t newdmac:1; /* rewrite destination MAC address */ 1064 uint32_t newsmac:1; /* rewrite source MAC address */ 1065 uint32_t newvlan:2; /* rewrite VLAN Tag */ 1066 uint8_t dmac[ETH_ALEN]; /* new destination MAC address */ 1067 uint8_t smac[ETH_ALEN]; /* new source MAC address */ 1068 uint16_t vlan; /* VLAN Tag to insert */ 1069 1070 /* Filter rule value/mask pairs. 1071 */ 1072 struct ch_filter_tuple val; 1073 struct ch_filter_tuple mask; 1074 }; 1075 1076 enum { 1077 FILTER_PASS = 0, /* default */ 1078 FILTER_DROP, 1079 FILTER_SWITCH 1080 }; 1081 1082 enum { 1083 VLAN_NOCHANGE = 0, /* default */ 1084 VLAN_REMOVE, 1085 VLAN_INSERT, 1086 VLAN_REWRITE 1087 }; 1088 1089 /* Host shadow copy of ingress filter entry. This is in host native format 1090 * and doesn't match the ordering or bit order, etc. of the hardware of the 1091 * firmware command. The use of bit-field structure elements is purely to 1092 * remind ourselves of the field size limitations and save memory in the case 1093 * where the filter table is large. 1094 */ 1095 struct filter_entry { 1096 /* Administrative fields for filter. */ 1097 u32 valid:1; /* filter allocated and valid */ 1098 u32 locked:1; /* filter is administratively locked */ 1099 1100 u32 pending:1; /* filter action is pending firmware reply */ 1101 u32 smtidx:8; /* Source MAC Table index for smac */ 1102 struct filter_ctx *ctx; /* Caller's completion hook */ 1103 struct l2t_entry *l2t; /* Layer Two Table entry for dmac */ 1104 struct net_device *dev; /* Associated net device */ 1105 u32 tid; /* This will store the actual tid */ 1106 1107 /* The filter itself. Most of this is a straight copy of information 1108 * provided by the extended ioctl(). Some fields are translated to 1109 * internal forms -- for instance the Ingress Queue ID passed in from 1110 * the ioctl() is translated into the Absolute Ingress Queue ID. 1111 */ 1112 struct ch_filter_specification fs; 1113 }; 1114 1115 static inline int is_offload(const struct adapter *adap) 1116 { 1117 return adap->params.offload; 1118 } 1119 1120 static inline int is_pci_uld(const struct adapter *adap) 1121 { 1122 return adap->params.crypto; 1123 } 1124 1125 static inline int is_uld(const struct adapter *adap) 1126 { 1127 return (adap->params.offload || adap->params.crypto); 1128 } 1129 1130 static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr) 1131 { 1132 return readl(adap->regs + reg_addr); 1133 } 1134 1135 static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val) 1136 { 1137 writel(val, adap->regs + reg_addr); 1138 } 1139 1140 #ifndef readq 1141 static inline u64 readq(const volatile void __iomem *addr) 1142 { 1143 return readl(addr) + ((u64)readl(addr + 4) << 32); 1144 } 1145 1146 static inline void writeq(u64 val, volatile void __iomem *addr) 1147 { 1148 writel(val, addr); 1149 writel(val >> 32, addr + 4); 1150 } 1151 #endif 1152 1153 static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr) 1154 { 1155 return readq(adap->regs + reg_addr); 1156 } 1157 1158 static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val) 1159 { 1160 writeq(val, adap->regs + reg_addr); 1161 } 1162 1163 /** 1164 * t4_set_hw_addr - store a port's MAC address in SW 1165 * @adapter: the adapter 1166 * @port_idx: the port index 1167 * @hw_addr: the Ethernet address 1168 * 1169 * Store the Ethernet address of the given port in SW. Called by the common 1170 * code when it retrieves a port's Ethernet address from EEPROM. 1171 */ 1172 static inline void t4_set_hw_addr(struct adapter *adapter, int port_idx, 1173 u8 hw_addr[]) 1174 { 1175 ether_addr_copy(adapter->port[port_idx]->dev_addr, hw_addr); 1176 ether_addr_copy(adapter->port[port_idx]->perm_addr, hw_addr); 1177 } 1178 1179 /** 1180 * netdev2pinfo - return the port_info structure associated with a net_device 1181 * @dev: the netdev 1182 * 1183 * Return the struct port_info associated with a net_device 1184 */ 1185 static inline struct port_info *netdev2pinfo(const struct net_device *dev) 1186 { 1187 return netdev_priv(dev); 1188 } 1189 1190 /** 1191 * adap2pinfo - return the port_info of a port 1192 * @adap: the adapter 1193 * @idx: the port index 1194 * 1195 * Return the port_info structure for the port of the given index. 1196 */ 1197 static inline struct port_info *adap2pinfo(struct adapter *adap, int idx) 1198 { 1199 return netdev_priv(adap->port[idx]); 1200 } 1201 1202 /** 1203 * netdev2adap - return the adapter structure associated with a net_device 1204 * @dev: the netdev 1205 * 1206 * Return the struct adapter associated with a net_device 1207 */ 1208 static inline struct adapter *netdev2adap(const struct net_device *dev) 1209 { 1210 return netdev2pinfo(dev)->adapter; 1211 } 1212 1213 /* Return a version number to identify the type of adapter. The scheme is: 1214 * - bits 0..9: chip version 1215 * - bits 10..15: chip revision 1216 * - bits 16..23: register dump version 1217 */ 1218 static inline unsigned int mk_adap_vers(struct adapter *ap) 1219 { 1220 return CHELSIO_CHIP_VERSION(ap->params.chip) | 1221 (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16); 1222 } 1223 1224 /* Return a queue's interrupt hold-off time in us. 0 means no timer. */ 1225 static inline unsigned int qtimer_val(const struct adapter *adap, 1226 const struct sge_rspq *q) 1227 { 1228 unsigned int idx = q->intr_params >> 1; 1229 1230 return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0; 1231 } 1232 1233 /* driver version & name used for ethtool_drvinfo */ 1234 extern char cxgb4_driver_name[]; 1235 extern const char cxgb4_driver_version[]; 1236 1237 void t4_os_portmod_changed(const struct adapter *adap, int port_id); 1238 void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat); 1239 1240 void t4_free_sge_resources(struct adapter *adap); 1241 void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q); 1242 irq_handler_t t4_intr_handler(struct adapter *adap); 1243 netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev); 1244 int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp, 1245 const struct pkt_gl *gl); 1246 int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb); 1247 int t4_ofld_send(struct adapter *adap, struct sk_buff *skb); 1248 int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, 1249 struct net_device *dev, int intr_idx, 1250 struct sge_fl *fl, rspq_handler_t hnd, 1251 rspq_flush_handler_t flush_handler, int cong); 1252 int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq, 1253 struct net_device *dev, struct netdev_queue *netdevq, 1254 unsigned int iqid); 1255 int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq, 1256 struct net_device *dev, unsigned int iqid, 1257 unsigned int cmplqid); 1258 int t4_sge_mod_ctrl_txq(struct adapter *adap, unsigned int eqid, 1259 unsigned int cmplqid); 1260 int t4_sge_alloc_uld_txq(struct adapter *adap, struct sge_uld_txq *txq, 1261 struct net_device *dev, unsigned int iqid, 1262 unsigned int uld_type); 1263 irqreturn_t t4_sge_intr_msix(int irq, void *cookie); 1264 int t4_sge_init(struct adapter *adap); 1265 void t4_sge_start(struct adapter *adap); 1266 void t4_sge_stop(struct adapter *adap); 1267 void cxgb4_set_ethtool_ops(struct net_device *netdev); 1268 int cxgb4_write_rss(const struct port_info *pi, const u16 *queues); 1269 extern int dbfifo_int_thresh; 1270 1271 #define for_each_port(adapter, iter) \ 1272 for (iter = 0; iter < (adapter)->params.nports; ++iter) 1273 1274 static inline int is_bypass(struct adapter *adap) 1275 { 1276 return adap->params.bypass; 1277 } 1278 1279 static inline int is_bypass_device(int device) 1280 { 1281 /* this should be set based upon device capabilities */ 1282 switch (device) { 1283 case 0x440b: 1284 case 0x440c: 1285 return 1; 1286 default: 1287 return 0; 1288 } 1289 } 1290 1291 static inline int is_10gbt_device(int device) 1292 { 1293 /* this should be set based upon device capabilities */ 1294 switch (device) { 1295 case 0x4409: 1296 case 0x4486: 1297 return 1; 1298 1299 default: 1300 return 0; 1301 } 1302 } 1303 1304 static inline unsigned int core_ticks_per_usec(const struct adapter *adap) 1305 { 1306 return adap->params.vpd.cclk / 1000; 1307 } 1308 1309 static inline unsigned int us_to_core_ticks(const struct adapter *adap, 1310 unsigned int us) 1311 { 1312 return (us * adap->params.vpd.cclk) / 1000; 1313 } 1314 1315 static inline unsigned int core_ticks_to_us(const struct adapter *adapter, 1316 unsigned int ticks) 1317 { 1318 /* add Core Clock / 2 to round ticks to nearest uS */ 1319 return ((ticks * 1000 + adapter->params.vpd.cclk/2) / 1320 adapter->params.vpd.cclk); 1321 } 1322 1323 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, 1324 u32 val); 1325 1326 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 1327 int size, void *rpl, bool sleep_ok, int timeout); 1328 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 1329 void *rpl, bool sleep_ok); 1330 1331 static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox, 1332 const void *cmd, int size, void *rpl, 1333 int timeout) 1334 { 1335 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true, 1336 timeout); 1337 } 1338 1339 static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, 1340 int size, void *rpl) 1341 { 1342 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true); 1343 } 1344 1345 static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, 1346 int size, void *rpl) 1347 { 1348 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false); 1349 } 1350 1351 /** 1352 * hash_mac_addr - return the hash value of a MAC address 1353 * @addr: the 48-bit Ethernet MAC address 1354 * 1355 * Hashes a MAC address according to the hash function used by HW inexact 1356 * (hash) address matching. 1357 */ 1358 static inline int hash_mac_addr(const u8 *addr) 1359 { 1360 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2]; 1361 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5]; 1362 1363 a ^= b; 1364 a ^= (a >> 12); 1365 a ^= (a >> 6); 1366 return a & 0x3f; 1367 } 1368 1369 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us, 1370 unsigned int cnt); 1371 static inline void init_rspq(struct adapter *adap, struct sge_rspq *q, 1372 unsigned int us, unsigned int cnt, 1373 unsigned int size, unsigned int iqe_size) 1374 { 1375 q->adap = adap; 1376 cxgb4_set_rspq_intr_params(q, us, cnt); 1377 q->iqe_len = iqe_size; 1378 q->size = size; 1379 } 1380 1381 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 1382 unsigned int data_reg, const u32 *vals, 1383 unsigned int nregs, unsigned int start_idx); 1384 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 1385 unsigned int data_reg, u32 *vals, unsigned int nregs, 1386 unsigned int start_idx); 1387 void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val); 1388 1389 struct fw_filter_wr; 1390 1391 void t4_intr_enable(struct adapter *adapter); 1392 void t4_intr_disable(struct adapter *adapter); 1393 int t4_slow_intr_handler(struct adapter *adapter); 1394 1395 int t4_wait_dev_ready(void __iomem *regs); 1396 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port, 1397 struct link_config *lc); 1398 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port); 1399 1400 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg); 1401 u32 t4_get_util_window(struct adapter *adap); 1402 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window); 1403 1404 #define T4_MEMORY_WRITE 0 1405 #define T4_MEMORY_READ 1 1406 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len, 1407 void *buf, int dir); 1408 static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr, 1409 u32 len, __be32 *buf) 1410 { 1411 return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0); 1412 } 1413 1414 unsigned int t4_get_regs_len(struct adapter *adapter); 1415 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size); 1416 1417 int t4_seeprom_wp(struct adapter *adapter, bool enable); 1418 int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p); 1419 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p); 1420 int t4_read_flash(struct adapter *adapter, unsigned int addr, 1421 unsigned int nwords, u32 *data, int byte_oriented); 1422 int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size); 1423 int t4_load_phy_fw(struct adapter *adap, 1424 int win, spinlock_t *lock, 1425 int (*phy_fw_version)(const u8 *, size_t), 1426 const u8 *phy_fw_data, size_t phy_fw_size); 1427 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver); 1428 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op); 1429 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 1430 const u8 *fw_data, unsigned int size, int force); 1431 int t4_fl_pkt_align(struct adapter *adap); 1432 unsigned int t4_flash_cfg_addr(struct adapter *adapter); 1433 int t4_check_fw_version(struct adapter *adap); 1434 int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size); 1435 int t4_get_fw_version(struct adapter *adapter, u32 *vers); 1436 int t4_get_bs_version(struct adapter *adapter, u32 *vers); 1437 int t4_get_tp_version(struct adapter *adapter, u32 *vers); 1438 int t4_get_exprom_version(struct adapter *adapter, u32 *vers); 1439 int t4_get_scfg_version(struct adapter *adapter, u32 *vers); 1440 int t4_get_vpd_version(struct adapter *adapter, u32 *vers); 1441 int t4_get_version_info(struct adapter *adapter); 1442 void t4_dump_version_info(struct adapter *adapter); 1443 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info, 1444 const u8 *fw_data, unsigned int fw_size, 1445 struct fw_hdr *card_fw, enum dev_state state, int *reset); 1446 int t4_prep_adapter(struct adapter *adapter); 1447 int t4_shutdown_adapter(struct adapter *adapter); 1448 1449 enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS }; 1450 int t4_bar2_sge_qregs(struct adapter *adapter, 1451 unsigned int qid, 1452 enum t4_bar2_qtype qtype, 1453 int user, 1454 u64 *pbar2_qoffset, 1455 unsigned int *pbar2_qid); 1456 1457 unsigned int qtimer_val(const struct adapter *adap, 1458 const struct sge_rspq *q); 1459 1460 int t4_init_devlog_params(struct adapter *adapter); 1461 int t4_init_sge_params(struct adapter *adapter); 1462 int t4_init_tp_params(struct adapter *adap, bool sleep_ok); 1463 int t4_filter_field_shift(const struct adapter *adap, int filter_sel); 1464 int t4_init_rss_mode(struct adapter *adap, int mbox); 1465 int t4_init_portinfo(struct port_info *pi, int mbox, 1466 int port, int pf, int vf, u8 mac[]); 1467 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf); 1468 void t4_fatal_err(struct adapter *adapter); 1469 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 1470 int start, int n, const u16 *rspq, unsigned int nrspq); 1471 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 1472 unsigned int flags); 1473 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 1474 unsigned int flags, unsigned int defq); 1475 int t4_read_rss(struct adapter *adapter, u16 *entries); 1476 void t4_read_rss_key(struct adapter *adapter, u32 *key, bool sleep_ok); 1477 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx, 1478 bool sleep_ok); 1479 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, 1480 u32 *valp, bool sleep_ok); 1481 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 1482 u32 *vfl, u32 *vfh, bool sleep_ok); 1483 u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok); 1484 u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok); 1485 1486 unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx); 1487 unsigned int t4_get_tp_ch_map(struct adapter *adapter, int pidx); 1488 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1489 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1490 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, 1491 size_t n); 1492 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, 1493 size_t n); 1494 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 1495 unsigned int *valp); 1496 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 1497 const unsigned int *valp); 1498 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr); 1499 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, 1500 unsigned int *pif_req_wrptr, 1501 unsigned int *pif_rsp_wrptr); 1502 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp); 1503 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres); 1504 const char *t4_get_port_type_description(enum fw_port_type port_type); 1505 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); 1506 void t4_get_port_stats_offset(struct adapter *adap, int idx, 1507 struct port_stats *stats, 1508 struct port_stats *offset); 1509 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p); 1510 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); 1511 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]); 1512 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 1513 unsigned int mask, unsigned int val); 1514 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr); 1515 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st, 1516 bool sleep_ok); 1517 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st, 1518 bool sleep_ok); 1519 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st, 1520 bool sleep_ok); 1521 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st, 1522 bool sleep_ok); 1523 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 1524 struct tp_tcp_stats *v6, bool sleep_ok); 1525 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 1526 struct tp_fcoe_stats *st, bool sleep_ok); 1527 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 1528 const unsigned short *alpha, const unsigned short *beta); 1529 1530 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf); 1531 1532 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate); 1533 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid); 1534 1535 void t4_wol_magic_enable(struct adapter *adap, unsigned int port, 1536 const u8 *addr); 1537 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 1538 u64 mask0, u64 mask1, unsigned int crc, bool enable); 1539 1540 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 1541 enum dev_master master, enum dev_state *state); 1542 int t4_fw_bye(struct adapter *adap, unsigned int mbox); 1543 int t4_early_init(struct adapter *adap, unsigned int mbox); 1544 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); 1545 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, 1546 unsigned int cache_line_size); 1547 int t4_fw_initialize(struct adapter *adap, unsigned int mbox); 1548 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1549 unsigned int vf, unsigned int nparams, const u32 *params, 1550 u32 *val); 1551 int t4_query_params_ns(struct adapter *adap, unsigned int mbox, unsigned int pf, 1552 unsigned int vf, unsigned int nparams, const u32 *params, 1553 u32 *val); 1554 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, 1555 unsigned int vf, unsigned int nparams, const u32 *params, 1556 u32 *val, int rw, bool sleep_ok); 1557 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 1558 unsigned int pf, unsigned int vf, 1559 unsigned int nparams, const u32 *params, 1560 const u32 *val, int timeout); 1561 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1562 unsigned int vf, unsigned int nparams, const u32 *params, 1563 const u32 *val); 1564 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 1565 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 1566 unsigned int rxqi, unsigned int rxq, unsigned int tc, 1567 unsigned int vi, unsigned int cmask, unsigned int pmask, 1568 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps); 1569 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 1570 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 1571 unsigned int *rss_size); 1572 int t4_free_vi(struct adapter *adap, unsigned int mbox, 1573 unsigned int pf, unsigned int vf, 1574 unsigned int viid); 1575 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 1576 int mtu, int promisc, int all_multi, int bcast, int vlanex, 1577 bool sleep_ok); 1578 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, 1579 unsigned int viid, bool free, unsigned int naddr, 1580 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok); 1581 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox, 1582 unsigned int viid, unsigned int naddr, 1583 const u8 **addr, bool sleep_ok); 1584 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 1585 int idx, const u8 *addr, bool persist, bool add_smt); 1586 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 1587 bool ucast, u64 vec, bool sleep_ok); 1588 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 1589 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en); 1590 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 1591 bool rx_en, bool tx_en); 1592 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 1593 unsigned int nblinks); 1594 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1595 unsigned int mmd, unsigned int reg, u16 *valp); 1596 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1597 unsigned int mmd, unsigned int reg, u16 val); 1598 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, 1599 unsigned int vf, unsigned int iqtype, unsigned int iqid, 1600 unsigned int fl0id, unsigned int fl1id); 1601 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1602 unsigned int vf, unsigned int iqtype, unsigned int iqid, 1603 unsigned int fl0id, unsigned int fl1id); 1604 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1605 unsigned int vf, unsigned int eqid); 1606 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1607 unsigned int vf, unsigned int eqid); 1608 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1609 unsigned int vf, unsigned int eqid); 1610 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox); 1611 void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl); 1612 int t4_update_port_info(struct port_info *pi); 1613 int t4_get_link_params(struct port_info *pi, unsigned int *link_okp, 1614 unsigned int *speedp, unsigned int *mtup); 1615 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); 1616 void t4_db_full(struct adapter *adapter); 1617 void t4_db_dropped(struct adapter *adapter); 1618 int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp, 1619 int filter_index, int enable); 1620 void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp, 1621 int filter_index, int *enabled); 1622 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, 1623 u32 addr, u32 val); 1624 int t4_sched_params(struct adapter *adapter, int type, int level, int mode, 1625 int rateunit, int ratemode, int channel, int class, 1626 int minrate, int maxrate, int weight, int pktsize); 1627 void t4_sge_decode_idma_state(struct adapter *adapter, int state); 1628 void t4_idma_monitor_init(struct adapter *adapter, 1629 struct sge_idma_monitor_state *idma); 1630 void t4_idma_monitor(struct adapter *adapter, 1631 struct sge_idma_monitor_state *idma, 1632 int hz, int ticks); 1633 int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf, 1634 unsigned int naddr, u8 *addr); 1635 void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 1636 u32 start_index, bool sleep_ok); 1637 void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 1638 u32 start_index, bool sleep_ok); 1639 void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, 1640 u32 start_index, bool sleep_ok); 1641 1642 void t4_uld_mem_free(struct adapter *adap); 1643 int t4_uld_mem_alloc(struct adapter *adap); 1644 void t4_uld_clean_up(struct adapter *adap); 1645 void t4_register_netevent_notifier(void); 1646 void free_rspq_fl(struct adapter *adap, struct sge_rspq *rq, struct sge_fl *fl); 1647 void free_tx_desc(struct adapter *adap, struct sge_txq *q, 1648 unsigned int n, bool unmap); 1649 void free_txq(struct adapter *adap, struct sge_txq *q); 1650 #endif /* __CXGB4_H__ */ 1651