1 /* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2003-2010 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #ifndef __CXGB4_H__ 36 #define __CXGB4_H__ 37 38 #include <linux/bitops.h> 39 #include <linux/cache.h> 40 #include <linux/interrupt.h> 41 #include <linux/list.h> 42 #include <linux/netdevice.h> 43 #include <linux/pci.h> 44 #include <linux/spinlock.h> 45 #include <linux/timer.h> 46 #include <linux/vmalloc.h> 47 #include <asm/io.h> 48 #include "cxgb4_uld.h" 49 #include "t4_hw.h" 50 51 #define FW_VERSION_MAJOR 1 52 #define FW_VERSION_MINOR 1 53 #define FW_VERSION_MICRO 0 54 55 #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__) 56 57 enum { 58 MAX_NPORTS = 4, /* max # of ports */ 59 SERNUM_LEN = 24, /* Serial # length */ 60 EC_LEN = 16, /* E/C length */ 61 ID_LEN = 16, /* ID length */ 62 }; 63 64 enum { 65 MEM_EDC0, 66 MEM_EDC1, 67 MEM_MC 68 }; 69 70 enum { 71 MEMWIN0_APERTURE = 2048, 72 MEMWIN0_BASE = 0x1b800, 73 MEMWIN1_APERTURE = 32768, 74 MEMWIN1_BASE = 0x28000, 75 MEMWIN2_APERTURE = 65536, 76 MEMWIN2_BASE = 0x30000, 77 }; 78 79 enum dev_master { 80 MASTER_CANT, 81 MASTER_MAY, 82 MASTER_MUST 83 }; 84 85 enum dev_state { 86 DEV_STATE_UNINIT, 87 DEV_STATE_INIT, 88 DEV_STATE_ERR 89 }; 90 91 enum { 92 PAUSE_RX = 1 << 0, 93 PAUSE_TX = 1 << 1, 94 PAUSE_AUTONEG = 1 << 2 95 }; 96 97 struct port_stats { 98 u64 tx_octets; /* total # of octets in good frames */ 99 u64 tx_frames; /* all good frames */ 100 u64 tx_bcast_frames; /* all broadcast frames */ 101 u64 tx_mcast_frames; /* all multicast frames */ 102 u64 tx_ucast_frames; /* all unicast frames */ 103 u64 tx_error_frames; /* all error frames */ 104 105 u64 tx_frames_64; /* # of Tx frames in a particular range */ 106 u64 tx_frames_65_127; 107 u64 tx_frames_128_255; 108 u64 tx_frames_256_511; 109 u64 tx_frames_512_1023; 110 u64 tx_frames_1024_1518; 111 u64 tx_frames_1519_max; 112 113 u64 tx_drop; /* # of dropped Tx frames */ 114 u64 tx_pause; /* # of transmitted pause frames */ 115 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ 116 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ 117 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ 118 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ 119 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ 120 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ 121 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ 122 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ 123 124 u64 rx_octets; /* total # of octets in good frames */ 125 u64 rx_frames; /* all good frames */ 126 u64 rx_bcast_frames; /* all broadcast frames */ 127 u64 rx_mcast_frames; /* all multicast frames */ 128 u64 rx_ucast_frames; /* all unicast frames */ 129 u64 rx_too_long; /* # of frames exceeding MTU */ 130 u64 rx_jabber; /* # of jabber frames */ 131 u64 rx_fcs_err; /* # of received frames with bad FCS */ 132 u64 rx_len_err; /* # of received frames with length error */ 133 u64 rx_symbol_err; /* symbol errors */ 134 u64 rx_runt; /* # of short frames */ 135 136 u64 rx_frames_64; /* # of Rx frames in a particular range */ 137 u64 rx_frames_65_127; 138 u64 rx_frames_128_255; 139 u64 rx_frames_256_511; 140 u64 rx_frames_512_1023; 141 u64 rx_frames_1024_1518; 142 u64 rx_frames_1519_max; 143 144 u64 rx_pause; /* # of received pause frames */ 145 u64 rx_ppp0; /* # of received PPP prio 0 frames */ 146 u64 rx_ppp1; /* # of received PPP prio 1 frames */ 147 u64 rx_ppp2; /* # of received PPP prio 2 frames */ 148 u64 rx_ppp3; /* # of received PPP prio 3 frames */ 149 u64 rx_ppp4; /* # of received PPP prio 4 frames */ 150 u64 rx_ppp5; /* # of received PPP prio 5 frames */ 151 u64 rx_ppp6; /* # of received PPP prio 6 frames */ 152 u64 rx_ppp7; /* # of received PPP prio 7 frames */ 153 154 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ 155 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ 156 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ 157 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ 158 u64 rx_trunc0; /* buffer-group 0 truncated packets */ 159 u64 rx_trunc1; /* buffer-group 1 truncated packets */ 160 u64 rx_trunc2; /* buffer-group 2 truncated packets */ 161 u64 rx_trunc3; /* buffer-group 3 truncated packets */ 162 }; 163 164 struct lb_port_stats { 165 u64 octets; 166 u64 frames; 167 u64 bcast_frames; 168 u64 mcast_frames; 169 u64 ucast_frames; 170 u64 error_frames; 171 172 u64 frames_64; 173 u64 frames_65_127; 174 u64 frames_128_255; 175 u64 frames_256_511; 176 u64 frames_512_1023; 177 u64 frames_1024_1518; 178 u64 frames_1519_max; 179 180 u64 drop; 181 182 u64 ovflow0; 183 u64 ovflow1; 184 u64 ovflow2; 185 u64 ovflow3; 186 u64 trunc0; 187 u64 trunc1; 188 u64 trunc2; 189 u64 trunc3; 190 }; 191 192 struct tp_tcp_stats { 193 u32 tcpOutRsts; 194 u64 tcpInSegs; 195 u64 tcpOutSegs; 196 u64 tcpRetransSegs; 197 }; 198 199 struct tp_err_stats { 200 u32 macInErrs[4]; 201 u32 hdrInErrs[4]; 202 u32 tcpInErrs[4]; 203 u32 tnlCongDrops[4]; 204 u32 ofldChanDrops[4]; 205 u32 tnlTxDrops[4]; 206 u32 ofldVlanDrops[4]; 207 u32 tcp6InErrs[4]; 208 u32 ofldNoNeigh; 209 u32 ofldCongDefer; 210 }; 211 212 struct tp_params { 213 unsigned int ntxchan; /* # of Tx channels */ 214 unsigned int tre; /* log2 of core clocks per TP tick */ 215 216 uint32_t dack_re; /* DACK timer resolution */ 217 unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */ 218 }; 219 220 struct vpd_params { 221 unsigned int cclk; 222 u8 ec[EC_LEN + 1]; 223 u8 sn[SERNUM_LEN + 1]; 224 u8 id[ID_LEN + 1]; 225 }; 226 227 struct pci_params { 228 unsigned char speed; 229 unsigned char width; 230 }; 231 232 struct adapter_params { 233 struct tp_params tp; 234 struct vpd_params vpd; 235 struct pci_params pci; 236 237 unsigned int sf_size; /* serial flash size in bytes */ 238 unsigned int sf_nsec; /* # of flash sectors */ 239 unsigned int sf_fw_start; /* start of FW image in flash */ 240 241 unsigned int fw_vers; 242 unsigned int tp_vers; 243 u8 api_vers[7]; 244 245 unsigned short mtus[NMTUS]; 246 unsigned short a_wnd[NCCTRL_WIN]; 247 unsigned short b_wnd[NCCTRL_WIN]; 248 249 unsigned char nports; /* # of ethernet ports */ 250 unsigned char portvec; 251 unsigned char rev; /* chip revision */ 252 unsigned char offload; 253 254 unsigned int ofldq_wr_cred; 255 }; 256 257 struct trace_params { 258 u32 data[TRACE_LEN / 4]; 259 u32 mask[TRACE_LEN / 4]; 260 unsigned short snap_len; 261 unsigned short min_len; 262 unsigned char skip_ofst; 263 unsigned char skip_len; 264 unsigned char invert; 265 unsigned char port; 266 }; 267 268 struct link_config { 269 unsigned short supported; /* link capabilities */ 270 unsigned short advertising; /* advertised capabilities */ 271 unsigned short requested_speed; /* speed user has requested */ 272 unsigned short speed; /* actual link speed */ 273 unsigned char requested_fc; /* flow control user has requested */ 274 unsigned char fc; /* actual link flow control */ 275 unsigned char autoneg; /* autonegotiating? */ 276 unsigned char link_ok; /* link up? */ 277 }; 278 279 #define FW_LEN16(fw_struct) FW_CMD_LEN16(sizeof(fw_struct) / 16) 280 281 enum { 282 MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */ 283 MAX_OFLD_QSETS = 16, /* # of offload Tx/Rx queue sets */ 284 MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */ 285 MAX_RDMA_QUEUES = NCHAN, /* # of streaming RDMA Rx queues */ 286 }; 287 288 enum { 289 MAX_EGRQ = 128, /* max # of egress queues, including FLs */ 290 MAX_INGQ = 64 /* max # of interrupt-capable ingress queues */ 291 }; 292 293 struct adapter; 294 struct sge_rspq; 295 296 struct port_info { 297 struct adapter *adapter; 298 u16 viid; 299 s16 xact_addr_filt; /* index of exact MAC address filter */ 300 u16 rss_size; /* size of VI's RSS table slice */ 301 s8 mdio_addr; 302 u8 port_type; 303 u8 mod_type; 304 u8 port_id; 305 u8 tx_chan; 306 u8 lport; /* associated offload logical port */ 307 u8 nqsets; /* # of qsets */ 308 u8 first_qset; /* index of first qset */ 309 u8 rss_mode; 310 struct link_config link_cfg; 311 u16 *rss; 312 }; 313 314 struct dentry; 315 struct work_struct; 316 317 enum { /* adapter flags */ 318 FULL_INIT_DONE = (1 << 0), 319 USING_MSI = (1 << 1), 320 USING_MSIX = (1 << 2), 321 FW_OK = (1 << 4), 322 RSS_TNLALLLOOKUP = (1 << 5), 323 USING_SOFT_PARAMS = (1 << 6), 324 MASTER_PF = (1 << 7), 325 FW_OFLD_CONN = (1 << 9), 326 }; 327 328 struct rx_sw_desc; 329 330 struct sge_fl { /* SGE free-buffer queue state */ 331 unsigned int avail; /* # of available Rx buffers */ 332 unsigned int pend_cred; /* new buffers since last FL DB ring */ 333 unsigned int cidx; /* consumer index */ 334 unsigned int pidx; /* producer index */ 335 unsigned long alloc_failed; /* # of times buffer allocation failed */ 336 unsigned long large_alloc_failed; 337 unsigned long starving; 338 /* RO fields */ 339 unsigned int cntxt_id; /* SGE context id for the free list */ 340 unsigned int size; /* capacity of free list */ 341 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */ 342 __be64 *desc; /* address of HW Rx descriptor ring */ 343 dma_addr_t addr; /* bus address of HW ring start */ 344 }; 345 346 /* A packet gather list */ 347 struct pkt_gl { 348 struct page_frag frags[MAX_SKB_FRAGS]; 349 void *va; /* virtual address of first byte */ 350 unsigned int nfrags; /* # of fragments */ 351 unsigned int tot_len; /* total length of fragments */ 352 }; 353 354 typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp, 355 const struct pkt_gl *gl); 356 357 struct sge_rspq { /* state for an SGE response queue */ 358 struct napi_struct napi; 359 const __be64 *cur_desc; /* current descriptor in queue */ 360 unsigned int cidx; /* consumer index */ 361 u8 gen; /* current generation bit */ 362 u8 intr_params; /* interrupt holdoff parameters */ 363 u8 next_intr_params; /* holdoff params for next interrupt */ 364 u8 pktcnt_idx; /* interrupt packet threshold */ 365 u8 uld; /* ULD handling this queue */ 366 u8 idx; /* queue index within its group */ 367 int offset; /* offset into current Rx buffer */ 368 u16 cntxt_id; /* SGE context id for the response q */ 369 u16 abs_id; /* absolute SGE id for the response q */ 370 __be64 *desc; /* address of HW response ring */ 371 dma_addr_t phys_addr; /* physical address of the ring */ 372 unsigned int iqe_len; /* entry size */ 373 unsigned int size; /* capacity of response queue */ 374 struct adapter *adap; 375 struct net_device *netdev; /* associated net device */ 376 rspq_handler_t handler; 377 }; 378 379 struct sge_eth_stats { /* Ethernet queue statistics */ 380 unsigned long pkts; /* # of ethernet packets */ 381 unsigned long lro_pkts; /* # of LRO super packets */ 382 unsigned long lro_merged; /* # of wire packets merged by LRO */ 383 unsigned long rx_cso; /* # of Rx checksum offloads */ 384 unsigned long vlan_ex; /* # of Rx VLAN extractions */ 385 unsigned long rx_drops; /* # of packets dropped due to no mem */ 386 }; 387 388 struct sge_eth_rxq { /* SW Ethernet Rx queue */ 389 struct sge_rspq rspq; 390 struct sge_fl fl; 391 struct sge_eth_stats stats; 392 } ____cacheline_aligned_in_smp; 393 394 struct sge_ofld_stats { /* offload queue statistics */ 395 unsigned long pkts; /* # of packets */ 396 unsigned long imm; /* # of immediate-data packets */ 397 unsigned long an; /* # of asynchronous notifications */ 398 unsigned long nomem; /* # of responses deferred due to no mem */ 399 }; 400 401 struct sge_ofld_rxq { /* SW offload Rx queue */ 402 struct sge_rspq rspq; 403 struct sge_fl fl; 404 struct sge_ofld_stats stats; 405 } ____cacheline_aligned_in_smp; 406 407 struct tx_desc { 408 __be64 flit[8]; 409 }; 410 411 struct tx_sw_desc; 412 413 struct sge_txq { 414 unsigned int in_use; /* # of in-use Tx descriptors */ 415 unsigned int size; /* # of descriptors */ 416 unsigned int cidx; /* SW consumer index */ 417 unsigned int pidx; /* producer index */ 418 unsigned long stops; /* # of times q has been stopped */ 419 unsigned long restarts; /* # of queue restarts */ 420 unsigned int cntxt_id; /* SGE context id for the Tx q */ 421 struct tx_desc *desc; /* address of HW Tx descriptor ring */ 422 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */ 423 struct sge_qstat *stat; /* queue status entry */ 424 dma_addr_t phys_addr; /* physical address of the ring */ 425 spinlock_t db_lock; 426 int db_disabled; 427 unsigned short db_pidx; 428 }; 429 430 struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */ 431 struct sge_txq q; 432 struct netdev_queue *txq; /* associated netdev TX queue */ 433 unsigned long tso; /* # of TSO requests */ 434 unsigned long tx_cso; /* # of Tx checksum offloads */ 435 unsigned long vlan_ins; /* # of Tx VLAN insertions */ 436 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 437 } ____cacheline_aligned_in_smp; 438 439 struct sge_ofld_txq { /* state for an SGE offload Tx queue */ 440 struct sge_txq q; 441 struct adapter *adap; 442 struct sk_buff_head sendq; /* list of backpressured packets */ 443 struct tasklet_struct qresume_tsk; /* restarts the queue */ 444 u8 full; /* the Tx ring is full */ 445 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 446 } ____cacheline_aligned_in_smp; 447 448 struct sge_ctrl_txq { /* state for an SGE control Tx queue */ 449 struct sge_txq q; 450 struct adapter *adap; 451 struct sk_buff_head sendq; /* list of backpressured packets */ 452 struct tasklet_struct qresume_tsk; /* restarts the queue */ 453 u8 full; /* the Tx ring is full */ 454 } ____cacheline_aligned_in_smp; 455 456 struct sge { 457 struct sge_eth_txq ethtxq[MAX_ETH_QSETS]; 458 struct sge_ofld_txq ofldtxq[MAX_OFLD_QSETS]; 459 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES]; 460 461 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS]; 462 struct sge_ofld_rxq ofldrxq[MAX_OFLD_QSETS]; 463 struct sge_ofld_rxq rdmarxq[MAX_RDMA_QUEUES]; 464 struct sge_rspq fw_evtq ____cacheline_aligned_in_smp; 465 466 struct sge_rspq intrq ____cacheline_aligned_in_smp; 467 spinlock_t intrq_lock; 468 469 u16 max_ethqsets; /* # of available Ethernet queue sets */ 470 u16 ethqsets; /* # of active Ethernet queue sets */ 471 u16 ethtxq_rover; /* Tx queue to clean up next */ 472 u16 ofldqsets; /* # of active offload queue sets */ 473 u16 rdmaqs; /* # of available RDMA Rx queues */ 474 u16 ofld_rxq[MAX_OFLD_QSETS]; 475 u16 rdma_rxq[NCHAN]; 476 u16 timer_val[SGE_NTIMERS]; 477 u8 counter_val[SGE_NCOUNTERS]; 478 u32 fl_pg_order; /* large page allocation size */ 479 u32 stat_len; /* length of status page at ring end */ 480 u32 pktshift; /* padding between CPL & packet data */ 481 u32 fl_align; /* response queue message alignment */ 482 u32 fl_starve_thres; /* Free List starvation threshold */ 483 unsigned int starve_thres; 484 u8 idma_state[2]; 485 unsigned int egr_start; 486 unsigned int ingr_start; 487 void *egr_map[MAX_EGRQ]; /* qid->queue egress queue map */ 488 struct sge_rspq *ingr_map[MAX_INGQ]; /* qid->queue ingress queue map */ 489 DECLARE_BITMAP(starving_fl, MAX_EGRQ); 490 DECLARE_BITMAP(txq_maperr, MAX_EGRQ); 491 struct timer_list rx_timer; /* refills starving FLs */ 492 struct timer_list tx_timer; /* checks Tx queues */ 493 }; 494 495 #define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++) 496 #define for_each_ofldrxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++) 497 #define for_each_rdmarxq(sge, i) for (i = 0; i < (sge)->rdmaqs; i++) 498 499 struct l2t_data; 500 501 struct adapter { 502 void __iomem *regs; 503 struct pci_dev *pdev; 504 struct device *pdev_dev; 505 unsigned int mbox; 506 unsigned int fn; 507 unsigned int flags; 508 509 int msg_enable; 510 511 struct adapter_params params; 512 struct cxgb4_virt_res vres; 513 unsigned int swintr; 514 515 unsigned int wol; 516 517 struct { 518 unsigned short vec; 519 char desc[IFNAMSIZ + 10]; 520 } msix_info[MAX_INGQ + 1]; 521 522 struct sge sge; 523 524 struct net_device *port[MAX_NPORTS]; 525 u8 chan_map[NCHAN]; /* channel -> port map */ 526 527 unsigned int l2t_start; 528 unsigned int l2t_end; 529 struct l2t_data *l2t; 530 void *uld_handle[CXGB4_ULD_MAX]; 531 struct list_head list_node; 532 533 struct tid_info tids; 534 void **tid_release_head; 535 spinlock_t tid_release_lock; 536 struct work_struct tid_release_task; 537 struct work_struct db_full_task; 538 struct work_struct db_drop_task; 539 bool tid_release_task_busy; 540 541 struct dentry *debugfs_root; 542 543 spinlock_t stats_lock; 544 }; 545 546 static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr) 547 { 548 return readl(adap->regs + reg_addr); 549 } 550 551 static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val) 552 { 553 writel(val, adap->regs + reg_addr); 554 } 555 556 #ifndef readq 557 static inline u64 readq(const volatile void __iomem *addr) 558 { 559 return readl(addr) + ((u64)readl(addr + 4) << 32); 560 } 561 562 static inline void writeq(u64 val, volatile void __iomem *addr) 563 { 564 writel(val, addr); 565 writel(val >> 32, addr + 4); 566 } 567 #endif 568 569 static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr) 570 { 571 return readq(adap->regs + reg_addr); 572 } 573 574 static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val) 575 { 576 writeq(val, adap->regs + reg_addr); 577 } 578 579 /** 580 * netdev2pinfo - return the port_info structure associated with a net_device 581 * @dev: the netdev 582 * 583 * Return the struct port_info associated with a net_device 584 */ 585 static inline struct port_info *netdev2pinfo(const struct net_device *dev) 586 { 587 return netdev_priv(dev); 588 } 589 590 /** 591 * adap2pinfo - return the port_info of a port 592 * @adap: the adapter 593 * @idx: the port index 594 * 595 * Return the port_info structure for the port of the given index. 596 */ 597 static inline struct port_info *adap2pinfo(struct adapter *adap, int idx) 598 { 599 return netdev_priv(adap->port[idx]); 600 } 601 602 /** 603 * netdev2adap - return the adapter structure associated with a net_device 604 * @dev: the netdev 605 * 606 * Return the struct adapter associated with a net_device 607 */ 608 static inline struct adapter *netdev2adap(const struct net_device *dev) 609 { 610 return netdev2pinfo(dev)->adapter; 611 } 612 613 void t4_os_portmod_changed(const struct adapter *adap, int port_id); 614 void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat); 615 616 void *t4_alloc_mem(size_t size); 617 618 void t4_free_sge_resources(struct adapter *adap); 619 irq_handler_t t4_intr_handler(struct adapter *adap); 620 netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev); 621 int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp, 622 const struct pkt_gl *gl); 623 int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb); 624 int t4_ofld_send(struct adapter *adap, struct sk_buff *skb); 625 int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, 626 struct net_device *dev, int intr_idx, 627 struct sge_fl *fl, rspq_handler_t hnd); 628 int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq, 629 struct net_device *dev, struct netdev_queue *netdevq, 630 unsigned int iqid); 631 int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq, 632 struct net_device *dev, unsigned int iqid, 633 unsigned int cmplqid); 634 int t4_sge_alloc_ofld_txq(struct adapter *adap, struct sge_ofld_txq *txq, 635 struct net_device *dev, unsigned int iqid); 636 irqreturn_t t4_sge_intr_msix(int irq, void *cookie); 637 int t4_sge_init(struct adapter *adap); 638 void t4_sge_start(struct adapter *adap); 639 void t4_sge_stop(struct adapter *adap); 640 extern int dbfifo_int_thresh; 641 642 #define for_each_port(adapter, iter) \ 643 for (iter = 0; iter < (adapter)->params.nports; ++iter) 644 645 static inline unsigned int core_ticks_per_usec(const struct adapter *adap) 646 { 647 return adap->params.vpd.cclk / 1000; 648 } 649 650 static inline unsigned int us_to_core_ticks(const struct adapter *adap, 651 unsigned int us) 652 { 653 return (us * adap->params.vpd.cclk) / 1000; 654 } 655 656 static inline unsigned int core_ticks_to_us(const struct adapter *adapter, 657 unsigned int ticks) 658 { 659 /* add Core Clock / 2 to round ticks to nearest uS */ 660 return ((ticks * 1000 + adapter->params.vpd.cclk/2) / 661 adapter->params.vpd.cclk); 662 } 663 664 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, 665 u32 val); 666 667 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 668 void *rpl, bool sleep_ok); 669 670 static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, 671 int size, void *rpl) 672 { 673 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true); 674 } 675 676 static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, 677 int size, void *rpl) 678 { 679 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false); 680 } 681 682 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 683 unsigned int data_reg, const u32 *vals, 684 unsigned int nregs, unsigned int start_idx); 685 void t4_intr_enable(struct adapter *adapter); 686 void t4_intr_disable(struct adapter *adapter); 687 int t4_slow_intr_handler(struct adapter *adapter); 688 689 int t4_wait_dev_ready(struct adapter *adap); 690 int t4_link_start(struct adapter *adap, unsigned int mbox, unsigned int port, 691 struct link_config *lc); 692 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port); 693 int t4_memory_write(struct adapter *adap, int mtype, u32 addr, u32 len, 694 __be32 *buf); 695 int t4_seeprom_wp(struct adapter *adapter, bool enable); 696 int get_vpd_params(struct adapter *adapter, struct vpd_params *p); 697 int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size); 698 unsigned int t4_flash_cfg_addr(struct adapter *adapter); 699 int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size); 700 int t4_check_fw_version(struct adapter *adapter); 701 int t4_prep_adapter(struct adapter *adapter); 702 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf); 703 void t4_fatal_err(struct adapter *adapter); 704 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 705 int start, int n, const u16 *rspq, unsigned int nrspq); 706 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 707 unsigned int flags); 708 int t4_mc_read(struct adapter *adap, u32 addr, __be32 *data, u64 *parity); 709 int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, 710 u64 *parity); 711 712 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); 713 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); 714 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 715 unsigned int mask, unsigned int val); 716 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 717 struct tp_tcp_stats *v6); 718 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 719 const unsigned short *alpha, const unsigned short *beta); 720 721 void t4_wol_magic_enable(struct adapter *adap, unsigned int port, 722 const u8 *addr); 723 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 724 u64 mask0, u64 mask1, unsigned int crc, bool enable); 725 726 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 727 enum dev_master master, enum dev_state *state); 728 int t4_fw_bye(struct adapter *adap, unsigned int mbox); 729 int t4_early_init(struct adapter *adap, unsigned int mbox); 730 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); 731 int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force); 732 int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset); 733 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 734 const u8 *fw_data, unsigned int size, int force); 735 int t4_fw_config_file(struct adapter *adap, unsigned int mbox, 736 unsigned int mtype, unsigned int maddr, 737 u32 *finiver, u32 *finicsum, u32 *cfcsum); 738 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, 739 unsigned int cache_line_size); 740 int t4_fw_initialize(struct adapter *adap, unsigned int mbox); 741 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 742 unsigned int vf, unsigned int nparams, const u32 *params, 743 u32 *val); 744 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 745 unsigned int vf, unsigned int nparams, const u32 *params, 746 const u32 *val); 747 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 748 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 749 unsigned int rxqi, unsigned int rxq, unsigned int tc, 750 unsigned int vi, unsigned int cmask, unsigned int pmask, 751 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps); 752 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 753 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 754 unsigned int *rss_size); 755 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 756 int mtu, int promisc, int all_multi, int bcast, int vlanex, 757 bool sleep_ok); 758 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, 759 unsigned int viid, bool free, unsigned int naddr, 760 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok); 761 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 762 int idx, const u8 *addr, bool persist, bool add_smt); 763 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 764 bool ucast, u64 vec, bool sleep_ok); 765 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 766 bool rx_en, bool tx_en); 767 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 768 unsigned int nblinks); 769 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 770 unsigned int mmd, unsigned int reg, u16 *valp); 771 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 772 unsigned int mmd, unsigned int reg, u16 val); 773 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 774 unsigned int vf, unsigned int iqtype, unsigned int iqid, 775 unsigned int fl0id, unsigned int fl1id); 776 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 777 unsigned int vf, unsigned int eqid); 778 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 779 unsigned int vf, unsigned int eqid); 780 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 781 unsigned int vf, unsigned int eqid); 782 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); 783 void t4_db_full(struct adapter *adapter); 784 void t4_db_dropped(struct adapter *adapter); 785 int t4_mem_win_read_len(struct adapter *adap, u32 addr, __be32 *data, int len); 786 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, 787 u32 addr, u32 val); 788 #endif /* __CXGB4_H__ */ 789