1 /* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #ifndef __CXGB4_H__ 36 #define __CXGB4_H__ 37 38 #include "t4_hw.h" 39 40 #include <linux/bitops.h> 41 #include <linux/cache.h> 42 #include <linux/interrupt.h> 43 #include <linux/list.h> 44 #include <linux/netdevice.h> 45 #include <linux/pci.h> 46 #include <linux/spinlock.h> 47 #include <linux/timer.h> 48 #include <linux/vmalloc.h> 49 #include <linux/etherdevice.h> 50 #include <linux/net_tstamp.h> 51 #include <asm/io.h> 52 #include "t4_chip_type.h" 53 #include "cxgb4_uld.h" 54 55 #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__) 56 57 enum { 58 MAX_NPORTS = 4, /* max # of ports */ 59 SERNUM_LEN = 24, /* Serial # length */ 60 EC_LEN = 16, /* E/C length */ 61 ID_LEN = 16, /* ID length */ 62 PN_LEN = 16, /* Part Number length */ 63 MACADDR_LEN = 12, /* MAC Address length */ 64 }; 65 66 enum { 67 T4_REGMAP_SIZE = (160 * 1024), 68 T5_REGMAP_SIZE = (332 * 1024), 69 }; 70 71 enum { 72 MEM_EDC0, 73 MEM_EDC1, 74 MEM_MC, 75 MEM_MC0 = MEM_MC, 76 MEM_MC1 77 }; 78 79 enum { 80 MEMWIN0_APERTURE = 2048, 81 MEMWIN0_BASE = 0x1b800, 82 MEMWIN1_APERTURE = 32768, 83 MEMWIN1_BASE = 0x28000, 84 MEMWIN1_BASE_T5 = 0x52000, 85 MEMWIN2_APERTURE = 65536, 86 MEMWIN2_BASE = 0x30000, 87 MEMWIN2_APERTURE_T5 = 131072, 88 MEMWIN2_BASE_T5 = 0x60000, 89 }; 90 91 enum dev_master { 92 MASTER_CANT, 93 MASTER_MAY, 94 MASTER_MUST 95 }; 96 97 enum dev_state { 98 DEV_STATE_UNINIT, 99 DEV_STATE_INIT, 100 DEV_STATE_ERR 101 }; 102 103 enum { 104 PAUSE_RX = 1 << 0, 105 PAUSE_TX = 1 << 1, 106 PAUSE_AUTONEG = 1 << 2 107 }; 108 109 struct port_stats { 110 u64 tx_octets; /* total # of octets in good frames */ 111 u64 tx_frames; /* all good frames */ 112 u64 tx_bcast_frames; /* all broadcast frames */ 113 u64 tx_mcast_frames; /* all multicast frames */ 114 u64 tx_ucast_frames; /* all unicast frames */ 115 u64 tx_error_frames; /* all error frames */ 116 117 u64 tx_frames_64; /* # of Tx frames in a particular range */ 118 u64 tx_frames_65_127; 119 u64 tx_frames_128_255; 120 u64 tx_frames_256_511; 121 u64 tx_frames_512_1023; 122 u64 tx_frames_1024_1518; 123 u64 tx_frames_1519_max; 124 125 u64 tx_drop; /* # of dropped Tx frames */ 126 u64 tx_pause; /* # of transmitted pause frames */ 127 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ 128 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ 129 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ 130 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ 131 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ 132 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ 133 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ 134 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ 135 136 u64 rx_octets; /* total # of octets in good frames */ 137 u64 rx_frames; /* all good frames */ 138 u64 rx_bcast_frames; /* all broadcast frames */ 139 u64 rx_mcast_frames; /* all multicast frames */ 140 u64 rx_ucast_frames; /* all unicast frames */ 141 u64 rx_too_long; /* # of frames exceeding MTU */ 142 u64 rx_jabber; /* # of jabber frames */ 143 u64 rx_fcs_err; /* # of received frames with bad FCS */ 144 u64 rx_len_err; /* # of received frames with length error */ 145 u64 rx_symbol_err; /* symbol errors */ 146 u64 rx_runt; /* # of short frames */ 147 148 u64 rx_frames_64; /* # of Rx frames in a particular range */ 149 u64 rx_frames_65_127; 150 u64 rx_frames_128_255; 151 u64 rx_frames_256_511; 152 u64 rx_frames_512_1023; 153 u64 rx_frames_1024_1518; 154 u64 rx_frames_1519_max; 155 156 u64 rx_pause; /* # of received pause frames */ 157 u64 rx_ppp0; /* # of received PPP prio 0 frames */ 158 u64 rx_ppp1; /* # of received PPP prio 1 frames */ 159 u64 rx_ppp2; /* # of received PPP prio 2 frames */ 160 u64 rx_ppp3; /* # of received PPP prio 3 frames */ 161 u64 rx_ppp4; /* # of received PPP prio 4 frames */ 162 u64 rx_ppp5; /* # of received PPP prio 5 frames */ 163 u64 rx_ppp6; /* # of received PPP prio 6 frames */ 164 u64 rx_ppp7; /* # of received PPP prio 7 frames */ 165 166 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ 167 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ 168 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ 169 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ 170 u64 rx_trunc0; /* buffer-group 0 truncated packets */ 171 u64 rx_trunc1; /* buffer-group 1 truncated packets */ 172 u64 rx_trunc2; /* buffer-group 2 truncated packets */ 173 u64 rx_trunc3; /* buffer-group 3 truncated packets */ 174 }; 175 176 struct lb_port_stats { 177 u64 octets; 178 u64 frames; 179 u64 bcast_frames; 180 u64 mcast_frames; 181 u64 ucast_frames; 182 u64 error_frames; 183 184 u64 frames_64; 185 u64 frames_65_127; 186 u64 frames_128_255; 187 u64 frames_256_511; 188 u64 frames_512_1023; 189 u64 frames_1024_1518; 190 u64 frames_1519_max; 191 192 u64 drop; 193 194 u64 ovflow0; 195 u64 ovflow1; 196 u64 ovflow2; 197 u64 ovflow3; 198 u64 trunc0; 199 u64 trunc1; 200 u64 trunc2; 201 u64 trunc3; 202 }; 203 204 struct tp_tcp_stats { 205 u32 tcp_out_rsts; 206 u64 tcp_in_segs; 207 u64 tcp_out_segs; 208 u64 tcp_retrans_segs; 209 }; 210 211 struct tp_usm_stats { 212 u32 frames; 213 u32 drops; 214 u64 octets; 215 }; 216 217 struct tp_fcoe_stats { 218 u32 frames_ddp; 219 u32 frames_drop; 220 u64 octets_ddp; 221 }; 222 223 struct tp_err_stats { 224 u32 mac_in_errs[4]; 225 u32 hdr_in_errs[4]; 226 u32 tcp_in_errs[4]; 227 u32 tnl_cong_drops[4]; 228 u32 ofld_chan_drops[4]; 229 u32 tnl_tx_drops[4]; 230 u32 ofld_vlan_drops[4]; 231 u32 tcp6_in_errs[4]; 232 u32 ofld_no_neigh; 233 u32 ofld_cong_defer; 234 }; 235 236 struct tp_cpl_stats { 237 u32 req[4]; 238 u32 rsp[4]; 239 }; 240 241 struct tp_rdma_stats { 242 u32 rqe_dfr_pkt; 243 u32 rqe_dfr_mod; 244 }; 245 246 struct sge_params { 247 u32 hps; /* host page size for our PF/VF */ 248 u32 eq_qpp; /* egress queues/page for our PF/VF */ 249 u32 iq_qpp; /* egress queues/page for our PF/VF */ 250 }; 251 252 struct tp_params { 253 unsigned int tre; /* log2 of core clocks per TP tick */ 254 unsigned int la_mask; /* what events are recorded by TP LA */ 255 unsigned short tx_modq_map; /* TX modulation scheduler queue to */ 256 /* channel map */ 257 258 uint32_t dack_re; /* DACK timer resolution */ 259 unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */ 260 261 u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */ 262 u32 ingress_config; /* cached TP_INGRESS_CONFIG */ 263 264 /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a 265 * subset of the set of fields which may be present in the Compressed 266 * Filter Tuple portion of filters and TCP TCB connections. The 267 * fields which are present are controlled by the TP_VLAN_PRI_MAP. 268 * Since a variable number of fields may or may not be present, their 269 * shifted field positions within the Compressed Filter Tuple may 270 * vary, or not even be present if the field isn't selected in 271 * TP_VLAN_PRI_MAP. Since some of these fields are needed in various 272 * places we store their offsets here, or a -1 if the field isn't 273 * present. 274 */ 275 int vlan_shift; 276 int vnic_shift; 277 int port_shift; 278 int protocol_shift; 279 }; 280 281 struct vpd_params { 282 unsigned int cclk; 283 u8 ec[EC_LEN + 1]; 284 u8 sn[SERNUM_LEN + 1]; 285 u8 id[ID_LEN + 1]; 286 u8 pn[PN_LEN + 1]; 287 u8 na[MACADDR_LEN + 1]; 288 }; 289 290 struct pci_params { 291 unsigned char speed; 292 unsigned char width; 293 }; 294 295 struct devlog_params { 296 u32 memtype; /* which memory (EDC0, EDC1, MC) */ 297 u32 start; /* start of log in firmware memory */ 298 u32 size; /* size of log */ 299 }; 300 301 /* Stores chip specific parameters */ 302 struct arch_specific_params { 303 u8 nchan; 304 u8 pm_stats_cnt; 305 u8 cng_ch_bits_log; /* congestion channel map bits width */ 306 u16 mps_rplc_size; 307 u16 vfcount; 308 u32 sge_fl_db; 309 u16 mps_tcam_size; 310 }; 311 312 struct adapter_params { 313 struct sge_params sge; 314 struct tp_params tp; 315 struct vpd_params vpd; 316 struct pci_params pci; 317 struct devlog_params devlog; 318 enum pcie_memwin drv_memwin; 319 320 unsigned int cim_la_size; 321 322 unsigned int sf_size; /* serial flash size in bytes */ 323 unsigned int sf_nsec; /* # of flash sectors */ 324 unsigned int sf_fw_start; /* start of FW image in flash */ 325 326 unsigned int fw_vers; 327 unsigned int bs_vers; /* bootstrap version */ 328 unsigned int tp_vers; 329 unsigned int er_vers; /* expansion ROM version */ 330 u8 api_vers[7]; 331 332 unsigned short mtus[NMTUS]; 333 unsigned short a_wnd[NCCTRL_WIN]; 334 unsigned short b_wnd[NCCTRL_WIN]; 335 336 unsigned char nports; /* # of ethernet ports */ 337 unsigned char portvec; 338 enum chip_type chip; /* chip code */ 339 struct arch_specific_params arch; /* chip specific params */ 340 unsigned char offload; 341 342 unsigned char bypass; 343 344 unsigned int ofldq_wr_cred; 345 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ 346 347 unsigned int max_ordird_qp; /* Max read depth per RDMA QP */ 348 unsigned int max_ird_adapter; /* Max read depth per adapter */ 349 }; 350 351 /* State needed to monitor the forward progress of SGE Ingress DMA activities 352 * and possible hangs. 353 */ 354 struct sge_idma_monitor_state { 355 unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */ 356 unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */ 357 unsigned int idma_state[2]; /* IDMA Hang detect state */ 358 unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */ 359 unsigned int idma_warn[2]; /* time to warning in HZ */ 360 }; 361 362 /* Firmware Mailbox Command/Reply log. All values are in Host-Endian format. 363 * The access and execute times are signed in order to accommodate negative 364 * error returns. 365 */ 366 struct mbox_cmd { 367 u64 cmd[MBOX_LEN / 8]; /* a Firmware Mailbox Command/Reply */ 368 u64 timestamp; /* OS-dependent timestamp */ 369 u32 seqno; /* sequence number */ 370 s16 access; /* time (ms) to access mailbox */ 371 s16 execute; /* time (ms) to execute */ 372 }; 373 374 struct mbox_cmd_log { 375 unsigned int size; /* number of entries in the log */ 376 unsigned int cursor; /* next position in the log to write */ 377 u32 seqno; /* next sequence number */ 378 /* variable length mailbox command log starts here */ 379 }; 380 381 /* Given a pointer to a Firmware Mailbox Command Log and a log entry index, 382 * return a pointer to the specified entry. 383 */ 384 static inline struct mbox_cmd *mbox_cmd_log_entry(struct mbox_cmd_log *log, 385 unsigned int entry_idx) 386 { 387 return &((struct mbox_cmd *)&(log)[1])[entry_idx]; 388 } 389 390 #include "t4fw_api.h" 391 392 #define FW_VERSION(chip) ( \ 393 FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \ 394 FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \ 395 FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \ 396 FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD)) 397 #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf) 398 399 struct fw_info { 400 u8 chip; 401 char *fs_name; 402 char *fw_mod_name; 403 struct fw_hdr fw_hdr; 404 }; 405 406 407 struct trace_params { 408 u32 data[TRACE_LEN / 4]; 409 u32 mask[TRACE_LEN / 4]; 410 unsigned short snap_len; 411 unsigned short min_len; 412 unsigned char skip_ofst; 413 unsigned char skip_len; 414 unsigned char invert; 415 unsigned char port; 416 }; 417 418 struct link_config { 419 unsigned short supported; /* link capabilities */ 420 unsigned short advertising; /* advertised capabilities */ 421 unsigned short requested_speed; /* speed user has requested */ 422 unsigned short speed; /* actual link speed */ 423 unsigned char requested_fc; /* flow control user has requested */ 424 unsigned char fc; /* actual link flow control */ 425 unsigned char autoneg; /* autonegotiating? */ 426 unsigned char link_ok; /* link up? */ 427 unsigned char link_down_rc; /* link down reason */ 428 }; 429 430 #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16) 431 432 enum { 433 MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */ 434 MAX_OFLD_QSETS = 16, /* # of offload Tx, iscsi Rx queue sets */ 435 MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */ 436 MAX_RDMA_QUEUES = NCHAN, /* # of streaming RDMA Rx queues */ 437 MAX_RDMA_CIQS = 32, /* # of RDMA concentrator IQs */ 438 439 /* # of streaming iSCSIT Rx queues */ 440 MAX_ISCSIT_QUEUES = MAX_OFLD_QSETS, 441 }; 442 443 enum { 444 MAX_TXQ_ENTRIES = 16384, 445 MAX_CTRL_TXQ_ENTRIES = 1024, 446 MAX_RSPQ_ENTRIES = 16384, 447 MAX_RX_BUFFERS = 16384, 448 MIN_TXQ_ENTRIES = 32, 449 MIN_CTRL_TXQ_ENTRIES = 32, 450 MIN_RSPQ_ENTRIES = 128, 451 MIN_FL_ENTRIES = 16 452 }; 453 454 enum { 455 INGQ_EXTRAS = 2, /* firmware event queue and */ 456 /* forwarded interrupts */ 457 MAX_INGQ = MAX_ETH_QSETS + MAX_OFLD_QSETS + MAX_RDMA_QUEUES + 458 MAX_RDMA_CIQS + MAX_ISCSIT_QUEUES + INGQ_EXTRAS, 459 }; 460 461 struct adapter; 462 struct sge_rspq; 463 464 #include "cxgb4_dcb.h" 465 466 #ifdef CONFIG_CHELSIO_T4_FCOE 467 #include "cxgb4_fcoe.h" 468 #endif /* CONFIG_CHELSIO_T4_FCOE */ 469 470 struct port_info { 471 struct adapter *adapter; 472 u16 viid; 473 s16 xact_addr_filt; /* index of exact MAC address filter */ 474 u16 rss_size; /* size of VI's RSS table slice */ 475 s8 mdio_addr; 476 enum fw_port_type port_type; 477 u8 mod_type; 478 u8 port_id; 479 u8 tx_chan; 480 u8 lport; /* associated offload logical port */ 481 u8 nqsets; /* # of qsets */ 482 u8 first_qset; /* index of first qset */ 483 u8 rss_mode; 484 struct link_config link_cfg; 485 u16 *rss; 486 struct port_stats stats_base; 487 #ifdef CONFIG_CHELSIO_T4_DCB 488 struct port_dcb_info dcb; /* Data Center Bridging support */ 489 #endif 490 #ifdef CONFIG_CHELSIO_T4_FCOE 491 struct cxgb_fcoe fcoe; 492 #endif /* CONFIG_CHELSIO_T4_FCOE */ 493 bool rxtstamp; /* Enable TS */ 494 struct hwtstamp_config tstamp_config; 495 }; 496 497 struct dentry; 498 struct work_struct; 499 500 enum { /* adapter flags */ 501 FULL_INIT_DONE = (1 << 0), 502 DEV_ENABLED = (1 << 1), 503 USING_MSI = (1 << 2), 504 USING_MSIX = (1 << 3), 505 FW_OK = (1 << 4), 506 RSS_TNLALLLOOKUP = (1 << 5), 507 USING_SOFT_PARAMS = (1 << 6), 508 MASTER_PF = (1 << 7), 509 FW_OFLD_CONN = (1 << 9), 510 }; 511 512 struct rx_sw_desc; 513 514 struct sge_fl { /* SGE free-buffer queue state */ 515 unsigned int avail; /* # of available Rx buffers */ 516 unsigned int pend_cred; /* new buffers since last FL DB ring */ 517 unsigned int cidx; /* consumer index */ 518 unsigned int pidx; /* producer index */ 519 unsigned long alloc_failed; /* # of times buffer allocation failed */ 520 unsigned long large_alloc_failed; 521 unsigned long mapping_err; /* # of RX Buffer DMA Mapping failures */ 522 unsigned long low; /* # of times momentarily starving */ 523 unsigned long starving; 524 /* RO fields */ 525 unsigned int cntxt_id; /* SGE context id for the free list */ 526 unsigned int size; /* capacity of free list */ 527 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */ 528 __be64 *desc; /* address of HW Rx descriptor ring */ 529 dma_addr_t addr; /* bus address of HW ring start */ 530 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 531 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 532 }; 533 534 /* A packet gather list */ 535 struct pkt_gl { 536 u64 sgetstamp; /* SGE Time Stamp for Ingress Packet */ 537 struct page_frag frags[MAX_SKB_FRAGS]; 538 void *va; /* virtual address of first byte */ 539 unsigned int nfrags; /* # of fragments */ 540 unsigned int tot_len; /* total length of fragments */ 541 }; 542 543 typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp, 544 const struct pkt_gl *gl); 545 typedef void (*rspq_flush_handler_t)(struct sge_rspq *q); 546 /* LRO related declarations for ULD */ 547 struct t4_lro_mgr { 548 #define MAX_LRO_SESSIONS 64 549 u8 lro_session_cnt; /* # of sessions to aggregate */ 550 unsigned long lro_pkts; /* # of LRO super packets */ 551 unsigned long lro_merged; /* # of wire packets merged by LRO */ 552 struct sk_buff_head lroq; /* list of aggregated sessions */ 553 }; 554 555 struct sge_rspq { /* state for an SGE response queue */ 556 struct napi_struct napi; 557 const __be64 *cur_desc; /* current descriptor in queue */ 558 unsigned int cidx; /* consumer index */ 559 u8 gen; /* current generation bit */ 560 u8 intr_params; /* interrupt holdoff parameters */ 561 u8 next_intr_params; /* holdoff params for next interrupt */ 562 u8 adaptive_rx; 563 u8 pktcnt_idx; /* interrupt packet threshold */ 564 u8 uld; /* ULD handling this queue */ 565 u8 idx; /* queue index within its group */ 566 int offset; /* offset into current Rx buffer */ 567 u16 cntxt_id; /* SGE context id for the response q */ 568 u16 abs_id; /* absolute SGE id for the response q */ 569 __be64 *desc; /* address of HW response ring */ 570 dma_addr_t phys_addr; /* physical address of the ring */ 571 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 572 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 573 unsigned int iqe_len; /* entry size */ 574 unsigned int size; /* capacity of response queue */ 575 struct adapter *adap; 576 struct net_device *netdev; /* associated net device */ 577 rspq_handler_t handler; 578 rspq_flush_handler_t flush_handler; 579 struct t4_lro_mgr lro_mgr; 580 #ifdef CONFIG_NET_RX_BUSY_POLL 581 #define CXGB_POLL_STATE_IDLE 0 582 #define CXGB_POLL_STATE_NAPI BIT(0) /* NAPI owns this poll */ 583 #define CXGB_POLL_STATE_POLL BIT(1) /* poll owns this poll */ 584 #define CXGB_POLL_STATE_NAPI_YIELD BIT(2) /* NAPI yielded this poll */ 585 #define CXGB_POLL_STATE_POLL_YIELD BIT(3) /* poll yielded this poll */ 586 #define CXGB_POLL_YIELD (CXGB_POLL_STATE_NAPI_YIELD | \ 587 CXGB_POLL_STATE_POLL_YIELD) 588 #define CXGB_POLL_LOCKED (CXGB_POLL_STATE_NAPI | \ 589 CXGB_POLL_STATE_POLL) 590 #define CXGB_POLL_USER_PEND (CXGB_POLL_STATE_POLL | \ 591 CXGB_POLL_STATE_POLL_YIELD) 592 unsigned int bpoll_state; 593 spinlock_t bpoll_lock; /* lock for busy poll */ 594 #endif /* CONFIG_NET_RX_BUSY_POLL */ 595 596 }; 597 598 struct sge_eth_stats { /* Ethernet queue statistics */ 599 unsigned long pkts; /* # of ethernet packets */ 600 unsigned long lro_pkts; /* # of LRO super packets */ 601 unsigned long lro_merged; /* # of wire packets merged by LRO */ 602 unsigned long rx_cso; /* # of Rx checksum offloads */ 603 unsigned long vlan_ex; /* # of Rx VLAN extractions */ 604 unsigned long rx_drops; /* # of packets dropped due to no mem */ 605 }; 606 607 struct sge_eth_rxq { /* SW Ethernet Rx queue */ 608 struct sge_rspq rspq; 609 struct sge_fl fl; 610 struct sge_eth_stats stats; 611 } ____cacheline_aligned_in_smp; 612 613 struct sge_ofld_stats { /* offload queue statistics */ 614 unsigned long pkts; /* # of packets */ 615 unsigned long imm; /* # of immediate-data packets */ 616 unsigned long an; /* # of asynchronous notifications */ 617 unsigned long nomem; /* # of responses deferred due to no mem */ 618 }; 619 620 struct sge_ofld_rxq { /* SW offload Rx queue */ 621 struct sge_rspq rspq; 622 struct sge_fl fl; 623 struct sge_ofld_stats stats; 624 } ____cacheline_aligned_in_smp; 625 626 struct tx_desc { 627 __be64 flit[8]; 628 }; 629 630 struct tx_sw_desc; 631 632 struct sge_txq { 633 unsigned int in_use; /* # of in-use Tx descriptors */ 634 unsigned int size; /* # of descriptors */ 635 unsigned int cidx; /* SW consumer index */ 636 unsigned int pidx; /* producer index */ 637 unsigned long stops; /* # of times q has been stopped */ 638 unsigned long restarts; /* # of queue restarts */ 639 unsigned int cntxt_id; /* SGE context id for the Tx q */ 640 struct tx_desc *desc; /* address of HW Tx descriptor ring */ 641 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */ 642 struct sge_qstat *stat; /* queue status entry */ 643 dma_addr_t phys_addr; /* physical address of the ring */ 644 spinlock_t db_lock; 645 int db_disabled; 646 unsigned short db_pidx; 647 unsigned short db_pidx_inc; 648 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 649 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 650 }; 651 652 struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */ 653 struct sge_txq q; 654 struct netdev_queue *txq; /* associated netdev TX queue */ 655 #ifdef CONFIG_CHELSIO_T4_DCB 656 u8 dcb_prio; /* DCB Priority bound to queue */ 657 #endif 658 unsigned long tso; /* # of TSO requests */ 659 unsigned long tx_cso; /* # of Tx checksum offloads */ 660 unsigned long vlan_ins; /* # of Tx VLAN insertions */ 661 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 662 } ____cacheline_aligned_in_smp; 663 664 struct sge_ofld_txq { /* state for an SGE offload Tx queue */ 665 struct sge_txq q; 666 struct adapter *adap; 667 struct sk_buff_head sendq; /* list of backpressured packets */ 668 struct tasklet_struct qresume_tsk; /* restarts the queue */ 669 bool service_ofldq_running; /* service_ofldq() is processing sendq */ 670 u8 full; /* the Tx ring is full */ 671 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 672 } ____cacheline_aligned_in_smp; 673 674 struct sge_ctrl_txq { /* state for an SGE control Tx queue */ 675 struct sge_txq q; 676 struct adapter *adap; 677 struct sk_buff_head sendq; /* list of backpressured packets */ 678 struct tasklet_struct qresume_tsk; /* restarts the queue */ 679 u8 full; /* the Tx ring is full */ 680 } ____cacheline_aligned_in_smp; 681 682 struct sge { 683 struct sge_eth_txq ethtxq[MAX_ETH_QSETS]; 684 struct sge_ofld_txq ofldtxq[MAX_OFLD_QSETS]; 685 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES]; 686 687 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS]; 688 struct sge_ofld_rxq iscsirxq[MAX_OFLD_QSETS]; 689 struct sge_ofld_rxq iscsitrxq[MAX_ISCSIT_QUEUES]; 690 struct sge_ofld_rxq rdmarxq[MAX_RDMA_QUEUES]; 691 struct sge_ofld_rxq rdmaciq[MAX_RDMA_CIQS]; 692 struct sge_rspq fw_evtq ____cacheline_aligned_in_smp; 693 694 struct sge_rspq intrq ____cacheline_aligned_in_smp; 695 spinlock_t intrq_lock; 696 697 u16 max_ethqsets; /* # of available Ethernet queue sets */ 698 u16 ethqsets; /* # of active Ethernet queue sets */ 699 u16 ethtxq_rover; /* Tx queue to clean up next */ 700 u16 iscsiqsets; /* # of active iSCSI queue sets */ 701 u16 niscsitq; /* # of available iSCST Rx queues */ 702 u16 rdmaqs; /* # of available RDMA Rx queues */ 703 u16 rdmaciqs; /* # of available RDMA concentrator IQs */ 704 u16 iscsi_rxq[MAX_OFLD_QSETS]; 705 u16 iscsit_rxq[MAX_ISCSIT_QUEUES]; 706 u16 rdma_rxq[MAX_RDMA_QUEUES]; 707 u16 rdma_ciq[MAX_RDMA_CIQS]; 708 u16 timer_val[SGE_NTIMERS]; 709 u8 counter_val[SGE_NCOUNTERS]; 710 u32 fl_pg_order; /* large page allocation size */ 711 u32 stat_len; /* length of status page at ring end */ 712 u32 pktshift; /* padding between CPL & packet data */ 713 u32 fl_align; /* response queue message alignment */ 714 u32 fl_starve_thres; /* Free List starvation threshold */ 715 716 struct sge_idma_monitor_state idma_monitor; 717 unsigned int egr_start; 718 unsigned int egr_sz; 719 unsigned int ingr_start; 720 unsigned int ingr_sz; 721 void **egr_map; /* qid->queue egress queue map */ 722 struct sge_rspq **ingr_map; /* qid->queue ingress queue map */ 723 unsigned long *starving_fl; 724 unsigned long *txq_maperr; 725 unsigned long *blocked_fl; 726 struct timer_list rx_timer; /* refills starving FLs */ 727 struct timer_list tx_timer; /* checks Tx queues */ 728 }; 729 730 #define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++) 731 #define for_each_iscsirxq(sge, i) for (i = 0; i < (sge)->iscsiqsets; i++) 732 #define for_each_iscsitrxq(sge, i) for (i = 0; i < (sge)->niscsitq; i++) 733 #define for_each_rdmarxq(sge, i) for (i = 0; i < (sge)->rdmaqs; i++) 734 #define for_each_rdmaciq(sge, i) for (i = 0; i < (sge)->rdmaciqs; i++) 735 736 struct l2t_data; 737 738 #ifdef CONFIG_PCI_IOV 739 740 /* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial 741 * Configuration initialization for T5 only has SR-IOV functionality enabled 742 * on PF0-3 in order to simplify everything. 743 */ 744 #define NUM_OF_PF_WITH_SRIOV 4 745 746 #endif 747 748 struct doorbell_stats { 749 u32 db_drop; 750 u32 db_empty; 751 u32 db_full; 752 }; 753 754 struct hash_mac_addr { 755 struct list_head list; 756 u8 addr[ETH_ALEN]; 757 }; 758 759 struct adapter { 760 void __iomem *regs; 761 void __iomem *bar2; 762 u32 t4_bar0; 763 struct pci_dev *pdev; 764 struct device *pdev_dev; 765 const char *name; 766 unsigned int mbox; 767 unsigned int pf; 768 unsigned int flags; 769 enum chip_type chip; 770 771 int msg_enable; 772 773 struct adapter_params params; 774 struct cxgb4_virt_res vres; 775 unsigned int swintr; 776 777 struct { 778 unsigned short vec; 779 char desc[IFNAMSIZ + 10]; 780 } msix_info[MAX_INGQ + 1]; 781 782 struct doorbell_stats db_stats; 783 struct sge sge; 784 785 struct net_device *port[MAX_NPORTS]; 786 u8 chan_map[NCHAN]; /* channel -> port map */ 787 788 u32 filter_mode; 789 unsigned int l2t_start; 790 unsigned int l2t_end; 791 struct l2t_data *l2t; 792 unsigned int clipt_start; 793 unsigned int clipt_end; 794 struct clip_tbl *clipt; 795 void *uld_handle[CXGB4_ULD_MAX]; 796 struct list_head list_node; 797 struct list_head rcu_node; 798 struct list_head mac_hlist; /* list of MAC addresses in MPS Hash */ 799 800 void *iscsi_ppm; 801 802 struct tid_info tids; 803 void **tid_release_head; 804 spinlock_t tid_release_lock; 805 struct workqueue_struct *workq; 806 struct work_struct tid_release_task; 807 struct work_struct db_full_task; 808 struct work_struct db_drop_task; 809 bool tid_release_task_busy; 810 811 /* support for mailbox command/reply logging */ 812 #define T4_OS_LOG_MBOX_CMDS 256 813 struct mbox_cmd_log *mbox_log; 814 815 struct dentry *debugfs_root; 816 bool use_bd; /* Use SGE Back Door intfc for reading SGE Contexts */ 817 bool trace_rss; /* 1 implies that different RSS flit per filter is 818 * used per filter else if 0 default RSS flit is 819 * used for all 4 filters. 820 */ 821 822 spinlock_t stats_lock; 823 spinlock_t win0_lock ____cacheline_aligned_in_smp; 824 }; 825 826 /* Defined bit width of user definable filter tuples 827 */ 828 #define ETHTYPE_BITWIDTH 16 829 #define FRAG_BITWIDTH 1 830 #define MACIDX_BITWIDTH 9 831 #define FCOE_BITWIDTH 1 832 #define IPORT_BITWIDTH 3 833 #define MATCHTYPE_BITWIDTH 3 834 #define PROTO_BITWIDTH 8 835 #define TOS_BITWIDTH 8 836 #define PF_BITWIDTH 8 837 #define VF_BITWIDTH 8 838 #define IVLAN_BITWIDTH 16 839 #define OVLAN_BITWIDTH 16 840 841 /* Filter matching rules. These consist of a set of ingress packet field 842 * (value, mask) tuples. The associated ingress packet field matches the 843 * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field 844 * rule can be constructed by specifying a tuple of (0, 0).) A filter rule 845 * matches an ingress packet when all of the individual individual field 846 * matching rules are true. 847 * 848 * Partial field masks are always valid, however, while it may be easy to 849 * understand their meanings for some fields (e.g. IP address to match a 850 * subnet), for others making sensible partial masks is less intuitive (e.g. 851 * MPS match type) ... 852 * 853 * Most of the following data structures are modeled on T4 capabilities. 854 * Drivers for earlier chips use the subsets which make sense for those chips. 855 * We really need to come up with a hardware-independent mechanism to 856 * represent hardware filter capabilities ... 857 */ 858 struct ch_filter_tuple { 859 /* Compressed header matching field rules. The TP_VLAN_PRI_MAP 860 * register selects which of these fields will participate in the 861 * filter match rules -- up to a maximum of 36 bits. Because 862 * TP_VLAN_PRI_MAP is a global register, all filters must use the same 863 * set of fields. 864 */ 865 uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */ 866 uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */ 867 uint32_t ivlan_vld:1; /* inner VLAN valid */ 868 uint32_t ovlan_vld:1; /* outer VLAN valid */ 869 uint32_t pfvf_vld:1; /* PF/VF valid */ 870 uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */ 871 uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */ 872 uint32_t iport:IPORT_BITWIDTH; /* ingress port */ 873 uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */ 874 uint32_t proto:PROTO_BITWIDTH; /* protocol type */ 875 uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */ 876 uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */ 877 uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */ 878 uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */ 879 uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */ 880 881 /* Uncompressed header matching field rules. These are always 882 * available for field rules. 883 */ 884 uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */ 885 uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */ 886 uint16_t lport; /* local port */ 887 uint16_t fport; /* foreign port */ 888 }; 889 890 /* A filter ioctl command. 891 */ 892 struct ch_filter_specification { 893 /* Administrative fields for filter. 894 */ 895 uint32_t hitcnts:1; /* count filter hits in TCB */ 896 uint32_t prio:1; /* filter has priority over active/server */ 897 898 /* Fundamental filter typing. This is the one element of filter 899 * matching that doesn't exist as a (value, mask) tuple. 900 */ 901 uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */ 902 903 /* Packet dispatch information. Ingress packets which match the 904 * filter rules will be dropped, passed to the host or switched back 905 * out as egress packets. 906 */ 907 uint32_t action:2; /* drop, pass, switch */ 908 909 uint32_t rpttid:1; /* report TID in RSS hash field */ 910 911 uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */ 912 uint32_t iq:10; /* ingress queue */ 913 914 uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */ 915 uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */ 916 /* 1 => TCB contains IQ ID */ 917 918 /* Switch proxy/rewrite fields. An ingress packet which matches a 919 * filter with "switch" set will be looped back out as an egress 920 * packet -- potentially with some Ethernet header rewriting. 921 */ 922 uint32_t eport:2; /* egress port to switch packet out */ 923 uint32_t newdmac:1; /* rewrite destination MAC address */ 924 uint32_t newsmac:1; /* rewrite source MAC address */ 925 uint32_t newvlan:2; /* rewrite VLAN Tag */ 926 uint8_t dmac[ETH_ALEN]; /* new destination MAC address */ 927 uint8_t smac[ETH_ALEN]; /* new source MAC address */ 928 uint16_t vlan; /* VLAN Tag to insert */ 929 930 /* Filter rule value/mask pairs. 931 */ 932 struct ch_filter_tuple val; 933 struct ch_filter_tuple mask; 934 }; 935 936 enum { 937 FILTER_PASS = 0, /* default */ 938 FILTER_DROP, 939 FILTER_SWITCH 940 }; 941 942 enum { 943 VLAN_NOCHANGE = 0, /* default */ 944 VLAN_REMOVE, 945 VLAN_INSERT, 946 VLAN_REWRITE 947 }; 948 949 static inline int is_offload(const struct adapter *adap) 950 { 951 return adap->params.offload; 952 } 953 954 static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr) 955 { 956 return readl(adap->regs + reg_addr); 957 } 958 959 static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val) 960 { 961 writel(val, adap->regs + reg_addr); 962 } 963 964 #ifndef readq 965 static inline u64 readq(const volatile void __iomem *addr) 966 { 967 return readl(addr) + ((u64)readl(addr + 4) << 32); 968 } 969 970 static inline void writeq(u64 val, volatile void __iomem *addr) 971 { 972 writel(val, addr); 973 writel(val >> 32, addr + 4); 974 } 975 #endif 976 977 static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr) 978 { 979 return readq(adap->regs + reg_addr); 980 } 981 982 static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val) 983 { 984 writeq(val, adap->regs + reg_addr); 985 } 986 987 /** 988 * t4_set_hw_addr - store a port's MAC address in SW 989 * @adapter: the adapter 990 * @port_idx: the port index 991 * @hw_addr: the Ethernet address 992 * 993 * Store the Ethernet address of the given port in SW. Called by the common 994 * code when it retrieves a port's Ethernet address from EEPROM. 995 */ 996 static inline void t4_set_hw_addr(struct adapter *adapter, int port_idx, 997 u8 hw_addr[]) 998 { 999 ether_addr_copy(adapter->port[port_idx]->dev_addr, hw_addr); 1000 ether_addr_copy(adapter->port[port_idx]->perm_addr, hw_addr); 1001 } 1002 1003 /** 1004 * netdev2pinfo - return the port_info structure associated with a net_device 1005 * @dev: the netdev 1006 * 1007 * Return the struct port_info associated with a net_device 1008 */ 1009 static inline struct port_info *netdev2pinfo(const struct net_device *dev) 1010 { 1011 return netdev_priv(dev); 1012 } 1013 1014 /** 1015 * adap2pinfo - return the port_info of a port 1016 * @adap: the adapter 1017 * @idx: the port index 1018 * 1019 * Return the port_info structure for the port of the given index. 1020 */ 1021 static inline struct port_info *adap2pinfo(struct adapter *adap, int idx) 1022 { 1023 return netdev_priv(adap->port[idx]); 1024 } 1025 1026 /** 1027 * netdev2adap - return the adapter structure associated with a net_device 1028 * @dev: the netdev 1029 * 1030 * Return the struct adapter associated with a net_device 1031 */ 1032 static inline struct adapter *netdev2adap(const struct net_device *dev) 1033 { 1034 return netdev2pinfo(dev)->adapter; 1035 } 1036 1037 #ifdef CONFIG_NET_RX_BUSY_POLL 1038 static inline void cxgb_busy_poll_init_lock(struct sge_rspq *q) 1039 { 1040 spin_lock_init(&q->bpoll_lock); 1041 q->bpoll_state = CXGB_POLL_STATE_IDLE; 1042 } 1043 1044 static inline bool cxgb_poll_lock_napi(struct sge_rspq *q) 1045 { 1046 bool rc = true; 1047 1048 spin_lock(&q->bpoll_lock); 1049 if (q->bpoll_state & CXGB_POLL_LOCKED) { 1050 q->bpoll_state |= CXGB_POLL_STATE_NAPI_YIELD; 1051 rc = false; 1052 } else { 1053 q->bpoll_state = CXGB_POLL_STATE_NAPI; 1054 } 1055 spin_unlock(&q->bpoll_lock); 1056 return rc; 1057 } 1058 1059 static inline bool cxgb_poll_unlock_napi(struct sge_rspq *q) 1060 { 1061 bool rc = false; 1062 1063 spin_lock(&q->bpoll_lock); 1064 if (q->bpoll_state & CXGB_POLL_STATE_POLL_YIELD) 1065 rc = true; 1066 q->bpoll_state = CXGB_POLL_STATE_IDLE; 1067 spin_unlock(&q->bpoll_lock); 1068 return rc; 1069 } 1070 1071 static inline bool cxgb_poll_lock_poll(struct sge_rspq *q) 1072 { 1073 bool rc = true; 1074 1075 spin_lock_bh(&q->bpoll_lock); 1076 if (q->bpoll_state & CXGB_POLL_LOCKED) { 1077 q->bpoll_state |= CXGB_POLL_STATE_POLL_YIELD; 1078 rc = false; 1079 } else { 1080 q->bpoll_state |= CXGB_POLL_STATE_POLL; 1081 } 1082 spin_unlock_bh(&q->bpoll_lock); 1083 return rc; 1084 } 1085 1086 static inline bool cxgb_poll_unlock_poll(struct sge_rspq *q) 1087 { 1088 bool rc = false; 1089 1090 spin_lock_bh(&q->bpoll_lock); 1091 if (q->bpoll_state & CXGB_POLL_STATE_POLL_YIELD) 1092 rc = true; 1093 q->bpoll_state = CXGB_POLL_STATE_IDLE; 1094 spin_unlock_bh(&q->bpoll_lock); 1095 return rc; 1096 } 1097 1098 static inline bool cxgb_poll_busy_polling(struct sge_rspq *q) 1099 { 1100 return q->bpoll_state & CXGB_POLL_USER_PEND; 1101 } 1102 #else 1103 static inline void cxgb_busy_poll_init_lock(struct sge_rspq *q) 1104 { 1105 } 1106 1107 static inline bool cxgb_poll_lock_napi(struct sge_rspq *q) 1108 { 1109 return true; 1110 } 1111 1112 static inline bool cxgb_poll_unlock_napi(struct sge_rspq *q) 1113 { 1114 return false; 1115 } 1116 1117 static inline bool cxgb_poll_lock_poll(struct sge_rspq *q) 1118 { 1119 return false; 1120 } 1121 1122 static inline bool cxgb_poll_unlock_poll(struct sge_rspq *q) 1123 { 1124 return false; 1125 } 1126 1127 static inline bool cxgb_poll_busy_polling(struct sge_rspq *q) 1128 { 1129 return false; 1130 } 1131 #endif /* CONFIG_NET_RX_BUSY_POLL */ 1132 1133 /* Return a version number to identify the type of adapter. The scheme is: 1134 * - bits 0..9: chip version 1135 * - bits 10..15: chip revision 1136 * - bits 16..23: register dump version 1137 */ 1138 static inline unsigned int mk_adap_vers(struct adapter *ap) 1139 { 1140 return CHELSIO_CHIP_VERSION(ap->params.chip) | 1141 (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16); 1142 } 1143 1144 /* Return a queue's interrupt hold-off time in us. 0 means no timer. */ 1145 static inline unsigned int qtimer_val(const struct adapter *adap, 1146 const struct sge_rspq *q) 1147 { 1148 unsigned int idx = q->intr_params >> 1; 1149 1150 return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0; 1151 } 1152 1153 /* driver version & name used for ethtool_drvinfo */ 1154 extern char cxgb4_driver_name[]; 1155 extern const char cxgb4_driver_version[]; 1156 1157 void t4_os_portmod_changed(const struct adapter *adap, int port_id); 1158 void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat); 1159 1160 void *t4_alloc_mem(size_t size); 1161 1162 void t4_free_sge_resources(struct adapter *adap); 1163 void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q); 1164 irq_handler_t t4_intr_handler(struct adapter *adap); 1165 netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev); 1166 int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp, 1167 const struct pkt_gl *gl); 1168 int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb); 1169 int t4_ofld_send(struct adapter *adap, struct sk_buff *skb); 1170 int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, 1171 struct net_device *dev, int intr_idx, 1172 struct sge_fl *fl, rspq_handler_t hnd, 1173 rspq_flush_handler_t flush_handler, int cong); 1174 int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq, 1175 struct net_device *dev, struct netdev_queue *netdevq, 1176 unsigned int iqid); 1177 int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq, 1178 struct net_device *dev, unsigned int iqid, 1179 unsigned int cmplqid); 1180 int t4_sge_alloc_ofld_txq(struct adapter *adap, struct sge_ofld_txq *txq, 1181 struct net_device *dev, unsigned int iqid); 1182 irqreturn_t t4_sge_intr_msix(int irq, void *cookie); 1183 int t4_sge_init(struct adapter *adap); 1184 void t4_sge_start(struct adapter *adap); 1185 void t4_sge_stop(struct adapter *adap); 1186 int cxgb_busy_poll(struct napi_struct *napi); 1187 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us, 1188 unsigned int cnt); 1189 void cxgb4_set_ethtool_ops(struct net_device *netdev); 1190 int cxgb4_write_rss(const struct port_info *pi, const u16 *queues); 1191 extern int dbfifo_int_thresh; 1192 1193 #define for_each_port(adapter, iter) \ 1194 for (iter = 0; iter < (adapter)->params.nports; ++iter) 1195 1196 static inline int is_bypass(struct adapter *adap) 1197 { 1198 return adap->params.bypass; 1199 } 1200 1201 static inline int is_bypass_device(int device) 1202 { 1203 /* this should be set based upon device capabilities */ 1204 switch (device) { 1205 case 0x440b: 1206 case 0x440c: 1207 return 1; 1208 default: 1209 return 0; 1210 } 1211 } 1212 1213 static inline int is_10gbt_device(int device) 1214 { 1215 /* this should be set based upon device capabilities */ 1216 switch (device) { 1217 case 0x4409: 1218 case 0x4486: 1219 return 1; 1220 1221 default: 1222 return 0; 1223 } 1224 } 1225 1226 static inline unsigned int core_ticks_per_usec(const struct adapter *adap) 1227 { 1228 return adap->params.vpd.cclk / 1000; 1229 } 1230 1231 static inline unsigned int us_to_core_ticks(const struct adapter *adap, 1232 unsigned int us) 1233 { 1234 return (us * adap->params.vpd.cclk) / 1000; 1235 } 1236 1237 static inline unsigned int core_ticks_to_us(const struct adapter *adapter, 1238 unsigned int ticks) 1239 { 1240 /* add Core Clock / 2 to round ticks to nearest uS */ 1241 return ((ticks * 1000 + adapter->params.vpd.cclk/2) / 1242 adapter->params.vpd.cclk); 1243 } 1244 1245 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, 1246 u32 val); 1247 1248 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 1249 int size, void *rpl, bool sleep_ok, int timeout); 1250 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 1251 void *rpl, bool sleep_ok); 1252 1253 static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox, 1254 const void *cmd, int size, void *rpl, 1255 int timeout) 1256 { 1257 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true, 1258 timeout); 1259 } 1260 1261 static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, 1262 int size, void *rpl) 1263 { 1264 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true); 1265 } 1266 1267 static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, 1268 int size, void *rpl) 1269 { 1270 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false); 1271 } 1272 1273 /** 1274 * hash_mac_addr - return the hash value of a MAC address 1275 * @addr: the 48-bit Ethernet MAC address 1276 * 1277 * Hashes a MAC address according to the hash function used by HW inexact 1278 * (hash) address matching. 1279 */ 1280 static inline int hash_mac_addr(const u8 *addr) 1281 { 1282 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2]; 1283 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5]; 1284 1285 a ^= b; 1286 a ^= (a >> 12); 1287 a ^= (a >> 6); 1288 return a & 0x3f; 1289 } 1290 1291 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 1292 unsigned int data_reg, const u32 *vals, 1293 unsigned int nregs, unsigned int start_idx); 1294 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 1295 unsigned int data_reg, u32 *vals, unsigned int nregs, 1296 unsigned int start_idx); 1297 void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val); 1298 1299 struct fw_filter_wr; 1300 1301 void t4_intr_enable(struct adapter *adapter); 1302 void t4_intr_disable(struct adapter *adapter); 1303 int t4_slow_intr_handler(struct adapter *adapter); 1304 1305 int t4_wait_dev_ready(void __iomem *regs); 1306 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port, 1307 struct link_config *lc); 1308 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port); 1309 1310 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg); 1311 u32 t4_get_util_window(struct adapter *adap); 1312 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window); 1313 1314 #define T4_MEMORY_WRITE 0 1315 #define T4_MEMORY_READ 1 1316 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len, 1317 void *buf, int dir); 1318 static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr, 1319 u32 len, __be32 *buf) 1320 { 1321 return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0); 1322 } 1323 1324 unsigned int t4_get_regs_len(struct adapter *adapter); 1325 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size); 1326 1327 int t4_seeprom_wp(struct adapter *adapter, bool enable); 1328 int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p); 1329 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p); 1330 int t4_read_flash(struct adapter *adapter, unsigned int addr, 1331 unsigned int nwords, u32 *data, int byte_oriented); 1332 int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size); 1333 int t4_load_phy_fw(struct adapter *adap, 1334 int win, spinlock_t *lock, 1335 int (*phy_fw_version)(const u8 *, size_t), 1336 const u8 *phy_fw_data, size_t phy_fw_size); 1337 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver); 1338 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op); 1339 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 1340 const u8 *fw_data, unsigned int size, int force); 1341 int t4_fl_pkt_align(struct adapter *adap); 1342 unsigned int t4_flash_cfg_addr(struct adapter *adapter); 1343 int t4_check_fw_version(struct adapter *adap); 1344 int t4_get_fw_version(struct adapter *adapter, u32 *vers); 1345 int t4_get_bs_version(struct adapter *adapter, u32 *vers); 1346 int t4_get_tp_version(struct adapter *adapter, u32 *vers); 1347 int t4_get_exprom_version(struct adapter *adapter, u32 *vers); 1348 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info, 1349 const u8 *fw_data, unsigned int fw_size, 1350 struct fw_hdr *card_fw, enum dev_state state, int *reset); 1351 int t4_prep_adapter(struct adapter *adapter); 1352 1353 enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS }; 1354 int t4_bar2_sge_qregs(struct adapter *adapter, 1355 unsigned int qid, 1356 enum t4_bar2_qtype qtype, 1357 int user, 1358 u64 *pbar2_qoffset, 1359 unsigned int *pbar2_qid); 1360 1361 unsigned int qtimer_val(const struct adapter *adap, 1362 const struct sge_rspq *q); 1363 1364 int t4_init_devlog_params(struct adapter *adapter); 1365 int t4_init_sge_params(struct adapter *adapter); 1366 int t4_init_tp_params(struct adapter *adap); 1367 int t4_filter_field_shift(const struct adapter *adap, int filter_sel); 1368 int t4_init_rss_mode(struct adapter *adap, int mbox); 1369 int t4_init_portinfo(struct port_info *pi, int mbox, 1370 int port, int pf, int vf, u8 mac[]); 1371 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf); 1372 void t4_fatal_err(struct adapter *adapter); 1373 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 1374 int start, int n, const u16 *rspq, unsigned int nrspq); 1375 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 1376 unsigned int flags); 1377 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 1378 unsigned int flags, unsigned int defq); 1379 int t4_read_rss(struct adapter *adapter, u16 *entries); 1380 void t4_read_rss_key(struct adapter *adapter, u32 *key); 1381 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx); 1382 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, 1383 u32 *valp); 1384 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 1385 u32 *vfl, u32 *vfh); 1386 u32 t4_read_rss_pf_map(struct adapter *adapter); 1387 u32 t4_read_rss_pf_mask(struct adapter *adapter); 1388 1389 unsigned int t4_get_mps_bg_map(struct adapter *adapter, int idx); 1390 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1391 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1392 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, 1393 size_t n); 1394 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, 1395 size_t n); 1396 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 1397 unsigned int *valp); 1398 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 1399 const unsigned int *valp); 1400 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr); 1401 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, 1402 unsigned int *pif_req_wrptr, 1403 unsigned int *pif_rsp_wrptr); 1404 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp); 1405 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres); 1406 const char *t4_get_port_type_description(enum fw_port_type port_type); 1407 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); 1408 void t4_get_port_stats_offset(struct adapter *adap, int idx, 1409 struct port_stats *stats, 1410 struct port_stats *offset); 1411 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p); 1412 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); 1413 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]); 1414 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 1415 unsigned int mask, unsigned int val); 1416 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr); 1417 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st); 1418 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st); 1419 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st); 1420 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st); 1421 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 1422 struct tp_tcp_stats *v6); 1423 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 1424 struct tp_fcoe_stats *st); 1425 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 1426 const unsigned short *alpha, const unsigned short *beta); 1427 1428 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf); 1429 1430 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate); 1431 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid); 1432 1433 void t4_wol_magic_enable(struct adapter *adap, unsigned int port, 1434 const u8 *addr); 1435 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 1436 u64 mask0, u64 mask1, unsigned int crc, bool enable); 1437 1438 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 1439 enum dev_master master, enum dev_state *state); 1440 int t4_fw_bye(struct adapter *adap, unsigned int mbox); 1441 int t4_early_init(struct adapter *adap, unsigned int mbox); 1442 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); 1443 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, 1444 unsigned int cache_line_size); 1445 int t4_fw_initialize(struct adapter *adap, unsigned int mbox); 1446 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1447 unsigned int vf, unsigned int nparams, const u32 *params, 1448 u32 *val); 1449 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, 1450 unsigned int vf, unsigned int nparams, const u32 *params, 1451 u32 *val, int rw); 1452 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 1453 unsigned int pf, unsigned int vf, 1454 unsigned int nparams, const u32 *params, 1455 const u32 *val, int timeout); 1456 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1457 unsigned int vf, unsigned int nparams, const u32 *params, 1458 const u32 *val); 1459 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 1460 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 1461 unsigned int rxqi, unsigned int rxq, unsigned int tc, 1462 unsigned int vi, unsigned int cmask, unsigned int pmask, 1463 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps); 1464 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 1465 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 1466 unsigned int *rss_size); 1467 int t4_free_vi(struct adapter *adap, unsigned int mbox, 1468 unsigned int pf, unsigned int vf, 1469 unsigned int viid); 1470 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 1471 int mtu, int promisc, int all_multi, int bcast, int vlanex, 1472 bool sleep_ok); 1473 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, 1474 unsigned int viid, bool free, unsigned int naddr, 1475 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok); 1476 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox, 1477 unsigned int viid, unsigned int naddr, 1478 const u8 **addr, bool sleep_ok); 1479 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 1480 int idx, const u8 *addr, bool persist, bool add_smt); 1481 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 1482 bool ucast, u64 vec, bool sleep_ok); 1483 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 1484 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en); 1485 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 1486 bool rx_en, bool tx_en); 1487 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 1488 unsigned int nblinks); 1489 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1490 unsigned int mmd, unsigned int reg, u16 *valp); 1491 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1492 unsigned int mmd, unsigned int reg, u16 val); 1493 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, 1494 unsigned int vf, unsigned int iqtype, unsigned int iqid, 1495 unsigned int fl0id, unsigned int fl1id); 1496 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1497 unsigned int vf, unsigned int iqtype, unsigned int iqid, 1498 unsigned int fl0id, unsigned int fl1id); 1499 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1500 unsigned int vf, unsigned int eqid); 1501 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1502 unsigned int vf, unsigned int eqid); 1503 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1504 unsigned int vf, unsigned int eqid); 1505 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox); 1506 void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl); 1507 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); 1508 void t4_db_full(struct adapter *adapter); 1509 void t4_db_dropped(struct adapter *adapter); 1510 int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp, 1511 int filter_index, int enable); 1512 void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp, 1513 int filter_index, int *enabled); 1514 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, 1515 u32 addr, u32 val); 1516 void t4_sge_decode_idma_state(struct adapter *adapter, int state); 1517 void t4_free_mem(void *addr); 1518 void t4_idma_monitor_init(struct adapter *adapter, 1519 struct sge_idma_monitor_state *idma); 1520 void t4_idma_monitor(struct adapter *adapter, 1521 struct sge_idma_monitor_state *idma, 1522 int hz, int ticks); 1523 #endif /* __CXGB4_H__ */ 1524