1 /* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #ifndef __CXGB4_H__ 36 #define __CXGB4_H__ 37 38 #include "t4_hw.h" 39 40 #include <linux/bitops.h> 41 #include <linux/cache.h> 42 #include <linux/interrupt.h> 43 #include <linux/list.h> 44 #include <linux/netdevice.h> 45 #include <linux/pci.h> 46 #include <linux/spinlock.h> 47 #include <linux/timer.h> 48 #include <linux/vmalloc.h> 49 #include <linux/etherdevice.h> 50 #include <linux/net_tstamp.h> 51 #include <asm/io.h> 52 #include "t4_chip_type.h" 53 #include "cxgb4_uld.h" 54 55 #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__) 56 extern struct list_head adapter_list; 57 extern struct mutex uld_mutex; 58 59 enum { 60 MAX_NPORTS = 4, /* max # of ports */ 61 SERNUM_LEN = 24, /* Serial # length */ 62 EC_LEN = 16, /* E/C length */ 63 ID_LEN = 16, /* ID length */ 64 PN_LEN = 16, /* Part Number length */ 65 MACADDR_LEN = 12, /* MAC Address length */ 66 }; 67 68 enum { 69 T4_REGMAP_SIZE = (160 * 1024), 70 T5_REGMAP_SIZE = (332 * 1024), 71 }; 72 73 enum { 74 MEM_EDC0, 75 MEM_EDC1, 76 MEM_MC, 77 MEM_MC0 = MEM_MC, 78 MEM_MC1 79 }; 80 81 enum { 82 MEMWIN0_APERTURE = 2048, 83 MEMWIN0_BASE = 0x1b800, 84 MEMWIN1_APERTURE = 32768, 85 MEMWIN1_BASE = 0x28000, 86 MEMWIN1_BASE_T5 = 0x52000, 87 MEMWIN2_APERTURE = 65536, 88 MEMWIN2_BASE = 0x30000, 89 MEMWIN2_APERTURE_T5 = 131072, 90 MEMWIN2_BASE_T5 = 0x60000, 91 }; 92 93 enum dev_master { 94 MASTER_CANT, 95 MASTER_MAY, 96 MASTER_MUST 97 }; 98 99 enum dev_state { 100 DEV_STATE_UNINIT, 101 DEV_STATE_INIT, 102 DEV_STATE_ERR 103 }; 104 105 enum { 106 PAUSE_RX = 1 << 0, 107 PAUSE_TX = 1 << 1, 108 PAUSE_AUTONEG = 1 << 2 109 }; 110 111 enum { 112 FEC_AUTO = 1 << 0, /* IEEE 802.3 "automatic" */ 113 FEC_RS = 1 << 1, /* Reed-Solomon */ 114 FEC_BASER_RS = 1 << 2 /* BaseR/Reed-Solomon */ 115 }; 116 117 struct port_stats { 118 u64 tx_octets; /* total # of octets in good frames */ 119 u64 tx_frames; /* all good frames */ 120 u64 tx_bcast_frames; /* all broadcast frames */ 121 u64 tx_mcast_frames; /* all multicast frames */ 122 u64 tx_ucast_frames; /* all unicast frames */ 123 u64 tx_error_frames; /* all error frames */ 124 125 u64 tx_frames_64; /* # of Tx frames in a particular range */ 126 u64 tx_frames_65_127; 127 u64 tx_frames_128_255; 128 u64 tx_frames_256_511; 129 u64 tx_frames_512_1023; 130 u64 tx_frames_1024_1518; 131 u64 tx_frames_1519_max; 132 133 u64 tx_drop; /* # of dropped Tx frames */ 134 u64 tx_pause; /* # of transmitted pause frames */ 135 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ 136 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ 137 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ 138 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ 139 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ 140 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ 141 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ 142 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ 143 144 u64 rx_octets; /* total # of octets in good frames */ 145 u64 rx_frames; /* all good frames */ 146 u64 rx_bcast_frames; /* all broadcast frames */ 147 u64 rx_mcast_frames; /* all multicast frames */ 148 u64 rx_ucast_frames; /* all unicast frames */ 149 u64 rx_too_long; /* # of frames exceeding MTU */ 150 u64 rx_jabber; /* # of jabber frames */ 151 u64 rx_fcs_err; /* # of received frames with bad FCS */ 152 u64 rx_len_err; /* # of received frames with length error */ 153 u64 rx_symbol_err; /* symbol errors */ 154 u64 rx_runt; /* # of short frames */ 155 156 u64 rx_frames_64; /* # of Rx frames in a particular range */ 157 u64 rx_frames_65_127; 158 u64 rx_frames_128_255; 159 u64 rx_frames_256_511; 160 u64 rx_frames_512_1023; 161 u64 rx_frames_1024_1518; 162 u64 rx_frames_1519_max; 163 164 u64 rx_pause; /* # of received pause frames */ 165 u64 rx_ppp0; /* # of received PPP prio 0 frames */ 166 u64 rx_ppp1; /* # of received PPP prio 1 frames */ 167 u64 rx_ppp2; /* # of received PPP prio 2 frames */ 168 u64 rx_ppp3; /* # of received PPP prio 3 frames */ 169 u64 rx_ppp4; /* # of received PPP prio 4 frames */ 170 u64 rx_ppp5; /* # of received PPP prio 5 frames */ 171 u64 rx_ppp6; /* # of received PPP prio 6 frames */ 172 u64 rx_ppp7; /* # of received PPP prio 7 frames */ 173 174 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ 175 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ 176 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ 177 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ 178 u64 rx_trunc0; /* buffer-group 0 truncated packets */ 179 u64 rx_trunc1; /* buffer-group 1 truncated packets */ 180 u64 rx_trunc2; /* buffer-group 2 truncated packets */ 181 u64 rx_trunc3; /* buffer-group 3 truncated packets */ 182 }; 183 184 struct lb_port_stats { 185 u64 octets; 186 u64 frames; 187 u64 bcast_frames; 188 u64 mcast_frames; 189 u64 ucast_frames; 190 u64 error_frames; 191 192 u64 frames_64; 193 u64 frames_65_127; 194 u64 frames_128_255; 195 u64 frames_256_511; 196 u64 frames_512_1023; 197 u64 frames_1024_1518; 198 u64 frames_1519_max; 199 200 u64 drop; 201 202 u64 ovflow0; 203 u64 ovflow1; 204 u64 ovflow2; 205 u64 ovflow3; 206 u64 trunc0; 207 u64 trunc1; 208 u64 trunc2; 209 u64 trunc3; 210 }; 211 212 struct tp_tcp_stats { 213 u32 tcp_out_rsts; 214 u64 tcp_in_segs; 215 u64 tcp_out_segs; 216 u64 tcp_retrans_segs; 217 }; 218 219 struct tp_usm_stats { 220 u32 frames; 221 u32 drops; 222 u64 octets; 223 }; 224 225 struct tp_fcoe_stats { 226 u32 frames_ddp; 227 u32 frames_drop; 228 u64 octets_ddp; 229 }; 230 231 struct tp_err_stats { 232 u32 mac_in_errs[4]; 233 u32 hdr_in_errs[4]; 234 u32 tcp_in_errs[4]; 235 u32 tnl_cong_drops[4]; 236 u32 ofld_chan_drops[4]; 237 u32 tnl_tx_drops[4]; 238 u32 ofld_vlan_drops[4]; 239 u32 tcp6_in_errs[4]; 240 u32 ofld_no_neigh; 241 u32 ofld_cong_defer; 242 }; 243 244 struct tp_cpl_stats { 245 u32 req[4]; 246 u32 rsp[4]; 247 }; 248 249 struct tp_rdma_stats { 250 u32 rqe_dfr_pkt; 251 u32 rqe_dfr_mod; 252 }; 253 254 struct sge_params { 255 u32 hps; /* host page size for our PF/VF */ 256 u32 eq_qpp; /* egress queues/page for our PF/VF */ 257 u32 iq_qpp; /* egress queues/page for our PF/VF */ 258 }; 259 260 struct tp_params { 261 unsigned int tre; /* log2 of core clocks per TP tick */ 262 unsigned int la_mask; /* what events are recorded by TP LA */ 263 unsigned short tx_modq_map; /* TX modulation scheduler queue to */ 264 /* channel map */ 265 266 uint32_t dack_re; /* DACK timer resolution */ 267 unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */ 268 269 u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */ 270 u32 ingress_config; /* cached TP_INGRESS_CONFIG */ 271 272 /* cached TP_OUT_CONFIG compressed error vector 273 * and passing outer header info for encapsulated packets. 274 */ 275 int rx_pkt_encap; 276 277 /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a 278 * subset of the set of fields which may be present in the Compressed 279 * Filter Tuple portion of filters and TCP TCB connections. The 280 * fields which are present are controlled by the TP_VLAN_PRI_MAP. 281 * Since a variable number of fields may or may not be present, their 282 * shifted field positions within the Compressed Filter Tuple may 283 * vary, or not even be present if the field isn't selected in 284 * TP_VLAN_PRI_MAP. Since some of these fields are needed in various 285 * places we store their offsets here, or a -1 if the field isn't 286 * present. 287 */ 288 int vlan_shift; 289 int vnic_shift; 290 int port_shift; 291 int protocol_shift; 292 }; 293 294 struct vpd_params { 295 unsigned int cclk; 296 u8 ec[EC_LEN + 1]; 297 u8 sn[SERNUM_LEN + 1]; 298 u8 id[ID_LEN + 1]; 299 u8 pn[PN_LEN + 1]; 300 u8 na[MACADDR_LEN + 1]; 301 }; 302 303 struct pci_params { 304 unsigned char speed; 305 unsigned char width; 306 }; 307 308 struct devlog_params { 309 u32 memtype; /* which memory (EDC0, EDC1, MC) */ 310 u32 start; /* start of log in firmware memory */ 311 u32 size; /* size of log */ 312 }; 313 314 /* Stores chip specific parameters */ 315 struct arch_specific_params { 316 u8 nchan; 317 u8 pm_stats_cnt; 318 u8 cng_ch_bits_log; /* congestion channel map bits width */ 319 u16 mps_rplc_size; 320 u16 vfcount; 321 u32 sge_fl_db; 322 u16 mps_tcam_size; 323 }; 324 325 struct adapter_params { 326 struct sge_params sge; 327 struct tp_params tp; 328 struct vpd_params vpd; 329 struct pci_params pci; 330 struct devlog_params devlog; 331 enum pcie_memwin drv_memwin; 332 333 unsigned int cim_la_size; 334 335 unsigned int sf_size; /* serial flash size in bytes */ 336 unsigned int sf_nsec; /* # of flash sectors */ 337 unsigned int sf_fw_start; /* start of FW image in flash */ 338 339 unsigned int fw_vers; 340 unsigned int bs_vers; /* bootstrap version */ 341 unsigned int tp_vers; 342 unsigned int er_vers; /* expansion ROM version */ 343 u8 api_vers[7]; 344 345 unsigned short mtus[NMTUS]; 346 unsigned short a_wnd[NCCTRL_WIN]; 347 unsigned short b_wnd[NCCTRL_WIN]; 348 349 unsigned char nports; /* # of ethernet ports */ 350 unsigned char portvec; 351 enum chip_type chip; /* chip code */ 352 struct arch_specific_params arch; /* chip specific params */ 353 unsigned char offload; 354 unsigned char crypto; /* HW capability for crypto */ 355 356 unsigned char bypass; 357 358 unsigned int ofldq_wr_cred; 359 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ 360 361 unsigned int nsched_cls; /* number of traffic classes */ 362 unsigned int max_ordird_qp; /* Max read depth per RDMA QP */ 363 unsigned int max_ird_adapter; /* Max read depth per adapter */ 364 bool fr_nsmr_tpte_wr_support; /* FW support for FR_NSMR_TPTE_WR */ 365 366 /* MPS Buffer Group Map[per Port]. Bit i is set if buffer group i is 367 * used by the Port 368 */ 369 u8 mps_bg_map[MAX_NPORTS]; /* MPS Buffer Group Map */ 370 }; 371 372 /* State needed to monitor the forward progress of SGE Ingress DMA activities 373 * and possible hangs. 374 */ 375 struct sge_idma_monitor_state { 376 unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */ 377 unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */ 378 unsigned int idma_state[2]; /* IDMA Hang detect state */ 379 unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */ 380 unsigned int idma_warn[2]; /* time to warning in HZ */ 381 }; 382 383 /* Firmware Mailbox Command/Reply log. All values are in Host-Endian format. 384 * The access and execute times are signed in order to accommodate negative 385 * error returns. 386 */ 387 struct mbox_cmd { 388 u64 cmd[MBOX_LEN / 8]; /* a Firmware Mailbox Command/Reply */ 389 u64 timestamp; /* OS-dependent timestamp */ 390 u32 seqno; /* sequence number */ 391 s16 access; /* time (ms) to access mailbox */ 392 s16 execute; /* time (ms) to execute */ 393 }; 394 395 struct mbox_cmd_log { 396 unsigned int size; /* number of entries in the log */ 397 unsigned int cursor; /* next position in the log to write */ 398 u32 seqno; /* next sequence number */ 399 /* variable length mailbox command log starts here */ 400 }; 401 402 /* Given a pointer to a Firmware Mailbox Command Log and a log entry index, 403 * return a pointer to the specified entry. 404 */ 405 static inline struct mbox_cmd *mbox_cmd_log_entry(struct mbox_cmd_log *log, 406 unsigned int entry_idx) 407 { 408 return &((struct mbox_cmd *)&(log)[1])[entry_idx]; 409 } 410 411 #include "t4fw_api.h" 412 413 #define FW_VERSION(chip) ( \ 414 FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \ 415 FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \ 416 FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \ 417 FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD)) 418 #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf) 419 420 struct fw_info { 421 u8 chip; 422 char *fs_name; 423 char *fw_mod_name; 424 struct fw_hdr fw_hdr; 425 }; 426 427 struct trace_params { 428 u32 data[TRACE_LEN / 4]; 429 u32 mask[TRACE_LEN / 4]; 430 unsigned short snap_len; 431 unsigned short min_len; 432 unsigned char skip_ofst; 433 unsigned char skip_len; 434 unsigned char invert; 435 unsigned char port; 436 }; 437 438 struct link_config { 439 unsigned short supported; /* link capabilities */ 440 unsigned short advertising; /* advertised capabilities */ 441 unsigned short lp_advertising; /* peer advertised capabilities */ 442 unsigned int requested_speed; /* speed user has requested */ 443 unsigned int speed; /* actual link speed */ 444 unsigned char requested_fc; /* flow control user has requested */ 445 unsigned char fc; /* actual link flow control */ 446 unsigned char auto_fec; /* Forward Error Correction: */ 447 unsigned char requested_fec; /* "automatic" (IEEE 802.3), */ 448 unsigned char fec; /* requested, and actual in use */ 449 unsigned char autoneg; /* autonegotiating? */ 450 unsigned char link_ok; /* link up? */ 451 unsigned char link_down_rc; /* link down reason */ 452 }; 453 454 #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16) 455 456 enum { 457 MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */ 458 MAX_OFLD_QSETS = 16, /* # of offload Tx, iscsi Rx queue sets */ 459 MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */ 460 }; 461 462 enum { 463 MAX_TXQ_ENTRIES = 16384, 464 MAX_CTRL_TXQ_ENTRIES = 1024, 465 MAX_RSPQ_ENTRIES = 16384, 466 MAX_RX_BUFFERS = 16384, 467 MIN_TXQ_ENTRIES = 32, 468 MIN_CTRL_TXQ_ENTRIES = 32, 469 MIN_RSPQ_ENTRIES = 128, 470 MIN_FL_ENTRIES = 16 471 }; 472 473 enum { 474 INGQ_EXTRAS = 2, /* firmware event queue and */ 475 /* forwarded interrupts */ 476 MAX_INGQ = MAX_ETH_QSETS + INGQ_EXTRAS, 477 }; 478 479 struct adapter; 480 struct sge_rspq; 481 482 #include "cxgb4_dcb.h" 483 484 #ifdef CONFIG_CHELSIO_T4_FCOE 485 #include "cxgb4_fcoe.h" 486 #endif /* CONFIG_CHELSIO_T4_FCOE */ 487 488 struct port_info { 489 struct adapter *adapter; 490 u16 viid; 491 s16 xact_addr_filt; /* index of exact MAC address filter */ 492 u16 rss_size; /* size of VI's RSS table slice */ 493 s8 mdio_addr; 494 enum fw_port_type port_type; 495 u8 mod_type; 496 u8 port_id; 497 u8 tx_chan; 498 u8 lport; /* associated offload logical port */ 499 u8 nqsets; /* # of qsets */ 500 u8 first_qset; /* index of first qset */ 501 u8 rss_mode; 502 struct link_config link_cfg; 503 u16 *rss; 504 struct port_stats stats_base; 505 #ifdef CONFIG_CHELSIO_T4_DCB 506 struct port_dcb_info dcb; /* Data Center Bridging support */ 507 #endif 508 #ifdef CONFIG_CHELSIO_T4_FCOE 509 struct cxgb_fcoe fcoe; 510 #endif /* CONFIG_CHELSIO_T4_FCOE */ 511 bool rxtstamp; /* Enable TS */ 512 struct hwtstamp_config tstamp_config; 513 struct sched_table *sched_tbl; 514 }; 515 516 struct dentry; 517 struct work_struct; 518 519 enum { /* adapter flags */ 520 FULL_INIT_DONE = (1 << 0), 521 DEV_ENABLED = (1 << 1), 522 USING_MSI = (1 << 2), 523 USING_MSIX = (1 << 3), 524 FW_OK = (1 << 4), 525 RSS_TNLALLLOOKUP = (1 << 5), 526 USING_SOFT_PARAMS = (1 << 6), 527 MASTER_PF = (1 << 7), 528 FW_OFLD_CONN = (1 << 9), 529 }; 530 531 enum { 532 ULP_CRYPTO_LOOKASIDE = 1 << 0, 533 }; 534 535 struct rx_sw_desc; 536 537 struct sge_fl { /* SGE free-buffer queue state */ 538 unsigned int avail; /* # of available Rx buffers */ 539 unsigned int pend_cred; /* new buffers since last FL DB ring */ 540 unsigned int cidx; /* consumer index */ 541 unsigned int pidx; /* producer index */ 542 unsigned long alloc_failed; /* # of times buffer allocation failed */ 543 unsigned long large_alloc_failed; 544 unsigned long mapping_err; /* # of RX Buffer DMA Mapping failures */ 545 unsigned long low; /* # of times momentarily starving */ 546 unsigned long starving; 547 /* RO fields */ 548 unsigned int cntxt_id; /* SGE context id for the free list */ 549 unsigned int size; /* capacity of free list */ 550 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */ 551 __be64 *desc; /* address of HW Rx descriptor ring */ 552 dma_addr_t addr; /* bus address of HW ring start */ 553 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 554 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 555 }; 556 557 /* A packet gather list */ 558 struct pkt_gl { 559 u64 sgetstamp; /* SGE Time Stamp for Ingress Packet */ 560 struct page_frag frags[MAX_SKB_FRAGS]; 561 void *va; /* virtual address of first byte */ 562 unsigned int nfrags; /* # of fragments */ 563 unsigned int tot_len; /* total length of fragments */ 564 }; 565 566 typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp, 567 const struct pkt_gl *gl); 568 typedef void (*rspq_flush_handler_t)(struct sge_rspq *q); 569 /* LRO related declarations for ULD */ 570 struct t4_lro_mgr { 571 #define MAX_LRO_SESSIONS 64 572 u8 lro_session_cnt; /* # of sessions to aggregate */ 573 unsigned long lro_pkts; /* # of LRO super packets */ 574 unsigned long lro_merged; /* # of wire packets merged by LRO */ 575 struct sk_buff_head lroq; /* list of aggregated sessions */ 576 }; 577 578 struct sge_rspq { /* state for an SGE response queue */ 579 struct napi_struct napi; 580 const __be64 *cur_desc; /* current descriptor in queue */ 581 unsigned int cidx; /* consumer index */ 582 u8 gen; /* current generation bit */ 583 u8 intr_params; /* interrupt holdoff parameters */ 584 u8 next_intr_params; /* holdoff params for next interrupt */ 585 u8 adaptive_rx; 586 u8 pktcnt_idx; /* interrupt packet threshold */ 587 u8 uld; /* ULD handling this queue */ 588 u8 idx; /* queue index within its group */ 589 int offset; /* offset into current Rx buffer */ 590 u16 cntxt_id; /* SGE context id for the response q */ 591 u16 abs_id; /* absolute SGE id for the response q */ 592 __be64 *desc; /* address of HW response ring */ 593 dma_addr_t phys_addr; /* physical address of the ring */ 594 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 595 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 596 unsigned int iqe_len; /* entry size */ 597 unsigned int size; /* capacity of response queue */ 598 struct adapter *adap; 599 struct net_device *netdev; /* associated net device */ 600 rspq_handler_t handler; 601 rspq_flush_handler_t flush_handler; 602 struct t4_lro_mgr lro_mgr; 603 }; 604 605 struct sge_eth_stats { /* Ethernet queue statistics */ 606 unsigned long pkts; /* # of ethernet packets */ 607 unsigned long lro_pkts; /* # of LRO super packets */ 608 unsigned long lro_merged; /* # of wire packets merged by LRO */ 609 unsigned long rx_cso; /* # of Rx checksum offloads */ 610 unsigned long vlan_ex; /* # of Rx VLAN extractions */ 611 unsigned long rx_drops; /* # of packets dropped due to no mem */ 612 }; 613 614 struct sge_eth_rxq { /* SW Ethernet Rx queue */ 615 struct sge_rspq rspq; 616 struct sge_fl fl; 617 struct sge_eth_stats stats; 618 } ____cacheline_aligned_in_smp; 619 620 struct sge_ofld_stats { /* offload queue statistics */ 621 unsigned long pkts; /* # of packets */ 622 unsigned long imm; /* # of immediate-data packets */ 623 unsigned long an; /* # of asynchronous notifications */ 624 unsigned long nomem; /* # of responses deferred due to no mem */ 625 }; 626 627 struct sge_ofld_rxq { /* SW offload Rx queue */ 628 struct sge_rspq rspq; 629 struct sge_fl fl; 630 struct sge_ofld_stats stats; 631 } ____cacheline_aligned_in_smp; 632 633 struct tx_desc { 634 __be64 flit[8]; 635 }; 636 637 struct tx_sw_desc; 638 639 struct sge_txq { 640 unsigned int in_use; /* # of in-use Tx descriptors */ 641 unsigned int q_type; /* Q type Eth/Ctrl/Ofld */ 642 unsigned int size; /* # of descriptors */ 643 unsigned int cidx; /* SW consumer index */ 644 unsigned int pidx; /* producer index */ 645 unsigned long stops; /* # of times q has been stopped */ 646 unsigned long restarts; /* # of queue restarts */ 647 unsigned int cntxt_id; /* SGE context id for the Tx q */ 648 struct tx_desc *desc; /* address of HW Tx descriptor ring */ 649 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */ 650 struct sge_qstat *stat; /* queue status entry */ 651 dma_addr_t phys_addr; /* physical address of the ring */ 652 spinlock_t db_lock; 653 int db_disabled; 654 unsigned short db_pidx; 655 unsigned short db_pidx_inc; 656 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 657 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 658 }; 659 660 struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */ 661 struct sge_txq q; 662 struct netdev_queue *txq; /* associated netdev TX queue */ 663 #ifdef CONFIG_CHELSIO_T4_DCB 664 u8 dcb_prio; /* DCB Priority bound to queue */ 665 #endif 666 unsigned long tso; /* # of TSO requests */ 667 unsigned long tx_cso; /* # of Tx checksum offloads */ 668 unsigned long vlan_ins; /* # of Tx VLAN insertions */ 669 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 670 } ____cacheline_aligned_in_smp; 671 672 struct sge_uld_txq { /* state for an SGE offload Tx queue */ 673 struct sge_txq q; 674 struct adapter *adap; 675 struct sk_buff_head sendq; /* list of backpressured packets */ 676 struct tasklet_struct qresume_tsk; /* restarts the queue */ 677 bool service_ofldq_running; /* service_ofldq() is processing sendq */ 678 u8 full; /* the Tx ring is full */ 679 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 680 } ____cacheline_aligned_in_smp; 681 682 struct sge_ctrl_txq { /* state for an SGE control Tx queue */ 683 struct sge_txq q; 684 struct adapter *adap; 685 struct sk_buff_head sendq; /* list of backpressured packets */ 686 struct tasklet_struct qresume_tsk; /* restarts the queue */ 687 u8 full; /* the Tx ring is full */ 688 } ____cacheline_aligned_in_smp; 689 690 struct sge_uld_rxq_info { 691 char name[IFNAMSIZ]; /* name of ULD driver */ 692 struct sge_ofld_rxq *uldrxq; /* Rxq's for ULD */ 693 u16 *msix_tbl; /* msix_tbl for uld */ 694 u16 *rspq_id; /* response queue id's of rxq */ 695 u16 nrxq; /* # of ingress uld queues */ 696 u16 nciq; /* # of completion queues */ 697 u8 uld; /* uld type */ 698 }; 699 700 struct sge_uld_txq_info { 701 struct sge_uld_txq *uldtxq; /* Txq's for ULD */ 702 atomic_t users; /* num users */ 703 u16 ntxq; /* # of egress uld queues */ 704 }; 705 706 struct sge { 707 struct sge_eth_txq ethtxq[MAX_ETH_QSETS]; 708 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES]; 709 710 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS]; 711 struct sge_rspq fw_evtq ____cacheline_aligned_in_smp; 712 struct sge_uld_rxq_info **uld_rxq_info; 713 struct sge_uld_txq_info **uld_txq_info; 714 715 struct sge_rspq intrq ____cacheline_aligned_in_smp; 716 spinlock_t intrq_lock; 717 718 u16 max_ethqsets; /* # of available Ethernet queue sets */ 719 u16 ethqsets; /* # of active Ethernet queue sets */ 720 u16 ethtxq_rover; /* Tx queue to clean up next */ 721 u16 ofldqsets; /* # of active ofld queue sets */ 722 u16 nqs_per_uld; /* # of Rx queues per ULD */ 723 u16 timer_val[SGE_NTIMERS]; 724 u8 counter_val[SGE_NCOUNTERS]; 725 u32 fl_pg_order; /* large page allocation size */ 726 u32 stat_len; /* length of status page at ring end */ 727 u32 pktshift; /* padding between CPL & packet data */ 728 u32 fl_align; /* response queue message alignment */ 729 u32 fl_starve_thres; /* Free List starvation threshold */ 730 731 struct sge_idma_monitor_state idma_monitor; 732 unsigned int egr_start; 733 unsigned int egr_sz; 734 unsigned int ingr_start; 735 unsigned int ingr_sz; 736 void **egr_map; /* qid->queue egress queue map */ 737 struct sge_rspq **ingr_map; /* qid->queue ingress queue map */ 738 unsigned long *starving_fl; 739 unsigned long *txq_maperr; 740 unsigned long *blocked_fl; 741 struct timer_list rx_timer; /* refills starving FLs */ 742 struct timer_list tx_timer; /* checks Tx queues */ 743 }; 744 745 #define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++) 746 #define for_each_ofldtxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++) 747 748 struct l2t_data; 749 750 #ifdef CONFIG_PCI_IOV 751 752 /* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial 753 * Configuration initialization for T5 only has SR-IOV functionality enabled 754 * on PF0-3 in order to simplify everything. 755 */ 756 #define NUM_OF_PF_WITH_SRIOV 4 757 758 #endif 759 760 struct doorbell_stats { 761 u32 db_drop; 762 u32 db_empty; 763 u32 db_full; 764 }; 765 766 struct hash_mac_addr { 767 struct list_head list; 768 u8 addr[ETH_ALEN]; 769 }; 770 771 struct uld_msix_bmap { 772 unsigned long *msix_bmap; 773 unsigned int mapsize; 774 spinlock_t lock; /* lock for acquiring bitmap */ 775 }; 776 777 struct uld_msix_info { 778 unsigned short vec; 779 char desc[IFNAMSIZ + 10]; 780 unsigned int idx; 781 }; 782 783 struct vf_info { 784 unsigned char vf_mac_addr[ETH_ALEN]; 785 unsigned int tx_rate; 786 bool pf_set_mac; 787 }; 788 789 struct mbox_list { 790 struct list_head list; 791 }; 792 793 struct adapter { 794 void __iomem *regs; 795 void __iomem *bar2; 796 u32 t4_bar0; 797 struct pci_dev *pdev; 798 struct device *pdev_dev; 799 const char *name; 800 unsigned int mbox; 801 unsigned int pf; 802 unsigned int flags; 803 unsigned int adap_idx; 804 enum chip_type chip; 805 806 int msg_enable; 807 808 struct adapter_params params; 809 struct cxgb4_virt_res vres; 810 unsigned int swintr; 811 812 struct { 813 unsigned short vec; 814 char desc[IFNAMSIZ + 10]; 815 } msix_info[MAX_INGQ + 1]; 816 struct uld_msix_info *msix_info_ulds; /* msix info for uld's */ 817 struct uld_msix_bmap msix_bmap_ulds; /* msix bitmap for all uld */ 818 int msi_idx; 819 820 struct doorbell_stats db_stats; 821 struct sge sge; 822 823 struct net_device *port[MAX_NPORTS]; 824 u8 chan_map[NCHAN]; /* channel -> port map */ 825 826 struct vf_info *vfinfo; 827 u8 num_vfs; 828 829 u32 filter_mode; 830 unsigned int l2t_start; 831 unsigned int l2t_end; 832 struct l2t_data *l2t; 833 unsigned int clipt_start; 834 unsigned int clipt_end; 835 struct clip_tbl *clipt; 836 struct cxgb4_uld_info *uld; 837 void *uld_handle[CXGB4_ULD_MAX]; 838 unsigned int num_uld; 839 unsigned int num_ofld_uld; 840 struct list_head list_node; 841 struct list_head rcu_node; 842 struct list_head mac_hlist; /* list of MAC addresses in MPS Hash */ 843 844 void *iscsi_ppm; 845 846 struct tid_info tids; 847 void **tid_release_head; 848 spinlock_t tid_release_lock; 849 struct workqueue_struct *workq; 850 struct work_struct tid_release_task; 851 struct work_struct db_full_task; 852 struct work_struct db_drop_task; 853 bool tid_release_task_busy; 854 855 /* lock for mailbox cmd list */ 856 spinlock_t mbox_lock; 857 struct mbox_list mlist; 858 859 /* support for mailbox command/reply logging */ 860 #define T4_OS_LOG_MBOX_CMDS 256 861 struct mbox_cmd_log *mbox_log; 862 863 struct mutex uld_mutex; 864 865 struct dentry *debugfs_root; 866 bool use_bd; /* Use SGE Back Door intfc for reading SGE Contexts */ 867 bool trace_rss; /* 1 implies that different RSS flit per filter is 868 * used per filter else if 0 default RSS flit is 869 * used for all 4 filters. 870 */ 871 872 spinlock_t stats_lock; 873 spinlock_t win0_lock ____cacheline_aligned_in_smp; 874 875 /* TC u32 offload */ 876 struct cxgb4_tc_u32_table *tc_u32; 877 }; 878 879 /* Support for "sched-class" command to allow a TX Scheduling Class to be 880 * programmed with various parameters. 881 */ 882 struct ch_sched_params { 883 s8 type; /* packet or flow */ 884 union { 885 struct { 886 s8 level; /* scheduler hierarchy level */ 887 s8 mode; /* per-class or per-flow */ 888 s8 rateunit; /* bit or packet rate */ 889 s8 ratemode; /* %port relative or kbps absolute */ 890 s8 channel; /* scheduler channel [0..N] */ 891 s8 class; /* scheduler class [0..N] */ 892 s32 minrate; /* minimum rate */ 893 s32 maxrate; /* maximum rate */ 894 s16 weight; /* percent weight */ 895 s16 pktsize; /* average packet size */ 896 } params; 897 } u; 898 }; 899 900 enum { 901 SCHED_CLASS_TYPE_PACKET = 0, /* class type */ 902 }; 903 904 enum { 905 SCHED_CLASS_LEVEL_CL_RL = 0, /* class rate limiter */ 906 }; 907 908 enum { 909 SCHED_CLASS_MODE_CLASS = 0, /* per-class scheduling */ 910 }; 911 912 enum { 913 SCHED_CLASS_RATEUNIT_BITS = 0, /* bit rate scheduling */ 914 }; 915 916 enum { 917 SCHED_CLASS_RATEMODE_ABS = 1, /* Kb/s */ 918 }; 919 920 /* Support for "sched_queue" command to allow one or more NIC TX Queues 921 * to be bound to a TX Scheduling Class. 922 */ 923 struct ch_sched_queue { 924 s8 queue; /* queue index */ 925 s8 class; /* class index */ 926 }; 927 928 /* Defined bit width of user definable filter tuples 929 */ 930 #define ETHTYPE_BITWIDTH 16 931 #define FRAG_BITWIDTH 1 932 #define MACIDX_BITWIDTH 9 933 #define FCOE_BITWIDTH 1 934 #define IPORT_BITWIDTH 3 935 #define MATCHTYPE_BITWIDTH 3 936 #define PROTO_BITWIDTH 8 937 #define TOS_BITWIDTH 8 938 #define PF_BITWIDTH 8 939 #define VF_BITWIDTH 8 940 #define IVLAN_BITWIDTH 16 941 #define OVLAN_BITWIDTH 16 942 943 /* Filter matching rules. These consist of a set of ingress packet field 944 * (value, mask) tuples. The associated ingress packet field matches the 945 * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field 946 * rule can be constructed by specifying a tuple of (0, 0).) A filter rule 947 * matches an ingress packet when all of the individual individual field 948 * matching rules are true. 949 * 950 * Partial field masks are always valid, however, while it may be easy to 951 * understand their meanings for some fields (e.g. IP address to match a 952 * subnet), for others making sensible partial masks is less intuitive (e.g. 953 * MPS match type) ... 954 * 955 * Most of the following data structures are modeled on T4 capabilities. 956 * Drivers for earlier chips use the subsets which make sense for those chips. 957 * We really need to come up with a hardware-independent mechanism to 958 * represent hardware filter capabilities ... 959 */ 960 struct ch_filter_tuple { 961 /* Compressed header matching field rules. The TP_VLAN_PRI_MAP 962 * register selects which of these fields will participate in the 963 * filter match rules -- up to a maximum of 36 bits. Because 964 * TP_VLAN_PRI_MAP is a global register, all filters must use the same 965 * set of fields. 966 */ 967 uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */ 968 uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */ 969 uint32_t ivlan_vld:1; /* inner VLAN valid */ 970 uint32_t ovlan_vld:1; /* outer VLAN valid */ 971 uint32_t pfvf_vld:1; /* PF/VF valid */ 972 uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */ 973 uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */ 974 uint32_t iport:IPORT_BITWIDTH; /* ingress port */ 975 uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */ 976 uint32_t proto:PROTO_BITWIDTH; /* protocol type */ 977 uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */ 978 uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */ 979 uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */ 980 uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */ 981 uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */ 982 983 /* Uncompressed header matching field rules. These are always 984 * available for field rules. 985 */ 986 uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */ 987 uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */ 988 uint16_t lport; /* local port */ 989 uint16_t fport; /* foreign port */ 990 }; 991 992 /* A filter ioctl command. 993 */ 994 struct ch_filter_specification { 995 /* Administrative fields for filter. 996 */ 997 uint32_t hitcnts:1; /* count filter hits in TCB */ 998 uint32_t prio:1; /* filter has priority over active/server */ 999 1000 /* Fundamental filter typing. This is the one element of filter 1001 * matching that doesn't exist as a (value, mask) tuple. 1002 */ 1003 uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */ 1004 1005 /* Packet dispatch information. Ingress packets which match the 1006 * filter rules will be dropped, passed to the host or switched back 1007 * out as egress packets. 1008 */ 1009 uint32_t action:2; /* drop, pass, switch */ 1010 1011 uint32_t rpttid:1; /* report TID in RSS hash field */ 1012 1013 uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */ 1014 uint32_t iq:10; /* ingress queue */ 1015 1016 uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */ 1017 uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */ 1018 /* 1 => TCB contains IQ ID */ 1019 1020 /* Switch proxy/rewrite fields. An ingress packet which matches a 1021 * filter with "switch" set will be looped back out as an egress 1022 * packet -- potentially with some Ethernet header rewriting. 1023 */ 1024 uint32_t eport:2; /* egress port to switch packet out */ 1025 uint32_t newdmac:1; /* rewrite destination MAC address */ 1026 uint32_t newsmac:1; /* rewrite source MAC address */ 1027 uint32_t newvlan:2; /* rewrite VLAN Tag */ 1028 uint8_t dmac[ETH_ALEN]; /* new destination MAC address */ 1029 uint8_t smac[ETH_ALEN]; /* new source MAC address */ 1030 uint16_t vlan; /* VLAN Tag to insert */ 1031 1032 /* Filter rule value/mask pairs. 1033 */ 1034 struct ch_filter_tuple val; 1035 struct ch_filter_tuple mask; 1036 }; 1037 1038 enum { 1039 FILTER_PASS = 0, /* default */ 1040 FILTER_DROP, 1041 FILTER_SWITCH 1042 }; 1043 1044 enum { 1045 VLAN_NOCHANGE = 0, /* default */ 1046 VLAN_REMOVE, 1047 VLAN_INSERT, 1048 VLAN_REWRITE 1049 }; 1050 1051 /* Host shadow copy of ingress filter entry. This is in host native format 1052 * and doesn't match the ordering or bit order, etc. of the hardware of the 1053 * firmware command. The use of bit-field structure elements is purely to 1054 * remind ourselves of the field size limitations and save memory in the case 1055 * where the filter table is large. 1056 */ 1057 struct filter_entry { 1058 /* Administrative fields for filter. */ 1059 u32 valid:1; /* filter allocated and valid */ 1060 u32 locked:1; /* filter is administratively locked */ 1061 1062 u32 pending:1; /* filter action is pending firmware reply */ 1063 u32 smtidx:8; /* Source MAC Table index for smac */ 1064 struct filter_ctx *ctx; /* Caller's completion hook */ 1065 struct l2t_entry *l2t; /* Layer Two Table entry for dmac */ 1066 struct net_device *dev; /* Associated net device */ 1067 u32 tid; /* This will store the actual tid */ 1068 1069 /* The filter itself. Most of this is a straight copy of information 1070 * provided by the extended ioctl(). Some fields are translated to 1071 * internal forms -- for instance the Ingress Queue ID passed in from 1072 * the ioctl() is translated into the Absolute Ingress Queue ID. 1073 */ 1074 struct ch_filter_specification fs; 1075 }; 1076 1077 static inline int is_offload(const struct adapter *adap) 1078 { 1079 return adap->params.offload; 1080 } 1081 1082 static inline int is_pci_uld(const struct adapter *adap) 1083 { 1084 return adap->params.crypto; 1085 } 1086 1087 static inline int is_uld(const struct adapter *adap) 1088 { 1089 return (adap->params.offload || adap->params.crypto); 1090 } 1091 1092 static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr) 1093 { 1094 return readl(adap->regs + reg_addr); 1095 } 1096 1097 static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val) 1098 { 1099 writel(val, adap->regs + reg_addr); 1100 } 1101 1102 #ifndef readq 1103 static inline u64 readq(const volatile void __iomem *addr) 1104 { 1105 return readl(addr) + ((u64)readl(addr + 4) << 32); 1106 } 1107 1108 static inline void writeq(u64 val, volatile void __iomem *addr) 1109 { 1110 writel(val, addr); 1111 writel(val >> 32, addr + 4); 1112 } 1113 #endif 1114 1115 static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr) 1116 { 1117 return readq(adap->regs + reg_addr); 1118 } 1119 1120 static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val) 1121 { 1122 writeq(val, adap->regs + reg_addr); 1123 } 1124 1125 /** 1126 * t4_set_hw_addr - store a port's MAC address in SW 1127 * @adapter: the adapter 1128 * @port_idx: the port index 1129 * @hw_addr: the Ethernet address 1130 * 1131 * Store the Ethernet address of the given port in SW. Called by the common 1132 * code when it retrieves a port's Ethernet address from EEPROM. 1133 */ 1134 static inline void t4_set_hw_addr(struct adapter *adapter, int port_idx, 1135 u8 hw_addr[]) 1136 { 1137 ether_addr_copy(adapter->port[port_idx]->dev_addr, hw_addr); 1138 ether_addr_copy(adapter->port[port_idx]->perm_addr, hw_addr); 1139 } 1140 1141 /** 1142 * netdev2pinfo - return the port_info structure associated with a net_device 1143 * @dev: the netdev 1144 * 1145 * Return the struct port_info associated with a net_device 1146 */ 1147 static inline struct port_info *netdev2pinfo(const struct net_device *dev) 1148 { 1149 return netdev_priv(dev); 1150 } 1151 1152 /** 1153 * adap2pinfo - return the port_info of a port 1154 * @adap: the adapter 1155 * @idx: the port index 1156 * 1157 * Return the port_info structure for the port of the given index. 1158 */ 1159 static inline struct port_info *adap2pinfo(struct adapter *adap, int idx) 1160 { 1161 return netdev_priv(adap->port[idx]); 1162 } 1163 1164 /** 1165 * netdev2adap - return the adapter structure associated with a net_device 1166 * @dev: the netdev 1167 * 1168 * Return the struct adapter associated with a net_device 1169 */ 1170 static inline struct adapter *netdev2adap(const struct net_device *dev) 1171 { 1172 return netdev2pinfo(dev)->adapter; 1173 } 1174 1175 /* Return a version number to identify the type of adapter. The scheme is: 1176 * - bits 0..9: chip version 1177 * - bits 10..15: chip revision 1178 * - bits 16..23: register dump version 1179 */ 1180 static inline unsigned int mk_adap_vers(struct adapter *ap) 1181 { 1182 return CHELSIO_CHIP_VERSION(ap->params.chip) | 1183 (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16); 1184 } 1185 1186 /* Return a queue's interrupt hold-off time in us. 0 means no timer. */ 1187 static inline unsigned int qtimer_val(const struct adapter *adap, 1188 const struct sge_rspq *q) 1189 { 1190 unsigned int idx = q->intr_params >> 1; 1191 1192 return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0; 1193 } 1194 1195 /* driver version & name used for ethtool_drvinfo */ 1196 extern char cxgb4_driver_name[]; 1197 extern const char cxgb4_driver_version[]; 1198 1199 void t4_os_portmod_changed(const struct adapter *adap, int port_id); 1200 void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat); 1201 1202 void t4_free_sge_resources(struct adapter *adap); 1203 void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q); 1204 irq_handler_t t4_intr_handler(struct adapter *adap); 1205 netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev); 1206 int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp, 1207 const struct pkt_gl *gl); 1208 int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb); 1209 int t4_ofld_send(struct adapter *adap, struct sk_buff *skb); 1210 int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, 1211 struct net_device *dev, int intr_idx, 1212 struct sge_fl *fl, rspq_handler_t hnd, 1213 rspq_flush_handler_t flush_handler, int cong); 1214 int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq, 1215 struct net_device *dev, struct netdev_queue *netdevq, 1216 unsigned int iqid); 1217 int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq, 1218 struct net_device *dev, unsigned int iqid, 1219 unsigned int cmplqid); 1220 int t4_sge_mod_ctrl_txq(struct adapter *adap, unsigned int eqid, 1221 unsigned int cmplqid); 1222 int t4_sge_alloc_uld_txq(struct adapter *adap, struct sge_uld_txq *txq, 1223 struct net_device *dev, unsigned int iqid, 1224 unsigned int uld_type); 1225 irqreturn_t t4_sge_intr_msix(int irq, void *cookie); 1226 int t4_sge_init(struct adapter *adap); 1227 void t4_sge_start(struct adapter *adap); 1228 void t4_sge_stop(struct adapter *adap); 1229 void cxgb4_set_ethtool_ops(struct net_device *netdev); 1230 int cxgb4_write_rss(const struct port_info *pi, const u16 *queues); 1231 extern int dbfifo_int_thresh; 1232 1233 #define for_each_port(adapter, iter) \ 1234 for (iter = 0; iter < (adapter)->params.nports; ++iter) 1235 1236 static inline int is_bypass(struct adapter *adap) 1237 { 1238 return adap->params.bypass; 1239 } 1240 1241 static inline int is_bypass_device(int device) 1242 { 1243 /* this should be set based upon device capabilities */ 1244 switch (device) { 1245 case 0x440b: 1246 case 0x440c: 1247 return 1; 1248 default: 1249 return 0; 1250 } 1251 } 1252 1253 static inline int is_10gbt_device(int device) 1254 { 1255 /* this should be set based upon device capabilities */ 1256 switch (device) { 1257 case 0x4409: 1258 case 0x4486: 1259 return 1; 1260 1261 default: 1262 return 0; 1263 } 1264 } 1265 1266 static inline unsigned int core_ticks_per_usec(const struct adapter *adap) 1267 { 1268 return adap->params.vpd.cclk / 1000; 1269 } 1270 1271 static inline unsigned int us_to_core_ticks(const struct adapter *adap, 1272 unsigned int us) 1273 { 1274 return (us * adap->params.vpd.cclk) / 1000; 1275 } 1276 1277 static inline unsigned int core_ticks_to_us(const struct adapter *adapter, 1278 unsigned int ticks) 1279 { 1280 /* add Core Clock / 2 to round ticks to nearest uS */ 1281 return ((ticks * 1000 + adapter->params.vpd.cclk/2) / 1282 adapter->params.vpd.cclk); 1283 } 1284 1285 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, 1286 u32 val); 1287 1288 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 1289 int size, void *rpl, bool sleep_ok, int timeout); 1290 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 1291 void *rpl, bool sleep_ok); 1292 1293 static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox, 1294 const void *cmd, int size, void *rpl, 1295 int timeout) 1296 { 1297 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true, 1298 timeout); 1299 } 1300 1301 static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, 1302 int size, void *rpl) 1303 { 1304 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true); 1305 } 1306 1307 static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, 1308 int size, void *rpl) 1309 { 1310 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false); 1311 } 1312 1313 /** 1314 * hash_mac_addr - return the hash value of a MAC address 1315 * @addr: the 48-bit Ethernet MAC address 1316 * 1317 * Hashes a MAC address according to the hash function used by HW inexact 1318 * (hash) address matching. 1319 */ 1320 static inline int hash_mac_addr(const u8 *addr) 1321 { 1322 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2]; 1323 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5]; 1324 1325 a ^= b; 1326 a ^= (a >> 12); 1327 a ^= (a >> 6); 1328 return a & 0x3f; 1329 } 1330 1331 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us, 1332 unsigned int cnt); 1333 static inline void init_rspq(struct adapter *adap, struct sge_rspq *q, 1334 unsigned int us, unsigned int cnt, 1335 unsigned int size, unsigned int iqe_size) 1336 { 1337 q->adap = adap; 1338 cxgb4_set_rspq_intr_params(q, us, cnt); 1339 q->iqe_len = iqe_size; 1340 q->size = size; 1341 } 1342 1343 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 1344 unsigned int data_reg, const u32 *vals, 1345 unsigned int nregs, unsigned int start_idx); 1346 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 1347 unsigned int data_reg, u32 *vals, unsigned int nregs, 1348 unsigned int start_idx); 1349 void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val); 1350 1351 struct fw_filter_wr; 1352 1353 void t4_intr_enable(struct adapter *adapter); 1354 void t4_intr_disable(struct adapter *adapter); 1355 int t4_slow_intr_handler(struct adapter *adapter); 1356 1357 int t4_wait_dev_ready(void __iomem *regs); 1358 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port, 1359 struct link_config *lc); 1360 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port); 1361 1362 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg); 1363 u32 t4_get_util_window(struct adapter *adap); 1364 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window); 1365 1366 #define T4_MEMORY_WRITE 0 1367 #define T4_MEMORY_READ 1 1368 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len, 1369 void *buf, int dir); 1370 static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr, 1371 u32 len, __be32 *buf) 1372 { 1373 return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0); 1374 } 1375 1376 unsigned int t4_get_regs_len(struct adapter *adapter); 1377 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size); 1378 1379 int t4_seeprom_wp(struct adapter *adapter, bool enable); 1380 int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p); 1381 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p); 1382 int t4_read_flash(struct adapter *adapter, unsigned int addr, 1383 unsigned int nwords, u32 *data, int byte_oriented); 1384 int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size); 1385 int t4_load_phy_fw(struct adapter *adap, 1386 int win, spinlock_t *lock, 1387 int (*phy_fw_version)(const u8 *, size_t), 1388 const u8 *phy_fw_data, size_t phy_fw_size); 1389 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver); 1390 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op); 1391 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 1392 const u8 *fw_data, unsigned int size, int force); 1393 int t4_fl_pkt_align(struct adapter *adap); 1394 unsigned int t4_flash_cfg_addr(struct adapter *adapter); 1395 int t4_check_fw_version(struct adapter *adap); 1396 int t4_get_fw_version(struct adapter *adapter, u32 *vers); 1397 int t4_get_bs_version(struct adapter *adapter, u32 *vers); 1398 int t4_get_tp_version(struct adapter *adapter, u32 *vers); 1399 int t4_get_exprom_version(struct adapter *adapter, u32 *vers); 1400 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info, 1401 const u8 *fw_data, unsigned int fw_size, 1402 struct fw_hdr *card_fw, enum dev_state state, int *reset); 1403 int t4_prep_adapter(struct adapter *adapter); 1404 int t4_shutdown_adapter(struct adapter *adapter); 1405 1406 enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS }; 1407 int t4_bar2_sge_qregs(struct adapter *adapter, 1408 unsigned int qid, 1409 enum t4_bar2_qtype qtype, 1410 int user, 1411 u64 *pbar2_qoffset, 1412 unsigned int *pbar2_qid); 1413 1414 unsigned int qtimer_val(const struct adapter *adap, 1415 const struct sge_rspq *q); 1416 1417 int t4_init_devlog_params(struct adapter *adapter); 1418 int t4_init_sge_params(struct adapter *adapter); 1419 int t4_init_tp_params(struct adapter *adap); 1420 int t4_filter_field_shift(const struct adapter *adap, int filter_sel); 1421 int t4_init_rss_mode(struct adapter *adap, int mbox); 1422 int t4_init_portinfo(struct port_info *pi, int mbox, 1423 int port, int pf, int vf, u8 mac[]); 1424 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf); 1425 void t4_fatal_err(struct adapter *adapter); 1426 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 1427 int start, int n, const u16 *rspq, unsigned int nrspq); 1428 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 1429 unsigned int flags); 1430 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 1431 unsigned int flags, unsigned int defq); 1432 int t4_read_rss(struct adapter *adapter, u16 *entries); 1433 void t4_read_rss_key(struct adapter *adapter, u32 *key); 1434 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx); 1435 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, 1436 u32 *valp); 1437 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 1438 u32 *vfl, u32 *vfh); 1439 u32 t4_read_rss_pf_map(struct adapter *adapter); 1440 u32 t4_read_rss_pf_mask(struct adapter *adapter); 1441 1442 unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx); 1443 unsigned int t4_get_tp_ch_map(struct adapter *adapter, int pidx); 1444 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1445 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1446 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, 1447 size_t n); 1448 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, 1449 size_t n); 1450 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 1451 unsigned int *valp); 1452 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 1453 const unsigned int *valp); 1454 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr); 1455 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, 1456 unsigned int *pif_req_wrptr, 1457 unsigned int *pif_rsp_wrptr); 1458 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp); 1459 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres); 1460 const char *t4_get_port_type_description(enum fw_port_type port_type); 1461 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); 1462 void t4_get_port_stats_offset(struct adapter *adap, int idx, 1463 struct port_stats *stats, 1464 struct port_stats *offset); 1465 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p); 1466 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); 1467 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]); 1468 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 1469 unsigned int mask, unsigned int val); 1470 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr); 1471 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st); 1472 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st); 1473 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st); 1474 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st); 1475 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 1476 struct tp_tcp_stats *v6); 1477 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 1478 struct tp_fcoe_stats *st); 1479 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 1480 const unsigned short *alpha, const unsigned short *beta); 1481 1482 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf); 1483 1484 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate); 1485 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid); 1486 1487 void t4_wol_magic_enable(struct adapter *adap, unsigned int port, 1488 const u8 *addr); 1489 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 1490 u64 mask0, u64 mask1, unsigned int crc, bool enable); 1491 1492 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 1493 enum dev_master master, enum dev_state *state); 1494 int t4_fw_bye(struct adapter *adap, unsigned int mbox); 1495 int t4_early_init(struct adapter *adap, unsigned int mbox); 1496 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); 1497 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, 1498 unsigned int cache_line_size); 1499 int t4_fw_initialize(struct adapter *adap, unsigned int mbox); 1500 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1501 unsigned int vf, unsigned int nparams, const u32 *params, 1502 u32 *val); 1503 int t4_query_params_ns(struct adapter *adap, unsigned int mbox, unsigned int pf, 1504 unsigned int vf, unsigned int nparams, const u32 *params, 1505 u32 *val); 1506 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, 1507 unsigned int vf, unsigned int nparams, const u32 *params, 1508 u32 *val, int rw, bool sleep_ok); 1509 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 1510 unsigned int pf, unsigned int vf, 1511 unsigned int nparams, const u32 *params, 1512 const u32 *val, int timeout); 1513 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1514 unsigned int vf, unsigned int nparams, const u32 *params, 1515 const u32 *val); 1516 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 1517 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 1518 unsigned int rxqi, unsigned int rxq, unsigned int tc, 1519 unsigned int vi, unsigned int cmask, unsigned int pmask, 1520 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps); 1521 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 1522 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 1523 unsigned int *rss_size); 1524 int t4_free_vi(struct adapter *adap, unsigned int mbox, 1525 unsigned int pf, unsigned int vf, 1526 unsigned int viid); 1527 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 1528 int mtu, int promisc, int all_multi, int bcast, int vlanex, 1529 bool sleep_ok); 1530 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, 1531 unsigned int viid, bool free, unsigned int naddr, 1532 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok); 1533 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox, 1534 unsigned int viid, unsigned int naddr, 1535 const u8 **addr, bool sleep_ok); 1536 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 1537 int idx, const u8 *addr, bool persist, bool add_smt); 1538 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 1539 bool ucast, u64 vec, bool sleep_ok); 1540 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 1541 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en); 1542 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 1543 bool rx_en, bool tx_en); 1544 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 1545 unsigned int nblinks); 1546 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1547 unsigned int mmd, unsigned int reg, u16 *valp); 1548 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1549 unsigned int mmd, unsigned int reg, u16 val); 1550 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, 1551 unsigned int vf, unsigned int iqtype, unsigned int iqid, 1552 unsigned int fl0id, unsigned int fl1id); 1553 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1554 unsigned int vf, unsigned int iqtype, unsigned int iqid, 1555 unsigned int fl0id, unsigned int fl1id); 1556 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1557 unsigned int vf, unsigned int eqid); 1558 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1559 unsigned int vf, unsigned int eqid); 1560 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1561 unsigned int vf, unsigned int eqid); 1562 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox); 1563 void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl); 1564 int t4_update_port_info(struct port_info *pi); 1565 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); 1566 void t4_db_full(struct adapter *adapter); 1567 void t4_db_dropped(struct adapter *adapter); 1568 int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp, 1569 int filter_index, int enable); 1570 void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp, 1571 int filter_index, int *enabled); 1572 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, 1573 u32 addr, u32 val); 1574 int t4_sched_params(struct adapter *adapter, int type, int level, int mode, 1575 int rateunit, int ratemode, int channel, int class, 1576 int minrate, int maxrate, int weight, int pktsize); 1577 void t4_sge_decode_idma_state(struct adapter *adapter, int state); 1578 void t4_idma_monitor_init(struct adapter *adapter, 1579 struct sge_idma_monitor_state *idma); 1580 void t4_idma_monitor(struct adapter *adapter, 1581 struct sge_idma_monitor_state *idma, 1582 int hz, int ticks); 1583 int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf, 1584 unsigned int naddr, u8 *addr); 1585 void t4_uld_mem_free(struct adapter *adap); 1586 int t4_uld_mem_alloc(struct adapter *adap); 1587 void t4_uld_clean_up(struct adapter *adap); 1588 void t4_register_netevent_notifier(void); 1589 void free_rspq_fl(struct adapter *adap, struct sge_rspq *rq, struct sge_fl *fl); 1590 void free_tx_desc(struct adapter *adap, struct sge_txq *q, 1591 unsigned int n, bool unmap); 1592 void free_txq(struct adapter *adap, struct sge_txq *q); 1593 #endif /* __CXGB4_H__ */ 1594