1 /* 2 * Copyright (C) 2017 Chelsio Communications. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * The full GNU General Public License is included in this distribution in 14 * the file called "COPYING". 15 * 16 */ 17 18 #ifndef __CUDBG_ENTITY_H__ 19 #define __CUDBG_ENTITY_H__ 20 21 #define EDC0_FLAG 3 22 #define EDC1_FLAG 4 23 24 struct card_mem { 25 u16 size_edc0; 26 u16 size_edc1; 27 u16 mem_flag; 28 }; 29 30 struct cudbg_mbox_log { 31 struct mbox_cmd entry; 32 u32 hi[MBOX_LEN / 8]; 33 u32 lo[MBOX_LEN / 8]; 34 }; 35 36 struct ireg_field { 37 u32 ireg_addr; 38 u32 ireg_data; 39 u32 ireg_local_offset; 40 u32 ireg_offset_range; 41 }; 42 43 struct ireg_buf { 44 struct ireg_field tp_pio; 45 u32 outbuf[32]; 46 }; 47 48 #define IREG_NUM_ELEM 4 49 50 static const u32 t6_tp_pio_array[][IREG_NUM_ELEM] = { 51 {0x7e40, 0x7e44, 0x020, 28}, /* t6_tp_pio_regs_20_to_3b */ 52 {0x7e40, 0x7e44, 0x040, 10}, /* t6_tp_pio_regs_40_to_49 */ 53 {0x7e40, 0x7e44, 0x050, 10}, /* t6_tp_pio_regs_50_to_59 */ 54 {0x7e40, 0x7e44, 0x060, 14}, /* t6_tp_pio_regs_60_to_6d */ 55 {0x7e40, 0x7e44, 0x06F, 1}, /* t6_tp_pio_regs_6f */ 56 {0x7e40, 0x7e44, 0x070, 6}, /* t6_tp_pio_regs_70_to_75 */ 57 {0x7e40, 0x7e44, 0x130, 18}, /* t6_tp_pio_regs_130_to_141 */ 58 {0x7e40, 0x7e44, 0x145, 19}, /* t6_tp_pio_regs_145_to_157 */ 59 {0x7e40, 0x7e44, 0x160, 1}, /* t6_tp_pio_regs_160 */ 60 {0x7e40, 0x7e44, 0x230, 25}, /* t6_tp_pio_regs_230_to_248 */ 61 {0x7e40, 0x7e44, 0x24a, 3}, /* t6_tp_pio_regs_24c */ 62 {0x7e40, 0x7e44, 0x8C0, 1} /* t6_tp_pio_regs_8c0 */ 63 }; 64 65 static const u32 t5_tp_pio_array[][IREG_NUM_ELEM] = { 66 {0x7e40, 0x7e44, 0x020, 28}, /* t5_tp_pio_regs_20_to_3b */ 67 {0x7e40, 0x7e44, 0x040, 19}, /* t5_tp_pio_regs_40_to_52 */ 68 {0x7e40, 0x7e44, 0x054, 2}, /* t5_tp_pio_regs_54_to_55 */ 69 {0x7e40, 0x7e44, 0x060, 13}, /* t5_tp_pio_regs_60_to_6c */ 70 {0x7e40, 0x7e44, 0x06F, 1}, /* t5_tp_pio_regs_6f */ 71 {0x7e40, 0x7e44, 0x120, 4}, /* t5_tp_pio_regs_120_to_123 */ 72 {0x7e40, 0x7e44, 0x12b, 2}, /* t5_tp_pio_regs_12b_to_12c */ 73 {0x7e40, 0x7e44, 0x12f, 21}, /* t5_tp_pio_regs_12f_to_143 */ 74 {0x7e40, 0x7e44, 0x145, 19}, /* t5_tp_pio_regs_145_to_157 */ 75 {0x7e40, 0x7e44, 0x230, 25}, /* t5_tp_pio_regs_230_to_248 */ 76 {0x7e40, 0x7e44, 0x8C0, 1} /* t5_tp_pio_regs_8c0 */ 77 }; 78 79 static const u32 t6_tp_tm_pio_array[][IREG_NUM_ELEM] = { 80 {0x7e18, 0x7e1c, 0x0, 12} 81 }; 82 83 static const u32 t5_tp_tm_pio_array[][IREG_NUM_ELEM] = { 84 {0x7e18, 0x7e1c, 0x0, 12} 85 }; 86 87 static const u32 t6_tp_mib_index_array[6][IREG_NUM_ELEM] = { 88 {0x7e50, 0x7e54, 0x0, 13}, 89 {0x7e50, 0x7e54, 0x10, 6}, 90 {0x7e50, 0x7e54, 0x18, 21}, 91 {0x7e50, 0x7e54, 0x30, 32}, 92 {0x7e50, 0x7e54, 0x50, 22}, 93 {0x7e50, 0x7e54, 0x68, 12} 94 }; 95 96 static const u32 t5_tp_mib_index_array[9][IREG_NUM_ELEM] = { 97 {0x7e50, 0x7e54, 0x0, 13}, 98 {0x7e50, 0x7e54, 0x10, 6}, 99 {0x7e50, 0x7e54, 0x18, 8}, 100 {0x7e50, 0x7e54, 0x20, 13}, 101 {0x7e50, 0x7e54, 0x30, 16}, 102 {0x7e50, 0x7e54, 0x40, 16}, 103 {0x7e50, 0x7e54, 0x50, 16}, 104 {0x7e50, 0x7e54, 0x60, 6}, 105 {0x7e50, 0x7e54, 0x68, 4} 106 }; 107 108 static const u32 t5_sge_dbg_index_array[2][IREG_NUM_ELEM] = { 109 {0x10cc, 0x10d0, 0x0, 16}, 110 {0x10cc, 0x10d4, 0x0, 16}, 111 }; 112 113 static const u32 t5_pcie_pdbg_array[][IREG_NUM_ELEM] = { 114 {0x5a04, 0x5a0c, 0x00, 0x20}, /* t5_pcie_pdbg_regs_00_to_20 */ 115 {0x5a04, 0x5a0c, 0x21, 0x20}, /* t5_pcie_pdbg_regs_21_to_40 */ 116 {0x5a04, 0x5a0c, 0x41, 0x10}, /* t5_pcie_pdbg_regs_41_to_50 */ 117 }; 118 119 static const u32 t5_pcie_cdbg_array[][IREG_NUM_ELEM] = { 120 {0x5a10, 0x5a18, 0x00, 0x20}, /* t5_pcie_cdbg_regs_00_to_20 */ 121 {0x5a10, 0x5a18, 0x21, 0x18}, /* t5_pcie_cdbg_regs_21_to_37 */ 122 }; 123 124 static const u32 t5_pm_rx_array[][IREG_NUM_ELEM] = { 125 {0x8FD0, 0x8FD4, 0x10000, 0x20}, /* t5_pm_rx_regs_10000_to_10020 */ 126 {0x8FD0, 0x8FD4, 0x10021, 0x0D}, /* t5_pm_rx_regs_10021_to_1002c */ 127 }; 128 129 static const u32 t5_pm_tx_array[][IREG_NUM_ELEM] = { 130 {0x8FF0, 0x8FF4, 0x10000, 0x20}, /* t5_pm_tx_regs_10000_to_10020 */ 131 {0x8FF0, 0x8FF4, 0x10021, 0x1D}, /* t5_pm_tx_regs_10021_to_1003c */ 132 }; 133 134 static const u32 t6_ma_ireg_array[][IREG_NUM_ELEM] = { 135 {0x78f8, 0x78fc, 0xa000, 23}, /* t6_ma_regs_a000_to_a016 */ 136 {0x78f8, 0x78fc, 0xa400, 30}, /* t6_ma_regs_a400_to_a41e */ 137 {0x78f8, 0x78fc, 0xa800, 20} /* t6_ma_regs_a800_to_a813 */ 138 }; 139 140 static const u32 t6_ma_ireg_array2[][IREG_NUM_ELEM] = { 141 {0x78f8, 0x78fc, 0xe400, 17}, /* t6_ma_regs_e400_to_e600 */ 142 {0x78f8, 0x78fc, 0xe640, 13} /* t6_ma_regs_e640_to_e7c0 */ 143 }; 144 145 static const u32 t6_up_cim_reg_array[][IREG_NUM_ELEM] = { 146 {0x7b50, 0x7b54, 0x2000, 0x20}, /* up_cim_2000_to_207c */ 147 {0x7b50, 0x7b54, 0x2080, 0x1d}, /* up_cim_2080_to_20fc */ 148 {0x7b50, 0x7b54, 0x00, 0x20}, /* up_cim_00_to_7c */ 149 {0x7b50, 0x7b54, 0x80, 0x20}, /* up_cim_80_to_fc */ 150 {0x7b50, 0x7b54, 0x100, 0x11}, /* up_cim_100_to_14c */ 151 {0x7b50, 0x7b54, 0x200, 0x10}, /* up_cim_200_to_23c */ 152 {0x7b50, 0x7b54, 0x240, 0x2}, /* up_cim_240_to_244 */ 153 {0x7b50, 0x7b54, 0x250, 0x2}, /* up_cim_250_to_254 */ 154 {0x7b50, 0x7b54, 0x260, 0x2}, /* up_cim_260_to_264 */ 155 {0x7b50, 0x7b54, 0x270, 0x2}, /* up_cim_270_to_274 */ 156 {0x7b50, 0x7b54, 0x280, 0x20}, /* up_cim_280_to_2fc */ 157 {0x7b50, 0x7b54, 0x300, 0x20}, /* up_cim_300_to_37c */ 158 {0x7b50, 0x7b54, 0x380, 0x14}, /* up_cim_380_to_3cc */ 159 160 }; 161 162 static const u32 t5_up_cim_reg_array[][IREG_NUM_ELEM] = { 163 {0x7b50, 0x7b54, 0x2000, 0x20}, /* up_cim_2000_to_207c */ 164 {0x7b50, 0x7b54, 0x2080, 0x19}, /* up_cim_2080_to_20ec */ 165 {0x7b50, 0x7b54, 0x00, 0x20}, /* up_cim_00_to_7c */ 166 {0x7b50, 0x7b54, 0x80, 0x20}, /* up_cim_80_to_fc */ 167 {0x7b50, 0x7b54, 0x100, 0x11}, /* up_cim_100_to_14c */ 168 {0x7b50, 0x7b54, 0x200, 0x10}, /* up_cim_200_to_23c */ 169 {0x7b50, 0x7b54, 0x240, 0x2}, /* up_cim_240_to_244 */ 170 {0x7b50, 0x7b54, 0x250, 0x2}, /* up_cim_250_to_254 */ 171 {0x7b50, 0x7b54, 0x260, 0x2}, /* up_cim_260_to_264 */ 172 {0x7b50, 0x7b54, 0x270, 0x2}, /* up_cim_270_to_274 */ 173 {0x7b50, 0x7b54, 0x280, 0x20}, /* up_cim_280_to_2fc */ 174 {0x7b50, 0x7b54, 0x300, 0x20}, /* up_cim_300_to_37c */ 175 {0x7b50, 0x7b54, 0x380, 0x14}, /* up_cim_380_to_3cc */ 176 }; 177 178 static const u32 t6_hma_ireg_array[][IREG_NUM_ELEM] = { 179 {0x51320, 0x51324, 0xa000, 32} /* t6_hma_regs_a000_to_a01f */ 180 }; 181 #endif /* __CUDBG_ENTITY_H__ */ 182