1 // SPDX-License-Identifier: GPL-2.0 2 /* $Date: 2006/02/07 04:21:54 $ $RCSfile: tp.c,v $ $Revision: 1.73 $ */ 3 #include "common.h" 4 #include "regs.h" 5 #include "tp.h" 6 #ifdef CONFIG_CHELSIO_T1_1G 7 #include "fpga_defs.h" 8 #endif 9 10 struct petp { 11 adapter_t *adapter; 12 }; 13 14 /* Pause deadlock avoidance parameters */ 15 #define DROP_MSEC 16 16 #define DROP_PKTS_CNT 1 17 18 static void tp_init(adapter_t * ap, const struct tp_params *p, 19 unsigned int tp_clk) 20 { 21 u32 val; 22 23 if (!t1_is_asic(ap)) 24 return; 25 26 val = F_TP_IN_CSPI_CPL | F_TP_IN_CSPI_CHECK_IP_CSUM | 27 F_TP_IN_CSPI_CHECK_TCP_CSUM | F_TP_IN_ESPI_ETHERNET; 28 if (!p->pm_size) 29 val |= F_OFFLOAD_DISABLE; 30 else 31 val |= F_TP_IN_ESPI_CHECK_IP_CSUM | F_TP_IN_ESPI_CHECK_TCP_CSUM; 32 writel(val, ap->regs + A_TP_IN_CONFIG); 33 writel(F_TP_OUT_CSPI_CPL | 34 F_TP_OUT_ESPI_ETHERNET | 35 F_TP_OUT_ESPI_GENERATE_IP_CSUM | 36 F_TP_OUT_ESPI_GENERATE_TCP_CSUM, ap->regs + A_TP_OUT_CONFIG); 37 writel(V_IP_TTL(64) | 38 F_PATH_MTU /* IP DF bit */ | 39 V_5TUPLE_LOOKUP(p->use_5tuple_mode) | 40 V_SYN_COOKIE_PARAMETER(29), ap->regs + A_TP_GLOBAL_CONFIG); 41 /* 42 * Enable pause frame deadlock prevention. 43 */ 44 if (is_T2(ap) && ap->params.nports > 1) { 45 u32 drop_ticks = DROP_MSEC * (tp_clk / 1000); 46 47 writel(F_ENABLE_TX_DROP | F_ENABLE_TX_ERROR | 48 V_DROP_TICKS_CNT(drop_ticks) | 49 V_NUM_PKTS_DROPPED(DROP_PKTS_CNT), 50 ap->regs + A_TP_TX_DROP_CONFIG); 51 } 52 } 53 54 void t1_tp_destroy(struct petp *tp) 55 { 56 kfree(tp); 57 } 58 59 struct petp *t1_tp_create(adapter_t *adapter, struct tp_params *p) 60 { 61 struct petp *tp = kzalloc(sizeof(*tp), GFP_KERNEL); 62 63 if (!tp) 64 return NULL; 65 66 tp->adapter = adapter; 67 68 return tp; 69 } 70 71 void t1_tp_intr_enable(struct petp *tp) 72 { 73 u32 tp_intr = readl(tp->adapter->regs + A_PL_ENABLE); 74 75 #ifdef CONFIG_CHELSIO_T1_1G 76 if (!t1_is_asic(tp->adapter)) { 77 /* FPGA */ 78 writel(0xffffffff, 79 tp->adapter->regs + FPGA_TP_ADDR_INTERRUPT_ENABLE); 80 writel(tp_intr | FPGA_PCIX_INTERRUPT_TP, 81 tp->adapter->regs + A_PL_ENABLE); 82 } else 83 #endif 84 { 85 /* We don't use any TP interrupts */ 86 writel(0, tp->adapter->regs + A_TP_INT_ENABLE); 87 writel(tp_intr | F_PL_INTR_TP, 88 tp->adapter->regs + A_PL_ENABLE); 89 } 90 } 91 92 void t1_tp_intr_disable(struct petp *tp) 93 { 94 u32 tp_intr = readl(tp->adapter->regs + A_PL_ENABLE); 95 96 #ifdef CONFIG_CHELSIO_T1_1G 97 if (!t1_is_asic(tp->adapter)) { 98 /* FPGA */ 99 writel(0, tp->adapter->regs + FPGA_TP_ADDR_INTERRUPT_ENABLE); 100 writel(tp_intr & ~FPGA_PCIX_INTERRUPT_TP, 101 tp->adapter->regs + A_PL_ENABLE); 102 } else 103 #endif 104 { 105 writel(0, tp->adapter->regs + A_TP_INT_ENABLE); 106 writel(tp_intr & ~F_PL_INTR_TP, 107 tp->adapter->regs + A_PL_ENABLE); 108 } 109 } 110 111 void t1_tp_intr_clear(struct petp *tp) 112 { 113 #ifdef CONFIG_CHELSIO_T1_1G 114 if (!t1_is_asic(tp->adapter)) { 115 writel(0xffffffff, 116 tp->adapter->regs + FPGA_TP_ADDR_INTERRUPT_CAUSE); 117 writel(FPGA_PCIX_INTERRUPT_TP, tp->adapter->regs + A_PL_CAUSE); 118 return; 119 } 120 #endif 121 writel(0xffffffff, tp->adapter->regs + A_TP_INT_CAUSE); 122 writel(F_PL_INTR_TP, tp->adapter->regs + A_PL_CAUSE); 123 } 124 125 int t1_tp_intr_handler(struct petp *tp) 126 { 127 u32 cause; 128 129 #ifdef CONFIG_CHELSIO_T1_1G 130 /* FPGA doesn't support TP interrupts. */ 131 if (!t1_is_asic(tp->adapter)) 132 return 1; 133 #endif 134 135 cause = readl(tp->adapter->regs + A_TP_INT_CAUSE); 136 writel(cause, tp->adapter->regs + A_TP_INT_CAUSE); 137 return 0; 138 } 139 140 static void set_csum_offload(struct petp *tp, u32 csum_bit, int enable) 141 { 142 u32 val = readl(tp->adapter->regs + A_TP_GLOBAL_CONFIG); 143 144 if (enable) 145 val |= csum_bit; 146 else 147 val &= ~csum_bit; 148 writel(val, tp->adapter->regs + A_TP_GLOBAL_CONFIG); 149 } 150 151 void t1_tp_set_ip_checksum_offload(struct petp *tp, int enable) 152 { 153 set_csum_offload(tp, F_IP_CSUM, enable); 154 } 155 156 void t1_tp_set_tcp_checksum_offload(struct petp *tp, int enable) 157 { 158 set_csum_offload(tp, F_TCP_CSUM, enable); 159 } 160 161 /* 162 * Initialize TP state. tp_params contains initial settings for some TP 163 * parameters, particularly the one-time PM and CM settings. 164 */ 165 int t1_tp_reset(struct petp *tp, struct tp_params *p, unsigned int tp_clk) 166 { 167 adapter_t *adapter = tp->adapter; 168 169 tp_init(adapter, p, tp_clk); 170 writel(F_TP_RESET, adapter->regs + A_TP_RESET); 171 return 0; 172 } 173