1 /* 2 * Copyright (C) 2015 Cavium, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of version 2 of the GNU General Public License 6 * as published by the Free Software Foundation. 7 */ 8 9 #include <linux/pci.h> 10 #include <linux/netdevice.h> 11 #include <linux/ip.h> 12 #include <linux/etherdevice.h> 13 #include <linux/iommu.h> 14 #include <net/ip.h> 15 #include <net/tso.h> 16 17 #include "nic_reg.h" 18 #include "nic.h" 19 #include "q_struct.h" 20 #include "nicvf_queues.h" 21 22 static inline void nicvf_sq_add_gather_subdesc(struct snd_queue *sq, int qentry, 23 int size, u64 data); 24 static void nicvf_get_page(struct nicvf *nic) 25 { 26 if (!nic->rb_pageref || !nic->rb_page) 27 return; 28 29 page_ref_add(nic->rb_page, nic->rb_pageref); 30 nic->rb_pageref = 0; 31 } 32 33 /* Poll a register for a specific value */ 34 static int nicvf_poll_reg(struct nicvf *nic, int qidx, 35 u64 reg, int bit_pos, int bits, int val) 36 { 37 u64 bit_mask; 38 u64 reg_val; 39 int timeout = 10; 40 41 bit_mask = (1ULL << bits) - 1; 42 bit_mask = (bit_mask << bit_pos); 43 44 while (timeout) { 45 reg_val = nicvf_queue_reg_read(nic, reg, qidx); 46 if (((reg_val & bit_mask) >> bit_pos) == val) 47 return 0; 48 usleep_range(1000, 2000); 49 timeout--; 50 } 51 netdev_err(nic->netdev, "Poll on reg 0x%llx failed\n", reg); 52 return 1; 53 } 54 55 /* Allocate memory for a queue's descriptors */ 56 static int nicvf_alloc_q_desc_mem(struct nicvf *nic, struct q_desc_mem *dmem, 57 int q_len, int desc_size, int align_bytes) 58 { 59 dmem->q_len = q_len; 60 dmem->size = (desc_size * q_len) + align_bytes; 61 /* Save address, need it while freeing */ 62 dmem->unalign_base = dma_zalloc_coherent(&nic->pdev->dev, dmem->size, 63 &dmem->dma, GFP_KERNEL); 64 if (!dmem->unalign_base) 65 return -ENOMEM; 66 67 /* Align memory address for 'align_bytes' */ 68 dmem->phys_base = NICVF_ALIGNED_ADDR((u64)dmem->dma, align_bytes); 69 dmem->base = dmem->unalign_base + (dmem->phys_base - dmem->dma); 70 return 0; 71 } 72 73 /* Free queue's descriptor memory */ 74 static void nicvf_free_q_desc_mem(struct nicvf *nic, struct q_desc_mem *dmem) 75 { 76 if (!dmem) 77 return; 78 79 dma_free_coherent(&nic->pdev->dev, dmem->size, 80 dmem->unalign_base, dmem->dma); 81 dmem->unalign_base = NULL; 82 dmem->base = NULL; 83 } 84 85 #define XDP_PAGE_REFCNT_REFILL 256 86 87 /* Allocate a new page or recycle one if possible 88 * 89 * We cannot optimize dma mapping here, since 90 * 1. It's only one RBDR ring for 8 Rx queues. 91 * 2. CQE_RX gives address of the buffer where pkt has been DMA'ed 92 * and not idx into RBDR ring, so can't refer to saved info. 93 * 3. There are multiple receive buffers per page 94 */ 95 static inline struct pgcache *nicvf_alloc_page(struct nicvf *nic, 96 struct rbdr *rbdr, gfp_t gfp) 97 { 98 int ref_count; 99 struct page *page = NULL; 100 struct pgcache *pgcache, *next; 101 102 /* Check if page is already allocated */ 103 pgcache = &rbdr->pgcache[rbdr->pgidx]; 104 page = pgcache->page; 105 /* Check if page can be recycled */ 106 if (page) { 107 ref_count = page_ref_count(page); 108 /* Check if this page has been used once i.e 'put_page' 109 * called after packet transmission i.e internal ref_count 110 * and page's ref_count are equal i.e page can be recycled. 111 */ 112 if (rbdr->is_xdp && (ref_count == pgcache->ref_count)) 113 pgcache->ref_count--; 114 else 115 page = NULL; 116 117 /* In non-XDP mode, page's ref_count needs to be '1' for it 118 * to be recycled. 119 */ 120 if (!rbdr->is_xdp && (ref_count != 1)) 121 page = NULL; 122 } 123 124 if (!page) { 125 page = alloc_pages(gfp | __GFP_COMP | __GFP_NOWARN, 0); 126 if (!page) 127 return NULL; 128 129 this_cpu_inc(nic->pnicvf->drv_stats->page_alloc); 130 131 /* Check for space */ 132 if (rbdr->pgalloc >= rbdr->pgcnt) { 133 /* Page can still be used */ 134 nic->rb_page = page; 135 return NULL; 136 } 137 138 /* Save the page in page cache */ 139 pgcache->page = page; 140 pgcache->dma_addr = 0; 141 pgcache->ref_count = 0; 142 rbdr->pgalloc++; 143 } 144 145 /* Take additional page references for recycling */ 146 if (rbdr->is_xdp) { 147 /* Since there is single RBDR (i.e single core doing 148 * page recycling) per 8 Rx queues, in XDP mode adjusting 149 * page references atomically is the biggest bottleneck, so 150 * take bunch of references at a time. 151 * 152 * So here, below reference counts defer by '1'. 153 */ 154 if (!pgcache->ref_count) { 155 pgcache->ref_count = XDP_PAGE_REFCNT_REFILL; 156 page_ref_add(page, XDP_PAGE_REFCNT_REFILL); 157 } 158 } else { 159 /* In non-XDP case, single 64K page is divided across multiple 160 * receive buffers, so cost of recycling is less anyway. 161 * So we can do with just one extra reference. 162 */ 163 page_ref_add(page, 1); 164 } 165 166 rbdr->pgidx++; 167 rbdr->pgidx &= (rbdr->pgcnt - 1); 168 169 /* Prefetch refcount of next page in page cache */ 170 next = &rbdr->pgcache[rbdr->pgidx]; 171 page = next->page; 172 if (page) 173 prefetch(&page->_refcount); 174 175 return pgcache; 176 } 177 178 /* Allocate buffer for packet reception */ 179 static inline int nicvf_alloc_rcv_buffer(struct nicvf *nic, struct rbdr *rbdr, 180 gfp_t gfp, u32 buf_len, u64 *rbuf) 181 { 182 struct pgcache *pgcache = NULL; 183 184 /* Check if request can be accomodated in previous allocated page. 185 * But in XDP mode only one buffer per page is permitted. 186 */ 187 if (!rbdr->is_xdp && nic->rb_page && 188 ((nic->rb_page_offset + buf_len) <= PAGE_SIZE)) { 189 nic->rb_pageref++; 190 goto ret; 191 } 192 193 nicvf_get_page(nic); 194 nic->rb_page = NULL; 195 196 /* Get new page, either recycled or new one */ 197 pgcache = nicvf_alloc_page(nic, rbdr, gfp); 198 if (!pgcache && !nic->rb_page) { 199 this_cpu_inc(nic->pnicvf->drv_stats->rcv_buffer_alloc_failures); 200 return -ENOMEM; 201 } 202 203 nic->rb_page_offset = 0; 204 205 /* Reserve space for header modifications by BPF program */ 206 if (rbdr->is_xdp) 207 buf_len += XDP_HEADROOM; 208 209 /* Check if it's recycled */ 210 if (pgcache) 211 nic->rb_page = pgcache->page; 212 ret: 213 if (rbdr->is_xdp && pgcache && pgcache->dma_addr) { 214 *rbuf = pgcache->dma_addr; 215 } else { 216 /* HW will ensure data coherency, CPU sync not required */ 217 *rbuf = (u64)dma_map_page_attrs(&nic->pdev->dev, nic->rb_page, 218 nic->rb_page_offset, buf_len, 219 DMA_FROM_DEVICE, 220 DMA_ATTR_SKIP_CPU_SYNC); 221 if (dma_mapping_error(&nic->pdev->dev, (dma_addr_t)*rbuf)) { 222 if (!nic->rb_page_offset) 223 __free_pages(nic->rb_page, 0); 224 nic->rb_page = NULL; 225 return -ENOMEM; 226 } 227 228 if (pgcache) 229 pgcache->dma_addr = *rbuf + XDP_HEADROOM; 230 nic->rb_page_offset += buf_len; 231 } 232 233 return 0; 234 } 235 236 /* Build skb around receive buffer */ 237 static struct sk_buff *nicvf_rb_ptr_to_skb(struct nicvf *nic, 238 u64 rb_ptr, int len) 239 { 240 void *data; 241 struct sk_buff *skb; 242 243 data = phys_to_virt(rb_ptr); 244 245 /* Now build an skb to give to stack */ 246 skb = build_skb(data, RCV_FRAG_LEN); 247 if (!skb) { 248 put_page(virt_to_page(data)); 249 return NULL; 250 } 251 252 prefetch(skb->data); 253 return skb; 254 } 255 256 /* Allocate RBDR ring and populate receive buffers */ 257 static int nicvf_init_rbdr(struct nicvf *nic, struct rbdr *rbdr, 258 int ring_len, int buf_size) 259 { 260 int idx; 261 u64 rbuf; 262 struct rbdr_entry_t *desc; 263 int err; 264 265 err = nicvf_alloc_q_desc_mem(nic, &rbdr->dmem, ring_len, 266 sizeof(struct rbdr_entry_t), 267 NICVF_RCV_BUF_ALIGN_BYTES); 268 if (err) 269 return err; 270 271 rbdr->desc = rbdr->dmem.base; 272 /* Buffer size has to be in multiples of 128 bytes */ 273 rbdr->dma_size = buf_size; 274 rbdr->enable = true; 275 rbdr->thresh = RBDR_THRESH; 276 rbdr->head = 0; 277 rbdr->tail = 0; 278 279 /* Initialize page recycling stuff. 280 * 281 * Can't use single buffer per page especially with 64K pages. 282 * On embedded platforms i.e 81xx/83xx available memory itself 283 * is low and minimum ring size of RBDR is 8K, that takes away 284 * lots of memory. 285 * 286 * But for XDP it has to be a single buffer per page. 287 */ 288 if (!nic->pnicvf->xdp_prog) { 289 rbdr->pgcnt = ring_len / (PAGE_SIZE / buf_size); 290 rbdr->is_xdp = false; 291 } else { 292 rbdr->pgcnt = ring_len; 293 rbdr->is_xdp = true; 294 } 295 rbdr->pgcnt = roundup_pow_of_two(rbdr->pgcnt); 296 rbdr->pgcache = kzalloc(sizeof(*rbdr->pgcache) * 297 rbdr->pgcnt, GFP_KERNEL); 298 if (!rbdr->pgcache) 299 return -ENOMEM; 300 rbdr->pgidx = 0; 301 rbdr->pgalloc = 0; 302 303 nic->rb_page = NULL; 304 for (idx = 0; idx < ring_len; idx++) { 305 err = nicvf_alloc_rcv_buffer(nic, rbdr, GFP_KERNEL, 306 RCV_FRAG_LEN, &rbuf); 307 if (err) { 308 /* To free already allocated and mapped ones */ 309 rbdr->tail = idx - 1; 310 return err; 311 } 312 313 desc = GET_RBDR_DESC(rbdr, idx); 314 desc->buf_addr = rbuf & ~(NICVF_RCV_BUF_ALIGN_BYTES - 1); 315 } 316 317 nicvf_get_page(nic); 318 319 return 0; 320 } 321 322 /* Free RBDR ring and its receive buffers */ 323 static void nicvf_free_rbdr(struct nicvf *nic, struct rbdr *rbdr) 324 { 325 int head, tail; 326 u64 buf_addr, phys_addr; 327 struct pgcache *pgcache; 328 struct rbdr_entry_t *desc; 329 330 if (!rbdr) 331 return; 332 333 rbdr->enable = false; 334 if (!rbdr->dmem.base) 335 return; 336 337 head = rbdr->head; 338 tail = rbdr->tail; 339 340 /* Release page references */ 341 while (head != tail) { 342 desc = GET_RBDR_DESC(rbdr, head); 343 buf_addr = desc->buf_addr; 344 phys_addr = nicvf_iova_to_phys(nic, buf_addr); 345 dma_unmap_page_attrs(&nic->pdev->dev, buf_addr, RCV_FRAG_LEN, 346 DMA_FROM_DEVICE, DMA_ATTR_SKIP_CPU_SYNC); 347 if (phys_addr) 348 put_page(virt_to_page(phys_to_virt(phys_addr))); 349 head++; 350 head &= (rbdr->dmem.q_len - 1); 351 } 352 /* Release buffer of tail desc */ 353 desc = GET_RBDR_DESC(rbdr, tail); 354 buf_addr = desc->buf_addr; 355 phys_addr = nicvf_iova_to_phys(nic, buf_addr); 356 dma_unmap_page_attrs(&nic->pdev->dev, buf_addr, RCV_FRAG_LEN, 357 DMA_FROM_DEVICE, DMA_ATTR_SKIP_CPU_SYNC); 358 if (phys_addr) 359 put_page(virt_to_page(phys_to_virt(phys_addr))); 360 361 /* Sync page cache info */ 362 smp_rmb(); 363 364 /* Release additional page references held for recycling */ 365 head = 0; 366 while (head < rbdr->pgcnt) { 367 pgcache = &rbdr->pgcache[head]; 368 if (pgcache->page && page_ref_count(pgcache->page) != 0) { 369 if (!rbdr->is_xdp) { 370 put_page(pgcache->page); 371 continue; 372 } 373 page_ref_sub(pgcache->page, pgcache->ref_count - 1); 374 put_page(pgcache->page); 375 } 376 head++; 377 } 378 379 /* Free RBDR ring */ 380 nicvf_free_q_desc_mem(nic, &rbdr->dmem); 381 } 382 383 /* Refill receive buffer descriptors with new buffers. 384 */ 385 static void nicvf_refill_rbdr(struct nicvf *nic, gfp_t gfp) 386 { 387 struct queue_set *qs = nic->qs; 388 int rbdr_idx = qs->rbdr_cnt; 389 int tail, qcount; 390 int refill_rb_cnt; 391 struct rbdr *rbdr; 392 struct rbdr_entry_t *desc; 393 u64 rbuf; 394 int new_rb = 0; 395 396 refill: 397 if (!rbdr_idx) 398 return; 399 rbdr_idx--; 400 rbdr = &qs->rbdr[rbdr_idx]; 401 /* Check if it's enabled */ 402 if (!rbdr->enable) 403 goto next_rbdr; 404 405 /* Get no of desc's to be refilled */ 406 qcount = nicvf_queue_reg_read(nic, NIC_QSET_RBDR_0_1_STATUS0, rbdr_idx); 407 qcount &= 0x7FFFF; 408 /* Doorbell can be ringed with a max of ring size minus 1 */ 409 if (qcount >= (qs->rbdr_len - 1)) 410 goto next_rbdr; 411 else 412 refill_rb_cnt = qs->rbdr_len - qcount - 1; 413 414 /* Sync page cache info */ 415 smp_rmb(); 416 417 /* Start filling descs from tail */ 418 tail = nicvf_queue_reg_read(nic, NIC_QSET_RBDR_0_1_TAIL, rbdr_idx) >> 3; 419 while (refill_rb_cnt) { 420 tail++; 421 tail &= (rbdr->dmem.q_len - 1); 422 423 if (nicvf_alloc_rcv_buffer(nic, rbdr, gfp, RCV_FRAG_LEN, &rbuf)) 424 break; 425 426 desc = GET_RBDR_DESC(rbdr, tail); 427 desc->buf_addr = rbuf & ~(NICVF_RCV_BUF_ALIGN_BYTES - 1); 428 refill_rb_cnt--; 429 new_rb++; 430 } 431 432 nicvf_get_page(nic); 433 434 /* make sure all memory stores are done before ringing doorbell */ 435 smp_wmb(); 436 437 /* Check if buffer allocation failed */ 438 if (refill_rb_cnt) 439 nic->rb_alloc_fail = true; 440 else 441 nic->rb_alloc_fail = false; 442 443 /* Notify HW */ 444 nicvf_queue_reg_write(nic, NIC_QSET_RBDR_0_1_DOOR, 445 rbdr_idx, new_rb); 446 next_rbdr: 447 /* Re-enable RBDR interrupts only if buffer allocation is success */ 448 if (!nic->rb_alloc_fail && rbdr->enable && 449 netif_running(nic->pnicvf->netdev)) 450 nicvf_enable_intr(nic, NICVF_INTR_RBDR, rbdr_idx); 451 452 if (rbdr_idx) 453 goto refill; 454 } 455 456 /* Alloc rcv buffers in non-atomic mode for better success */ 457 void nicvf_rbdr_work(struct work_struct *work) 458 { 459 struct nicvf *nic = container_of(work, struct nicvf, rbdr_work.work); 460 461 nicvf_refill_rbdr(nic, GFP_KERNEL); 462 if (nic->rb_alloc_fail) 463 schedule_delayed_work(&nic->rbdr_work, msecs_to_jiffies(10)); 464 else 465 nic->rb_work_scheduled = false; 466 } 467 468 /* In Softirq context, alloc rcv buffers in atomic mode */ 469 void nicvf_rbdr_task(unsigned long data) 470 { 471 struct nicvf *nic = (struct nicvf *)data; 472 473 nicvf_refill_rbdr(nic, GFP_ATOMIC); 474 if (nic->rb_alloc_fail) { 475 nic->rb_work_scheduled = true; 476 schedule_delayed_work(&nic->rbdr_work, msecs_to_jiffies(10)); 477 } 478 } 479 480 /* Initialize completion queue */ 481 static int nicvf_init_cmp_queue(struct nicvf *nic, 482 struct cmp_queue *cq, int q_len) 483 { 484 int err; 485 486 err = nicvf_alloc_q_desc_mem(nic, &cq->dmem, q_len, CMP_QUEUE_DESC_SIZE, 487 NICVF_CQ_BASE_ALIGN_BYTES); 488 if (err) 489 return err; 490 491 cq->desc = cq->dmem.base; 492 cq->thresh = pass1_silicon(nic->pdev) ? 0 : CMP_QUEUE_CQE_THRESH; 493 nic->cq_coalesce_usecs = (CMP_QUEUE_TIMER_THRESH * 0.05) - 1; 494 495 return 0; 496 } 497 498 static void nicvf_free_cmp_queue(struct nicvf *nic, struct cmp_queue *cq) 499 { 500 if (!cq) 501 return; 502 if (!cq->dmem.base) 503 return; 504 505 nicvf_free_q_desc_mem(nic, &cq->dmem); 506 } 507 508 /* Initialize transmit queue */ 509 static int nicvf_init_snd_queue(struct nicvf *nic, 510 struct snd_queue *sq, int q_len, int qidx) 511 { 512 int err; 513 514 err = nicvf_alloc_q_desc_mem(nic, &sq->dmem, q_len, SND_QUEUE_DESC_SIZE, 515 NICVF_SQ_BASE_ALIGN_BYTES); 516 if (err) 517 return err; 518 519 sq->desc = sq->dmem.base; 520 sq->skbuff = kcalloc(q_len, sizeof(u64), GFP_KERNEL); 521 if (!sq->skbuff) 522 return -ENOMEM; 523 524 sq->head = 0; 525 sq->tail = 0; 526 sq->thresh = SND_QUEUE_THRESH; 527 528 /* Check if this SQ is a XDP TX queue */ 529 if (nic->sqs_mode) 530 qidx += ((nic->sqs_id + 1) * MAX_SND_QUEUES_PER_QS); 531 if (qidx < nic->pnicvf->xdp_tx_queues) { 532 /* Alloc memory to save page pointers for XDP_TX */ 533 sq->xdp_page = kcalloc(q_len, sizeof(u64), GFP_KERNEL); 534 if (!sq->xdp_page) 535 return -ENOMEM; 536 sq->xdp_desc_cnt = 0; 537 sq->xdp_free_cnt = q_len - 1; 538 sq->is_xdp = true; 539 } else { 540 sq->xdp_page = NULL; 541 sq->xdp_desc_cnt = 0; 542 sq->xdp_free_cnt = 0; 543 sq->is_xdp = false; 544 545 atomic_set(&sq->free_cnt, q_len - 1); 546 547 /* Preallocate memory for TSO segment's header */ 548 sq->tso_hdrs = dma_alloc_coherent(&nic->pdev->dev, 549 q_len * TSO_HEADER_SIZE, 550 &sq->tso_hdrs_phys, 551 GFP_KERNEL); 552 if (!sq->tso_hdrs) 553 return -ENOMEM; 554 } 555 556 return 0; 557 } 558 559 void nicvf_unmap_sndq_buffers(struct nicvf *nic, struct snd_queue *sq, 560 int hdr_sqe, u8 subdesc_cnt) 561 { 562 u8 idx; 563 struct sq_gather_subdesc *gather; 564 565 /* Unmap DMA mapped skb data buffers */ 566 for (idx = 0; idx < subdesc_cnt; idx++) { 567 hdr_sqe++; 568 hdr_sqe &= (sq->dmem.q_len - 1); 569 gather = (struct sq_gather_subdesc *)GET_SQ_DESC(sq, hdr_sqe); 570 /* HW will ensure data coherency, CPU sync not required */ 571 dma_unmap_page_attrs(&nic->pdev->dev, gather->addr, 572 gather->size, DMA_TO_DEVICE, 573 DMA_ATTR_SKIP_CPU_SYNC); 574 } 575 } 576 577 static void nicvf_free_snd_queue(struct nicvf *nic, struct snd_queue *sq) 578 { 579 struct sk_buff *skb; 580 struct page *page; 581 struct sq_hdr_subdesc *hdr; 582 struct sq_hdr_subdesc *tso_sqe; 583 584 if (!sq) 585 return; 586 if (!sq->dmem.base) 587 return; 588 589 if (sq->tso_hdrs) 590 dma_free_coherent(&nic->pdev->dev, 591 sq->dmem.q_len * TSO_HEADER_SIZE, 592 sq->tso_hdrs, sq->tso_hdrs_phys); 593 594 /* Free pending skbs in the queue */ 595 smp_rmb(); 596 while (sq->head != sq->tail) { 597 skb = (struct sk_buff *)sq->skbuff[sq->head]; 598 if (!skb || !sq->xdp_page) 599 goto next; 600 601 page = (struct page *)sq->xdp_page[sq->head]; 602 if (!page) 603 goto next; 604 else 605 put_page(page); 606 607 hdr = (struct sq_hdr_subdesc *)GET_SQ_DESC(sq, sq->head); 608 /* Check for dummy descriptor used for HW TSO offload on 88xx */ 609 if (hdr->dont_send) { 610 /* Get actual TSO descriptors and unmap them */ 611 tso_sqe = 612 (struct sq_hdr_subdesc *)GET_SQ_DESC(sq, hdr->rsvd2); 613 nicvf_unmap_sndq_buffers(nic, sq, hdr->rsvd2, 614 tso_sqe->subdesc_cnt); 615 } else { 616 nicvf_unmap_sndq_buffers(nic, sq, sq->head, 617 hdr->subdesc_cnt); 618 } 619 if (skb) 620 dev_kfree_skb_any(skb); 621 next: 622 sq->head++; 623 sq->head &= (sq->dmem.q_len - 1); 624 } 625 kfree(sq->skbuff); 626 kfree(sq->xdp_page); 627 nicvf_free_q_desc_mem(nic, &sq->dmem); 628 } 629 630 static void nicvf_reclaim_snd_queue(struct nicvf *nic, 631 struct queue_set *qs, int qidx) 632 { 633 /* Disable send queue */ 634 nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_CFG, qidx, 0); 635 /* Check if SQ is stopped */ 636 if (nicvf_poll_reg(nic, qidx, NIC_QSET_SQ_0_7_STATUS, 21, 1, 0x01)) 637 return; 638 /* Reset send queue */ 639 nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_CFG, qidx, NICVF_SQ_RESET); 640 } 641 642 static void nicvf_reclaim_rcv_queue(struct nicvf *nic, 643 struct queue_set *qs, int qidx) 644 { 645 union nic_mbx mbx = {}; 646 647 /* Make sure all packets in the pipeline are written back into mem */ 648 mbx.msg.msg = NIC_MBOX_MSG_RQ_SW_SYNC; 649 nicvf_send_msg_to_pf(nic, &mbx); 650 } 651 652 static void nicvf_reclaim_cmp_queue(struct nicvf *nic, 653 struct queue_set *qs, int qidx) 654 { 655 /* Disable timer threshold (doesn't get reset upon CQ reset */ 656 nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_CFG2, qidx, 0); 657 /* Disable completion queue */ 658 nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_CFG, qidx, 0); 659 /* Reset completion queue */ 660 nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_CFG, qidx, NICVF_CQ_RESET); 661 } 662 663 static void nicvf_reclaim_rbdr(struct nicvf *nic, 664 struct rbdr *rbdr, int qidx) 665 { 666 u64 tmp, fifo_state; 667 int timeout = 10; 668 669 /* Save head and tail pointers for feeing up buffers */ 670 rbdr->head = nicvf_queue_reg_read(nic, 671 NIC_QSET_RBDR_0_1_HEAD, 672 qidx) >> 3; 673 rbdr->tail = nicvf_queue_reg_read(nic, 674 NIC_QSET_RBDR_0_1_TAIL, 675 qidx) >> 3; 676 677 /* If RBDR FIFO is in 'FAIL' state then do a reset first 678 * before relaiming. 679 */ 680 fifo_state = nicvf_queue_reg_read(nic, NIC_QSET_RBDR_0_1_STATUS0, qidx); 681 if (((fifo_state >> 62) & 0x03) == 0x3) 682 nicvf_queue_reg_write(nic, NIC_QSET_RBDR_0_1_CFG, 683 qidx, NICVF_RBDR_RESET); 684 685 /* Disable RBDR */ 686 nicvf_queue_reg_write(nic, NIC_QSET_RBDR_0_1_CFG, qidx, 0); 687 if (nicvf_poll_reg(nic, qidx, NIC_QSET_RBDR_0_1_STATUS0, 62, 2, 0x00)) 688 return; 689 while (1) { 690 tmp = nicvf_queue_reg_read(nic, 691 NIC_QSET_RBDR_0_1_PREFETCH_STATUS, 692 qidx); 693 if ((tmp & 0xFFFFFFFF) == ((tmp >> 32) & 0xFFFFFFFF)) 694 break; 695 usleep_range(1000, 2000); 696 timeout--; 697 if (!timeout) { 698 netdev_err(nic->netdev, 699 "Failed polling on prefetch status\n"); 700 return; 701 } 702 } 703 nicvf_queue_reg_write(nic, NIC_QSET_RBDR_0_1_CFG, 704 qidx, NICVF_RBDR_RESET); 705 706 if (nicvf_poll_reg(nic, qidx, NIC_QSET_RBDR_0_1_STATUS0, 62, 2, 0x02)) 707 return; 708 nicvf_queue_reg_write(nic, NIC_QSET_RBDR_0_1_CFG, qidx, 0x00); 709 if (nicvf_poll_reg(nic, qidx, NIC_QSET_RBDR_0_1_STATUS0, 62, 2, 0x00)) 710 return; 711 } 712 713 void nicvf_config_vlan_stripping(struct nicvf *nic, netdev_features_t features) 714 { 715 u64 rq_cfg; 716 int sqs; 717 718 rq_cfg = nicvf_queue_reg_read(nic, NIC_QSET_RQ_GEN_CFG, 0); 719 720 /* Enable first VLAN stripping */ 721 if (features & NETIF_F_HW_VLAN_CTAG_RX) 722 rq_cfg |= (1ULL << 25); 723 else 724 rq_cfg &= ~(1ULL << 25); 725 nicvf_queue_reg_write(nic, NIC_QSET_RQ_GEN_CFG, 0, rq_cfg); 726 727 /* Configure Secondary Qsets, if any */ 728 for (sqs = 0; sqs < nic->sqs_count; sqs++) 729 if (nic->snicvf[sqs]) 730 nicvf_queue_reg_write(nic->snicvf[sqs], 731 NIC_QSET_RQ_GEN_CFG, 0, rq_cfg); 732 } 733 734 static void nicvf_reset_rcv_queue_stats(struct nicvf *nic) 735 { 736 union nic_mbx mbx = {}; 737 738 /* Reset all RQ/SQ and VF stats */ 739 mbx.reset_stat.msg = NIC_MBOX_MSG_RESET_STAT_COUNTER; 740 mbx.reset_stat.rx_stat_mask = 0x3FFF; 741 mbx.reset_stat.tx_stat_mask = 0x1F; 742 mbx.reset_stat.rq_stat_mask = 0xFFFF; 743 mbx.reset_stat.sq_stat_mask = 0xFFFF; 744 nicvf_send_msg_to_pf(nic, &mbx); 745 } 746 747 /* Configures receive queue */ 748 static void nicvf_rcv_queue_config(struct nicvf *nic, struct queue_set *qs, 749 int qidx, bool enable) 750 { 751 union nic_mbx mbx = {}; 752 struct rcv_queue *rq; 753 struct rq_cfg rq_cfg; 754 755 rq = &qs->rq[qidx]; 756 rq->enable = enable; 757 758 /* Disable receive queue */ 759 nicvf_queue_reg_write(nic, NIC_QSET_RQ_0_7_CFG, qidx, 0); 760 761 if (!rq->enable) { 762 nicvf_reclaim_rcv_queue(nic, qs, qidx); 763 return; 764 } 765 766 rq->cq_qs = qs->vnic_id; 767 rq->cq_idx = qidx; 768 rq->start_rbdr_qs = qs->vnic_id; 769 rq->start_qs_rbdr_idx = qs->rbdr_cnt - 1; 770 rq->cont_rbdr_qs = qs->vnic_id; 771 rq->cont_qs_rbdr_idx = qs->rbdr_cnt - 1; 772 /* all writes of RBDR data to be loaded into L2 Cache as well*/ 773 rq->caching = 1; 774 775 /* Send a mailbox msg to PF to config RQ */ 776 mbx.rq.msg = NIC_MBOX_MSG_RQ_CFG; 777 mbx.rq.qs_num = qs->vnic_id; 778 mbx.rq.rq_num = qidx; 779 mbx.rq.cfg = (rq->caching << 26) | (rq->cq_qs << 19) | 780 (rq->cq_idx << 16) | (rq->cont_rbdr_qs << 9) | 781 (rq->cont_qs_rbdr_idx << 8) | 782 (rq->start_rbdr_qs << 1) | (rq->start_qs_rbdr_idx); 783 nicvf_send_msg_to_pf(nic, &mbx); 784 785 mbx.rq.msg = NIC_MBOX_MSG_RQ_BP_CFG; 786 mbx.rq.cfg = BIT_ULL(63) | BIT_ULL(62) | 787 (RQ_PASS_RBDR_LVL << 16) | (RQ_PASS_CQ_LVL << 8) | 788 (qs->vnic_id << 0); 789 nicvf_send_msg_to_pf(nic, &mbx); 790 791 /* RQ drop config 792 * Enable CQ drop to reserve sufficient CQEs for all tx packets 793 */ 794 mbx.rq.msg = NIC_MBOX_MSG_RQ_DROP_CFG; 795 mbx.rq.cfg = BIT_ULL(63) | BIT_ULL(62) | 796 (RQ_PASS_RBDR_LVL << 40) | (RQ_DROP_RBDR_LVL << 32) | 797 (RQ_PASS_CQ_LVL << 16) | (RQ_DROP_CQ_LVL << 8); 798 nicvf_send_msg_to_pf(nic, &mbx); 799 800 if (!nic->sqs_mode && (qidx == 0)) { 801 /* Enable checking L3/L4 length and TCP/UDP checksums 802 * Also allow IPv6 pkts with zero UDP checksum. 803 */ 804 nicvf_queue_reg_write(nic, NIC_QSET_RQ_GEN_CFG, 0, 805 (BIT(24) | BIT(23) | BIT(21) | BIT(20))); 806 nicvf_config_vlan_stripping(nic, nic->netdev->features); 807 } 808 809 /* Enable Receive queue */ 810 memset(&rq_cfg, 0, sizeof(struct rq_cfg)); 811 rq_cfg.ena = 1; 812 rq_cfg.tcp_ena = 0; 813 nicvf_queue_reg_write(nic, NIC_QSET_RQ_0_7_CFG, qidx, *(u64 *)&rq_cfg); 814 } 815 816 /* Configures completion queue */ 817 void nicvf_cmp_queue_config(struct nicvf *nic, struct queue_set *qs, 818 int qidx, bool enable) 819 { 820 struct cmp_queue *cq; 821 struct cq_cfg cq_cfg; 822 823 cq = &qs->cq[qidx]; 824 cq->enable = enable; 825 826 if (!cq->enable) { 827 nicvf_reclaim_cmp_queue(nic, qs, qidx); 828 return; 829 } 830 831 /* Reset completion queue */ 832 nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_CFG, qidx, NICVF_CQ_RESET); 833 834 if (!cq->enable) 835 return; 836 837 spin_lock_init(&cq->lock); 838 /* Set completion queue base address */ 839 nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_BASE, 840 qidx, (u64)(cq->dmem.phys_base)); 841 842 /* Enable Completion queue */ 843 memset(&cq_cfg, 0, sizeof(struct cq_cfg)); 844 cq_cfg.ena = 1; 845 cq_cfg.reset = 0; 846 cq_cfg.caching = 0; 847 cq_cfg.qsize = ilog2(qs->cq_len >> 10); 848 cq_cfg.avg_con = 0; 849 nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_CFG, qidx, *(u64 *)&cq_cfg); 850 851 /* Set threshold value for interrupt generation */ 852 nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_THRESH, qidx, cq->thresh); 853 nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_CFG2, 854 qidx, CMP_QUEUE_TIMER_THRESH); 855 } 856 857 /* Configures transmit queue */ 858 static void nicvf_snd_queue_config(struct nicvf *nic, struct queue_set *qs, 859 int qidx, bool enable) 860 { 861 union nic_mbx mbx = {}; 862 struct snd_queue *sq; 863 struct sq_cfg sq_cfg; 864 865 sq = &qs->sq[qidx]; 866 sq->enable = enable; 867 868 if (!sq->enable) { 869 nicvf_reclaim_snd_queue(nic, qs, qidx); 870 return; 871 } 872 873 /* Reset send queue */ 874 nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_CFG, qidx, NICVF_SQ_RESET); 875 876 sq->cq_qs = qs->vnic_id; 877 sq->cq_idx = qidx; 878 879 /* Send a mailbox msg to PF to config SQ */ 880 mbx.sq.msg = NIC_MBOX_MSG_SQ_CFG; 881 mbx.sq.qs_num = qs->vnic_id; 882 mbx.sq.sq_num = qidx; 883 mbx.sq.sqs_mode = nic->sqs_mode; 884 mbx.sq.cfg = (sq->cq_qs << 3) | sq->cq_idx; 885 nicvf_send_msg_to_pf(nic, &mbx); 886 887 /* Set queue base address */ 888 nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_BASE, 889 qidx, (u64)(sq->dmem.phys_base)); 890 891 /* Enable send queue & set queue size */ 892 memset(&sq_cfg, 0, sizeof(struct sq_cfg)); 893 sq_cfg.ena = 1; 894 sq_cfg.reset = 0; 895 sq_cfg.ldwb = 0; 896 sq_cfg.qsize = ilog2(qs->sq_len >> 10); 897 sq_cfg.tstmp_bgx_intf = 0; 898 /* CQ's level at which HW will stop processing SQEs to avoid 899 * transmitting a pkt with no space in CQ to post CQE_TX. 900 */ 901 sq_cfg.cq_limit = (CMP_QUEUE_PIPELINE_RSVD * 256) / qs->cq_len; 902 nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_CFG, qidx, *(u64 *)&sq_cfg); 903 904 /* Set threshold value for interrupt generation */ 905 nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_THRESH, qidx, sq->thresh); 906 907 /* Set queue:cpu affinity for better load distribution */ 908 if (cpu_online(qidx)) { 909 cpumask_set_cpu(qidx, &sq->affinity_mask); 910 netif_set_xps_queue(nic->netdev, 911 &sq->affinity_mask, qidx); 912 } 913 } 914 915 /* Configures receive buffer descriptor ring */ 916 static void nicvf_rbdr_config(struct nicvf *nic, struct queue_set *qs, 917 int qidx, bool enable) 918 { 919 struct rbdr *rbdr; 920 struct rbdr_cfg rbdr_cfg; 921 922 rbdr = &qs->rbdr[qidx]; 923 nicvf_reclaim_rbdr(nic, rbdr, qidx); 924 if (!enable) 925 return; 926 927 /* Set descriptor base address */ 928 nicvf_queue_reg_write(nic, NIC_QSET_RBDR_0_1_BASE, 929 qidx, (u64)(rbdr->dmem.phys_base)); 930 931 /* Enable RBDR & set queue size */ 932 /* Buffer size should be in multiples of 128 bytes */ 933 memset(&rbdr_cfg, 0, sizeof(struct rbdr_cfg)); 934 rbdr_cfg.ena = 1; 935 rbdr_cfg.reset = 0; 936 rbdr_cfg.ldwb = 0; 937 rbdr_cfg.qsize = RBDR_SIZE; 938 rbdr_cfg.avg_con = 0; 939 rbdr_cfg.lines = rbdr->dma_size / 128; 940 nicvf_queue_reg_write(nic, NIC_QSET_RBDR_0_1_CFG, 941 qidx, *(u64 *)&rbdr_cfg); 942 943 /* Notify HW */ 944 nicvf_queue_reg_write(nic, NIC_QSET_RBDR_0_1_DOOR, 945 qidx, qs->rbdr_len - 1); 946 947 /* Set threshold value for interrupt generation */ 948 nicvf_queue_reg_write(nic, NIC_QSET_RBDR_0_1_THRESH, 949 qidx, rbdr->thresh - 1); 950 } 951 952 /* Requests PF to assign and enable Qset */ 953 void nicvf_qset_config(struct nicvf *nic, bool enable) 954 { 955 union nic_mbx mbx = {}; 956 struct queue_set *qs = nic->qs; 957 struct qs_cfg *qs_cfg; 958 959 if (!qs) { 960 netdev_warn(nic->netdev, 961 "Qset is still not allocated, don't init queues\n"); 962 return; 963 } 964 965 qs->enable = enable; 966 qs->vnic_id = nic->vf_id; 967 968 /* Send a mailbox msg to PF to config Qset */ 969 mbx.qs.msg = NIC_MBOX_MSG_QS_CFG; 970 mbx.qs.num = qs->vnic_id; 971 mbx.qs.sqs_count = nic->sqs_count; 972 973 mbx.qs.cfg = 0; 974 qs_cfg = (struct qs_cfg *)&mbx.qs.cfg; 975 if (qs->enable) { 976 qs_cfg->ena = 1; 977 #ifdef __BIG_ENDIAN 978 qs_cfg->be = 1; 979 #endif 980 qs_cfg->vnic = qs->vnic_id; 981 } 982 nicvf_send_msg_to_pf(nic, &mbx); 983 } 984 985 static void nicvf_free_resources(struct nicvf *nic) 986 { 987 int qidx; 988 struct queue_set *qs = nic->qs; 989 990 /* Free receive buffer descriptor ring */ 991 for (qidx = 0; qidx < qs->rbdr_cnt; qidx++) 992 nicvf_free_rbdr(nic, &qs->rbdr[qidx]); 993 994 /* Free completion queue */ 995 for (qidx = 0; qidx < qs->cq_cnt; qidx++) 996 nicvf_free_cmp_queue(nic, &qs->cq[qidx]); 997 998 /* Free send queue */ 999 for (qidx = 0; qidx < qs->sq_cnt; qidx++) 1000 nicvf_free_snd_queue(nic, &qs->sq[qidx]); 1001 } 1002 1003 static int nicvf_alloc_resources(struct nicvf *nic) 1004 { 1005 int qidx; 1006 struct queue_set *qs = nic->qs; 1007 1008 /* Alloc receive buffer descriptor ring */ 1009 for (qidx = 0; qidx < qs->rbdr_cnt; qidx++) { 1010 if (nicvf_init_rbdr(nic, &qs->rbdr[qidx], qs->rbdr_len, 1011 DMA_BUFFER_LEN)) 1012 goto alloc_fail; 1013 } 1014 1015 /* Alloc send queue */ 1016 for (qidx = 0; qidx < qs->sq_cnt; qidx++) { 1017 if (nicvf_init_snd_queue(nic, &qs->sq[qidx], qs->sq_len, qidx)) 1018 goto alloc_fail; 1019 } 1020 1021 /* Alloc completion queue */ 1022 for (qidx = 0; qidx < qs->cq_cnt; qidx++) { 1023 if (nicvf_init_cmp_queue(nic, &qs->cq[qidx], qs->cq_len)) 1024 goto alloc_fail; 1025 } 1026 1027 return 0; 1028 alloc_fail: 1029 nicvf_free_resources(nic); 1030 return -ENOMEM; 1031 } 1032 1033 int nicvf_set_qset_resources(struct nicvf *nic) 1034 { 1035 struct queue_set *qs; 1036 1037 qs = devm_kzalloc(&nic->pdev->dev, sizeof(*qs), GFP_KERNEL); 1038 if (!qs) 1039 return -ENOMEM; 1040 nic->qs = qs; 1041 1042 /* Set count of each queue */ 1043 qs->rbdr_cnt = DEFAULT_RBDR_CNT; 1044 qs->rq_cnt = min_t(u8, MAX_RCV_QUEUES_PER_QS, num_online_cpus()); 1045 qs->sq_cnt = min_t(u8, MAX_SND_QUEUES_PER_QS, num_online_cpus()); 1046 qs->cq_cnt = max_t(u8, qs->rq_cnt, qs->sq_cnt); 1047 1048 /* Set queue lengths */ 1049 qs->rbdr_len = RCV_BUF_COUNT; 1050 qs->sq_len = SND_QUEUE_LEN; 1051 qs->cq_len = CMP_QUEUE_LEN; 1052 1053 nic->rx_queues = qs->rq_cnt; 1054 nic->tx_queues = qs->sq_cnt; 1055 nic->xdp_tx_queues = 0; 1056 1057 return 0; 1058 } 1059 1060 int nicvf_config_data_transfer(struct nicvf *nic, bool enable) 1061 { 1062 bool disable = false; 1063 struct queue_set *qs = nic->qs; 1064 struct queue_set *pqs = nic->pnicvf->qs; 1065 int qidx; 1066 1067 if (!qs) 1068 return 0; 1069 1070 /* Take primary VF's queue lengths. 1071 * This is needed to take queue lengths set from ethtool 1072 * into consideration. 1073 */ 1074 if (nic->sqs_mode && pqs) { 1075 qs->cq_len = pqs->cq_len; 1076 qs->sq_len = pqs->sq_len; 1077 } 1078 1079 if (enable) { 1080 if (nicvf_alloc_resources(nic)) 1081 return -ENOMEM; 1082 1083 for (qidx = 0; qidx < qs->sq_cnt; qidx++) 1084 nicvf_snd_queue_config(nic, qs, qidx, enable); 1085 for (qidx = 0; qidx < qs->cq_cnt; qidx++) 1086 nicvf_cmp_queue_config(nic, qs, qidx, enable); 1087 for (qidx = 0; qidx < qs->rbdr_cnt; qidx++) 1088 nicvf_rbdr_config(nic, qs, qidx, enable); 1089 for (qidx = 0; qidx < qs->rq_cnt; qidx++) 1090 nicvf_rcv_queue_config(nic, qs, qidx, enable); 1091 } else { 1092 for (qidx = 0; qidx < qs->rq_cnt; qidx++) 1093 nicvf_rcv_queue_config(nic, qs, qidx, disable); 1094 for (qidx = 0; qidx < qs->rbdr_cnt; qidx++) 1095 nicvf_rbdr_config(nic, qs, qidx, disable); 1096 for (qidx = 0; qidx < qs->sq_cnt; qidx++) 1097 nicvf_snd_queue_config(nic, qs, qidx, disable); 1098 for (qidx = 0; qidx < qs->cq_cnt; qidx++) 1099 nicvf_cmp_queue_config(nic, qs, qidx, disable); 1100 1101 nicvf_free_resources(nic); 1102 } 1103 1104 /* Reset RXQ's stats. 1105 * SQ's stats will get reset automatically once SQ is reset. 1106 */ 1107 nicvf_reset_rcv_queue_stats(nic); 1108 1109 return 0; 1110 } 1111 1112 /* Get a free desc from SQ 1113 * returns descriptor ponter & descriptor number 1114 */ 1115 static inline int nicvf_get_sq_desc(struct snd_queue *sq, int desc_cnt) 1116 { 1117 int qentry; 1118 1119 qentry = sq->tail; 1120 if (!sq->is_xdp) 1121 atomic_sub(desc_cnt, &sq->free_cnt); 1122 else 1123 sq->xdp_free_cnt -= desc_cnt; 1124 sq->tail += desc_cnt; 1125 sq->tail &= (sq->dmem.q_len - 1); 1126 1127 return qentry; 1128 } 1129 1130 /* Rollback to previous tail pointer when descriptors not used */ 1131 static inline void nicvf_rollback_sq_desc(struct snd_queue *sq, 1132 int qentry, int desc_cnt) 1133 { 1134 sq->tail = qentry; 1135 atomic_add(desc_cnt, &sq->free_cnt); 1136 } 1137 1138 /* Free descriptor back to SQ for future use */ 1139 void nicvf_put_sq_desc(struct snd_queue *sq, int desc_cnt) 1140 { 1141 if (!sq->is_xdp) 1142 atomic_add(desc_cnt, &sq->free_cnt); 1143 else 1144 sq->xdp_free_cnt += desc_cnt; 1145 sq->head += desc_cnt; 1146 sq->head &= (sq->dmem.q_len - 1); 1147 } 1148 1149 static inline int nicvf_get_nxt_sqentry(struct snd_queue *sq, int qentry) 1150 { 1151 qentry++; 1152 qentry &= (sq->dmem.q_len - 1); 1153 return qentry; 1154 } 1155 1156 void nicvf_sq_enable(struct nicvf *nic, struct snd_queue *sq, int qidx) 1157 { 1158 u64 sq_cfg; 1159 1160 sq_cfg = nicvf_queue_reg_read(nic, NIC_QSET_SQ_0_7_CFG, qidx); 1161 sq_cfg |= NICVF_SQ_EN; 1162 nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_CFG, qidx, sq_cfg); 1163 /* Ring doorbell so that H/W restarts processing SQEs */ 1164 nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_DOOR, qidx, 0); 1165 } 1166 1167 void nicvf_sq_disable(struct nicvf *nic, int qidx) 1168 { 1169 u64 sq_cfg; 1170 1171 sq_cfg = nicvf_queue_reg_read(nic, NIC_QSET_SQ_0_7_CFG, qidx); 1172 sq_cfg &= ~NICVF_SQ_EN; 1173 nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_CFG, qidx, sq_cfg); 1174 } 1175 1176 void nicvf_sq_free_used_descs(struct net_device *netdev, struct snd_queue *sq, 1177 int qidx) 1178 { 1179 u64 head, tail; 1180 struct sk_buff *skb; 1181 struct nicvf *nic = netdev_priv(netdev); 1182 struct sq_hdr_subdesc *hdr; 1183 1184 head = nicvf_queue_reg_read(nic, NIC_QSET_SQ_0_7_HEAD, qidx) >> 4; 1185 tail = nicvf_queue_reg_read(nic, NIC_QSET_SQ_0_7_TAIL, qidx) >> 4; 1186 while (sq->head != head) { 1187 hdr = (struct sq_hdr_subdesc *)GET_SQ_DESC(sq, sq->head); 1188 if (hdr->subdesc_type != SQ_DESC_TYPE_HEADER) { 1189 nicvf_put_sq_desc(sq, 1); 1190 continue; 1191 } 1192 skb = (struct sk_buff *)sq->skbuff[sq->head]; 1193 if (skb) 1194 dev_kfree_skb_any(skb); 1195 atomic64_add(1, (atomic64_t *)&netdev->stats.tx_packets); 1196 atomic64_add(hdr->tot_len, 1197 (atomic64_t *)&netdev->stats.tx_bytes); 1198 nicvf_put_sq_desc(sq, hdr->subdesc_cnt + 1); 1199 } 1200 } 1201 1202 /* XDP Transmit APIs */ 1203 void nicvf_xdp_sq_doorbell(struct nicvf *nic, 1204 struct snd_queue *sq, int sq_num) 1205 { 1206 if (!sq->xdp_desc_cnt) 1207 return; 1208 1209 /* make sure all memory stores are done before ringing doorbell */ 1210 wmb(); 1211 1212 /* Inform HW to xmit all TSO segments */ 1213 nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_DOOR, 1214 sq_num, sq->xdp_desc_cnt); 1215 sq->xdp_desc_cnt = 0; 1216 } 1217 1218 static inline void 1219 nicvf_xdp_sq_add_hdr_subdesc(struct snd_queue *sq, int qentry, 1220 int subdesc_cnt, u64 data, int len) 1221 { 1222 struct sq_hdr_subdesc *hdr; 1223 1224 hdr = (struct sq_hdr_subdesc *)GET_SQ_DESC(sq, qentry); 1225 memset(hdr, 0, SND_QUEUE_DESC_SIZE); 1226 hdr->subdesc_type = SQ_DESC_TYPE_HEADER; 1227 hdr->subdesc_cnt = subdesc_cnt; 1228 hdr->tot_len = len; 1229 hdr->post_cqe = 1; 1230 sq->xdp_page[qentry] = (u64)virt_to_page((void *)data); 1231 } 1232 1233 int nicvf_xdp_sq_append_pkt(struct nicvf *nic, struct snd_queue *sq, 1234 u64 bufaddr, u64 dma_addr, u16 len) 1235 { 1236 int subdesc_cnt = MIN_SQ_DESC_PER_PKT_XMIT; 1237 int qentry; 1238 1239 if (subdesc_cnt > sq->xdp_free_cnt) 1240 return -1; 1241 1242 qentry = nicvf_get_sq_desc(sq, subdesc_cnt); 1243 1244 nicvf_xdp_sq_add_hdr_subdesc(sq, qentry, subdesc_cnt - 1, bufaddr, len); 1245 1246 qentry = nicvf_get_nxt_sqentry(sq, qentry); 1247 nicvf_sq_add_gather_subdesc(sq, qentry, len, dma_addr); 1248 1249 sq->xdp_desc_cnt += subdesc_cnt; 1250 1251 return 0; 1252 } 1253 1254 /* Calculate no of SQ subdescriptors needed to transmit all 1255 * segments of this TSO packet. 1256 * Taken from 'Tilera network driver' with a minor modification. 1257 */ 1258 static int nicvf_tso_count_subdescs(struct sk_buff *skb) 1259 { 1260 struct skb_shared_info *sh = skb_shinfo(skb); 1261 unsigned int sh_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 1262 unsigned int data_len = skb->len - sh_len; 1263 unsigned int p_len = sh->gso_size; 1264 long f_id = -1; /* id of the current fragment */ 1265 long f_size = skb_headlen(skb) - sh_len; /* current fragment size */ 1266 long f_used = 0; /* bytes used from the current fragment */ 1267 long n; /* size of the current piece of payload */ 1268 int num_edescs = 0; 1269 int segment; 1270 1271 for (segment = 0; segment < sh->gso_segs; segment++) { 1272 unsigned int p_used = 0; 1273 1274 /* One edesc for header and for each piece of the payload. */ 1275 for (num_edescs++; p_used < p_len; num_edescs++) { 1276 /* Advance as needed. */ 1277 while (f_used >= f_size) { 1278 f_id++; 1279 f_size = skb_frag_size(&sh->frags[f_id]); 1280 f_used = 0; 1281 } 1282 1283 /* Use bytes from the current fragment. */ 1284 n = p_len - p_used; 1285 if (n > f_size - f_used) 1286 n = f_size - f_used; 1287 f_used += n; 1288 p_used += n; 1289 } 1290 1291 /* The last segment may be less than gso_size. */ 1292 data_len -= p_len; 1293 if (data_len < p_len) 1294 p_len = data_len; 1295 } 1296 1297 /* '+ gso_segs' for SQ_HDR_SUDESCs for each segment */ 1298 return num_edescs + sh->gso_segs; 1299 } 1300 1301 #define POST_CQE_DESC_COUNT 2 1302 1303 /* Get the number of SQ descriptors needed to xmit this skb */ 1304 static int nicvf_sq_subdesc_required(struct nicvf *nic, struct sk_buff *skb) 1305 { 1306 int subdesc_cnt = MIN_SQ_DESC_PER_PKT_XMIT; 1307 1308 if (skb_shinfo(skb)->gso_size && !nic->hw_tso) { 1309 subdesc_cnt = nicvf_tso_count_subdescs(skb); 1310 return subdesc_cnt; 1311 } 1312 1313 /* Dummy descriptors to get TSO pkt completion notification */ 1314 if (nic->t88 && nic->hw_tso && skb_shinfo(skb)->gso_size) 1315 subdesc_cnt += POST_CQE_DESC_COUNT; 1316 1317 if (skb_shinfo(skb)->nr_frags) 1318 subdesc_cnt += skb_shinfo(skb)->nr_frags; 1319 1320 return subdesc_cnt; 1321 } 1322 1323 /* Add SQ HEADER subdescriptor. 1324 * First subdescriptor for every send descriptor. 1325 */ 1326 static inline void 1327 nicvf_sq_add_hdr_subdesc(struct nicvf *nic, struct snd_queue *sq, int qentry, 1328 int subdesc_cnt, struct sk_buff *skb, int len) 1329 { 1330 int proto; 1331 struct sq_hdr_subdesc *hdr; 1332 union { 1333 struct iphdr *v4; 1334 struct ipv6hdr *v6; 1335 unsigned char *hdr; 1336 } ip; 1337 1338 ip.hdr = skb_network_header(skb); 1339 hdr = (struct sq_hdr_subdesc *)GET_SQ_DESC(sq, qentry); 1340 memset(hdr, 0, SND_QUEUE_DESC_SIZE); 1341 hdr->subdesc_type = SQ_DESC_TYPE_HEADER; 1342 1343 if (nic->t88 && nic->hw_tso && skb_shinfo(skb)->gso_size) { 1344 /* post_cqe = 0, to avoid HW posting a CQE for every TSO 1345 * segment transmitted on 88xx. 1346 */ 1347 hdr->subdesc_cnt = subdesc_cnt - POST_CQE_DESC_COUNT; 1348 } else { 1349 sq->skbuff[qentry] = (u64)skb; 1350 /* Enable notification via CQE after processing SQE */ 1351 hdr->post_cqe = 1; 1352 /* No of subdescriptors following this */ 1353 hdr->subdesc_cnt = subdesc_cnt; 1354 } 1355 hdr->tot_len = len; 1356 1357 /* Offload checksum calculation to HW */ 1358 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1359 if (ip.v4->version == 4) 1360 hdr->csum_l3 = 1; /* Enable IP csum calculation */ 1361 hdr->l3_offset = skb_network_offset(skb); 1362 hdr->l4_offset = skb_transport_offset(skb); 1363 1364 proto = (ip.v4->version == 4) ? ip.v4->protocol : 1365 ip.v6->nexthdr; 1366 1367 switch (proto) { 1368 case IPPROTO_TCP: 1369 hdr->csum_l4 = SEND_L4_CSUM_TCP; 1370 break; 1371 case IPPROTO_UDP: 1372 hdr->csum_l4 = SEND_L4_CSUM_UDP; 1373 break; 1374 case IPPROTO_SCTP: 1375 hdr->csum_l4 = SEND_L4_CSUM_SCTP; 1376 break; 1377 } 1378 } 1379 1380 if (nic->hw_tso && skb_shinfo(skb)->gso_size) { 1381 hdr->tso = 1; 1382 hdr->tso_start = skb_transport_offset(skb) + tcp_hdrlen(skb); 1383 hdr->tso_max_paysize = skb_shinfo(skb)->gso_size; 1384 /* For non-tunneled pkts, point this to L2 ethertype */ 1385 hdr->inner_l3_offset = skb_network_offset(skb) - 2; 1386 this_cpu_inc(nic->pnicvf->drv_stats->tx_tso); 1387 } 1388 } 1389 1390 /* SQ GATHER subdescriptor 1391 * Must follow HDR descriptor 1392 */ 1393 static inline void nicvf_sq_add_gather_subdesc(struct snd_queue *sq, int qentry, 1394 int size, u64 data) 1395 { 1396 struct sq_gather_subdesc *gather; 1397 1398 qentry &= (sq->dmem.q_len - 1); 1399 gather = (struct sq_gather_subdesc *)GET_SQ_DESC(sq, qentry); 1400 1401 memset(gather, 0, SND_QUEUE_DESC_SIZE); 1402 gather->subdesc_type = SQ_DESC_TYPE_GATHER; 1403 gather->ld_type = NIC_SEND_LD_TYPE_E_LDD; 1404 gather->size = size; 1405 gather->addr = data; 1406 } 1407 1408 /* Add HDR + IMMEDIATE subdescriptors right after descriptors of a TSO 1409 * packet so that a CQE is posted as a notifation for transmission of 1410 * TSO packet. 1411 */ 1412 static inline void nicvf_sq_add_cqe_subdesc(struct snd_queue *sq, int qentry, 1413 int tso_sqe, struct sk_buff *skb) 1414 { 1415 struct sq_imm_subdesc *imm; 1416 struct sq_hdr_subdesc *hdr; 1417 1418 sq->skbuff[qentry] = (u64)skb; 1419 1420 hdr = (struct sq_hdr_subdesc *)GET_SQ_DESC(sq, qentry); 1421 memset(hdr, 0, SND_QUEUE_DESC_SIZE); 1422 hdr->subdesc_type = SQ_DESC_TYPE_HEADER; 1423 /* Enable notification via CQE after processing SQE */ 1424 hdr->post_cqe = 1; 1425 /* There is no packet to transmit here */ 1426 hdr->dont_send = 1; 1427 hdr->subdesc_cnt = POST_CQE_DESC_COUNT - 1; 1428 hdr->tot_len = 1; 1429 /* Actual TSO header SQE index, needed for cleanup */ 1430 hdr->rsvd2 = tso_sqe; 1431 1432 qentry = nicvf_get_nxt_sqentry(sq, qentry); 1433 imm = (struct sq_imm_subdesc *)GET_SQ_DESC(sq, qentry); 1434 memset(imm, 0, SND_QUEUE_DESC_SIZE); 1435 imm->subdesc_type = SQ_DESC_TYPE_IMMEDIATE; 1436 imm->len = 1; 1437 } 1438 1439 static inline void nicvf_sq_doorbell(struct nicvf *nic, struct sk_buff *skb, 1440 int sq_num, int desc_cnt) 1441 { 1442 struct netdev_queue *txq; 1443 1444 txq = netdev_get_tx_queue(nic->pnicvf->netdev, 1445 skb_get_queue_mapping(skb)); 1446 1447 netdev_tx_sent_queue(txq, skb->len); 1448 1449 /* make sure all memory stores are done before ringing doorbell */ 1450 smp_wmb(); 1451 1452 /* Inform HW to xmit all TSO segments */ 1453 nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_DOOR, 1454 sq_num, desc_cnt); 1455 } 1456 1457 /* Segment a TSO packet into 'gso_size' segments and append 1458 * them to SQ for transfer 1459 */ 1460 static int nicvf_sq_append_tso(struct nicvf *nic, struct snd_queue *sq, 1461 int sq_num, int qentry, struct sk_buff *skb) 1462 { 1463 struct tso_t tso; 1464 int seg_subdescs = 0, desc_cnt = 0; 1465 int seg_len, total_len, data_left; 1466 int hdr_qentry = qentry; 1467 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 1468 1469 tso_start(skb, &tso); 1470 total_len = skb->len - hdr_len; 1471 while (total_len > 0) { 1472 char *hdr; 1473 1474 /* Save Qentry for adding HDR_SUBDESC at the end */ 1475 hdr_qentry = qentry; 1476 1477 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); 1478 total_len -= data_left; 1479 1480 /* Add segment's header */ 1481 qentry = nicvf_get_nxt_sqentry(sq, qentry); 1482 hdr = sq->tso_hdrs + qentry * TSO_HEADER_SIZE; 1483 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); 1484 nicvf_sq_add_gather_subdesc(sq, qentry, hdr_len, 1485 sq->tso_hdrs_phys + 1486 qentry * TSO_HEADER_SIZE); 1487 /* HDR_SUDESC + GATHER */ 1488 seg_subdescs = 2; 1489 seg_len = hdr_len; 1490 1491 /* Add segment's payload fragments */ 1492 while (data_left > 0) { 1493 int size; 1494 1495 size = min_t(int, tso.size, data_left); 1496 1497 qentry = nicvf_get_nxt_sqentry(sq, qentry); 1498 nicvf_sq_add_gather_subdesc(sq, qentry, size, 1499 virt_to_phys(tso.data)); 1500 seg_subdescs++; 1501 seg_len += size; 1502 1503 data_left -= size; 1504 tso_build_data(skb, &tso, size); 1505 } 1506 nicvf_sq_add_hdr_subdesc(nic, sq, hdr_qentry, 1507 seg_subdescs - 1, skb, seg_len); 1508 sq->skbuff[hdr_qentry] = (u64)NULL; 1509 qentry = nicvf_get_nxt_sqentry(sq, qentry); 1510 1511 desc_cnt += seg_subdescs; 1512 } 1513 /* Save SKB in the last segment for freeing */ 1514 sq->skbuff[hdr_qentry] = (u64)skb; 1515 1516 nicvf_sq_doorbell(nic, skb, sq_num, desc_cnt); 1517 1518 this_cpu_inc(nic->pnicvf->drv_stats->tx_tso); 1519 return 1; 1520 } 1521 1522 /* Append an skb to a SQ for packet transfer. */ 1523 int nicvf_sq_append_skb(struct nicvf *nic, struct snd_queue *sq, 1524 struct sk_buff *skb, u8 sq_num) 1525 { 1526 int i, size; 1527 int subdesc_cnt, hdr_sqe = 0; 1528 int qentry; 1529 u64 dma_addr; 1530 1531 subdesc_cnt = nicvf_sq_subdesc_required(nic, skb); 1532 if (subdesc_cnt > atomic_read(&sq->free_cnt)) 1533 goto append_fail; 1534 1535 qentry = nicvf_get_sq_desc(sq, subdesc_cnt); 1536 1537 /* Check if its a TSO packet */ 1538 if (skb_shinfo(skb)->gso_size && !nic->hw_tso) 1539 return nicvf_sq_append_tso(nic, sq, sq_num, qentry, skb); 1540 1541 /* Add SQ header subdesc */ 1542 nicvf_sq_add_hdr_subdesc(nic, sq, qentry, subdesc_cnt - 1, 1543 skb, skb->len); 1544 hdr_sqe = qentry; 1545 1546 /* Add SQ gather subdescs */ 1547 qentry = nicvf_get_nxt_sqentry(sq, qentry); 1548 size = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len; 1549 /* HW will ensure data coherency, CPU sync not required */ 1550 dma_addr = dma_map_page_attrs(&nic->pdev->dev, virt_to_page(skb->data), 1551 offset_in_page(skb->data), size, 1552 DMA_TO_DEVICE, DMA_ATTR_SKIP_CPU_SYNC); 1553 if (dma_mapping_error(&nic->pdev->dev, dma_addr)) { 1554 nicvf_rollback_sq_desc(sq, qentry, subdesc_cnt); 1555 return 0; 1556 } 1557 1558 nicvf_sq_add_gather_subdesc(sq, qentry, size, dma_addr); 1559 1560 /* Check for scattered buffer */ 1561 if (!skb_is_nonlinear(skb)) 1562 goto doorbell; 1563 1564 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1565 const struct skb_frag_struct *frag; 1566 1567 frag = &skb_shinfo(skb)->frags[i]; 1568 1569 qentry = nicvf_get_nxt_sqentry(sq, qentry); 1570 size = skb_frag_size(frag); 1571 dma_addr = dma_map_page_attrs(&nic->pdev->dev, 1572 skb_frag_page(frag), 1573 frag->page_offset, size, 1574 DMA_TO_DEVICE, 1575 DMA_ATTR_SKIP_CPU_SYNC); 1576 if (dma_mapping_error(&nic->pdev->dev, dma_addr)) { 1577 /* Free entire chain of mapped buffers 1578 * here 'i' = frags mapped + above mapped skb->data 1579 */ 1580 nicvf_unmap_sndq_buffers(nic, sq, hdr_sqe, i); 1581 nicvf_rollback_sq_desc(sq, qentry, subdesc_cnt); 1582 return 0; 1583 } 1584 nicvf_sq_add_gather_subdesc(sq, qentry, size, dma_addr); 1585 } 1586 1587 doorbell: 1588 if (nic->t88 && skb_shinfo(skb)->gso_size) { 1589 qentry = nicvf_get_nxt_sqentry(sq, qentry); 1590 nicvf_sq_add_cqe_subdesc(sq, qentry, hdr_sqe, skb); 1591 } 1592 1593 nicvf_sq_doorbell(nic, skb, sq_num, subdesc_cnt); 1594 1595 return 1; 1596 1597 append_fail: 1598 /* Use original PCI dev for debug log */ 1599 nic = nic->pnicvf; 1600 netdev_dbg(nic->netdev, "Not enough SQ descriptors to xmit pkt\n"); 1601 return 0; 1602 } 1603 1604 static inline unsigned frag_num(unsigned i) 1605 { 1606 #ifdef __BIG_ENDIAN 1607 return (i & ~3) + 3 - (i & 3); 1608 #else 1609 return i; 1610 #endif 1611 } 1612 1613 static void nicvf_unmap_rcv_buffer(struct nicvf *nic, u64 dma_addr, 1614 u64 buf_addr, bool xdp) 1615 { 1616 struct page *page = NULL; 1617 int len = RCV_FRAG_LEN; 1618 1619 if (xdp) { 1620 page = virt_to_page(phys_to_virt(buf_addr)); 1621 /* Check if it's a recycled page, if not 1622 * unmap the DMA mapping. 1623 * 1624 * Recycled page holds an extra reference. 1625 */ 1626 if (page_ref_count(page) != 1) 1627 return; 1628 1629 len += XDP_HEADROOM; 1630 /* Receive buffers in XDP mode are mapped from page start */ 1631 dma_addr &= PAGE_MASK; 1632 } 1633 dma_unmap_page_attrs(&nic->pdev->dev, dma_addr, len, 1634 DMA_FROM_DEVICE, DMA_ATTR_SKIP_CPU_SYNC); 1635 } 1636 1637 /* Returns SKB for a received packet */ 1638 struct sk_buff *nicvf_get_rcv_skb(struct nicvf *nic, 1639 struct cqe_rx_t *cqe_rx, bool xdp) 1640 { 1641 int frag; 1642 int payload_len = 0; 1643 struct sk_buff *skb = NULL; 1644 struct page *page; 1645 int offset; 1646 u16 *rb_lens = NULL; 1647 u64 *rb_ptrs = NULL; 1648 u64 phys_addr; 1649 1650 rb_lens = (void *)cqe_rx + (3 * sizeof(u64)); 1651 /* Except 88xx pass1 on all other chips CQE_RX2_S is added to 1652 * CQE_RX at word6, hence buffer pointers move by word 1653 * 1654 * Use existing 'hw_tso' flag which will be set for all chips 1655 * except 88xx pass1 instead of a additional cache line 1656 * access (or miss) by using pci dev's revision. 1657 */ 1658 if (!nic->hw_tso) 1659 rb_ptrs = (void *)cqe_rx + (6 * sizeof(u64)); 1660 else 1661 rb_ptrs = (void *)cqe_rx + (7 * sizeof(u64)); 1662 1663 for (frag = 0; frag < cqe_rx->rb_cnt; frag++) { 1664 payload_len = rb_lens[frag_num(frag)]; 1665 phys_addr = nicvf_iova_to_phys(nic, *rb_ptrs); 1666 if (!phys_addr) { 1667 if (skb) 1668 dev_kfree_skb_any(skb); 1669 return NULL; 1670 } 1671 1672 if (!frag) { 1673 /* First fragment */ 1674 nicvf_unmap_rcv_buffer(nic, 1675 *rb_ptrs - cqe_rx->align_pad, 1676 phys_addr, xdp); 1677 skb = nicvf_rb_ptr_to_skb(nic, 1678 phys_addr - cqe_rx->align_pad, 1679 payload_len); 1680 if (!skb) 1681 return NULL; 1682 skb_reserve(skb, cqe_rx->align_pad); 1683 skb_put(skb, payload_len); 1684 } else { 1685 /* Add fragments */ 1686 nicvf_unmap_rcv_buffer(nic, *rb_ptrs, phys_addr, xdp); 1687 page = virt_to_page(phys_to_virt(phys_addr)); 1688 offset = phys_to_virt(phys_addr) - page_address(page); 1689 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page, 1690 offset, payload_len, RCV_FRAG_LEN); 1691 } 1692 /* Next buffer pointer */ 1693 rb_ptrs++; 1694 } 1695 return skb; 1696 } 1697 1698 static u64 nicvf_int_type_to_mask(int int_type, int q_idx) 1699 { 1700 u64 reg_val; 1701 1702 switch (int_type) { 1703 case NICVF_INTR_CQ: 1704 reg_val = ((1ULL << q_idx) << NICVF_INTR_CQ_SHIFT); 1705 break; 1706 case NICVF_INTR_SQ: 1707 reg_val = ((1ULL << q_idx) << NICVF_INTR_SQ_SHIFT); 1708 break; 1709 case NICVF_INTR_RBDR: 1710 reg_val = ((1ULL << q_idx) << NICVF_INTR_RBDR_SHIFT); 1711 break; 1712 case NICVF_INTR_PKT_DROP: 1713 reg_val = (1ULL << NICVF_INTR_PKT_DROP_SHIFT); 1714 break; 1715 case NICVF_INTR_TCP_TIMER: 1716 reg_val = (1ULL << NICVF_INTR_TCP_TIMER_SHIFT); 1717 break; 1718 case NICVF_INTR_MBOX: 1719 reg_val = (1ULL << NICVF_INTR_MBOX_SHIFT); 1720 break; 1721 case NICVF_INTR_QS_ERR: 1722 reg_val = (1ULL << NICVF_INTR_QS_ERR_SHIFT); 1723 break; 1724 default: 1725 reg_val = 0; 1726 } 1727 1728 return reg_val; 1729 } 1730 1731 /* Enable interrupt */ 1732 void nicvf_enable_intr(struct nicvf *nic, int int_type, int q_idx) 1733 { 1734 u64 mask = nicvf_int_type_to_mask(int_type, q_idx); 1735 1736 if (!mask) { 1737 netdev_dbg(nic->netdev, 1738 "Failed to enable interrupt: unknown type\n"); 1739 return; 1740 } 1741 nicvf_reg_write(nic, NIC_VF_ENA_W1S, 1742 nicvf_reg_read(nic, NIC_VF_ENA_W1S) | mask); 1743 } 1744 1745 /* Disable interrupt */ 1746 void nicvf_disable_intr(struct nicvf *nic, int int_type, int q_idx) 1747 { 1748 u64 mask = nicvf_int_type_to_mask(int_type, q_idx); 1749 1750 if (!mask) { 1751 netdev_dbg(nic->netdev, 1752 "Failed to disable interrupt: unknown type\n"); 1753 return; 1754 } 1755 1756 nicvf_reg_write(nic, NIC_VF_ENA_W1C, mask); 1757 } 1758 1759 /* Clear interrupt */ 1760 void nicvf_clear_intr(struct nicvf *nic, int int_type, int q_idx) 1761 { 1762 u64 mask = nicvf_int_type_to_mask(int_type, q_idx); 1763 1764 if (!mask) { 1765 netdev_dbg(nic->netdev, 1766 "Failed to clear interrupt: unknown type\n"); 1767 return; 1768 } 1769 1770 nicvf_reg_write(nic, NIC_VF_INT, mask); 1771 } 1772 1773 /* Check if interrupt is enabled */ 1774 int nicvf_is_intr_enabled(struct nicvf *nic, int int_type, int q_idx) 1775 { 1776 u64 mask = nicvf_int_type_to_mask(int_type, q_idx); 1777 /* If interrupt type is unknown, we treat it disabled. */ 1778 if (!mask) { 1779 netdev_dbg(nic->netdev, 1780 "Failed to check interrupt enable: unknown type\n"); 1781 return 0; 1782 } 1783 1784 return mask & nicvf_reg_read(nic, NIC_VF_ENA_W1S); 1785 } 1786 1787 void nicvf_update_rq_stats(struct nicvf *nic, int rq_idx) 1788 { 1789 struct rcv_queue *rq; 1790 1791 #define GET_RQ_STATS(reg) \ 1792 nicvf_reg_read(nic, NIC_QSET_RQ_0_7_STAT_0_1 |\ 1793 (rq_idx << NIC_Q_NUM_SHIFT) | (reg << 3)) 1794 1795 rq = &nic->qs->rq[rq_idx]; 1796 rq->stats.bytes = GET_RQ_STATS(RQ_SQ_STATS_OCTS); 1797 rq->stats.pkts = GET_RQ_STATS(RQ_SQ_STATS_PKTS); 1798 } 1799 1800 void nicvf_update_sq_stats(struct nicvf *nic, int sq_idx) 1801 { 1802 struct snd_queue *sq; 1803 1804 #define GET_SQ_STATS(reg) \ 1805 nicvf_reg_read(nic, NIC_QSET_SQ_0_7_STAT_0_1 |\ 1806 (sq_idx << NIC_Q_NUM_SHIFT) | (reg << 3)) 1807 1808 sq = &nic->qs->sq[sq_idx]; 1809 sq->stats.bytes = GET_SQ_STATS(RQ_SQ_STATS_OCTS); 1810 sq->stats.pkts = GET_SQ_STATS(RQ_SQ_STATS_PKTS); 1811 } 1812 1813 /* Check for errors in the receive cmp.queue entry */ 1814 int nicvf_check_cqe_rx_errs(struct nicvf *nic, struct cqe_rx_t *cqe_rx) 1815 { 1816 netif_err(nic, rx_err, nic->netdev, 1817 "RX error CQE err_level 0x%x err_opcode 0x%x\n", 1818 cqe_rx->err_level, cqe_rx->err_opcode); 1819 1820 switch (cqe_rx->err_opcode) { 1821 case CQ_RX_ERROP_RE_PARTIAL: 1822 this_cpu_inc(nic->drv_stats->rx_bgx_truncated_pkts); 1823 break; 1824 case CQ_RX_ERROP_RE_JABBER: 1825 this_cpu_inc(nic->drv_stats->rx_jabber_errs); 1826 break; 1827 case CQ_RX_ERROP_RE_FCS: 1828 this_cpu_inc(nic->drv_stats->rx_fcs_errs); 1829 break; 1830 case CQ_RX_ERROP_RE_RX_CTL: 1831 this_cpu_inc(nic->drv_stats->rx_bgx_errs); 1832 break; 1833 case CQ_RX_ERROP_PREL2_ERR: 1834 this_cpu_inc(nic->drv_stats->rx_prel2_errs); 1835 break; 1836 case CQ_RX_ERROP_L2_MAL: 1837 this_cpu_inc(nic->drv_stats->rx_l2_hdr_malformed); 1838 break; 1839 case CQ_RX_ERROP_L2_OVERSIZE: 1840 this_cpu_inc(nic->drv_stats->rx_oversize); 1841 break; 1842 case CQ_RX_ERROP_L2_UNDERSIZE: 1843 this_cpu_inc(nic->drv_stats->rx_undersize); 1844 break; 1845 case CQ_RX_ERROP_L2_LENMISM: 1846 this_cpu_inc(nic->drv_stats->rx_l2_len_mismatch); 1847 break; 1848 case CQ_RX_ERROP_L2_PCLP: 1849 this_cpu_inc(nic->drv_stats->rx_l2_pclp); 1850 break; 1851 case CQ_RX_ERROP_IP_NOT: 1852 this_cpu_inc(nic->drv_stats->rx_ip_ver_errs); 1853 break; 1854 case CQ_RX_ERROP_IP_CSUM_ERR: 1855 this_cpu_inc(nic->drv_stats->rx_ip_csum_errs); 1856 break; 1857 case CQ_RX_ERROP_IP_MAL: 1858 this_cpu_inc(nic->drv_stats->rx_ip_hdr_malformed); 1859 break; 1860 case CQ_RX_ERROP_IP_MALD: 1861 this_cpu_inc(nic->drv_stats->rx_ip_payload_malformed); 1862 break; 1863 case CQ_RX_ERROP_IP_HOP: 1864 this_cpu_inc(nic->drv_stats->rx_ip_ttl_errs); 1865 break; 1866 case CQ_RX_ERROP_L3_PCLP: 1867 this_cpu_inc(nic->drv_stats->rx_l3_pclp); 1868 break; 1869 case CQ_RX_ERROP_L4_MAL: 1870 this_cpu_inc(nic->drv_stats->rx_l4_malformed); 1871 break; 1872 case CQ_RX_ERROP_L4_CHK: 1873 this_cpu_inc(nic->drv_stats->rx_l4_csum_errs); 1874 break; 1875 case CQ_RX_ERROP_UDP_LEN: 1876 this_cpu_inc(nic->drv_stats->rx_udp_len_errs); 1877 break; 1878 case CQ_RX_ERROP_L4_PORT: 1879 this_cpu_inc(nic->drv_stats->rx_l4_port_errs); 1880 break; 1881 case CQ_RX_ERROP_TCP_FLAG: 1882 this_cpu_inc(nic->drv_stats->rx_tcp_flag_errs); 1883 break; 1884 case CQ_RX_ERROP_TCP_OFFSET: 1885 this_cpu_inc(nic->drv_stats->rx_tcp_offset_errs); 1886 break; 1887 case CQ_RX_ERROP_L4_PCLP: 1888 this_cpu_inc(nic->drv_stats->rx_l4_pclp); 1889 break; 1890 case CQ_RX_ERROP_RBDR_TRUNC: 1891 this_cpu_inc(nic->drv_stats->rx_truncated_pkts); 1892 break; 1893 } 1894 1895 return 1; 1896 } 1897 1898 /* Check for errors in the send cmp.queue entry */ 1899 int nicvf_check_cqe_tx_errs(struct nicvf *nic, struct cqe_send_t *cqe_tx) 1900 { 1901 switch (cqe_tx->send_status) { 1902 case CQ_TX_ERROP_DESC_FAULT: 1903 this_cpu_inc(nic->drv_stats->tx_desc_fault); 1904 break; 1905 case CQ_TX_ERROP_HDR_CONS_ERR: 1906 this_cpu_inc(nic->drv_stats->tx_hdr_cons_err); 1907 break; 1908 case CQ_TX_ERROP_SUBDC_ERR: 1909 this_cpu_inc(nic->drv_stats->tx_subdesc_err); 1910 break; 1911 case CQ_TX_ERROP_MAX_SIZE_VIOL: 1912 this_cpu_inc(nic->drv_stats->tx_max_size_exceeded); 1913 break; 1914 case CQ_TX_ERROP_IMM_SIZE_OFLOW: 1915 this_cpu_inc(nic->drv_stats->tx_imm_size_oflow); 1916 break; 1917 case CQ_TX_ERROP_DATA_SEQUENCE_ERR: 1918 this_cpu_inc(nic->drv_stats->tx_data_seq_err); 1919 break; 1920 case CQ_TX_ERROP_MEM_SEQUENCE_ERR: 1921 this_cpu_inc(nic->drv_stats->tx_mem_seq_err); 1922 break; 1923 case CQ_TX_ERROP_LOCK_VIOL: 1924 this_cpu_inc(nic->drv_stats->tx_lock_viol); 1925 break; 1926 case CQ_TX_ERROP_DATA_FAULT: 1927 this_cpu_inc(nic->drv_stats->tx_data_fault); 1928 break; 1929 case CQ_TX_ERROP_TSTMP_CONFLICT: 1930 this_cpu_inc(nic->drv_stats->tx_tstmp_conflict); 1931 break; 1932 case CQ_TX_ERROP_TSTMP_TIMEOUT: 1933 this_cpu_inc(nic->drv_stats->tx_tstmp_timeout); 1934 break; 1935 case CQ_TX_ERROP_MEM_FAULT: 1936 this_cpu_inc(nic->drv_stats->tx_mem_fault); 1937 break; 1938 case CQ_TX_ERROP_CK_OVERLAP: 1939 this_cpu_inc(nic->drv_stats->tx_csum_overlap); 1940 break; 1941 case CQ_TX_ERROP_CK_OFLOW: 1942 this_cpu_inc(nic->drv_stats->tx_csum_overflow); 1943 break; 1944 } 1945 1946 return 1; 1947 } 1948