1 /* 2 * Copyright (C) 2015 Cavium, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of version 2 of the GNU General Public License 6 * as published by the Free Software Foundation. 7 */ 8 9 #include <linux/module.h> 10 #include <linux/interrupt.h> 11 #include <linux/pci.h> 12 #include <linux/netdevice.h> 13 #include <linux/if_vlan.h> 14 #include <linux/etherdevice.h> 15 #include <linux/ethtool.h> 16 #include <linux/log2.h> 17 #include <linux/prefetch.h> 18 #include <linux/irq.h> 19 20 #include "nic_reg.h" 21 #include "nic.h" 22 #include "nicvf_queues.h" 23 #include "thunder_bgx.h" 24 25 #define DRV_NAME "thunder-nicvf" 26 #define DRV_VERSION "1.0" 27 28 /* Supported devices */ 29 static const struct pci_device_id nicvf_id_table[] = { 30 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, 31 PCI_DEVICE_ID_THUNDER_NIC_VF, 32 PCI_VENDOR_ID_CAVIUM, 33 PCI_SUBSYS_DEVID_88XX_NIC_VF) }, 34 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, 35 PCI_DEVICE_ID_THUNDER_PASS1_NIC_VF, 36 PCI_VENDOR_ID_CAVIUM, 37 PCI_SUBSYS_DEVID_88XX_PASS1_NIC_VF) }, 38 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, 39 PCI_DEVICE_ID_THUNDER_NIC_VF, 40 PCI_VENDOR_ID_CAVIUM, 41 PCI_SUBSYS_DEVID_81XX_NIC_VF) }, 42 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, 43 PCI_DEVICE_ID_THUNDER_NIC_VF, 44 PCI_VENDOR_ID_CAVIUM, 45 PCI_SUBSYS_DEVID_83XX_NIC_VF) }, 46 { 0, } /* end of table */ 47 }; 48 49 MODULE_AUTHOR("Sunil Goutham"); 50 MODULE_DESCRIPTION("Cavium Thunder NIC Virtual Function Driver"); 51 MODULE_LICENSE("GPL v2"); 52 MODULE_VERSION(DRV_VERSION); 53 MODULE_DEVICE_TABLE(pci, nicvf_id_table); 54 55 static int debug = 0x00; 56 module_param(debug, int, 0644); 57 MODULE_PARM_DESC(debug, "Debug message level bitmap"); 58 59 static int cpi_alg = CPI_ALG_NONE; 60 module_param(cpi_alg, int, S_IRUGO); 61 MODULE_PARM_DESC(cpi_alg, 62 "PFC algorithm (0=none, 1=VLAN, 2=VLAN16, 3=IP Diffserv)"); 63 64 static inline u8 nicvf_netdev_qidx(struct nicvf *nic, u8 qidx) 65 { 66 if (nic->sqs_mode) 67 return qidx + ((nic->sqs_id + 1) * MAX_CMP_QUEUES_PER_QS); 68 else 69 return qidx; 70 } 71 72 /* The Cavium ThunderX network controller can *only* be found in SoCs 73 * containing the ThunderX ARM64 CPU implementation. All accesses to the device 74 * registers on this platform are implicitly strongly ordered with respect 75 * to memory accesses. So writeq_relaxed() and readq_relaxed() are safe to use 76 * with no memory barriers in this driver. The readq()/writeq() functions add 77 * explicit ordering operation which in this case are redundant, and only 78 * add overhead. 79 */ 80 81 /* Register read/write APIs */ 82 void nicvf_reg_write(struct nicvf *nic, u64 offset, u64 val) 83 { 84 writeq_relaxed(val, nic->reg_base + offset); 85 } 86 87 u64 nicvf_reg_read(struct nicvf *nic, u64 offset) 88 { 89 return readq_relaxed(nic->reg_base + offset); 90 } 91 92 void nicvf_queue_reg_write(struct nicvf *nic, u64 offset, 93 u64 qidx, u64 val) 94 { 95 void __iomem *addr = nic->reg_base + offset; 96 97 writeq_relaxed(val, addr + (qidx << NIC_Q_NUM_SHIFT)); 98 } 99 100 u64 nicvf_queue_reg_read(struct nicvf *nic, u64 offset, u64 qidx) 101 { 102 void __iomem *addr = nic->reg_base + offset; 103 104 return readq_relaxed(addr + (qidx << NIC_Q_NUM_SHIFT)); 105 } 106 107 /* VF -> PF mailbox communication */ 108 static void nicvf_write_to_mbx(struct nicvf *nic, union nic_mbx *mbx) 109 { 110 u64 *msg = (u64 *)mbx; 111 112 nicvf_reg_write(nic, NIC_VF_PF_MAILBOX_0_1 + 0, msg[0]); 113 nicvf_reg_write(nic, NIC_VF_PF_MAILBOX_0_1 + 8, msg[1]); 114 } 115 116 int nicvf_send_msg_to_pf(struct nicvf *nic, union nic_mbx *mbx) 117 { 118 int timeout = NIC_MBOX_MSG_TIMEOUT; 119 int sleep = 10; 120 121 nic->pf_acked = false; 122 nic->pf_nacked = false; 123 124 nicvf_write_to_mbx(nic, mbx); 125 126 /* Wait for previous message to be acked, timeout 2sec */ 127 while (!nic->pf_acked) { 128 if (nic->pf_nacked) { 129 netdev_err(nic->netdev, 130 "PF NACK to mbox msg 0x%02x from VF%d\n", 131 (mbx->msg.msg & 0xFF), nic->vf_id); 132 return -EINVAL; 133 } 134 msleep(sleep); 135 if (nic->pf_acked) 136 break; 137 timeout -= sleep; 138 if (!timeout) { 139 netdev_err(nic->netdev, 140 "PF didn't ACK to mbox msg 0x%02x from VF%d\n", 141 (mbx->msg.msg & 0xFF), nic->vf_id); 142 return -EBUSY; 143 } 144 } 145 return 0; 146 } 147 148 /* Checks if VF is able to comminicate with PF 149 * and also gets the VNIC number this VF is associated to. 150 */ 151 static int nicvf_check_pf_ready(struct nicvf *nic) 152 { 153 union nic_mbx mbx = {}; 154 155 mbx.msg.msg = NIC_MBOX_MSG_READY; 156 if (nicvf_send_msg_to_pf(nic, &mbx)) { 157 netdev_err(nic->netdev, 158 "PF didn't respond to READY msg\n"); 159 return 0; 160 } 161 162 return 1; 163 } 164 165 static void nicvf_read_bgx_stats(struct nicvf *nic, struct bgx_stats_msg *bgx) 166 { 167 if (bgx->rx) 168 nic->bgx_stats.rx_stats[bgx->idx] = bgx->stats; 169 else 170 nic->bgx_stats.tx_stats[bgx->idx] = bgx->stats; 171 } 172 173 static void nicvf_handle_mbx_intr(struct nicvf *nic) 174 { 175 union nic_mbx mbx = {}; 176 u64 *mbx_data; 177 u64 mbx_addr; 178 int i; 179 180 mbx_addr = NIC_VF_PF_MAILBOX_0_1; 181 mbx_data = (u64 *)&mbx; 182 183 for (i = 0; i < NIC_PF_VF_MAILBOX_SIZE; i++) { 184 *mbx_data = nicvf_reg_read(nic, mbx_addr); 185 mbx_data++; 186 mbx_addr += sizeof(u64); 187 } 188 189 netdev_dbg(nic->netdev, "Mbox message: msg: 0x%x\n", mbx.msg.msg); 190 switch (mbx.msg.msg) { 191 case NIC_MBOX_MSG_READY: 192 nic->pf_acked = true; 193 nic->vf_id = mbx.nic_cfg.vf_id & 0x7F; 194 nic->tns_mode = mbx.nic_cfg.tns_mode & 0x7F; 195 nic->node = mbx.nic_cfg.node_id; 196 if (!nic->set_mac_pending) 197 ether_addr_copy(nic->netdev->dev_addr, 198 mbx.nic_cfg.mac_addr); 199 nic->sqs_mode = mbx.nic_cfg.sqs_mode; 200 nic->loopback_supported = mbx.nic_cfg.loopback_supported; 201 nic->link_up = false; 202 nic->duplex = 0; 203 nic->speed = 0; 204 break; 205 case NIC_MBOX_MSG_ACK: 206 nic->pf_acked = true; 207 break; 208 case NIC_MBOX_MSG_NACK: 209 nic->pf_nacked = true; 210 break; 211 case NIC_MBOX_MSG_RSS_SIZE: 212 nic->rss_info.rss_size = mbx.rss_size.ind_tbl_size; 213 nic->pf_acked = true; 214 break; 215 case NIC_MBOX_MSG_BGX_STATS: 216 nicvf_read_bgx_stats(nic, &mbx.bgx_stats); 217 nic->pf_acked = true; 218 break; 219 case NIC_MBOX_MSG_BGX_LINK_CHANGE: 220 nic->pf_acked = true; 221 nic->link_up = mbx.link_status.link_up; 222 nic->duplex = mbx.link_status.duplex; 223 nic->speed = mbx.link_status.speed; 224 nic->mac_type = mbx.link_status.mac_type; 225 if (nic->link_up) { 226 netdev_info(nic->netdev, "%s: Link is Up %d Mbps %s\n", 227 nic->netdev->name, nic->speed, 228 nic->duplex == DUPLEX_FULL ? 229 "Full duplex" : "Half duplex"); 230 netif_carrier_on(nic->netdev); 231 netif_tx_start_all_queues(nic->netdev); 232 } else { 233 netdev_info(nic->netdev, "%s: Link is Down\n", 234 nic->netdev->name); 235 netif_carrier_off(nic->netdev); 236 netif_tx_stop_all_queues(nic->netdev); 237 } 238 break; 239 case NIC_MBOX_MSG_ALLOC_SQS: 240 nic->sqs_count = mbx.sqs_alloc.qs_count; 241 nic->pf_acked = true; 242 break; 243 case NIC_MBOX_MSG_SNICVF_PTR: 244 /* Primary VF: make note of secondary VF's pointer 245 * to be used while packet transmission. 246 */ 247 nic->snicvf[mbx.nicvf.sqs_id] = 248 (struct nicvf *)mbx.nicvf.nicvf; 249 nic->pf_acked = true; 250 break; 251 case NIC_MBOX_MSG_PNICVF_PTR: 252 /* Secondary VF/Qset: make note of primary VF's pointer 253 * to be used while packet reception, to handover packet 254 * to primary VF's netdev. 255 */ 256 nic->pnicvf = (struct nicvf *)mbx.nicvf.nicvf; 257 nic->pf_acked = true; 258 break; 259 case NIC_MBOX_MSG_PFC: 260 nic->pfc.autoneg = mbx.pfc.autoneg; 261 nic->pfc.fc_rx = mbx.pfc.fc_rx; 262 nic->pfc.fc_tx = mbx.pfc.fc_tx; 263 nic->pf_acked = true; 264 break; 265 default: 266 netdev_err(nic->netdev, 267 "Invalid message from PF, msg 0x%x\n", mbx.msg.msg); 268 break; 269 } 270 nicvf_clear_intr(nic, NICVF_INTR_MBOX, 0); 271 } 272 273 static int nicvf_hw_set_mac_addr(struct nicvf *nic, struct net_device *netdev) 274 { 275 union nic_mbx mbx = {}; 276 277 mbx.mac.msg = NIC_MBOX_MSG_SET_MAC; 278 mbx.mac.vf_id = nic->vf_id; 279 ether_addr_copy(mbx.mac.mac_addr, netdev->dev_addr); 280 281 return nicvf_send_msg_to_pf(nic, &mbx); 282 } 283 284 static void nicvf_config_cpi(struct nicvf *nic) 285 { 286 union nic_mbx mbx = {}; 287 288 mbx.cpi_cfg.msg = NIC_MBOX_MSG_CPI_CFG; 289 mbx.cpi_cfg.vf_id = nic->vf_id; 290 mbx.cpi_cfg.cpi_alg = nic->cpi_alg; 291 mbx.cpi_cfg.rq_cnt = nic->qs->rq_cnt; 292 293 nicvf_send_msg_to_pf(nic, &mbx); 294 } 295 296 static void nicvf_get_rss_size(struct nicvf *nic) 297 { 298 union nic_mbx mbx = {}; 299 300 mbx.rss_size.msg = NIC_MBOX_MSG_RSS_SIZE; 301 mbx.rss_size.vf_id = nic->vf_id; 302 nicvf_send_msg_to_pf(nic, &mbx); 303 } 304 305 void nicvf_config_rss(struct nicvf *nic) 306 { 307 union nic_mbx mbx = {}; 308 struct nicvf_rss_info *rss = &nic->rss_info; 309 int ind_tbl_len = rss->rss_size; 310 int i, nextq = 0; 311 312 mbx.rss_cfg.vf_id = nic->vf_id; 313 mbx.rss_cfg.hash_bits = rss->hash_bits; 314 while (ind_tbl_len) { 315 mbx.rss_cfg.tbl_offset = nextq; 316 mbx.rss_cfg.tbl_len = min(ind_tbl_len, 317 RSS_IND_TBL_LEN_PER_MBX_MSG); 318 mbx.rss_cfg.msg = mbx.rss_cfg.tbl_offset ? 319 NIC_MBOX_MSG_RSS_CFG_CONT : NIC_MBOX_MSG_RSS_CFG; 320 321 for (i = 0; i < mbx.rss_cfg.tbl_len; i++) 322 mbx.rss_cfg.ind_tbl[i] = rss->ind_tbl[nextq++]; 323 324 nicvf_send_msg_to_pf(nic, &mbx); 325 326 ind_tbl_len -= mbx.rss_cfg.tbl_len; 327 } 328 } 329 330 void nicvf_set_rss_key(struct nicvf *nic) 331 { 332 struct nicvf_rss_info *rss = &nic->rss_info; 333 u64 key_addr = NIC_VNIC_RSS_KEY_0_4; 334 int idx; 335 336 for (idx = 0; idx < RSS_HASH_KEY_SIZE; idx++) { 337 nicvf_reg_write(nic, key_addr, rss->key[idx]); 338 key_addr += sizeof(u64); 339 } 340 } 341 342 static int nicvf_rss_init(struct nicvf *nic) 343 { 344 struct nicvf_rss_info *rss = &nic->rss_info; 345 int idx; 346 347 nicvf_get_rss_size(nic); 348 349 if (cpi_alg != CPI_ALG_NONE) { 350 rss->enable = false; 351 rss->hash_bits = 0; 352 return 0; 353 } 354 355 rss->enable = true; 356 357 netdev_rss_key_fill(rss->key, RSS_HASH_KEY_SIZE * sizeof(u64)); 358 nicvf_set_rss_key(nic); 359 360 rss->cfg = RSS_IP_HASH_ENA | RSS_TCP_HASH_ENA | RSS_UDP_HASH_ENA; 361 nicvf_reg_write(nic, NIC_VNIC_RSS_CFG, rss->cfg); 362 363 rss->hash_bits = ilog2(rounddown_pow_of_two(rss->rss_size)); 364 365 for (idx = 0; idx < rss->rss_size; idx++) 366 rss->ind_tbl[idx] = ethtool_rxfh_indir_default(idx, 367 nic->rx_queues); 368 nicvf_config_rss(nic); 369 return 1; 370 } 371 372 /* Request PF to allocate additional Qsets */ 373 static void nicvf_request_sqs(struct nicvf *nic) 374 { 375 union nic_mbx mbx = {}; 376 int sqs; 377 int sqs_count = nic->sqs_count; 378 int rx_queues = 0, tx_queues = 0; 379 380 /* Only primary VF should request */ 381 if (nic->sqs_mode || !nic->sqs_count) 382 return; 383 384 mbx.sqs_alloc.msg = NIC_MBOX_MSG_ALLOC_SQS; 385 mbx.sqs_alloc.vf_id = nic->vf_id; 386 mbx.sqs_alloc.qs_count = nic->sqs_count; 387 if (nicvf_send_msg_to_pf(nic, &mbx)) { 388 /* No response from PF */ 389 nic->sqs_count = 0; 390 return; 391 } 392 393 /* Return if no Secondary Qsets available */ 394 if (!nic->sqs_count) 395 return; 396 397 if (nic->rx_queues > MAX_RCV_QUEUES_PER_QS) 398 rx_queues = nic->rx_queues - MAX_RCV_QUEUES_PER_QS; 399 if (nic->tx_queues > MAX_SND_QUEUES_PER_QS) 400 tx_queues = nic->tx_queues - MAX_SND_QUEUES_PER_QS; 401 402 /* Set no of Rx/Tx queues in each of the SQsets */ 403 for (sqs = 0; sqs < nic->sqs_count; sqs++) { 404 mbx.nicvf.msg = NIC_MBOX_MSG_SNICVF_PTR; 405 mbx.nicvf.vf_id = nic->vf_id; 406 mbx.nicvf.sqs_id = sqs; 407 nicvf_send_msg_to_pf(nic, &mbx); 408 409 nic->snicvf[sqs]->sqs_id = sqs; 410 if (rx_queues > MAX_RCV_QUEUES_PER_QS) { 411 nic->snicvf[sqs]->qs->rq_cnt = MAX_RCV_QUEUES_PER_QS; 412 rx_queues -= MAX_RCV_QUEUES_PER_QS; 413 } else { 414 nic->snicvf[sqs]->qs->rq_cnt = rx_queues; 415 rx_queues = 0; 416 } 417 418 if (tx_queues > MAX_SND_QUEUES_PER_QS) { 419 nic->snicvf[sqs]->qs->sq_cnt = MAX_SND_QUEUES_PER_QS; 420 tx_queues -= MAX_SND_QUEUES_PER_QS; 421 } else { 422 nic->snicvf[sqs]->qs->sq_cnt = tx_queues; 423 tx_queues = 0; 424 } 425 426 nic->snicvf[sqs]->qs->cq_cnt = 427 max(nic->snicvf[sqs]->qs->rq_cnt, nic->snicvf[sqs]->qs->sq_cnt); 428 429 /* Initialize secondary Qset's queues and its interrupts */ 430 nicvf_open(nic->snicvf[sqs]->netdev); 431 } 432 433 /* Update stack with actual Rx/Tx queue count allocated */ 434 if (sqs_count != nic->sqs_count) 435 nicvf_set_real_num_queues(nic->netdev, 436 nic->tx_queues, nic->rx_queues); 437 } 438 439 /* Send this Qset's nicvf pointer to PF. 440 * PF inturn sends primary VF's nicvf struct to secondary Qsets/VFs 441 * so that packets received by these Qsets can use primary VF's netdev 442 */ 443 static void nicvf_send_vf_struct(struct nicvf *nic) 444 { 445 union nic_mbx mbx = {}; 446 447 mbx.nicvf.msg = NIC_MBOX_MSG_NICVF_PTR; 448 mbx.nicvf.sqs_mode = nic->sqs_mode; 449 mbx.nicvf.nicvf = (u64)nic; 450 nicvf_send_msg_to_pf(nic, &mbx); 451 } 452 453 static void nicvf_get_primary_vf_struct(struct nicvf *nic) 454 { 455 union nic_mbx mbx = {}; 456 457 mbx.nicvf.msg = NIC_MBOX_MSG_PNICVF_PTR; 458 nicvf_send_msg_to_pf(nic, &mbx); 459 } 460 461 int nicvf_set_real_num_queues(struct net_device *netdev, 462 int tx_queues, int rx_queues) 463 { 464 int err = 0; 465 466 err = netif_set_real_num_tx_queues(netdev, tx_queues); 467 if (err) { 468 netdev_err(netdev, 469 "Failed to set no of Tx queues: %d\n", tx_queues); 470 return err; 471 } 472 473 err = netif_set_real_num_rx_queues(netdev, rx_queues); 474 if (err) 475 netdev_err(netdev, 476 "Failed to set no of Rx queues: %d\n", rx_queues); 477 return err; 478 } 479 480 static int nicvf_init_resources(struct nicvf *nic) 481 { 482 int err; 483 484 /* Enable Qset */ 485 nicvf_qset_config(nic, true); 486 487 /* Initialize queues and HW for data transfer */ 488 err = nicvf_config_data_transfer(nic, true); 489 if (err) { 490 netdev_err(nic->netdev, 491 "Failed to alloc/config VF's QSet resources\n"); 492 return err; 493 } 494 495 return 0; 496 } 497 498 static void nicvf_snd_pkt_handler(struct net_device *netdev, 499 struct cqe_send_t *cqe_tx, 500 int cqe_type, int budget, 501 unsigned int *tx_pkts, unsigned int *tx_bytes) 502 { 503 struct sk_buff *skb = NULL; 504 struct nicvf *nic = netdev_priv(netdev); 505 struct snd_queue *sq; 506 struct sq_hdr_subdesc *hdr; 507 struct sq_hdr_subdesc *tso_sqe; 508 509 sq = &nic->qs->sq[cqe_tx->sq_idx]; 510 511 hdr = (struct sq_hdr_subdesc *)GET_SQ_DESC(sq, cqe_tx->sqe_ptr); 512 if (hdr->subdesc_type != SQ_DESC_TYPE_HEADER) 513 return; 514 515 netdev_dbg(nic->netdev, 516 "%s Qset #%d SQ #%d SQ ptr #%d subdesc count %d\n", 517 __func__, cqe_tx->sq_qs, cqe_tx->sq_idx, 518 cqe_tx->sqe_ptr, hdr->subdesc_cnt); 519 520 nicvf_check_cqe_tx_errs(nic, cqe_tx); 521 skb = (struct sk_buff *)sq->skbuff[cqe_tx->sqe_ptr]; 522 if (skb) { 523 /* Check for dummy descriptor used for HW TSO offload on 88xx */ 524 if (hdr->dont_send) { 525 /* Get actual TSO descriptors and free them */ 526 tso_sqe = 527 (struct sq_hdr_subdesc *)GET_SQ_DESC(sq, hdr->rsvd2); 528 nicvf_put_sq_desc(sq, tso_sqe->subdesc_cnt + 1); 529 } 530 nicvf_put_sq_desc(sq, hdr->subdesc_cnt + 1); 531 prefetch(skb); 532 (*tx_pkts)++; 533 *tx_bytes += skb->len; 534 napi_consume_skb(skb, budget); 535 sq->skbuff[cqe_tx->sqe_ptr] = (u64)NULL; 536 } else { 537 /* In case of SW TSO on 88xx, only last segment will have 538 * a SKB attached, so just free SQEs here. 539 */ 540 if (!nic->hw_tso) 541 nicvf_put_sq_desc(sq, hdr->subdesc_cnt + 1); 542 } 543 } 544 545 static inline void nicvf_set_rxhash(struct net_device *netdev, 546 struct cqe_rx_t *cqe_rx, 547 struct sk_buff *skb) 548 { 549 u8 hash_type; 550 u32 hash; 551 552 if (!(netdev->features & NETIF_F_RXHASH)) 553 return; 554 555 switch (cqe_rx->rss_alg) { 556 case RSS_ALG_TCP_IP: 557 case RSS_ALG_UDP_IP: 558 hash_type = PKT_HASH_TYPE_L4; 559 hash = cqe_rx->rss_tag; 560 break; 561 case RSS_ALG_IP: 562 hash_type = PKT_HASH_TYPE_L3; 563 hash = cqe_rx->rss_tag; 564 break; 565 default: 566 hash_type = PKT_HASH_TYPE_NONE; 567 hash = 0; 568 } 569 570 skb_set_hash(skb, hash, hash_type); 571 } 572 573 static void nicvf_rcv_pkt_handler(struct net_device *netdev, 574 struct napi_struct *napi, 575 struct cqe_rx_t *cqe_rx) 576 { 577 struct sk_buff *skb; 578 struct nicvf *nic = netdev_priv(netdev); 579 int err = 0; 580 int rq_idx; 581 582 rq_idx = nicvf_netdev_qidx(nic, cqe_rx->rq_idx); 583 584 if (nic->sqs_mode) { 585 /* Use primary VF's 'nicvf' struct */ 586 nic = nic->pnicvf; 587 netdev = nic->netdev; 588 } 589 590 /* Check for errors */ 591 err = nicvf_check_cqe_rx_errs(nic, cqe_rx); 592 if (err && !cqe_rx->rb_cnt) 593 return; 594 595 skb = nicvf_get_rcv_skb(nic, cqe_rx); 596 if (!skb) { 597 netdev_dbg(nic->netdev, "Packet not received\n"); 598 return; 599 } 600 601 if (netif_msg_pktdata(nic)) { 602 netdev_info(nic->netdev, "%s: skb 0x%p, len=%d\n", netdev->name, 603 skb, skb->len); 604 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1, 605 skb->data, skb->len, true); 606 } 607 608 /* If error packet, drop it here */ 609 if (err) { 610 dev_kfree_skb_any(skb); 611 return; 612 } 613 614 nicvf_set_rxhash(netdev, cqe_rx, skb); 615 616 skb_record_rx_queue(skb, rq_idx); 617 if (netdev->hw_features & NETIF_F_RXCSUM) { 618 /* HW by default verifies TCP/UDP/SCTP checksums */ 619 skb->ip_summed = CHECKSUM_UNNECESSARY; 620 } else { 621 skb_checksum_none_assert(skb); 622 } 623 624 skb->protocol = eth_type_trans(skb, netdev); 625 626 /* Check for stripped VLAN */ 627 if (cqe_rx->vlan_found && cqe_rx->vlan_stripped) 628 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 629 ntohs((__force __be16)cqe_rx->vlan_tci)); 630 631 if (napi && (netdev->features & NETIF_F_GRO)) 632 napi_gro_receive(napi, skb); 633 else 634 netif_receive_skb(skb); 635 } 636 637 static int nicvf_cq_intr_handler(struct net_device *netdev, u8 cq_idx, 638 struct napi_struct *napi, int budget) 639 { 640 int processed_cqe, work_done = 0, tx_done = 0; 641 int cqe_count, cqe_head; 642 struct nicvf *nic = netdev_priv(netdev); 643 struct queue_set *qs = nic->qs; 644 struct cmp_queue *cq = &qs->cq[cq_idx]; 645 struct cqe_rx_t *cq_desc; 646 struct netdev_queue *txq; 647 unsigned int tx_pkts = 0, tx_bytes = 0; 648 649 spin_lock_bh(&cq->lock); 650 loop: 651 processed_cqe = 0; 652 /* Get no of valid CQ entries to process */ 653 cqe_count = nicvf_queue_reg_read(nic, NIC_QSET_CQ_0_7_STATUS, cq_idx); 654 cqe_count &= CQ_CQE_COUNT; 655 if (!cqe_count) 656 goto done; 657 658 /* Get head of the valid CQ entries */ 659 cqe_head = nicvf_queue_reg_read(nic, NIC_QSET_CQ_0_7_HEAD, cq_idx) >> 9; 660 cqe_head &= 0xFFFF; 661 662 netdev_dbg(nic->netdev, "%s CQ%d cqe_count %d cqe_head %d\n", 663 __func__, cq_idx, cqe_count, cqe_head); 664 while (processed_cqe < cqe_count) { 665 /* Get the CQ descriptor */ 666 cq_desc = (struct cqe_rx_t *)GET_CQ_DESC(cq, cqe_head); 667 cqe_head++; 668 cqe_head &= (cq->dmem.q_len - 1); 669 /* Initiate prefetch for next descriptor */ 670 prefetch((struct cqe_rx_t *)GET_CQ_DESC(cq, cqe_head)); 671 672 if ((work_done >= budget) && napi && 673 (cq_desc->cqe_type != CQE_TYPE_SEND)) { 674 break; 675 } 676 677 netdev_dbg(nic->netdev, "CQ%d cq_desc->cqe_type %d\n", 678 cq_idx, cq_desc->cqe_type); 679 switch (cq_desc->cqe_type) { 680 case CQE_TYPE_RX: 681 nicvf_rcv_pkt_handler(netdev, napi, cq_desc); 682 work_done++; 683 break; 684 case CQE_TYPE_SEND: 685 nicvf_snd_pkt_handler(netdev, 686 (void *)cq_desc, CQE_TYPE_SEND, 687 budget, &tx_pkts, &tx_bytes); 688 tx_done++; 689 break; 690 case CQE_TYPE_INVALID: 691 case CQE_TYPE_RX_SPLIT: 692 case CQE_TYPE_RX_TCP: 693 case CQE_TYPE_SEND_PTP: 694 /* Ignore for now */ 695 break; 696 } 697 processed_cqe++; 698 } 699 netdev_dbg(nic->netdev, 700 "%s CQ%d processed_cqe %d work_done %d budget %d\n", 701 __func__, cq_idx, processed_cqe, work_done, budget); 702 703 /* Ring doorbell to inform H/W to reuse processed CQEs */ 704 nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_DOOR, 705 cq_idx, processed_cqe); 706 707 if ((work_done < budget) && napi) 708 goto loop; 709 710 done: 711 /* Wakeup TXQ if its stopped earlier due to SQ full */ 712 if (tx_done) { 713 netdev = nic->pnicvf->netdev; 714 txq = netdev_get_tx_queue(netdev, 715 nicvf_netdev_qidx(nic, cq_idx)); 716 if (tx_pkts) 717 netdev_tx_completed_queue(txq, tx_pkts, tx_bytes); 718 719 nic = nic->pnicvf; 720 if (netif_tx_queue_stopped(txq) && netif_carrier_ok(netdev)) { 721 netif_tx_start_queue(txq); 722 this_cpu_inc(nic->drv_stats->txq_wake); 723 if (netif_msg_tx_err(nic)) 724 netdev_warn(netdev, 725 "%s: Transmit queue wakeup SQ%d\n", 726 netdev->name, cq_idx); 727 } 728 } 729 730 spin_unlock_bh(&cq->lock); 731 return work_done; 732 } 733 734 static int nicvf_poll(struct napi_struct *napi, int budget) 735 { 736 u64 cq_head; 737 int work_done = 0; 738 struct net_device *netdev = napi->dev; 739 struct nicvf *nic = netdev_priv(netdev); 740 struct nicvf_cq_poll *cq; 741 742 cq = container_of(napi, struct nicvf_cq_poll, napi); 743 work_done = nicvf_cq_intr_handler(netdev, cq->cq_idx, napi, budget); 744 745 if (work_done < budget) { 746 /* Slow packet rate, exit polling */ 747 napi_complete(napi); 748 /* Re-enable interrupts */ 749 cq_head = nicvf_queue_reg_read(nic, NIC_QSET_CQ_0_7_HEAD, 750 cq->cq_idx); 751 nicvf_clear_intr(nic, NICVF_INTR_CQ, cq->cq_idx); 752 nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_HEAD, 753 cq->cq_idx, cq_head); 754 nicvf_enable_intr(nic, NICVF_INTR_CQ, cq->cq_idx); 755 } 756 return work_done; 757 } 758 759 /* Qset error interrupt handler 760 * 761 * As of now only CQ errors are handled 762 */ 763 static void nicvf_handle_qs_err(unsigned long data) 764 { 765 struct nicvf *nic = (struct nicvf *)data; 766 struct queue_set *qs = nic->qs; 767 int qidx; 768 u64 status; 769 770 netif_tx_disable(nic->netdev); 771 772 /* Check if it is CQ err */ 773 for (qidx = 0; qidx < qs->cq_cnt; qidx++) { 774 status = nicvf_queue_reg_read(nic, NIC_QSET_CQ_0_7_STATUS, 775 qidx); 776 if (!(status & CQ_ERR_MASK)) 777 continue; 778 /* Process already queued CQEs and reconfig CQ */ 779 nicvf_disable_intr(nic, NICVF_INTR_CQ, qidx); 780 nicvf_sq_disable(nic, qidx); 781 nicvf_cq_intr_handler(nic->netdev, qidx, NULL, 0); 782 nicvf_cmp_queue_config(nic, qs, qidx, true); 783 nicvf_sq_free_used_descs(nic->netdev, &qs->sq[qidx], qidx); 784 nicvf_sq_enable(nic, &qs->sq[qidx], qidx); 785 786 nicvf_enable_intr(nic, NICVF_INTR_CQ, qidx); 787 } 788 789 netif_tx_start_all_queues(nic->netdev); 790 /* Re-enable Qset error interrupt */ 791 nicvf_enable_intr(nic, NICVF_INTR_QS_ERR, 0); 792 } 793 794 static void nicvf_dump_intr_status(struct nicvf *nic) 795 { 796 if (netif_msg_intr(nic)) 797 netdev_info(nic->netdev, "%s: interrupt status 0x%llx\n", 798 nic->netdev->name, nicvf_reg_read(nic, NIC_VF_INT)); 799 } 800 801 static irqreturn_t nicvf_misc_intr_handler(int irq, void *nicvf_irq) 802 { 803 struct nicvf *nic = (struct nicvf *)nicvf_irq; 804 u64 intr; 805 806 nicvf_dump_intr_status(nic); 807 808 intr = nicvf_reg_read(nic, NIC_VF_INT); 809 /* Check for spurious interrupt */ 810 if (!(intr & NICVF_INTR_MBOX_MASK)) 811 return IRQ_HANDLED; 812 813 nicvf_handle_mbx_intr(nic); 814 815 return IRQ_HANDLED; 816 } 817 818 static irqreturn_t nicvf_intr_handler(int irq, void *cq_irq) 819 { 820 struct nicvf_cq_poll *cq_poll = (struct nicvf_cq_poll *)cq_irq; 821 struct nicvf *nic = cq_poll->nicvf; 822 int qidx = cq_poll->cq_idx; 823 824 nicvf_dump_intr_status(nic); 825 826 /* Disable interrupts */ 827 nicvf_disable_intr(nic, NICVF_INTR_CQ, qidx); 828 829 /* Schedule NAPI */ 830 napi_schedule_irqoff(&cq_poll->napi); 831 832 /* Clear interrupt */ 833 nicvf_clear_intr(nic, NICVF_INTR_CQ, qidx); 834 835 return IRQ_HANDLED; 836 } 837 838 static irqreturn_t nicvf_rbdr_intr_handler(int irq, void *nicvf_irq) 839 { 840 struct nicvf *nic = (struct nicvf *)nicvf_irq; 841 u8 qidx; 842 843 844 nicvf_dump_intr_status(nic); 845 846 /* Disable RBDR interrupt and schedule softirq */ 847 for (qidx = 0; qidx < nic->qs->rbdr_cnt; qidx++) { 848 if (!nicvf_is_intr_enabled(nic, NICVF_INTR_RBDR, qidx)) 849 continue; 850 nicvf_disable_intr(nic, NICVF_INTR_RBDR, qidx); 851 tasklet_hi_schedule(&nic->rbdr_task); 852 /* Clear interrupt */ 853 nicvf_clear_intr(nic, NICVF_INTR_RBDR, qidx); 854 } 855 856 return IRQ_HANDLED; 857 } 858 859 static irqreturn_t nicvf_qs_err_intr_handler(int irq, void *nicvf_irq) 860 { 861 struct nicvf *nic = (struct nicvf *)nicvf_irq; 862 863 nicvf_dump_intr_status(nic); 864 865 /* Disable Qset err interrupt and schedule softirq */ 866 nicvf_disable_intr(nic, NICVF_INTR_QS_ERR, 0); 867 tasklet_hi_schedule(&nic->qs_err_task); 868 nicvf_clear_intr(nic, NICVF_INTR_QS_ERR, 0); 869 870 return IRQ_HANDLED; 871 } 872 873 static int nicvf_enable_msix(struct nicvf *nic) 874 { 875 int ret, vec; 876 877 nic->num_vec = NIC_VF_MSIX_VECTORS; 878 879 for (vec = 0; vec < nic->num_vec; vec++) 880 nic->msix_entries[vec].entry = vec; 881 882 ret = pci_enable_msix(nic->pdev, nic->msix_entries, nic->num_vec); 883 if (ret) { 884 netdev_err(nic->netdev, 885 "Req for #%d msix vectors failed\n", nic->num_vec); 886 return 0; 887 } 888 nic->msix_enabled = 1; 889 return 1; 890 } 891 892 static void nicvf_disable_msix(struct nicvf *nic) 893 { 894 if (nic->msix_enabled) { 895 pci_disable_msix(nic->pdev); 896 nic->msix_enabled = 0; 897 nic->num_vec = 0; 898 } 899 } 900 901 static void nicvf_set_irq_affinity(struct nicvf *nic) 902 { 903 int vec, cpu; 904 int irqnum; 905 906 for (vec = 0; vec < nic->num_vec; vec++) { 907 if (!nic->irq_allocated[vec]) 908 continue; 909 910 if (!zalloc_cpumask_var(&nic->affinity_mask[vec], GFP_KERNEL)) 911 return; 912 /* CQ interrupts */ 913 if (vec < NICVF_INTR_ID_SQ) 914 /* Leave CPU0 for RBDR and other interrupts */ 915 cpu = nicvf_netdev_qidx(nic, vec) + 1; 916 else 917 cpu = 0; 918 919 cpumask_set_cpu(cpumask_local_spread(cpu, nic->node), 920 nic->affinity_mask[vec]); 921 irqnum = nic->msix_entries[vec].vector; 922 irq_set_affinity_hint(irqnum, nic->affinity_mask[vec]); 923 } 924 } 925 926 static int nicvf_register_interrupts(struct nicvf *nic) 927 { 928 int irq, ret = 0; 929 int vector; 930 931 for_each_cq_irq(irq) 932 sprintf(nic->irq_name[irq], "%s-rxtx-%d", 933 nic->pnicvf->netdev->name, 934 nicvf_netdev_qidx(nic, irq)); 935 936 for_each_sq_irq(irq) 937 sprintf(nic->irq_name[irq], "%s-sq-%d", 938 nic->pnicvf->netdev->name, 939 nicvf_netdev_qidx(nic, irq - NICVF_INTR_ID_SQ)); 940 941 for_each_rbdr_irq(irq) 942 sprintf(nic->irq_name[irq], "%s-rbdr-%d", 943 nic->pnicvf->netdev->name, 944 nic->sqs_mode ? (nic->sqs_id + 1) : 0); 945 946 /* Register CQ interrupts */ 947 for (irq = 0; irq < nic->qs->cq_cnt; irq++) { 948 vector = nic->msix_entries[irq].vector; 949 ret = request_irq(vector, nicvf_intr_handler, 950 0, nic->irq_name[irq], nic->napi[irq]); 951 if (ret) 952 goto err; 953 nic->irq_allocated[irq] = true; 954 } 955 956 /* Register RBDR interrupt */ 957 for (irq = NICVF_INTR_ID_RBDR; 958 irq < (NICVF_INTR_ID_RBDR + nic->qs->rbdr_cnt); irq++) { 959 vector = nic->msix_entries[irq].vector; 960 ret = request_irq(vector, nicvf_rbdr_intr_handler, 961 0, nic->irq_name[irq], nic); 962 if (ret) 963 goto err; 964 nic->irq_allocated[irq] = true; 965 } 966 967 /* Register QS error interrupt */ 968 sprintf(nic->irq_name[NICVF_INTR_ID_QS_ERR], "%s-qset-err-%d", 969 nic->pnicvf->netdev->name, 970 nic->sqs_mode ? (nic->sqs_id + 1) : 0); 971 irq = NICVF_INTR_ID_QS_ERR; 972 ret = request_irq(nic->msix_entries[irq].vector, 973 nicvf_qs_err_intr_handler, 974 0, nic->irq_name[irq], nic); 975 if (ret) 976 goto err; 977 978 nic->irq_allocated[irq] = true; 979 980 /* Set IRQ affinities */ 981 nicvf_set_irq_affinity(nic); 982 983 err: 984 if (ret) 985 netdev_err(nic->netdev, "request_irq failed, vector %d\n", irq); 986 987 return ret; 988 } 989 990 static void nicvf_unregister_interrupts(struct nicvf *nic) 991 { 992 int irq; 993 994 /* Free registered interrupts */ 995 for (irq = 0; irq < nic->num_vec; irq++) { 996 if (!nic->irq_allocated[irq]) 997 continue; 998 999 irq_set_affinity_hint(nic->msix_entries[irq].vector, NULL); 1000 free_cpumask_var(nic->affinity_mask[irq]); 1001 1002 if (irq < NICVF_INTR_ID_SQ) 1003 free_irq(nic->msix_entries[irq].vector, nic->napi[irq]); 1004 else 1005 free_irq(nic->msix_entries[irq].vector, nic); 1006 1007 nic->irq_allocated[irq] = false; 1008 } 1009 1010 /* Disable MSI-X */ 1011 nicvf_disable_msix(nic); 1012 } 1013 1014 /* Initialize MSIX vectors and register MISC interrupt. 1015 * Send READY message to PF to check if its alive 1016 */ 1017 static int nicvf_register_misc_interrupt(struct nicvf *nic) 1018 { 1019 int ret = 0; 1020 int irq = NICVF_INTR_ID_MISC; 1021 1022 /* Return if mailbox interrupt is already registered */ 1023 if (nic->msix_enabled) 1024 return 0; 1025 1026 /* Enable MSI-X */ 1027 if (!nicvf_enable_msix(nic)) 1028 return 1; 1029 1030 sprintf(nic->irq_name[irq], "%s Mbox", "NICVF"); 1031 /* Register Misc interrupt */ 1032 ret = request_irq(nic->msix_entries[irq].vector, 1033 nicvf_misc_intr_handler, 0, nic->irq_name[irq], nic); 1034 1035 if (ret) 1036 return ret; 1037 nic->irq_allocated[irq] = true; 1038 1039 /* Enable mailbox interrupt */ 1040 nicvf_enable_intr(nic, NICVF_INTR_MBOX, 0); 1041 1042 /* Check if VF is able to communicate with PF */ 1043 if (!nicvf_check_pf_ready(nic)) { 1044 nicvf_disable_intr(nic, NICVF_INTR_MBOX, 0); 1045 nicvf_unregister_interrupts(nic); 1046 return 1; 1047 } 1048 1049 return 0; 1050 } 1051 1052 static netdev_tx_t nicvf_xmit(struct sk_buff *skb, struct net_device *netdev) 1053 { 1054 struct nicvf *nic = netdev_priv(netdev); 1055 int qid = skb_get_queue_mapping(skb); 1056 struct netdev_queue *txq = netdev_get_tx_queue(netdev, qid); 1057 1058 /* Check for minimum packet length */ 1059 if (skb->len <= ETH_HLEN) { 1060 dev_kfree_skb(skb); 1061 return NETDEV_TX_OK; 1062 } 1063 1064 if (!netif_tx_queue_stopped(txq) && !nicvf_sq_append_skb(nic, skb)) { 1065 netif_tx_stop_queue(txq); 1066 this_cpu_inc(nic->drv_stats->txq_stop); 1067 if (netif_msg_tx_err(nic)) 1068 netdev_warn(netdev, 1069 "%s: Transmit ring full, stopping SQ%d\n", 1070 netdev->name, qid); 1071 return NETDEV_TX_BUSY; 1072 } 1073 1074 return NETDEV_TX_OK; 1075 } 1076 1077 static inline void nicvf_free_cq_poll(struct nicvf *nic) 1078 { 1079 struct nicvf_cq_poll *cq_poll; 1080 int qidx; 1081 1082 for (qidx = 0; qidx < nic->qs->cq_cnt; qidx++) { 1083 cq_poll = nic->napi[qidx]; 1084 if (!cq_poll) 1085 continue; 1086 nic->napi[qidx] = NULL; 1087 kfree(cq_poll); 1088 } 1089 } 1090 1091 int nicvf_stop(struct net_device *netdev) 1092 { 1093 int irq, qidx; 1094 struct nicvf *nic = netdev_priv(netdev); 1095 struct queue_set *qs = nic->qs; 1096 struct nicvf_cq_poll *cq_poll = NULL; 1097 union nic_mbx mbx = {}; 1098 1099 mbx.msg.msg = NIC_MBOX_MSG_SHUTDOWN; 1100 nicvf_send_msg_to_pf(nic, &mbx); 1101 1102 netif_carrier_off(netdev); 1103 netif_tx_stop_all_queues(nic->netdev); 1104 nic->link_up = false; 1105 1106 /* Teardown secondary qsets first */ 1107 if (!nic->sqs_mode) { 1108 for (qidx = 0; qidx < nic->sqs_count; qidx++) { 1109 if (!nic->snicvf[qidx]) 1110 continue; 1111 nicvf_stop(nic->snicvf[qidx]->netdev); 1112 nic->snicvf[qidx] = NULL; 1113 } 1114 } 1115 1116 /* Disable RBDR & QS error interrupts */ 1117 for (qidx = 0; qidx < qs->rbdr_cnt; qidx++) { 1118 nicvf_disable_intr(nic, NICVF_INTR_RBDR, qidx); 1119 nicvf_clear_intr(nic, NICVF_INTR_RBDR, qidx); 1120 } 1121 nicvf_disable_intr(nic, NICVF_INTR_QS_ERR, 0); 1122 nicvf_clear_intr(nic, NICVF_INTR_QS_ERR, 0); 1123 1124 /* Wait for pending IRQ handlers to finish */ 1125 for (irq = 0; irq < nic->num_vec; irq++) 1126 synchronize_irq(nic->msix_entries[irq].vector); 1127 1128 tasklet_kill(&nic->rbdr_task); 1129 tasklet_kill(&nic->qs_err_task); 1130 if (nic->rb_work_scheduled) 1131 cancel_delayed_work_sync(&nic->rbdr_work); 1132 1133 for (qidx = 0; qidx < nic->qs->cq_cnt; qidx++) { 1134 cq_poll = nic->napi[qidx]; 1135 if (!cq_poll) 1136 continue; 1137 napi_synchronize(&cq_poll->napi); 1138 /* CQ intr is enabled while napi_complete, 1139 * so disable it now 1140 */ 1141 nicvf_disable_intr(nic, NICVF_INTR_CQ, qidx); 1142 nicvf_clear_intr(nic, NICVF_INTR_CQ, qidx); 1143 napi_disable(&cq_poll->napi); 1144 netif_napi_del(&cq_poll->napi); 1145 } 1146 1147 netif_tx_disable(netdev); 1148 1149 for (qidx = 0; qidx < netdev->num_tx_queues; qidx++) 1150 netdev_tx_reset_queue(netdev_get_tx_queue(netdev, qidx)); 1151 1152 /* Free resources */ 1153 nicvf_config_data_transfer(nic, false); 1154 1155 /* Disable HW Qset */ 1156 nicvf_qset_config(nic, false); 1157 1158 /* disable mailbox interrupt */ 1159 nicvf_disable_intr(nic, NICVF_INTR_MBOX, 0); 1160 1161 nicvf_unregister_interrupts(nic); 1162 1163 nicvf_free_cq_poll(nic); 1164 1165 /* Clear multiqset info */ 1166 nic->pnicvf = nic; 1167 1168 return 0; 1169 } 1170 1171 static int nicvf_update_hw_max_frs(struct nicvf *nic, int mtu) 1172 { 1173 union nic_mbx mbx = {}; 1174 1175 mbx.frs.msg = NIC_MBOX_MSG_SET_MAX_FRS; 1176 mbx.frs.max_frs = mtu; 1177 mbx.frs.vf_id = nic->vf_id; 1178 1179 return nicvf_send_msg_to_pf(nic, &mbx); 1180 } 1181 1182 int nicvf_open(struct net_device *netdev) 1183 { 1184 int cpu, err, qidx; 1185 struct nicvf *nic = netdev_priv(netdev); 1186 struct queue_set *qs = nic->qs; 1187 struct nicvf_cq_poll *cq_poll = NULL; 1188 union nic_mbx mbx = {}; 1189 1190 netif_carrier_off(netdev); 1191 1192 err = nicvf_register_misc_interrupt(nic); 1193 if (err) 1194 return err; 1195 1196 /* Register NAPI handler for processing CQEs */ 1197 for (qidx = 0; qidx < qs->cq_cnt; qidx++) { 1198 cq_poll = kzalloc(sizeof(*cq_poll), GFP_KERNEL); 1199 if (!cq_poll) { 1200 err = -ENOMEM; 1201 goto napi_del; 1202 } 1203 cq_poll->cq_idx = qidx; 1204 cq_poll->nicvf = nic; 1205 netif_napi_add(netdev, &cq_poll->napi, nicvf_poll, 1206 NAPI_POLL_WEIGHT); 1207 napi_enable(&cq_poll->napi); 1208 nic->napi[qidx] = cq_poll; 1209 } 1210 1211 /* Check if we got MAC address from PF or else generate a radom MAC */ 1212 if (!nic->sqs_mode && is_zero_ether_addr(netdev->dev_addr)) { 1213 eth_hw_addr_random(netdev); 1214 nicvf_hw_set_mac_addr(nic, netdev); 1215 } 1216 1217 if (nic->set_mac_pending) { 1218 nic->set_mac_pending = false; 1219 nicvf_hw_set_mac_addr(nic, netdev); 1220 } 1221 1222 /* Init tasklet for handling Qset err interrupt */ 1223 tasklet_init(&nic->qs_err_task, nicvf_handle_qs_err, 1224 (unsigned long)nic); 1225 1226 /* Init RBDR tasklet which will refill RBDR */ 1227 tasklet_init(&nic->rbdr_task, nicvf_rbdr_task, 1228 (unsigned long)nic); 1229 INIT_DELAYED_WORK(&nic->rbdr_work, nicvf_rbdr_work); 1230 1231 /* Configure CPI alorithm */ 1232 nic->cpi_alg = cpi_alg; 1233 if (!nic->sqs_mode) 1234 nicvf_config_cpi(nic); 1235 1236 nicvf_request_sqs(nic); 1237 if (nic->sqs_mode) 1238 nicvf_get_primary_vf_struct(nic); 1239 1240 /* Configure receive side scaling and MTU */ 1241 if (!nic->sqs_mode) { 1242 nicvf_rss_init(nic); 1243 if (nicvf_update_hw_max_frs(nic, netdev->mtu)) 1244 goto cleanup; 1245 1246 /* Clear percpu stats */ 1247 for_each_possible_cpu(cpu) 1248 memset(per_cpu_ptr(nic->drv_stats, cpu), 0, 1249 sizeof(struct nicvf_drv_stats)); 1250 } 1251 1252 err = nicvf_register_interrupts(nic); 1253 if (err) 1254 goto cleanup; 1255 1256 /* Initialize the queues */ 1257 err = nicvf_init_resources(nic); 1258 if (err) 1259 goto cleanup; 1260 1261 /* Make sure queue initialization is written */ 1262 wmb(); 1263 1264 nicvf_reg_write(nic, NIC_VF_INT, -1); 1265 /* Enable Qset err interrupt */ 1266 nicvf_enable_intr(nic, NICVF_INTR_QS_ERR, 0); 1267 1268 /* Enable completion queue interrupt */ 1269 for (qidx = 0; qidx < qs->cq_cnt; qidx++) 1270 nicvf_enable_intr(nic, NICVF_INTR_CQ, qidx); 1271 1272 /* Enable RBDR threshold interrupt */ 1273 for (qidx = 0; qidx < qs->rbdr_cnt; qidx++) 1274 nicvf_enable_intr(nic, NICVF_INTR_RBDR, qidx); 1275 1276 /* Send VF config done msg to PF */ 1277 mbx.msg.msg = NIC_MBOX_MSG_CFG_DONE; 1278 nicvf_write_to_mbx(nic, &mbx); 1279 1280 return 0; 1281 cleanup: 1282 nicvf_disable_intr(nic, NICVF_INTR_MBOX, 0); 1283 nicvf_unregister_interrupts(nic); 1284 tasklet_kill(&nic->qs_err_task); 1285 tasklet_kill(&nic->rbdr_task); 1286 napi_del: 1287 for (qidx = 0; qidx < qs->cq_cnt; qidx++) { 1288 cq_poll = nic->napi[qidx]; 1289 if (!cq_poll) 1290 continue; 1291 napi_disable(&cq_poll->napi); 1292 netif_napi_del(&cq_poll->napi); 1293 } 1294 nicvf_free_cq_poll(nic); 1295 return err; 1296 } 1297 1298 static int nicvf_change_mtu(struct net_device *netdev, int new_mtu) 1299 { 1300 struct nicvf *nic = netdev_priv(netdev); 1301 int orig_mtu = netdev->mtu; 1302 1303 netdev->mtu = new_mtu; 1304 1305 if (!netif_running(netdev)) 1306 return 0; 1307 1308 if (nicvf_update_hw_max_frs(nic, new_mtu)) { 1309 netdev->mtu = orig_mtu; 1310 return -EINVAL; 1311 } 1312 1313 return 0; 1314 } 1315 1316 static int nicvf_set_mac_address(struct net_device *netdev, void *p) 1317 { 1318 struct sockaddr *addr = p; 1319 struct nicvf *nic = netdev_priv(netdev); 1320 1321 if (!is_valid_ether_addr(addr->sa_data)) 1322 return -EADDRNOTAVAIL; 1323 1324 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 1325 1326 if (nic->msix_enabled) { 1327 if (nicvf_hw_set_mac_addr(nic, netdev)) 1328 return -EBUSY; 1329 } else { 1330 nic->set_mac_pending = true; 1331 } 1332 1333 return 0; 1334 } 1335 1336 void nicvf_update_lmac_stats(struct nicvf *nic) 1337 { 1338 int stat = 0; 1339 union nic_mbx mbx = {}; 1340 1341 if (!netif_running(nic->netdev)) 1342 return; 1343 1344 mbx.bgx_stats.msg = NIC_MBOX_MSG_BGX_STATS; 1345 mbx.bgx_stats.vf_id = nic->vf_id; 1346 /* Rx stats */ 1347 mbx.bgx_stats.rx = 1; 1348 while (stat < BGX_RX_STATS_COUNT) { 1349 mbx.bgx_stats.idx = stat; 1350 if (nicvf_send_msg_to_pf(nic, &mbx)) 1351 return; 1352 stat++; 1353 } 1354 1355 stat = 0; 1356 1357 /* Tx stats */ 1358 mbx.bgx_stats.rx = 0; 1359 while (stat < BGX_TX_STATS_COUNT) { 1360 mbx.bgx_stats.idx = stat; 1361 if (nicvf_send_msg_to_pf(nic, &mbx)) 1362 return; 1363 stat++; 1364 } 1365 } 1366 1367 void nicvf_update_stats(struct nicvf *nic) 1368 { 1369 int qidx, cpu; 1370 u64 tmp_stats = 0; 1371 struct nicvf_hw_stats *stats = &nic->hw_stats; 1372 struct nicvf_drv_stats *drv_stats; 1373 struct queue_set *qs = nic->qs; 1374 1375 #define GET_RX_STATS(reg) \ 1376 nicvf_reg_read(nic, NIC_VNIC_RX_STAT_0_13 | (reg << 3)) 1377 #define GET_TX_STATS(reg) \ 1378 nicvf_reg_read(nic, NIC_VNIC_TX_STAT_0_4 | (reg << 3)) 1379 1380 stats->rx_bytes = GET_RX_STATS(RX_OCTS); 1381 stats->rx_ucast_frames = GET_RX_STATS(RX_UCAST); 1382 stats->rx_bcast_frames = GET_RX_STATS(RX_BCAST); 1383 stats->rx_mcast_frames = GET_RX_STATS(RX_MCAST); 1384 stats->rx_fcs_errors = GET_RX_STATS(RX_FCS); 1385 stats->rx_l2_errors = GET_RX_STATS(RX_L2ERR); 1386 stats->rx_drop_red = GET_RX_STATS(RX_RED); 1387 stats->rx_drop_red_bytes = GET_RX_STATS(RX_RED_OCTS); 1388 stats->rx_drop_overrun = GET_RX_STATS(RX_ORUN); 1389 stats->rx_drop_overrun_bytes = GET_RX_STATS(RX_ORUN_OCTS); 1390 stats->rx_drop_bcast = GET_RX_STATS(RX_DRP_BCAST); 1391 stats->rx_drop_mcast = GET_RX_STATS(RX_DRP_MCAST); 1392 stats->rx_drop_l3_bcast = GET_RX_STATS(RX_DRP_L3BCAST); 1393 stats->rx_drop_l3_mcast = GET_RX_STATS(RX_DRP_L3MCAST); 1394 1395 stats->tx_bytes = GET_TX_STATS(TX_OCTS); 1396 stats->tx_ucast_frames = GET_TX_STATS(TX_UCAST); 1397 stats->tx_bcast_frames = GET_TX_STATS(TX_BCAST); 1398 stats->tx_mcast_frames = GET_TX_STATS(TX_MCAST); 1399 stats->tx_drops = GET_TX_STATS(TX_DROP); 1400 1401 /* On T88 pass 2.0, the dummy SQE added for TSO notification 1402 * via CQE has 'dont_send' set. Hence HW drops the pkt pointed 1403 * pointed by dummy SQE and results in tx_drops counter being 1404 * incremented. Subtracting it from tx_tso counter will give 1405 * exact tx_drops counter. 1406 */ 1407 if (nic->t88 && nic->hw_tso) { 1408 for_each_possible_cpu(cpu) { 1409 drv_stats = per_cpu_ptr(nic->drv_stats, cpu); 1410 tmp_stats += drv_stats->tx_tso; 1411 } 1412 stats->tx_drops = tmp_stats - stats->tx_drops; 1413 } 1414 stats->tx_frames = stats->tx_ucast_frames + 1415 stats->tx_bcast_frames + 1416 stats->tx_mcast_frames; 1417 stats->rx_frames = stats->rx_ucast_frames + 1418 stats->rx_bcast_frames + 1419 stats->rx_mcast_frames; 1420 stats->rx_drops = stats->rx_drop_red + 1421 stats->rx_drop_overrun; 1422 1423 /* Update RQ and SQ stats */ 1424 for (qidx = 0; qidx < qs->rq_cnt; qidx++) 1425 nicvf_update_rq_stats(nic, qidx); 1426 for (qidx = 0; qidx < qs->sq_cnt; qidx++) 1427 nicvf_update_sq_stats(nic, qidx); 1428 } 1429 1430 static struct rtnl_link_stats64 *nicvf_get_stats64(struct net_device *netdev, 1431 struct rtnl_link_stats64 *stats) 1432 { 1433 struct nicvf *nic = netdev_priv(netdev); 1434 struct nicvf_hw_stats *hw_stats = &nic->hw_stats; 1435 1436 nicvf_update_stats(nic); 1437 1438 stats->rx_bytes = hw_stats->rx_bytes; 1439 stats->rx_packets = hw_stats->rx_frames; 1440 stats->rx_dropped = hw_stats->rx_drops; 1441 stats->multicast = hw_stats->rx_mcast_frames; 1442 1443 stats->tx_bytes = hw_stats->tx_bytes; 1444 stats->tx_packets = hw_stats->tx_frames; 1445 stats->tx_dropped = hw_stats->tx_drops; 1446 1447 return stats; 1448 } 1449 1450 static void nicvf_tx_timeout(struct net_device *dev) 1451 { 1452 struct nicvf *nic = netdev_priv(dev); 1453 1454 if (netif_msg_tx_err(nic)) 1455 netdev_warn(dev, "%s: Transmit timed out, resetting\n", 1456 dev->name); 1457 1458 this_cpu_inc(nic->drv_stats->tx_timeout); 1459 schedule_work(&nic->reset_task); 1460 } 1461 1462 static void nicvf_reset_task(struct work_struct *work) 1463 { 1464 struct nicvf *nic; 1465 1466 nic = container_of(work, struct nicvf, reset_task); 1467 1468 if (!netif_running(nic->netdev)) 1469 return; 1470 1471 nicvf_stop(nic->netdev); 1472 nicvf_open(nic->netdev); 1473 netif_trans_update(nic->netdev); 1474 } 1475 1476 static int nicvf_config_loopback(struct nicvf *nic, 1477 netdev_features_t features) 1478 { 1479 union nic_mbx mbx = {}; 1480 1481 mbx.lbk.msg = NIC_MBOX_MSG_LOOPBACK; 1482 mbx.lbk.vf_id = nic->vf_id; 1483 mbx.lbk.enable = (features & NETIF_F_LOOPBACK) != 0; 1484 1485 return nicvf_send_msg_to_pf(nic, &mbx); 1486 } 1487 1488 static netdev_features_t nicvf_fix_features(struct net_device *netdev, 1489 netdev_features_t features) 1490 { 1491 struct nicvf *nic = netdev_priv(netdev); 1492 1493 if ((features & NETIF_F_LOOPBACK) && 1494 netif_running(netdev) && !nic->loopback_supported) 1495 features &= ~NETIF_F_LOOPBACK; 1496 1497 return features; 1498 } 1499 1500 static int nicvf_set_features(struct net_device *netdev, 1501 netdev_features_t features) 1502 { 1503 struct nicvf *nic = netdev_priv(netdev); 1504 netdev_features_t changed = features ^ netdev->features; 1505 1506 if (changed & NETIF_F_HW_VLAN_CTAG_RX) 1507 nicvf_config_vlan_stripping(nic, features); 1508 1509 if ((changed & NETIF_F_LOOPBACK) && netif_running(netdev)) 1510 return nicvf_config_loopback(nic, features); 1511 1512 return 0; 1513 } 1514 1515 static const struct net_device_ops nicvf_netdev_ops = { 1516 .ndo_open = nicvf_open, 1517 .ndo_stop = nicvf_stop, 1518 .ndo_start_xmit = nicvf_xmit, 1519 .ndo_change_mtu = nicvf_change_mtu, 1520 .ndo_set_mac_address = nicvf_set_mac_address, 1521 .ndo_get_stats64 = nicvf_get_stats64, 1522 .ndo_tx_timeout = nicvf_tx_timeout, 1523 .ndo_fix_features = nicvf_fix_features, 1524 .ndo_set_features = nicvf_set_features, 1525 }; 1526 1527 static int nicvf_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1528 { 1529 struct device *dev = &pdev->dev; 1530 struct net_device *netdev; 1531 struct nicvf *nic; 1532 int err, qcount; 1533 u16 sdevid; 1534 1535 err = pci_enable_device(pdev); 1536 if (err) { 1537 dev_err(dev, "Failed to enable PCI device\n"); 1538 return err; 1539 } 1540 1541 err = pci_request_regions(pdev, DRV_NAME); 1542 if (err) { 1543 dev_err(dev, "PCI request regions failed 0x%x\n", err); 1544 goto err_disable_device; 1545 } 1546 1547 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(48)); 1548 if (err) { 1549 dev_err(dev, "Unable to get usable DMA configuration\n"); 1550 goto err_release_regions; 1551 } 1552 1553 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(48)); 1554 if (err) { 1555 dev_err(dev, "unable to get 48-bit DMA for consistent allocations\n"); 1556 goto err_release_regions; 1557 } 1558 1559 qcount = netif_get_num_default_rss_queues(); 1560 1561 /* Restrict multiqset support only for host bound VFs */ 1562 if (pdev->is_virtfn) { 1563 /* Set max number of queues per VF */ 1564 qcount = min_t(int, num_online_cpus(), 1565 (MAX_SQS_PER_VF + 1) * MAX_CMP_QUEUES_PER_QS); 1566 } 1567 1568 netdev = alloc_etherdev_mqs(sizeof(struct nicvf), qcount, qcount); 1569 if (!netdev) { 1570 err = -ENOMEM; 1571 goto err_release_regions; 1572 } 1573 1574 pci_set_drvdata(pdev, netdev); 1575 1576 SET_NETDEV_DEV(netdev, &pdev->dev); 1577 1578 nic = netdev_priv(netdev); 1579 nic->netdev = netdev; 1580 nic->pdev = pdev; 1581 nic->pnicvf = nic; 1582 nic->max_queues = qcount; 1583 1584 /* MAP VF's configuration registers */ 1585 nic->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0); 1586 if (!nic->reg_base) { 1587 dev_err(dev, "Cannot map config register space, aborting\n"); 1588 err = -ENOMEM; 1589 goto err_free_netdev; 1590 } 1591 1592 nic->drv_stats = netdev_alloc_pcpu_stats(struct nicvf_drv_stats); 1593 if (!nic->drv_stats) { 1594 err = -ENOMEM; 1595 goto err_free_netdev; 1596 } 1597 1598 err = nicvf_set_qset_resources(nic); 1599 if (err) 1600 goto err_free_netdev; 1601 1602 /* Check if PF is alive and get MAC address for this VF */ 1603 err = nicvf_register_misc_interrupt(nic); 1604 if (err) 1605 goto err_free_netdev; 1606 1607 nicvf_send_vf_struct(nic); 1608 1609 if (!pass1_silicon(nic->pdev)) 1610 nic->hw_tso = true; 1611 1612 pci_read_config_word(nic->pdev, PCI_SUBSYSTEM_ID, &sdevid); 1613 if (sdevid == 0xA134) 1614 nic->t88 = true; 1615 1616 /* Check if this VF is in QS only mode */ 1617 if (nic->sqs_mode) 1618 return 0; 1619 1620 err = nicvf_set_real_num_queues(netdev, nic->tx_queues, nic->rx_queues); 1621 if (err) 1622 goto err_unregister_interrupts; 1623 1624 netdev->hw_features = (NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG | 1625 NETIF_F_TSO | NETIF_F_GRO | 1626 NETIF_F_HW_VLAN_CTAG_RX); 1627 1628 netdev->hw_features |= NETIF_F_RXHASH; 1629 1630 netdev->features |= netdev->hw_features; 1631 netdev->hw_features |= NETIF_F_LOOPBACK; 1632 1633 netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; 1634 1635 netdev->netdev_ops = &nicvf_netdev_ops; 1636 netdev->watchdog_timeo = NICVF_TX_TIMEOUT; 1637 1638 /* MTU range: 64 - 9200 */ 1639 netdev->min_mtu = NIC_HW_MIN_FRS; 1640 netdev->max_mtu = NIC_HW_MAX_FRS; 1641 1642 INIT_WORK(&nic->reset_task, nicvf_reset_task); 1643 1644 err = register_netdev(netdev); 1645 if (err) { 1646 dev_err(dev, "Failed to register netdevice\n"); 1647 goto err_unregister_interrupts; 1648 } 1649 1650 nic->msg_enable = debug; 1651 1652 nicvf_set_ethtool_ops(netdev); 1653 1654 return 0; 1655 1656 err_unregister_interrupts: 1657 nicvf_unregister_interrupts(nic); 1658 err_free_netdev: 1659 pci_set_drvdata(pdev, NULL); 1660 if (nic->drv_stats) 1661 free_percpu(nic->drv_stats); 1662 free_netdev(netdev); 1663 err_release_regions: 1664 pci_release_regions(pdev); 1665 err_disable_device: 1666 pci_disable_device(pdev); 1667 return err; 1668 } 1669 1670 static void nicvf_remove(struct pci_dev *pdev) 1671 { 1672 struct net_device *netdev = pci_get_drvdata(pdev); 1673 struct nicvf *nic; 1674 struct net_device *pnetdev; 1675 1676 if (!netdev) 1677 return; 1678 1679 nic = netdev_priv(netdev); 1680 pnetdev = nic->pnicvf->netdev; 1681 1682 /* Check if this Qset is assigned to different VF. 1683 * If yes, clean primary and all secondary Qsets. 1684 */ 1685 if (pnetdev && (pnetdev->reg_state == NETREG_REGISTERED)) 1686 unregister_netdev(pnetdev); 1687 nicvf_unregister_interrupts(nic); 1688 pci_set_drvdata(pdev, NULL); 1689 if (nic->drv_stats) 1690 free_percpu(nic->drv_stats); 1691 free_netdev(netdev); 1692 pci_release_regions(pdev); 1693 pci_disable_device(pdev); 1694 } 1695 1696 static void nicvf_shutdown(struct pci_dev *pdev) 1697 { 1698 nicvf_remove(pdev); 1699 } 1700 1701 static struct pci_driver nicvf_driver = { 1702 .name = DRV_NAME, 1703 .id_table = nicvf_id_table, 1704 .probe = nicvf_probe, 1705 .remove = nicvf_remove, 1706 .shutdown = nicvf_shutdown, 1707 }; 1708 1709 static int __init nicvf_init_module(void) 1710 { 1711 pr_info("%s, ver %s\n", DRV_NAME, DRV_VERSION); 1712 1713 return pci_register_driver(&nicvf_driver); 1714 } 1715 1716 static void __exit nicvf_cleanup_module(void) 1717 { 1718 pci_unregister_driver(&nicvf_driver); 1719 } 1720 1721 module_init(nicvf_init_module); 1722 module_exit(nicvf_cleanup_module); 1723