1 /* 2 * Copyright (C) 2015 Cavium, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of version 2 of the GNU General Public License 6 * as published by the Free Software Foundation. 7 */ 8 9 #ifndef NIC_H 10 #define NIC_H 11 12 #include <linux/netdevice.h> 13 #include <linux/interrupt.h> 14 #include <linux/pci.h> 15 #include "thunder_bgx.h" 16 17 /* PCI device IDs */ 18 #define PCI_DEVICE_ID_THUNDER_NIC_PF 0xA01E 19 #define PCI_DEVICE_ID_THUNDER_PASS1_NIC_VF 0x0011 20 #define PCI_DEVICE_ID_THUNDER_NIC_VF 0xA034 21 #define PCI_DEVICE_ID_THUNDER_BGX 0xA026 22 23 /* PCI BAR nos */ 24 #define PCI_CFG_REG_BAR_NUM 0 25 #define PCI_MSIX_REG_BAR_NUM 4 26 27 /* NIC SRIOV VF count */ 28 #define MAX_NUM_VFS_SUPPORTED 128 29 #define DEFAULT_NUM_VF_ENABLED 8 30 31 #define NIC_TNS_BYPASS_MODE 0 32 #define NIC_TNS_MODE 1 33 34 /* NIC priv flags */ 35 #define NIC_SRIOV_ENABLED BIT(0) 36 37 /* Min/Max packet size */ 38 #define NIC_HW_MIN_FRS 64 39 #define NIC_HW_MAX_FRS 9200 /* 9216 max packet including FCS */ 40 41 /* Max pkinds */ 42 #define NIC_MAX_PKIND 16 43 44 /* Rx Channels */ 45 /* Receive channel configuration in TNS bypass mode 46 * Below is configuration in TNS bypass mode 47 * BGX0-LMAC0-CHAN0 - VNIC CHAN0 48 * BGX0-LMAC1-CHAN0 - VNIC CHAN16 49 * ... 50 * BGX1-LMAC0-CHAN0 - VNIC CHAN128 51 * ... 52 * BGX1-LMAC3-CHAN0 - VNIC CHAN174 53 */ 54 #define NIC_INTF_COUNT 2 /* Interfaces btw VNIC and TNS/BGX */ 55 #define NIC_CHANS_PER_INF 128 56 #define NIC_MAX_CHANS (NIC_INTF_COUNT * NIC_CHANS_PER_INF) 57 #define NIC_CPI_COUNT 2048 /* No of channel parse indices */ 58 59 /* TNS bypass mode: 1-1 mapping between VNIC and BGX:LMAC */ 60 #define NIC_MAX_BGX MAX_BGX_PER_CN88XX 61 #define NIC_CPI_PER_BGX (NIC_CPI_COUNT / NIC_MAX_BGX) 62 #define NIC_MAX_CPI_PER_LMAC 64 /* Max when CPI_ALG is IP diffserv */ 63 #define NIC_RSSI_PER_BGX (NIC_RSSI_COUNT / NIC_MAX_BGX) 64 65 /* Tx scheduling */ 66 #define NIC_MAX_TL4 1024 67 #define NIC_MAX_TL4_SHAPERS 256 /* 1 shaper for 4 TL4s */ 68 #define NIC_MAX_TL3 256 69 #define NIC_MAX_TL3_SHAPERS 64 /* 1 shaper for 4 TL3s */ 70 #define NIC_MAX_TL2 64 71 #define NIC_MAX_TL2_SHAPERS 2 /* 1 shaper for 32 TL2s */ 72 #define NIC_MAX_TL1 2 73 74 /* TNS bypass mode */ 75 #define NIC_TL2_PER_BGX 32 76 #define NIC_TL4_PER_BGX (NIC_MAX_TL4 / NIC_MAX_BGX) 77 #define NIC_TL4_PER_LMAC (NIC_MAX_TL4 / NIC_CHANS_PER_INF) 78 79 /* NIC VF Interrupts */ 80 #define NICVF_INTR_CQ 0 81 #define NICVF_INTR_SQ 1 82 #define NICVF_INTR_RBDR 2 83 #define NICVF_INTR_PKT_DROP 3 84 #define NICVF_INTR_TCP_TIMER 4 85 #define NICVF_INTR_MBOX 5 86 #define NICVF_INTR_QS_ERR 6 87 88 #define NICVF_INTR_CQ_SHIFT 0 89 #define NICVF_INTR_SQ_SHIFT 8 90 #define NICVF_INTR_RBDR_SHIFT 16 91 #define NICVF_INTR_PKT_DROP_SHIFT 20 92 #define NICVF_INTR_TCP_TIMER_SHIFT 21 93 #define NICVF_INTR_MBOX_SHIFT 22 94 #define NICVF_INTR_QS_ERR_SHIFT 23 95 96 #define NICVF_INTR_CQ_MASK (0xFF << NICVF_INTR_CQ_SHIFT) 97 #define NICVF_INTR_SQ_MASK (0xFF << NICVF_INTR_SQ_SHIFT) 98 #define NICVF_INTR_RBDR_MASK (0x03 << NICVF_INTR_RBDR_SHIFT) 99 #define NICVF_INTR_PKT_DROP_MASK BIT(NICVF_INTR_PKT_DROP_SHIFT) 100 #define NICVF_INTR_TCP_TIMER_MASK BIT(NICVF_INTR_TCP_TIMER_SHIFT) 101 #define NICVF_INTR_MBOX_MASK BIT(NICVF_INTR_MBOX_SHIFT) 102 #define NICVF_INTR_QS_ERR_MASK BIT(NICVF_INTR_QS_ERR_SHIFT) 103 104 /* MSI-X interrupts */ 105 #define NIC_PF_MSIX_VECTORS 10 106 #define NIC_VF_MSIX_VECTORS 20 107 108 #define NIC_PF_INTR_ID_ECC0_SBE 0 109 #define NIC_PF_INTR_ID_ECC0_DBE 1 110 #define NIC_PF_INTR_ID_ECC1_SBE 2 111 #define NIC_PF_INTR_ID_ECC1_DBE 3 112 #define NIC_PF_INTR_ID_ECC2_SBE 4 113 #define NIC_PF_INTR_ID_ECC2_DBE 5 114 #define NIC_PF_INTR_ID_ECC3_SBE 6 115 #define NIC_PF_INTR_ID_ECC3_DBE 7 116 #define NIC_PF_INTR_ID_MBOX0 8 117 #define NIC_PF_INTR_ID_MBOX1 9 118 119 /* Minimum FIFO level before all packets for the CQ are dropped 120 * 121 * This value ensures that once a packet has been "accepted" 122 * for reception it will not get dropped due to non-availability 123 * of CQ descriptor. An errata in HW mandates this value to be 124 * atleast 0x100. 125 */ 126 #define NICPF_CQM_MIN_DROP_LEVEL 0x100 127 128 /* Global timer for CQ timer thresh interrupts 129 * Calculated for SCLK of 700Mhz 130 * value written should be a 1/16th of what is expected 131 * 132 * 1 tick per 0.025usec 133 */ 134 #define NICPF_CLK_PER_INT_TICK 1 135 136 /* Time to wait before we decide that a SQ is stuck. 137 * 138 * Since both pkt rx and tx notifications are done with same CQ, 139 * when packets are being received at very high rate (eg: L2 forwarding) 140 * then freeing transmitted skbs will be delayed and watchdog 141 * will kick in, resetting interface. Hence keeping this value high. 142 */ 143 #define NICVF_TX_TIMEOUT (50 * HZ) 144 145 struct nicvf_cq_poll { 146 struct nicvf *nicvf; 147 u8 cq_idx; /* Completion queue index */ 148 struct napi_struct napi; 149 }; 150 151 #define NIC_RSSI_COUNT 4096 /* Total no of RSS indices */ 152 #define NIC_MAX_RSS_HASH_BITS 8 153 #define NIC_MAX_RSS_IDR_TBL_SIZE (1 << NIC_MAX_RSS_HASH_BITS) 154 #define RSS_HASH_KEY_SIZE 5 /* 320 bit key */ 155 156 struct nicvf_rss_info { 157 bool enable; 158 #define RSS_L2_EXTENDED_HASH_ENA BIT(0) 159 #define RSS_IP_HASH_ENA BIT(1) 160 #define RSS_TCP_HASH_ENA BIT(2) 161 #define RSS_TCP_SYN_DIS BIT(3) 162 #define RSS_UDP_HASH_ENA BIT(4) 163 #define RSS_L4_EXTENDED_HASH_ENA BIT(5) 164 #define RSS_ROCE_ENA BIT(6) 165 #define RSS_L3_BI_DIRECTION_ENA BIT(7) 166 #define RSS_L4_BI_DIRECTION_ENA BIT(8) 167 u64 cfg; 168 u8 hash_bits; 169 u16 rss_size; 170 u8 ind_tbl[NIC_MAX_RSS_IDR_TBL_SIZE]; 171 u64 key[RSS_HASH_KEY_SIZE]; 172 } ____cacheline_aligned_in_smp; 173 174 enum rx_stats_reg_offset { 175 RX_OCTS = 0x0, 176 RX_UCAST = 0x1, 177 RX_BCAST = 0x2, 178 RX_MCAST = 0x3, 179 RX_RED = 0x4, 180 RX_RED_OCTS = 0x5, 181 RX_ORUN = 0x6, 182 RX_ORUN_OCTS = 0x7, 183 RX_FCS = 0x8, 184 RX_L2ERR = 0x9, 185 RX_DRP_BCAST = 0xa, 186 RX_DRP_MCAST = 0xb, 187 RX_DRP_L3BCAST = 0xc, 188 RX_DRP_L3MCAST = 0xd, 189 RX_STATS_ENUM_LAST, 190 }; 191 192 enum tx_stats_reg_offset { 193 TX_OCTS = 0x0, 194 TX_UCAST = 0x1, 195 TX_BCAST = 0x2, 196 TX_MCAST = 0x3, 197 TX_DROP = 0x4, 198 TX_STATS_ENUM_LAST, 199 }; 200 201 struct nicvf_hw_stats { 202 u64 rx_bytes; 203 u64 rx_ucast_frames; 204 u64 rx_bcast_frames; 205 u64 rx_mcast_frames; 206 u64 rx_fcs_errors; 207 u64 rx_l2_errors; 208 u64 rx_drop_red; 209 u64 rx_drop_red_bytes; 210 u64 rx_drop_overrun; 211 u64 rx_drop_overrun_bytes; 212 u64 rx_drop_bcast; 213 u64 rx_drop_mcast; 214 u64 rx_drop_l3_bcast; 215 u64 rx_drop_l3_mcast; 216 u64 rx_bgx_truncated_pkts; 217 u64 rx_jabber_errs; 218 u64 rx_fcs_errs; 219 u64 rx_bgx_errs; 220 u64 rx_prel2_errs; 221 u64 rx_l2_hdr_malformed; 222 u64 rx_oversize; 223 u64 rx_undersize; 224 u64 rx_l2_len_mismatch; 225 u64 rx_l2_pclp; 226 u64 rx_ip_ver_errs; 227 u64 rx_ip_csum_errs; 228 u64 rx_ip_hdr_malformed; 229 u64 rx_ip_payload_malformed; 230 u64 rx_ip_ttl_errs; 231 u64 rx_l3_pclp; 232 u64 rx_l4_malformed; 233 u64 rx_l4_csum_errs; 234 u64 rx_udp_len_errs; 235 u64 rx_l4_port_errs; 236 u64 rx_tcp_flag_errs; 237 u64 rx_tcp_offset_errs; 238 u64 rx_l4_pclp; 239 u64 rx_truncated_pkts; 240 241 u64 tx_bytes_ok; 242 u64 tx_ucast_frames_ok; 243 u64 tx_bcast_frames_ok; 244 u64 tx_mcast_frames_ok; 245 u64 tx_drops; 246 }; 247 248 struct nicvf_drv_stats { 249 /* Rx */ 250 u64 rx_frames_ok; 251 u64 rx_frames_64; 252 u64 rx_frames_127; 253 u64 rx_frames_255; 254 u64 rx_frames_511; 255 u64 rx_frames_1023; 256 u64 rx_frames_1518; 257 u64 rx_frames_jumbo; 258 u64 rx_drops; 259 260 u64 rcv_buffer_alloc_failures; 261 262 /* Tx */ 263 u64 tx_frames_ok; 264 u64 tx_drops; 265 u64 tx_tso; 266 u64 tx_timeout; 267 u64 txq_stop; 268 u64 txq_wake; 269 }; 270 271 struct nicvf { 272 struct nicvf *pnicvf; 273 struct net_device *netdev; 274 struct pci_dev *pdev; 275 void __iomem *reg_base; 276 struct queue_set *qs; 277 struct nicvf_cq_poll *napi[8]; 278 u8 vf_id; 279 u8 sqs_id; 280 bool sqs_mode; 281 bool hw_tso; 282 283 /* Receive buffer alloc */ 284 u32 rb_page_offset; 285 u16 rb_pageref; 286 bool rb_alloc_fail; 287 bool rb_work_scheduled; 288 struct page *rb_page; 289 struct delayed_work rbdr_work; 290 struct tasklet_struct rbdr_task; 291 292 /* Secondary Qset */ 293 u8 sqs_count; 294 #define MAX_SQS_PER_VF_SINGLE_NODE 5 295 #define MAX_SQS_PER_VF 11 296 struct nicvf *snicvf[MAX_SQS_PER_VF]; 297 298 /* Queue count */ 299 u8 rx_queues; 300 u8 tx_queues; 301 u8 max_queues; 302 303 u8 node; 304 u8 cpi_alg; 305 u16 mtu; 306 bool link_up; 307 u8 duplex; 308 u32 speed; 309 bool tns_mode; 310 bool loopback_supported; 311 struct nicvf_rss_info rss_info; 312 struct tasklet_struct qs_err_task; 313 struct work_struct reset_task; 314 315 /* Interrupt coalescing settings */ 316 u32 cq_coalesce_usecs; 317 u32 msg_enable; 318 319 /* Stats */ 320 struct nicvf_hw_stats hw_stats; 321 struct nicvf_drv_stats drv_stats; 322 struct bgx_stats bgx_stats; 323 324 /* MSI-X */ 325 bool msix_enabled; 326 u8 num_vec; 327 struct msix_entry msix_entries[NIC_VF_MSIX_VECTORS]; 328 char irq_name[NIC_VF_MSIX_VECTORS][20]; 329 bool irq_allocated[NIC_VF_MSIX_VECTORS]; 330 cpumask_var_t affinity_mask[NIC_VF_MSIX_VECTORS]; 331 332 /* VF <-> PF mailbox communication */ 333 bool pf_acked; 334 bool pf_nacked; 335 bool set_mac_pending; 336 } ____cacheline_aligned_in_smp; 337 338 /* PF <--> VF Mailbox communication 339 * Eight 64bit registers are shared between PF and VF. 340 * Separate set for each VF. 341 * Writing '1' into last register mbx7 means end of message. 342 */ 343 344 /* PF <--> VF mailbox communication */ 345 #define NIC_PF_VF_MAILBOX_SIZE 2 346 #define NIC_MBOX_MSG_TIMEOUT 2000 /* ms */ 347 348 /* Mailbox message types */ 349 #define NIC_MBOX_MSG_READY 0x01 /* Is PF ready to rcv msgs */ 350 #define NIC_MBOX_MSG_ACK 0x02 /* ACK the message received */ 351 #define NIC_MBOX_MSG_NACK 0x03 /* NACK the message received */ 352 #define NIC_MBOX_MSG_QS_CFG 0x04 /* Configure Qset */ 353 #define NIC_MBOX_MSG_RQ_CFG 0x05 /* Configure receive queue */ 354 #define NIC_MBOX_MSG_SQ_CFG 0x06 /* Configure Send queue */ 355 #define NIC_MBOX_MSG_RQ_DROP_CFG 0x07 /* Configure receive queue */ 356 #define NIC_MBOX_MSG_SET_MAC 0x08 /* Add MAC ID to DMAC filter */ 357 #define NIC_MBOX_MSG_SET_MAX_FRS 0x09 /* Set max frame size */ 358 #define NIC_MBOX_MSG_CPI_CFG 0x0A /* Config CPI, RSSI */ 359 #define NIC_MBOX_MSG_RSS_SIZE 0x0B /* Get RSS indir_tbl size */ 360 #define NIC_MBOX_MSG_RSS_CFG 0x0C /* Config RSS table */ 361 #define NIC_MBOX_MSG_RSS_CFG_CONT 0x0D /* RSS config continuation */ 362 #define NIC_MBOX_MSG_RQ_BP_CFG 0x0E /* RQ backpressure config */ 363 #define NIC_MBOX_MSG_RQ_SW_SYNC 0x0F /* Flush inflight pkts to RQ */ 364 #define NIC_MBOX_MSG_BGX_STATS 0x10 /* Get stats from BGX */ 365 #define NIC_MBOX_MSG_BGX_LINK_CHANGE 0x11 /* BGX:LMAC link status */ 366 #define NIC_MBOX_MSG_ALLOC_SQS 0x12 /* Allocate secondary Qset */ 367 #define NIC_MBOX_MSG_NICVF_PTR 0x13 /* Send nicvf ptr to PF */ 368 #define NIC_MBOX_MSG_PNICVF_PTR 0x14 /* Get primary qset nicvf ptr */ 369 #define NIC_MBOX_MSG_SNICVF_PTR 0x15 /* Send sqet nicvf ptr to PVF */ 370 #define NIC_MBOX_MSG_LOOPBACK 0x16 /* Set interface in loopback */ 371 #define NIC_MBOX_MSG_CFG_DONE 0xF0 /* VF configuration done */ 372 #define NIC_MBOX_MSG_SHUTDOWN 0xF1 /* VF is being shutdown */ 373 374 struct nic_cfg_msg { 375 u8 msg; 376 u8 vf_id; 377 u8 node_id; 378 u8 tns_mode:1; 379 u8 sqs_mode:1; 380 u8 loopback_supported:1; 381 u8 mac_addr[ETH_ALEN]; 382 }; 383 384 /* Qset configuration */ 385 struct qs_cfg_msg { 386 u8 msg; 387 u8 num; 388 u8 sqs_count; 389 u64 cfg; 390 }; 391 392 /* Receive queue configuration */ 393 struct rq_cfg_msg { 394 u8 msg; 395 u8 qs_num; 396 u8 rq_num; 397 u64 cfg; 398 }; 399 400 /* Send queue configuration */ 401 struct sq_cfg_msg { 402 u8 msg; 403 u8 qs_num; 404 u8 sq_num; 405 bool sqs_mode; 406 u64 cfg; 407 }; 408 409 /* Set VF's MAC address */ 410 struct set_mac_msg { 411 u8 msg; 412 u8 vf_id; 413 u8 mac_addr[ETH_ALEN]; 414 }; 415 416 /* Set Maximum frame size */ 417 struct set_frs_msg { 418 u8 msg; 419 u8 vf_id; 420 u16 max_frs; 421 }; 422 423 /* Set CPI algorithm type */ 424 struct cpi_cfg_msg { 425 u8 msg; 426 u8 vf_id; 427 u8 rq_cnt; 428 u8 cpi_alg; 429 }; 430 431 /* Get RSS table size */ 432 struct rss_sz_msg { 433 u8 msg; 434 u8 vf_id; 435 u16 ind_tbl_size; 436 }; 437 438 /* Set RSS configuration */ 439 struct rss_cfg_msg { 440 u8 msg; 441 u8 vf_id; 442 u8 hash_bits; 443 u8 tbl_len; 444 u8 tbl_offset; 445 #define RSS_IND_TBL_LEN_PER_MBX_MSG 8 446 u8 ind_tbl[RSS_IND_TBL_LEN_PER_MBX_MSG]; 447 }; 448 449 struct bgx_stats_msg { 450 u8 msg; 451 u8 vf_id; 452 u8 rx; 453 u8 idx; 454 u64 stats; 455 }; 456 457 /* Physical interface link status */ 458 struct bgx_link_status { 459 u8 msg; 460 u8 link_up; 461 u8 duplex; 462 u32 speed; 463 }; 464 465 /* Get Extra Qset IDs */ 466 struct sqs_alloc { 467 u8 msg; 468 u8 vf_id; 469 u8 qs_count; 470 }; 471 472 struct nicvf_ptr { 473 u8 msg; 474 u8 vf_id; 475 bool sqs_mode; 476 u8 sqs_id; 477 u64 nicvf; 478 }; 479 480 /* Set interface in loopback mode */ 481 struct set_loopback { 482 u8 msg; 483 u8 vf_id; 484 bool enable; 485 }; 486 487 /* 128 bit shared memory between PF and each VF */ 488 union nic_mbx { 489 struct { u8 msg; } msg; 490 struct nic_cfg_msg nic_cfg; 491 struct qs_cfg_msg qs; 492 struct rq_cfg_msg rq; 493 struct sq_cfg_msg sq; 494 struct set_mac_msg mac; 495 struct set_frs_msg frs; 496 struct cpi_cfg_msg cpi_cfg; 497 struct rss_sz_msg rss_size; 498 struct rss_cfg_msg rss_cfg; 499 struct bgx_stats_msg bgx_stats; 500 struct bgx_link_status link_status; 501 struct sqs_alloc sqs_alloc; 502 struct nicvf_ptr nicvf; 503 struct set_loopback lbk; 504 }; 505 506 #define NIC_NODE_ID_MASK 0x03 507 #define NIC_NODE_ID_SHIFT 44 508 509 static inline int nic_get_node_id(struct pci_dev *pdev) 510 { 511 u64 addr = pci_resource_start(pdev, PCI_CFG_REG_BAR_NUM); 512 return ((addr >> NIC_NODE_ID_SHIFT) & NIC_NODE_ID_MASK); 513 } 514 515 static inline bool pass1_silicon(struct pci_dev *pdev) 516 { 517 return pdev->revision < 8; 518 } 519 520 int nicvf_set_real_num_queues(struct net_device *netdev, 521 int tx_queues, int rx_queues); 522 int nicvf_open(struct net_device *netdev); 523 int nicvf_stop(struct net_device *netdev); 524 int nicvf_send_msg_to_pf(struct nicvf *vf, union nic_mbx *mbx); 525 void nicvf_config_rss(struct nicvf *nic); 526 void nicvf_set_rss_key(struct nicvf *nic); 527 void nicvf_set_ethtool_ops(struct net_device *netdev); 528 void nicvf_update_stats(struct nicvf *nic); 529 void nicvf_update_lmac_stats(struct nicvf *nic); 530 531 #endif /* NIC_H */ 532