1 /********************************************************************** 2 * Author: Cavium, Inc. 3 * 4 * Contact: support@cavium.com 5 * Please include "LiquidIO" in the subject. 6 * 7 * Copyright (c) 2003-2016 Cavium, Inc. 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more details. 17 ***********************************************************************/ 18 /*! \file liquidio_common.h 19 * \brief Common: Structures and macros used in PCI-NIC package by core and 20 * host driver. 21 */ 22 23 #ifndef __LIQUIDIO_COMMON_H__ 24 #define __LIQUIDIO_COMMON_H__ 25 26 #include "octeon_config.h" 27 28 #define LIQUIDIO_PACKAGE "" 29 #define LIQUIDIO_BASE_MAJOR_VERSION 1 30 #define LIQUIDIO_BASE_MINOR_VERSION 7 31 #define LIQUIDIO_BASE_MICRO_VERSION 2 32 #define LIQUIDIO_BASE_VERSION __stringify(LIQUIDIO_BASE_MAJOR_VERSION) "." \ 33 __stringify(LIQUIDIO_BASE_MINOR_VERSION) 34 #define LIQUIDIO_MICRO_VERSION "." __stringify(LIQUIDIO_BASE_MICRO_VERSION) 35 #define LIQUIDIO_VERSION LIQUIDIO_PACKAGE \ 36 __stringify(LIQUIDIO_BASE_MAJOR_VERSION) "." \ 37 __stringify(LIQUIDIO_BASE_MINOR_VERSION) \ 38 "." __stringify(LIQUIDIO_BASE_MICRO_VERSION) 39 40 struct lio_version { 41 u16 major; 42 u16 minor; 43 u16 micro; 44 u16 reserved; 45 }; 46 47 #define CONTROL_IQ 0 48 /** Tag types used by Octeon cores in its work. */ 49 enum octeon_tag_type { 50 ORDERED_TAG = 0, 51 ATOMIC_TAG = 1, 52 NULL_TAG = 2, 53 NULL_NULL_TAG = 3 54 }; 55 56 /* pre-defined host->NIC tag values */ 57 #define LIO_CONTROL (0x11111110) 58 #define LIO_DATA(i) (0x11111111 + (i)) 59 60 /* Opcodes used by host driver/apps to perform operations on the core. 61 * These are used to identify the major subsystem that the operation 62 * is for. 63 */ 64 #define OPCODE_CORE 0 /* used for generic core operations */ 65 #define OPCODE_NIC 1 /* used for NIC operations */ 66 /* Subcodes are used by host driver/apps to identify the sub-operation 67 * for the core. They only need to by unique for a given subsystem. 68 */ 69 #define OPCODE_SUBCODE(op, sub) ((((op) & 0x0f) << 8) | ((sub) & 0x7f)) 70 71 /** OPCODE_CORE subcodes. For future use. */ 72 73 /** OPCODE_NIC subcodes */ 74 75 /* This subcode is sent by core PCI driver to indicate cores are ready. */ 76 #define OPCODE_NIC_CORE_DRV_ACTIVE 0x01 77 #define OPCODE_NIC_NW_DATA 0x02 /* network packet data */ 78 #define OPCODE_NIC_CMD 0x03 79 #define OPCODE_NIC_INFO 0x04 80 #define OPCODE_NIC_PORT_STATS 0x05 81 #define OPCODE_NIC_MDIO45 0x06 82 #define OPCODE_NIC_TIMESTAMP 0x07 83 #define OPCODE_NIC_INTRMOD_CFG 0x08 84 #define OPCODE_NIC_IF_CFG 0x09 85 #define OPCODE_NIC_VF_DRV_NOTICE 0x0A 86 #define OPCODE_NIC_INTRMOD_PARAMS 0x0B 87 #define OPCODE_NIC_QCOUNT_UPDATE 0x12 88 #define OPCODE_NIC_SET_TRUSTED_VF 0x13 89 #define OPCODE_NIC_SYNC_OCTEON_TIME 0x14 90 #define VF_DRV_LOADED 1 91 #define VF_DRV_REMOVED -1 92 #define VF_DRV_MACADDR_CHANGED 2 93 94 #define OPCODE_NIC_VF_REP_PKT 0x15 95 #define OPCODE_NIC_VF_REP_CMD 0x16 96 #define OPCODE_NIC_UBOOT_CTL 0x17 97 98 #define CORE_DRV_TEST_SCATTER_OP 0xFFF5 99 100 /* Application codes advertised by the core driver initialization packet. */ 101 #define CVM_DRV_APP_START 0x0 102 #define CVM_DRV_NO_APP 0 103 #define CVM_DRV_APP_COUNT 0x2 104 #define CVM_DRV_BASE_APP (CVM_DRV_APP_START + 0x0) 105 #define CVM_DRV_NIC_APP (CVM_DRV_APP_START + 0x1) 106 #define CVM_DRV_INVALID_APP (CVM_DRV_APP_START + 0x2) 107 #define CVM_DRV_APP_END (CVM_DRV_INVALID_APP - 1) 108 109 #define BYTES_PER_DHLEN_UNIT 8 110 #define MAX_REG_CNT 2000000U 111 #define INTRNAMSIZ 32 112 #define IRQ_NAME_OFF(i) ((i) * INTRNAMSIZ) 113 #define MAX_IOQ_INTERRUPTS_PER_PF (64 * 2) 114 #define MAX_IOQ_INTERRUPTS_PER_VF (8 * 2) 115 116 #define SCR2_BIT_FW_LOADED 63 117 118 /* App specific capabilities from firmware to pf driver */ 119 #define LIQUIDIO_TIME_SYNC_CAP 0x1 120 #define LIQUIDIO_SWITCHDEV_CAP 0x2 121 122 static inline u32 incr_index(u32 index, u32 count, u32 max) 123 { 124 if ((index + count) >= max) 125 index = index + count - max; 126 else 127 index += count; 128 129 return index; 130 } 131 132 #define OCT_BOARD_NAME 32 133 #define OCT_SERIAL_LEN 64 134 135 /* Structure used by core driver to send indication that the Octeon 136 * application is ready. 137 */ 138 struct octeon_core_setup { 139 u64 corefreq; 140 141 char boardname[OCT_BOARD_NAME]; 142 143 char board_serial_number[OCT_SERIAL_LEN]; 144 145 u64 board_rev_major; 146 147 u64 board_rev_minor; 148 149 }; 150 151 /*--------------------------- SCATTER GATHER ENTRY -----------------------*/ 152 153 /* The Scatter-Gather List Entry. The scatter or gather component used with 154 * a Octeon input instruction has this format. 155 */ 156 struct octeon_sg_entry { 157 /** The first 64 bit gives the size of data in each dptr.*/ 158 union { 159 u16 size[4]; 160 u64 size64; 161 } u; 162 163 /** The 4 dptr pointers for this entry. */ 164 u64 ptr[4]; 165 166 }; 167 168 #define OCT_SG_ENTRY_SIZE (sizeof(struct octeon_sg_entry)) 169 170 /* \brief Add size to gather list 171 * @param sg_entry scatter/gather entry 172 * @param size size to add 173 * @param pos position to add it. 174 */ 175 static inline void add_sg_size(struct octeon_sg_entry *sg_entry, 176 u16 size, 177 u32 pos) 178 { 179 #ifdef __BIG_ENDIAN_BITFIELD 180 sg_entry->u.size[pos] = size; 181 #else 182 sg_entry->u.size[3 - pos] = size; 183 #endif 184 } 185 186 /*------------------------- End Scatter/Gather ---------------------------*/ 187 188 #define OCTNET_FRM_LENGTH_SIZE 8 189 190 #define OCTNET_FRM_PTP_HEADER_SIZE 8 191 192 #define OCTNET_FRM_HEADER_SIZE 22 /* VLAN + Ethernet */ 193 194 #define OCTNET_MIN_FRM_SIZE 64 195 196 #define OCTNET_MAX_FRM_SIZE (16000 + OCTNET_FRM_HEADER_SIZE) 197 198 #define OCTNET_DEFAULT_MTU (1500) 199 #define OCTNET_DEFAULT_FRM_SIZE (OCTNET_DEFAULT_MTU + OCTNET_FRM_HEADER_SIZE) 200 201 /** NIC Commands are sent using this Octeon Input Queue */ 202 #define OCTNET_CMD_Q 0 203 204 /* NIC Command types */ 205 #define OCTNET_CMD_CHANGE_MTU 0x1 206 #define OCTNET_CMD_CHANGE_MACADDR 0x2 207 #define OCTNET_CMD_CHANGE_DEVFLAGS 0x3 208 #define OCTNET_CMD_RX_CTL 0x4 209 210 #define OCTNET_CMD_SET_MULTI_LIST 0x5 211 #define OCTNET_CMD_CLEAR_STATS 0x6 212 213 /* command for setting the speed, duplex & autoneg */ 214 #define OCTNET_CMD_SET_SETTINGS 0x7 215 #define OCTNET_CMD_SET_FLOW_CTL 0x8 216 217 #define OCTNET_CMD_MDIO_READ_WRITE 0x9 218 #define OCTNET_CMD_GPIO_ACCESS 0xA 219 #define OCTNET_CMD_LRO_ENABLE 0xB 220 #define OCTNET_CMD_LRO_DISABLE 0xC 221 #define OCTNET_CMD_SET_RSS 0xD 222 #define OCTNET_CMD_WRITE_SA 0xE 223 #define OCTNET_CMD_DELETE_SA 0xF 224 #define OCTNET_CMD_UPDATE_SA 0x12 225 226 #define OCTNET_CMD_TNL_RX_CSUM_CTL 0x10 227 #define OCTNET_CMD_TNL_TX_CSUM_CTL 0x11 228 #define OCTNET_CMD_IPSECV2_AH_ESP_CTL 0x13 229 #define OCTNET_CMD_VERBOSE_ENABLE 0x14 230 #define OCTNET_CMD_VERBOSE_DISABLE 0x15 231 232 #define OCTNET_CMD_VLAN_FILTER_CTL 0x16 233 #define OCTNET_CMD_ADD_VLAN_FILTER 0x17 234 #define OCTNET_CMD_DEL_VLAN_FILTER 0x18 235 #define OCTNET_CMD_VXLAN_PORT_CONFIG 0x19 236 237 #define OCTNET_CMD_ID_ACTIVE 0x1a 238 239 #define OCTNET_CMD_SET_UC_LIST 0x1b 240 #define OCTNET_CMD_SET_VF_LINKSTATE 0x1c 241 242 #define OCTNET_CMD_QUEUE_COUNT_CTL 0x1f 243 244 #define OCTNET_CMD_VXLAN_PORT_ADD 0x0 245 #define OCTNET_CMD_VXLAN_PORT_DEL 0x1 246 #define OCTNET_CMD_RXCSUM_ENABLE 0x0 247 #define OCTNET_CMD_RXCSUM_DISABLE 0x1 248 #define OCTNET_CMD_TXCSUM_ENABLE 0x0 249 #define OCTNET_CMD_TXCSUM_DISABLE 0x1 250 #define OCTNET_CMD_VLAN_FILTER_ENABLE 0x1 251 #define OCTNET_CMD_VLAN_FILTER_DISABLE 0x0 252 253 #define OCTNET_CMD_FAIL 0x1 254 255 #define SEAPI_CMD_SPEED_SET 0x2 256 #define SEAPI_CMD_SPEED_GET 0x3 257 258 #define LIO_CMD_WAIT_TM 100 259 260 /* RX(packets coming from wire) Checksum verification flags */ 261 /* TCP/UDP csum */ 262 #define CNNIC_L4SUM_VERIFIED 0x1 263 #define CNNIC_IPSUM_VERIFIED 0x2 264 #define CNNIC_TUN_CSUM_VERIFIED 0x4 265 #define CNNIC_CSUM_VERIFIED (CNNIC_IPSUM_VERIFIED | CNNIC_L4SUM_VERIFIED) 266 267 /*LROIPV4 and LROIPV6 Flags*/ 268 #define OCTNIC_LROIPV4 0x1 269 #define OCTNIC_LROIPV6 0x2 270 271 /* Interface flags communicated between host driver and core app. */ 272 enum octnet_ifflags { 273 OCTNET_IFFLAG_PROMISC = 0x01, 274 OCTNET_IFFLAG_ALLMULTI = 0x02, 275 OCTNET_IFFLAG_MULTICAST = 0x04, 276 OCTNET_IFFLAG_BROADCAST = 0x08, 277 OCTNET_IFFLAG_UNICAST = 0x10 278 }; 279 280 /* wqe 281 * --------------- 0 282 * | wqe word0-3 | 283 * --------------- 32 284 * | PCI IH | 285 * --------------- 40 286 * | RPTR | 287 * --------------- 48 288 * | PCI IRH | 289 * --------------- 56 290 * | OCT_NET_CMD | 291 * --------------- 64 292 * | Addtl 8-BData | 293 * | | 294 * --------------- 295 */ 296 297 union octnet_cmd { 298 u64 u64; 299 300 struct { 301 #ifdef __BIG_ENDIAN_BITFIELD 302 u64 cmd:5; 303 304 u64 more:6; /* How many udd words follow the command */ 305 306 u64 reserved:29; 307 308 u64 param1:16; 309 310 u64 param2:8; 311 312 #else 313 314 u64 param2:8; 315 316 u64 param1:16; 317 318 u64 reserved:29; 319 320 u64 more:6; 321 322 u64 cmd:5; 323 324 #endif 325 } s; 326 327 }; 328 329 #define OCTNET_CMD_SIZE (sizeof(union octnet_cmd)) 330 331 /*pkiih3 + irh + ossp[0] + ossp[1] + rdp + rptr = 40 bytes */ 332 #define LIO_SOFTCMDRESP_IH2 40 333 #define LIO_SOFTCMDRESP_IH3 (40 + 8) 334 335 #define LIO_PCICMD_O2 24 336 #define LIO_PCICMD_O3 (24 + 8) 337 338 /* Instruction Header(DPI) - for OCTEON-III models */ 339 struct octeon_instr_ih3 { 340 #ifdef __BIG_ENDIAN_BITFIELD 341 342 /** Reserved3 */ 343 u64 reserved3:1; 344 345 /** Gather indicator 1=gather*/ 346 u64 gather:1; 347 348 /** Data length OR no. of entries in gather list */ 349 u64 dlengsz:14; 350 351 /** Front Data size */ 352 u64 fsz:6; 353 354 /** Reserved2 */ 355 u64 reserved2:4; 356 357 /** PKI port kind - PKIND */ 358 u64 pkind:6; 359 360 /** Reserved1 */ 361 u64 reserved1:32; 362 363 #else 364 /** Reserved1 */ 365 u64 reserved1:32; 366 367 /** PKI port kind - PKIND */ 368 u64 pkind:6; 369 370 /** Reserved2 */ 371 u64 reserved2:4; 372 373 /** Front Data size */ 374 u64 fsz:6; 375 376 /** Data length OR no. of entries in gather list */ 377 u64 dlengsz:14; 378 379 /** Gather indicator 1=gather*/ 380 u64 gather:1; 381 382 /** Reserved3 */ 383 u64 reserved3:1; 384 385 #endif 386 }; 387 388 /* Optional PKI Instruction Header(PKI IH) - for OCTEON-III models */ 389 /** BIG ENDIAN format. */ 390 struct octeon_instr_pki_ih3 { 391 #ifdef __BIG_ENDIAN_BITFIELD 392 393 /** Wider bit */ 394 u64 w:1; 395 396 /** Raw mode indicator 1 = RAW */ 397 u64 raw:1; 398 399 /** Use Tag */ 400 u64 utag:1; 401 402 /** Use QPG */ 403 u64 uqpg:1; 404 405 /** Reserved2 */ 406 u64 reserved2:1; 407 408 /** Parse Mode */ 409 u64 pm:3; 410 411 /** Skip Length */ 412 u64 sl:8; 413 414 /** Use Tag Type */ 415 u64 utt:1; 416 417 /** Tag type */ 418 u64 tagtype:2; 419 420 /** Reserved1 */ 421 u64 reserved1:2; 422 423 /** QPG Value */ 424 u64 qpg:11; 425 426 /** Tag Value */ 427 u64 tag:32; 428 429 #else 430 431 /** Tag Value */ 432 u64 tag:32; 433 434 /** QPG Value */ 435 u64 qpg:11; 436 437 /** Reserved1 */ 438 u64 reserved1:2; 439 440 /** Tag type */ 441 u64 tagtype:2; 442 443 /** Use Tag Type */ 444 u64 utt:1; 445 446 /** Skip Length */ 447 u64 sl:8; 448 449 /** Parse Mode */ 450 u64 pm:3; 451 452 /** Reserved2 */ 453 u64 reserved2:1; 454 455 /** Use QPG */ 456 u64 uqpg:1; 457 458 /** Use Tag */ 459 u64 utag:1; 460 461 /** Raw mode indicator 1 = RAW */ 462 u64 raw:1; 463 464 /** Wider bit */ 465 u64 w:1; 466 #endif 467 468 }; 469 470 /** Instruction Header */ 471 struct octeon_instr_ih2 { 472 #ifdef __BIG_ENDIAN_BITFIELD 473 /** Raw mode indicator 1 = RAW */ 474 u64 raw:1; 475 476 /** Gather indicator 1=gather*/ 477 u64 gather:1; 478 479 /** Data length OR no. of entries in gather list */ 480 u64 dlengsz:14; 481 482 /** Front Data size */ 483 u64 fsz:6; 484 485 /** Packet Order / Work Unit selection (1 of 8)*/ 486 u64 qos:3; 487 488 /** Core group selection (1 of 16) */ 489 u64 grp:4; 490 491 /** Short Raw Packet Indicator 1=short raw pkt */ 492 u64 rs:1; 493 494 /** Tag type */ 495 u64 tagtype:2; 496 497 /** Tag Value */ 498 u64 tag:32; 499 #else 500 /** Tag Value */ 501 u64 tag:32; 502 503 /** Tag type */ 504 u64 tagtype:2; 505 506 /** Short Raw Packet Indicator 1=short raw pkt */ 507 u64 rs:1; 508 509 /** Core group selection (1 of 16) */ 510 u64 grp:4; 511 512 /** Packet Order / Work Unit selection (1 of 8)*/ 513 u64 qos:3; 514 515 /** Front Data size */ 516 u64 fsz:6; 517 518 /** Data length OR no. of entries in gather list */ 519 u64 dlengsz:14; 520 521 /** Gather indicator 1=gather*/ 522 u64 gather:1; 523 524 /** Raw mode indicator 1 = RAW */ 525 u64 raw:1; 526 #endif 527 }; 528 529 /** Input Request Header */ 530 struct octeon_instr_irh { 531 #ifdef __BIG_ENDIAN_BITFIELD 532 u64 opcode:4; 533 u64 rflag:1; 534 u64 subcode:7; 535 u64 vlan:12; 536 u64 priority:3; 537 u64 reserved:5; 538 u64 ossp:32; /* opcode/subcode specific parameters */ 539 #else 540 u64 ossp:32; /* opcode/subcode specific parameters */ 541 u64 reserved:5; 542 u64 priority:3; 543 u64 vlan:12; 544 u64 subcode:7; 545 u64 rflag:1; 546 u64 opcode:4; 547 #endif 548 }; 549 550 /** Return Data Parameters */ 551 struct octeon_instr_rdp { 552 #ifdef __BIG_ENDIAN_BITFIELD 553 u64 reserved:49; 554 u64 pcie_port:3; 555 u64 rlen:12; 556 #else 557 u64 rlen:12; 558 u64 pcie_port:3; 559 u64 reserved:49; 560 #endif 561 }; 562 563 /** Receive Header */ 564 union octeon_rh { 565 #ifdef __BIG_ENDIAN_BITFIELD 566 u64 u64; 567 struct { 568 u64 opcode:4; 569 u64 subcode:8; 570 u64 len:3; /** additional 64-bit words */ 571 u64 reserved:17; 572 u64 ossp:32; /** opcode/subcode specific parameters */ 573 } r; 574 struct { 575 u64 opcode:4; 576 u64 subcode:8; 577 u64 len:3; /** additional 64-bit words */ 578 u64 extra:28; 579 u64 vlan:12; 580 u64 priority:3; 581 u64 csum_verified:3; /** checksum verified. */ 582 u64 has_hwtstamp:1; /** Has hardware timestamp. 1 = yes. */ 583 u64 encap_on:1; 584 u64 has_hash:1; /** Has hash (rth or rss). 1 = yes. */ 585 } r_dh; 586 struct { 587 u64 opcode:4; 588 u64 subcode:8; 589 u64 len:3; /** additional 64-bit words */ 590 u64 reserved:11; 591 u64 num_gmx_ports:8; 592 u64 max_nic_ports:10; 593 u64 app_cap_flags:4; 594 u64 app_mode:8; 595 u64 pkind:8; 596 } r_core_drv_init; 597 struct { 598 u64 opcode:4; 599 u64 subcode:8; 600 u64 len:3; /** additional 64-bit words */ 601 u64 reserved:8; 602 u64 extra:25; 603 u64 gmxport:16; 604 } r_nic_info; 605 #else 606 u64 u64; 607 struct { 608 u64 ossp:32; /** opcode/subcode specific parameters */ 609 u64 reserved:17; 610 u64 len:3; /** additional 64-bit words */ 611 u64 subcode:8; 612 u64 opcode:4; 613 } r; 614 struct { 615 u64 has_hash:1; /** Has hash (rth or rss). 1 = yes. */ 616 u64 encap_on:1; 617 u64 has_hwtstamp:1; /** 1 = has hwtstamp */ 618 u64 csum_verified:3; /** checksum verified. */ 619 u64 priority:3; 620 u64 vlan:12; 621 u64 extra:28; 622 u64 len:3; /** additional 64-bit words */ 623 u64 subcode:8; 624 u64 opcode:4; 625 } r_dh; 626 struct { 627 u64 pkind:8; 628 u64 app_mode:8; 629 u64 app_cap_flags:4; 630 u64 max_nic_ports:10; 631 u64 num_gmx_ports:8; 632 u64 reserved:11; 633 u64 len:3; /** additional 64-bit words */ 634 u64 subcode:8; 635 u64 opcode:4; 636 } r_core_drv_init; 637 struct { 638 u64 gmxport:16; 639 u64 extra:25; 640 u64 reserved:8; 641 u64 len:3; /** additional 64-bit words */ 642 u64 subcode:8; 643 u64 opcode:4; 644 } r_nic_info; 645 #endif 646 }; 647 648 #define OCT_RH_SIZE (sizeof(union octeon_rh)) 649 650 union octnic_packet_params { 651 u32 u32; 652 struct { 653 #ifdef __BIG_ENDIAN_BITFIELD 654 u32 reserved:24; 655 u32 ip_csum:1; /* Perform IP header checksum(s) */ 656 /* Perform Outer transport header checksum */ 657 u32 transport_csum:1; 658 /* Find tunnel, and perform transport csum. */ 659 u32 tnl_csum:1; 660 u32 tsflag:1; /* Timestamp this packet */ 661 u32 ipsec_ops:4; /* IPsec operation */ 662 #else 663 u32 ipsec_ops:4; 664 u32 tsflag:1; 665 u32 tnl_csum:1; 666 u32 transport_csum:1; 667 u32 ip_csum:1; 668 u32 reserved:24; 669 #endif 670 } s; 671 }; 672 673 /** Status of a RGMII Link on Octeon as seen by core driver. */ 674 union oct_link_status { 675 u64 u64; 676 677 struct { 678 #ifdef __BIG_ENDIAN_BITFIELD 679 u64 duplex:8; 680 u64 mtu:16; 681 u64 speed:16; 682 u64 link_up:1; 683 u64 autoneg:1; 684 u64 if_mode:5; 685 u64 pause:1; 686 u64 flashing:1; 687 u64 phy_type:5; 688 u64 reserved:10; 689 #else 690 u64 reserved:10; 691 u64 phy_type:5; 692 u64 flashing:1; 693 u64 pause:1; 694 u64 if_mode:5; 695 u64 autoneg:1; 696 u64 link_up:1; 697 u64 speed:16; 698 u64 mtu:16; 699 u64 duplex:8; 700 #endif 701 } s; 702 }; 703 704 enum lio_phy_type { 705 LIO_PHY_PORT_TP = 0x0, 706 LIO_PHY_PORT_FIBRE = 0x1, 707 LIO_PHY_PORT_UNKNOWN, 708 }; 709 710 /** The txpciq info passed to host from the firmware */ 711 712 union oct_txpciq { 713 u64 u64; 714 715 struct { 716 #ifdef __BIG_ENDIAN_BITFIELD 717 u64 q_no:8; 718 u64 port:8; 719 u64 pkind:6; 720 u64 use_qpg:1; 721 u64 qpg:11; 722 u64 reserved0:10; 723 u64 ctrl_qpg:11; 724 u64 reserved:9; 725 #else 726 u64 reserved:9; 727 u64 ctrl_qpg:11; 728 u64 reserved0:10; 729 u64 qpg:11; 730 u64 use_qpg:1; 731 u64 pkind:6; 732 u64 port:8; 733 u64 q_no:8; 734 #endif 735 } s; 736 }; 737 738 /** The rxpciq info passed to host from the firmware */ 739 740 union oct_rxpciq { 741 u64 u64; 742 743 struct { 744 #ifdef __BIG_ENDIAN_BITFIELD 745 u64 q_no:8; 746 u64 reserved:56; 747 #else 748 u64 reserved:56; 749 u64 q_no:8; 750 #endif 751 } s; 752 }; 753 754 /** Information for a OCTEON ethernet interface shared between core & host. */ 755 struct oct_link_info { 756 union oct_link_status link; 757 u64 hw_addr; 758 759 #ifdef __BIG_ENDIAN_BITFIELD 760 u64 gmxport:16; 761 u64 macaddr_is_admin_asgnd:1; 762 u64 rsvd:31; 763 u64 num_txpciq:8; 764 u64 num_rxpciq:8; 765 #else 766 u64 num_rxpciq:8; 767 u64 num_txpciq:8; 768 u64 rsvd:31; 769 u64 macaddr_is_admin_asgnd:1; 770 u64 gmxport:16; 771 #endif 772 773 union oct_txpciq txpciq[MAX_IOQS_PER_NICIF]; 774 union oct_rxpciq rxpciq[MAX_IOQS_PER_NICIF]; 775 }; 776 777 #define OCT_LINK_INFO_SIZE (sizeof(struct oct_link_info)) 778 779 struct liquidio_if_cfg_info { 780 u64 iqmask; /** mask for IQs enabled for the port */ 781 u64 oqmask; /** mask for OQs enabled for the port */ 782 struct oct_link_info linfo; /** initial link information */ 783 char liquidio_firmware_version[32]; 784 }; 785 786 /** Stats for each NIC port in RX direction. */ 787 struct nic_rx_stats { 788 /* link-level stats */ 789 u64 total_rcvd; /* Received packets */ 790 u64 bytes_rcvd; /* Octets of received packets */ 791 u64 total_bcst; /* Number of non-dropped L2 broadcast packets */ 792 u64 total_mcst; /* Number of non-dropped L2 multicast packets */ 793 u64 runts; /* Packets shorter than allowed */ 794 u64 ctl_rcvd; /* Received PAUSE packets */ 795 u64 fifo_err; /* Packets dropped due to RX FIFO full */ 796 u64 dmac_drop; /* Packets dropped by the DMAC filter */ 797 u64 fcs_err; /* Sum of fragment, overrun, and FCS errors */ 798 u64 jabber_err; /* Packets larger than allowed */ 799 u64 l2_err; /* Sum of DMA, parity, PCAM access, no memory, 800 * buffer overflow, malformed L2 header or 801 * length, oversize errors 802 **/ 803 u64 frame_err; /* Sum of IPv4 and L4 checksum errors */ 804 u64 red_drops; /* Packets dropped by RED due to buffer 805 * exhaustion 806 **/ 807 808 /* firmware stats */ 809 u64 fw_total_rcvd; 810 u64 fw_total_fwd; 811 u64 fw_total_fwd_bytes; 812 u64 fw_total_mcast; 813 u64 fw_total_bcast; 814 815 u64 fw_err_pko; 816 u64 fw_err_link; 817 u64 fw_err_drop; 818 u64 fw_rx_vxlan; 819 u64 fw_rx_vxlan_err; 820 821 /* LRO */ 822 u64 fw_lro_pkts; /* Number of packets that are LROed */ 823 u64 fw_lro_octs; /* Number of octets that are LROed */ 824 u64 fw_total_lro; /* Number of LRO packets formed */ 825 u64 fw_lro_aborts; /* Number of times LRO of packet aborted */ 826 u64 fw_lro_aborts_port; 827 u64 fw_lro_aborts_seq; 828 u64 fw_lro_aborts_tsval; 829 u64 fw_lro_aborts_timer; /* Timer setting error */ 830 /* intrmod: packet forward rate */ 831 u64 fwd_rate; 832 }; 833 834 /** Stats for each NIC port in RX direction. */ 835 struct nic_tx_stats { 836 /* link-level stats */ 837 u64 total_pkts_sent; /* Total frames sent on the interface */ 838 u64 total_bytes_sent; /* Total octets sent on the interface */ 839 u64 mcast_pkts_sent; /* Packets sent to the multicast DMAC */ 840 u64 bcast_pkts_sent; /* Packets sent to a broadcast DMAC */ 841 u64 ctl_sent; /* Control/PAUSE packets sent */ 842 u64 one_collision_sent; /* Packets sent that experienced a 843 * single collision before successful 844 * transmission 845 **/ 846 u64 multi_collision_sent; /* Packets sent that experienced 847 * multiple collisions before successful 848 * transmission 849 **/ 850 u64 max_collision_fail; /* Packets dropped due to excessive 851 * collisions 852 **/ 853 u64 max_deferral_fail; /* Packets not sent due to max 854 * deferrals 855 **/ 856 u64 fifo_err; /* Packets sent that experienced a 857 * transmit underflow and were 858 * truncated 859 **/ 860 u64 runts; /* Packets sent with an octet count 861 * lessthan 64 862 **/ 863 u64 total_collisions; /* Packets dropped due to excessive 864 * collisions 865 **/ 866 867 /* firmware stats */ 868 u64 fw_total_sent; 869 u64 fw_total_fwd; 870 u64 fw_total_fwd_bytes; 871 u64 fw_total_mcast_sent; 872 u64 fw_total_bcast_sent; 873 u64 fw_err_pko; 874 u64 fw_err_link; 875 u64 fw_err_drop; 876 u64 fw_err_tso; 877 u64 fw_tso; /* number of tso requests */ 878 u64 fw_tso_fwd; /* number of packets segmented in tso */ 879 u64 fw_tx_vxlan; 880 u64 fw_err_pki; 881 }; 882 883 struct oct_link_stats { 884 struct nic_rx_stats fromwire; 885 struct nic_tx_stats fromhost; 886 887 }; 888 889 static inline int opcode_slow_path(union octeon_rh *rh) 890 { 891 u16 subcode1, subcode2; 892 893 subcode1 = OPCODE_SUBCODE((rh)->r.opcode, (rh)->r.subcode); 894 subcode2 = OPCODE_SUBCODE(OPCODE_NIC, OPCODE_NIC_NW_DATA); 895 896 return (subcode2 != subcode1); 897 } 898 899 #define LIO68XX_LED_CTRL_ADDR 0x3501 900 #define LIO68XX_LED_CTRL_CFGON 0x1f 901 #define LIO68XX_LED_CTRL_CFGOFF 0x100 902 #define LIO68XX_LED_BEACON_ADDR 0x3508 903 #define LIO68XX_LED_BEACON_CFGON 0x47fd 904 #define LIO68XX_LED_BEACON_CFGOFF 0x11fc 905 #define VITESSE_PHY_GPIO_DRIVEON 0x1 906 #define VITESSE_PHY_GPIO_CFG 0x8 907 #define VITESSE_PHY_GPIO_DRIVEOFF 0x4 908 #define VITESSE_PHY_GPIO_HIGH 0x2 909 #define VITESSE_PHY_GPIO_LOW 0x3 910 #define LED_IDENTIFICATION_ON 0x1 911 #define LED_IDENTIFICATION_OFF 0x0 912 #define LIO23XX_COPPERHEAD_LED_GPIO 0x2 913 914 struct oct_mdio_cmd { 915 u64 op; 916 u64 mdio_addr; 917 u64 value1; 918 u64 value2; 919 u64 value3; 920 }; 921 922 #define OCT_LINK_STATS_SIZE (sizeof(struct oct_link_stats)) 923 924 struct oct_intrmod_cfg { 925 u64 rx_enable; 926 u64 tx_enable; 927 u64 check_intrvl; 928 u64 maxpkt_ratethr; 929 u64 minpkt_ratethr; 930 u64 rx_maxcnt_trigger; 931 u64 rx_mincnt_trigger; 932 u64 rx_maxtmr_trigger; 933 u64 rx_mintmr_trigger; 934 u64 tx_mincnt_trigger; 935 u64 tx_maxcnt_trigger; 936 u64 rx_frames; 937 u64 tx_frames; 938 u64 rx_usecs; 939 }; 940 941 #define BASE_QUEUE_NOT_REQUESTED 65535 942 943 union oct_nic_if_cfg { 944 u64 u64; 945 struct { 946 #ifdef __BIG_ENDIAN_BITFIELD 947 u64 base_queue:16; 948 u64 num_iqueues:16; 949 u64 num_oqueues:16; 950 u64 gmx_port_id:8; 951 u64 vf_id:8; 952 #else 953 u64 vf_id:8; 954 u64 gmx_port_id:8; 955 u64 num_oqueues:16; 956 u64 num_iqueues:16; 957 u64 base_queue:16; 958 #endif 959 } s; 960 }; 961 962 struct lio_trusted_vf { 963 uint64_t active: 1; 964 uint64_t id : 8; 965 uint64_t reserved: 55; 966 }; 967 968 struct lio_time { 969 s64 sec; /* seconds */ 970 s64 nsec; /* nanoseconds */ 971 }; 972 973 struct lio_vf_rep_stats { 974 u64 tx_packets; 975 u64 tx_bytes; 976 u64 tx_dropped; 977 978 u64 rx_packets; 979 u64 rx_bytes; 980 u64 rx_dropped; 981 }; 982 983 enum lio_vf_rep_req_type { 984 LIO_VF_REP_REQ_NONE, 985 LIO_VF_REP_REQ_STATE, 986 LIO_VF_REP_REQ_MTU, 987 LIO_VF_REP_REQ_STATS, 988 LIO_VF_REP_REQ_DEVNAME 989 }; 990 991 enum { 992 LIO_VF_REP_STATE_DOWN, 993 LIO_VF_REP_STATE_UP 994 }; 995 996 #define LIO_IF_NAME_SIZE 16 997 struct lio_vf_rep_req { 998 u8 req_type; 999 u8 ifidx; 1000 u8 rsvd[6]; 1001 1002 union { 1003 struct lio_vf_rep_name { 1004 char name[LIO_IF_NAME_SIZE]; 1005 } rep_name; 1006 1007 struct lio_vf_rep_mtu { 1008 u32 mtu; 1009 u32 rsvd; 1010 } rep_mtu; 1011 1012 struct lio_vf_rep_state { 1013 u8 state; 1014 u8 rsvd[7]; 1015 } rep_state; 1016 }; 1017 }; 1018 1019 struct lio_vf_rep_resp { 1020 u64 rh; 1021 u8 status; 1022 u8 rsvd[7]; 1023 }; 1024 #endif 1025