1 /********************************************************************** 2 * Author: Cavium, Inc. 3 * 4 * Contact: support@cavium.com 5 * Please include "LiquidIO" in the subject. 6 * 7 * Copyright (c) 2003-2016 Cavium, Inc. 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more details. 17 ***********************************************************************/ 18 #include <linux/module.h> 19 #include <linux/interrupt.h> 20 #include <linux/pci.h> 21 #include <linux/firmware.h> 22 #include <net/vxlan.h> 23 #include <linux/kthread.h> 24 #include "liquidio_common.h" 25 #include "octeon_droq.h" 26 #include "octeon_iq.h" 27 #include "response_manager.h" 28 #include "octeon_device.h" 29 #include "octeon_nic.h" 30 #include "octeon_main.h" 31 #include "octeon_network.h" 32 #include "cn66xx_regs.h" 33 #include "cn66xx_device.h" 34 #include "cn68xx_device.h" 35 #include "cn23xx_pf_device.h" 36 #include "liquidio_image.h" 37 38 MODULE_AUTHOR("Cavium Networks, <support@cavium.com>"); 39 MODULE_DESCRIPTION("Cavium LiquidIO Intelligent Server Adapter Driver"); 40 MODULE_LICENSE("GPL"); 41 MODULE_VERSION(LIQUIDIO_VERSION); 42 MODULE_FIRMWARE(LIO_FW_DIR LIO_FW_BASE_NAME LIO_210SV_NAME 43 "_" LIO_FW_NAME_TYPE_NIC LIO_FW_NAME_SUFFIX); 44 MODULE_FIRMWARE(LIO_FW_DIR LIO_FW_BASE_NAME LIO_210NV_NAME 45 "_" LIO_FW_NAME_TYPE_NIC LIO_FW_NAME_SUFFIX); 46 MODULE_FIRMWARE(LIO_FW_DIR LIO_FW_BASE_NAME LIO_410NV_NAME 47 "_" LIO_FW_NAME_TYPE_NIC LIO_FW_NAME_SUFFIX); 48 MODULE_FIRMWARE(LIO_FW_DIR LIO_FW_BASE_NAME LIO_23XX_NAME 49 "_" LIO_FW_NAME_TYPE_NIC LIO_FW_NAME_SUFFIX); 50 51 static int ddr_timeout = 10000; 52 module_param(ddr_timeout, int, 0644); 53 MODULE_PARM_DESC(ddr_timeout, 54 "Number of milliseconds to wait for DDR initialization. 0 waits for ddr_timeout to be set to non-zero value before starting to check"); 55 56 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK) 57 58 static int debug = -1; 59 module_param(debug, int, 0644); 60 MODULE_PARM_DESC(debug, "NETIF_MSG debug bits"); 61 62 static char fw_type[LIO_MAX_FW_TYPE_LEN] = LIO_FW_NAME_TYPE_AUTO; 63 module_param_string(fw_type, fw_type, sizeof(fw_type), 0444); 64 MODULE_PARM_DESC(fw_type, "Type of firmware to be loaded (default is \"auto\"), which uses firmware in flash, if present, else loads \"nic\"."); 65 66 static u32 console_bitmask; 67 module_param(console_bitmask, int, 0644); 68 MODULE_PARM_DESC(console_bitmask, 69 "Bitmask indicating which consoles have debug output redirected to syslog."); 70 71 /** 72 * \brief determines if a given console has debug enabled. 73 * @param console console to check 74 * @returns 1 = enabled. 0 otherwise 75 */ 76 static int octeon_console_debug_enabled(u32 console) 77 { 78 return (console_bitmask >> (console)) & 0x1; 79 } 80 81 /* Polling interval for determining when NIC application is alive */ 82 #define LIQUIDIO_STARTER_POLL_INTERVAL_MS 100 83 84 /* runtime link query interval */ 85 #define LIQUIDIO_LINK_QUERY_INTERVAL_MS 1000 86 87 struct liquidio_if_cfg_context { 88 int octeon_id; 89 90 wait_queue_head_t wc; 91 92 int cond; 93 }; 94 95 struct liquidio_if_cfg_resp { 96 u64 rh; 97 struct liquidio_if_cfg_info cfg_info; 98 u64 status; 99 }; 100 101 struct liquidio_rx_ctl_context { 102 int octeon_id; 103 104 wait_queue_head_t wc; 105 106 int cond; 107 }; 108 109 struct oct_link_status_resp { 110 u64 rh; 111 struct oct_link_info link_info; 112 u64 status; 113 }; 114 115 struct oct_timestamp_resp { 116 u64 rh; 117 u64 timestamp; 118 u64 status; 119 }; 120 121 #define OCT_TIMESTAMP_RESP_SIZE (sizeof(struct oct_timestamp_resp)) 122 123 union tx_info { 124 u64 u64; 125 struct { 126 #ifdef __BIG_ENDIAN_BITFIELD 127 u16 gso_size; 128 u16 gso_segs; 129 u32 reserved; 130 #else 131 u32 reserved; 132 u16 gso_segs; 133 u16 gso_size; 134 #endif 135 } s; 136 }; 137 138 /** Octeon device properties to be used by the NIC module. 139 * Each octeon device in the system will be represented 140 * by this structure in the NIC module. 141 */ 142 143 #define OCTNIC_MAX_SG (MAX_SKB_FRAGS) 144 145 #define OCTNIC_GSO_MAX_HEADER_SIZE 128 146 #define OCTNIC_GSO_MAX_SIZE \ 147 (CN23XX_DEFAULT_INPUT_JABBER - OCTNIC_GSO_MAX_HEADER_SIZE) 148 149 /** Structure of a node in list of gather components maintained by 150 * NIC driver for each network device. 151 */ 152 struct octnic_gather { 153 /** List manipulation. Next and prev pointers. */ 154 struct list_head list; 155 156 /** Size of the gather component at sg in bytes. */ 157 int sg_size; 158 159 /** Number of bytes that sg was adjusted to make it 8B-aligned. */ 160 int adjust; 161 162 /** Gather component that can accommodate max sized fragment list 163 * received from the IP layer. 164 */ 165 struct octeon_sg_entry *sg; 166 167 dma_addr_t sg_dma_ptr; 168 }; 169 170 struct handshake { 171 struct completion init; 172 struct completion started; 173 struct pci_dev *pci_dev; 174 int init_ok; 175 int started_ok; 176 }; 177 178 #ifdef CONFIG_PCI_IOV 179 static int liquidio_enable_sriov(struct pci_dev *dev, int num_vfs); 180 #endif 181 182 static int octeon_dbg_console_print(struct octeon_device *oct, u32 console_num, 183 char *prefix, char *suffix); 184 185 static int octeon_device_init(struct octeon_device *); 186 static int liquidio_stop(struct net_device *netdev); 187 static void liquidio_remove(struct pci_dev *pdev); 188 static int liquidio_probe(struct pci_dev *pdev, 189 const struct pci_device_id *ent); 190 static int liquidio_set_vf_link_state(struct net_device *netdev, int vfidx, 191 int linkstate); 192 193 static struct handshake handshake[MAX_OCTEON_DEVICES]; 194 static struct completion first_stage; 195 196 static void octeon_droq_bh(unsigned long pdev) 197 { 198 int q_no; 199 int reschedule = 0; 200 struct octeon_device *oct = (struct octeon_device *)pdev; 201 struct octeon_device_priv *oct_priv = 202 (struct octeon_device_priv *)oct->priv; 203 204 for (q_no = 0; q_no < MAX_OCTEON_OUTPUT_QUEUES(oct); q_no++) { 205 if (!(oct->io_qmask.oq & BIT_ULL(q_no))) 206 continue; 207 reschedule |= octeon_droq_process_packets(oct, oct->droq[q_no], 208 MAX_PACKET_BUDGET); 209 lio_enable_irq(oct->droq[q_no], NULL); 210 211 if (OCTEON_CN23XX_PF(oct) && oct->msix_on) { 212 /* set time and cnt interrupt thresholds for this DROQ 213 * for NAPI 214 */ 215 int adjusted_q_no = q_no + oct->sriov_info.pf_srn; 216 217 octeon_write_csr64( 218 oct, CN23XX_SLI_OQ_PKT_INT_LEVELS(adjusted_q_no), 219 0x5700000040ULL); 220 octeon_write_csr64( 221 oct, CN23XX_SLI_OQ_PKTS_SENT(adjusted_q_no), 0); 222 } 223 } 224 225 if (reschedule) 226 tasklet_schedule(&oct_priv->droq_tasklet); 227 } 228 229 static int lio_wait_for_oq_pkts(struct octeon_device *oct) 230 { 231 struct octeon_device_priv *oct_priv = 232 (struct octeon_device_priv *)oct->priv; 233 int retry = 100, pkt_cnt = 0, pending_pkts = 0; 234 int i; 235 236 do { 237 pending_pkts = 0; 238 239 for (i = 0; i < MAX_OCTEON_OUTPUT_QUEUES(oct); i++) { 240 if (!(oct->io_qmask.oq & BIT_ULL(i))) 241 continue; 242 pkt_cnt += octeon_droq_check_hw_for_pkts(oct->droq[i]); 243 } 244 if (pkt_cnt > 0) { 245 pending_pkts += pkt_cnt; 246 tasklet_schedule(&oct_priv->droq_tasklet); 247 } 248 pkt_cnt = 0; 249 schedule_timeout_uninterruptible(1); 250 251 } while (retry-- && pending_pkts); 252 253 return pkt_cnt; 254 } 255 256 /** 257 * \brief Forces all IO queues off on a given device 258 * @param oct Pointer to Octeon device 259 */ 260 static void force_io_queues_off(struct octeon_device *oct) 261 { 262 if ((oct->chip_id == OCTEON_CN66XX) || 263 (oct->chip_id == OCTEON_CN68XX)) { 264 /* Reset the Enable bits for Input Queues. */ 265 octeon_write_csr(oct, CN6XXX_SLI_PKT_INSTR_ENB, 0); 266 267 /* Reset the Enable bits for Output Queues. */ 268 octeon_write_csr(oct, CN6XXX_SLI_PKT_OUT_ENB, 0); 269 } 270 } 271 272 /** 273 * \brief Cause device to go quiet so it can be safely removed/reset/etc 274 * @param oct Pointer to Octeon device 275 */ 276 static inline void pcierror_quiesce_device(struct octeon_device *oct) 277 { 278 int i; 279 280 /* Disable the input and output queues now. No more packets will 281 * arrive from Octeon, but we should wait for all packet processing 282 * to finish. 283 */ 284 force_io_queues_off(oct); 285 286 /* To allow for in-flight requests */ 287 schedule_timeout_uninterruptible(100); 288 289 if (wait_for_pending_requests(oct)) 290 dev_err(&oct->pci_dev->dev, "There were pending requests\n"); 291 292 /* Force all requests waiting to be fetched by OCTEON to complete. */ 293 for (i = 0; i < MAX_OCTEON_INSTR_QUEUES(oct); i++) { 294 struct octeon_instr_queue *iq; 295 296 if (!(oct->io_qmask.iq & BIT_ULL(i))) 297 continue; 298 iq = oct->instr_queue[i]; 299 300 if (atomic_read(&iq->instr_pending)) { 301 spin_lock_bh(&iq->lock); 302 iq->fill_cnt = 0; 303 iq->octeon_read_index = iq->host_write_index; 304 iq->stats.instr_processed += 305 atomic_read(&iq->instr_pending); 306 lio_process_iq_request_list(oct, iq, 0); 307 spin_unlock_bh(&iq->lock); 308 } 309 } 310 311 /* Force all pending ordered list requests to time out. */ 312 lio_process_ordered_list(oct, 1); 313 314 /* We do not need to wait for output queue packets to be processed. */ 315 } 316 317 /** 318 * \brief Cleanup PCI AER uncorrectable error status 319 * @param dev Pointer to PCI device 320 */ 321 static void cleanup_aer_uncorrect_error_status(struct pci_dev *dev) 322 { 323 int pos = 0x100; 324 u32 status, mask; 325 326 pr_info("%s :\n", __func__); 327 328 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, &status); 329 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, &mask); 330 if (dev->error_state == pci_channel_io_normal) 331 status &= ~mask; /* Clear corresponding nonfatal bits */ 332 else 333 status &= mask; /* Clear corresponding fatal bits */ 334 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, status); 335 } 336 337 /** 338 * \brief Stop all PCI IO to a given device 339 * @param dev Pointer to Octeon device 340 */ 341 static void stop_pci_io(struct octeon_device *oct) 342 { 343 /* No more instructions will be forwarded. */ 344 atomic_set(&oct->status, OCT_DEV_IN_RESET); 345 346 pci_disable_device(oct->pci_dev); 347 348 /* Disable interrupts */ 349 oct->fn_list.disable_interrupt(oct, OCTEON_ALL_INTR); 350 351 pcierror_quiesce_device(oct); 352 353 /* Release the interrupt line */ 354 free_irq(oct->pci_dev->irq, oct); 355 356 if (oct->flags & LIO_FLAG_MSI_ENABLED) 357 pci_disable_msi(oct->pci_dev); 358 359 dev_dbg(&oct->pci_dev->dev, "Device state is now %s\n", 360 lio_get_state_string(&oct->status)); 361 362 /* making it a common function for all OCTEON models */ 363 cleanup_aer_uncorrect_error_status(oct->pci_dev); 364 } 365 366 /** 367 * \brief called when PCI error is detected 368 * @param pdev Pointer to PCI device 369 * @param state The current pci connection state 370 * 371 * This function is called after a PCI bus error affecting 372 * this device has been detected. 373 */ 374 static pci_ers_result_t liquidio_pcie_error_detected(struct pci_dev *pdev, 375 pci_channel_state_t state) 376 { 377 struct octeon_device *oct = pci_get_drvdata(pdev); 378 379 /* Non-correctable Non-fatal errors */ 380 if (state == pci_channel_io_normal) { 381 dev_err(&oct->pci_dev->dev, "Non-correctable non-fatal error reported:\n"); 382 cleanup_aer_uncorrect_error_status(oct->pci_dev); 383 return PCI_ERS_RESULT_CAN_RECOVER; 384 } 385 386 /* Non-correctable Fatal errors */ 387 dev_err(&oct->pci_dev->dev, "Non-correctable FATAL reported by PCI AER driver\n"); 388 stop_pci_io(oct); 389 390 /* Always return a DISCONNECT. There is no support for recovery but only 391 * for a clean shutdown. 392 */ 393 return PCI_ERS_RESULT_DISCONNECT; 394 } 395 396 /** 397 * \brief mmio handler 398 * @param pdev Pointer to PCI device 399 */ 400 static pci_ers_result_t liquidio_pcie_mmio_enabled( 401 struct pci_dev *pdev __attribute__((unused))) 402 { 403 /* We should never hit this since we never ask for a reset for a Fatal 404 * Error. We always return DISCONNECT in io_error above. 405 * But play safe and return RECOVERED for now. 406 */ 407 return PCI_ERS_RESULT_RECOVERED; 408 } 409 410 /** 411 * \brief called after the pci bus has been reset. 412 * @param pdev Pointer to PCI device 413 * 414 * Restart the card from scratch, as if from a cold-boot. Implementation 415 * resembles the first-half of the octeon_resume routine. 416 */ 417 static pci_ers_result_t liquidio_pcie_slot_reset( 418 struct pci_dev *pdev __attribute__((unused))) 419 { 420 /* We should never hit this since we never ask for a reset for a Fatal 421 * Error. We always return DISCONNECT in io_error above. 422 * But play safe and return RECOVERED for now. 423 */ 424 return PCI_ERS_RESULT_RECOVERED; 425 } 426 427 /** 428 * \brief called when traffic can start flowing again. 429 * @param pdev Pointer to PCI device 430 * 431 * This callback is called when the error recovery driver tells us that 432 * its OK to resume normal operation. Implementation resembles the 433 * second-half of the octeon_resume routine. 434 */ 435 static void liquidio_pcie_resume(struct pci_dev *pdev __attribute__((unused))) 436 { 437 /* Nothing to be done here. */ 438 } 439 440 #ifdef CONFIG_PM 441 /** 442 * \brief called when suspending 443 * @param pdev Pointer to PCI device 444 * @param state state to suspend to 445 */ 446 static int liquidio_suspend(struct pci_dev *pdev __attribute__((unused)), 447 pm_message_t state __attribute__((unused))) 448 { 449 return 0; 450 } 451 452 /** 453 * \brief called when resuming 454 * @param pdev Pointer to PCI device 455 */ 456 static int liquidio_resume(struct pci_dev *pdev __attribute__((unused))) 457 { 458 return 0; 459 } 460 #endif 461 462 /* For PCI-E Advanced Error Recovery (AER) Interface */ 463 static const struct pci_error_handlers liquidio_err_handler = { 464 .error_detected = liquidio_pcie_error_detected, 465 .mmio_enabled = liquidio_pcie_mmio_enabled, 466 .slot_reset = liquidio_pcie_slot_reset, 467 .resume = liquidio_pcie_resume, 468 }; 469 470 static const struct pci_device_id liquidio_pci_tbl[] = { 471 { /* 68xx */ 472 PCI_VENDOR_ID_CAVIUM, 0x91, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 473 }, 474 { /* 66xx */ 475 PCI_VENDOR_ID_CAVIUM, 0x92, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 476 }, 477 { /* 23xx pf */ 478 PCI_VENDOR_ID_CAVIUM, 0x9702, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 479 }, 480 { 481 0, 0, 0, 0, 0, 0, 0 482 } 483 }; 484 MODULE_DEVICE_TABLE(pci, liquidio_pci_tbl); 485 486 static struct pci_driver liquidio_pci_driver = { 487 .name = "LiquidIO", 488 .id_table = liquidio_pci_tbl, 489 .probe = liquidio_probe, 490 .remove = liquidio_remove, 491 .err_handler = &liquidio_err_handler, /* For AER */ 492 493 #ifdef CONFIG_PM 494 .suspend = liquidio_suspend, 495 .resume = liquidio_resume, 496 #endif 497 #ifdef CONFIG_PCI_IOV 498 .sriov_configure = liquidio_enable_sriov, 499 #endif 500 }; 501 502 /** 503 * \brief register PCI driver 504 */ 505 static int liquidio_init_pci(void) 506 { 507 return pci_register_driver(&liquidio_pci_driver); 508 } 509 510 /** 511 * \brief unregister PCI driver 512 */ 513 static void liquidio_deinit_pci(void) 514 { 515 pci_unregister_driver(&liquidio_pci_driver); 516 } 517 518 /** 519 * \brief Stop Tx queues 520 * @param netdev network device 521 */ 522 static inline void txqs_stop(struct net_device *netdev) 523 { 524 if (netif_is_multiqueue(netdev)) { 525 int i; 526 527 for (i = 0; i < netdev->num_tx_queues; i++) 528 netif_stop_subqueue(netdev, i); 529 } else { 530 netif_stop_queue(netdev); 531 } 532 } 533 534 /** 535 * \brief Start Tx queues 536 * @param netdev network device 537 */ 538 static inline void txqs_start(struct net_device *netdev) 539 { 540 if (netif_is_multiqueue(netdev)) { 541 int i; 542 543 for (i = 0; i < netdev->num_tx_queues; i++) 544 netif_start_subqueue(netdev, i); 545 } else { 546 netif_start_queue(netdev); 547 } 548 } 549 550 /** 551 * \brief Wake Tx queues 552 * @param netdev network device 553 */ 554 static inline void txqs_wake(struct net_device *netdev) 555 { 556 struct lio *lio = GET_LIO(netdev); 557 558 if (netif_is_multiqueue(netdev)) { 559 int i; 560 561 for (i = 0; i < netdev->num_tx_queues; i++) { 562 int qno = lio->linfo.txpciq[i % 563 lio->oct_dev->num_iqs].s.q_no; 564 565 if (__netif_subqueue_stopped(netdev, i)) { 566 INCR_INSTRQUEUE_PKT_COUNT(lio->oct_dev, qno, 567 tx_restart, 1); 568 netif_wake_subqueue(netdev, i); 569 } 570 } 571 } else { 572 INCR_INSTRQUEUE_PKT_COUNT(lio->oct_dev, lio->txq, 573 tx_restart, 1); 574 netif_wake_queue(netdev); 575 } 576 } 577 578 /** 579 * \brief Stop Tx queue 580 * @param netdev network device 581 */ 582 static void stop_txq(struct net_device *netdev) 583 { 584 txqs_stop(netdev); 585 } 586 587 /** 588 * \brief Start Tx queue 589 * @param netdev network device 590 */ 591 static void start_txq(struct net_device *netdev) 592 { 593 struct lio *lio = GET_LIO(netdev); 594 595 if (lio->linfo.link.s.link_up) { 596 txqs_start(netdev); 597 return; 598 } 599 } 600 601 /** 602 * \brief Wake a queue 603 * @param netdev network device 604 * @param q which queue to wake 605 */ 606 static inline void wake_q(struct net_device *netdev, int q) 607 { 608 if (netif_is_multiqueue(netdev)) 609 netif_wake_subqueue(netdev, q); 610 else 611 netif_wake_queue(netdev); 612 } 613 614 /** 615 * \brief Stop a queue 616 * @param netdev network device 617 * @param q which queue to stop 618 */ 619 static inline void stop_q(struct net_device *netdev, int q) 620 { 621 if (netif_is_multiqueue(netdev)) 622 netif_stop_subqueue(netdev, q); 623 else 624 netif_stop_queue(netdev); 625 } 626 627 /** 628 * \brief Check Tx queue status, and take appropriate action 629 * @param lio per-network private data 630 * @returns 0 if full, number of queues woken up otherwise 631 */ 632 static inline int check_txq_status(struct lio *lio) 633 { 634 int ret_val = 0; 635 636 if (netif_is_multiqueue(lio->netdev)) { 637 int numqs = lio->netdev->num_tx_queues; 638 int q, iq = 0; 639 640 /* check each sub-queue state */ 641 for (q = 0; q < numqs; q++) { 642 iq = lio->linfo.txpciq[q % 643 lio->oct_dev->num_iqs].s.q_no; 644 if (octnet_iq_is_full(lio->oct_dev, iq)) 645 continue; 646 if (__netif_subqueue_stopped(lio->netdev, q)) { 647 wake_q(lio->netdev, q); 648 INCR_INSTRQUEUE_PKT_COUNT(lio->oct_dev, iq, 649 tx_restart, 1); 650 ret_val++; 651 } 652 } 653 } else { 654 if (octnet_iq_is_full(lio->oct_dev, lio->txq)) 655 return 0; 656 wake_q(lio->netdev, lio->txq); 657 INCR_INSTRQUEUE_PKT_COUNT(lio->oct_dev, lio->txq, 658 tx_restart, 1); 659 ret_val = 1; 660 } 661 return ret_val; 662 } 663 664 /** 665 * Remove the node at the head of the list. The list would be empty at 666 * the end of this call if there are no more nodes in the list. 667 */ 668 static inline struct list_head *list_delete_head(struct list_head *root) 669 { 670 struct list_head *node; 671 672 if ((root->prev == root) && (root->next == root)) 673 node = NULL; 674 else 675 node = root->next; 676 677 if (node) 678 list_del(node); 679 680 return node; 681 } 682 683 /** 684 * \brief Delete gather lists 685 * @param lio per-network private data 686 */ 687 static void delete_glists(struct lio *lio) 688 { 689 struct octnic_gather *g; 690 int i; 691 692 kfree(lio->glist_lock); 693 lio->glist_lock = NULL; 694 695 if (!lio->glist) 696 return; 697 698 for (i = 0; i < lio->linfo.num_txpciq; i++) { 699 do { 700 g = (struct octnic_gather *) 701 list_delete_head(&lio->glist[i]); 702 if (g) 703 kfree(g); 704 } while (g); 705 706 if (lio->glists_virt_base && lio->glists_virt_base[i] && 707 lio->glists_dma_base && lio->glists_dma_base[i]) { 708 lio_dma_free(lio->oct_dev, 709 lio->glist_entry_size * lio->tx_qsize, 710 lio->glists_virt_base[i], 711 lio->glists_dma_base[i]); 712 } 713 } 714 715 kfree(lio->glists_virt_base); 716 lio->glists_virt_base = NULL; 717 718 kfree(lio->glists_dma_base); 719 lio->glists_dma_base = NULL; 720 721 kfree(lio->glist); 722 lio->glist = NULL; 723 } 724 725 /** 726 * \brief Setup gather lists 727 * @param lio per-network private data 728 */ 729 static int setup_glists(struct octeon_device *oct, struct lio *lio, int num_iqs) 730 { 731 int i, j; 732 struct octnic_gather *g; 733 734 lio->glist_lock = kcalloc(num_iqs, sizeof(*lio->glist_lock), 735 GFP_KERNEL); 736 if (!lio->glist_lock) 737 return -ENOMEM; 738 739 lio->glist = kcalloc(num_iqs, sizeof(*lio->glist), 740 GFP_KERNEL); 741 if (!lio->glist) { 742 kfree(lio->glist_lock); 743 lio->glist_lock = NULL; 744 return -ENOMEM; 745 } 746 747 lio->glist_entry_size = 748 ROUNDUP8((ROUNDUP4(OCTNIC_MAX_SG) >> 2) * OCT_SG_ENTRY_SIZE); 749 750 /* allocate memory to store virtual and dma base address of 751 * per glist consistent memory 752 */ 753 lio->glists_virt_base = kcalloc(num_iqs, sizeof(*lio->glists_virt_base), 754 GFP_KERNEL); 755 lio->glists_dma_base = kcalloc(num_iqs, sizeof(*lio->glists_dma_base), 756 GFP_KERNEL); 757 758 if (!lio->glists_virt_base || !lio->glists_dma_base) { 759 delete_glists(lio); 760 return -ENOMEM; 761 } 762 763 for (i = 0; i < num_iqs; i++) { 764 int numa_node = dev_to_node(&oct->pci_dev->dev); 765 766 spin_lock_init(&lio->glist_lock[i]); 767 768 INIT_LIST_HEAD(&lio->glist[i]); 769 770 lio->glists_virt_base[i] = 771 lio_dma_alloc(oct, 772 lio->glist_entry_size * lio->tx_qsize, 773 &lio->glists_dma_base[i]); 774 775 if (!lio->glists_virt_base[i]) { 776 delete_glists(lio); 777 return -ENOMEM; 778 } 779 780 for (j = 0; j < lio->tx_qsize; j++) { 781 g = kzalloc_node(sizeof(*g), GFP_KERNEL, 782 numa_node); 783 if (!g) 784 g = kzalloc(sizeof(*g), GFP_KERNEL); 785 if (!g) 786 break; 787 788 g->sg = lio->glists_virt_base[i] + 789 (j * lio->glist_entry_size); 790 791 g->sg_dma_ptr = lio->glists_dma_base[i] + 792 (j * lio->glist_entry_size); 793 794 list_add_tail(&g->list, &lio->glist[i]); 795 } 796 797 if (j != lio->tx_qsize) { 798 delete_glists(lio); 799 return -ENOMEM; 800 } 801 } 802 803 return 0; 804 } 805 806 /** 807 * \brief Print link information 808 * @param netdev network device 809 */ 810 static void print_link_info(struct net_device *netdev) 811 { 812 struct lio *lio = GET_LIO(netdev); 813 814 if (!ifstate_check(lio, LIO_IFSTATE_RESETTING) && 815 ifstate_check(lio, LIO_IFSTATE_REGISTERED)) { 816 struct oct_link_info *linfo = &lio->linfo; 817 818 if (linfo->link.s.link_up) { 819 netif_info(lio, link, lio->netdev, "%d Mbps %s Duplex UP\n", 820 linfo->link.s.speed, 821 (linfo->link.s.duplex) ? "Full" : "Half"); 822 } else { 823 netif_info(lio, link, lio->netdev, "Link Down\n"); 824 } 825 } 826 } 827 828 /** 829 * \brief Routine to notify MTU change 830 * @param work work_struct data structure 831 */ 832 static void octnet_link_status_change(struct work_struct *work) 833 { 834 struct cavium_wk *wk = (struct cavium_wk *)work; 835 struct lio *lio = (struct lio *)wk->ctxptr; 836 837 rtnl_lock(); 838 call_netdevice_notifiers(NETDEV_CHANGEMTU, lio->netdev); 839 rtnl_unlock(); 840 } 841 842 /** 843 * \brief Sets up the mtu status change work 844 * @param netdev network device 845 */ 846 static inline int setup_link_status_change_wq(struct net_device *netdev) 847 { 848 struct lio *lio = GET_LIO(netdev); 849 struct octeon_device *oct = lio->oct_dev; 850 851 lio->link_status_wq.wq = alloc_workqueue("link-status", 852 WQ_MEM_RECLAIM, 0); 853 if (!lio->link_status_wq.wq) { 854 dev_err(&oct->pci_dev->dev, "unable to create cavium link status wq\n"); 855 return -1; 856 } 857 INIT_DELAYED_WORK(&lio->link_status_wq.wk.work, 858 octnet_link_status_change); 859 lio->link_status_wq.wk.ctxptr = lio; 860 861 return 0; 862 } 863 864 static inline void cleanup_link_status_change_wq(struct net_device *netdev) 865 { 866 struct lio *lio = GET_LIO(netdev); 867 868 if (lio->link_status_wq.wq) { 869 cancel_delayed_work_sync(&lio->link_status_wq.wk.work); 870 destroy_workqueue(lio->link_status_wq.wq); 871 } 872 } 873 874 /** 875 * \brief Update link status 876 * @param netdev network device 877 * @param ls link status structure 878 * 879 * Called on receipt of a link status response from the core application to 880 * update each interface's link status. 881 */ 882 static inline void update_link_status(struct net_device *netdev, 883 union oct_link_status *ls) 884 { 885 struct lio *lio = GET_LIO(netdev); 886 int changed = (lio->linfo.link.u64 != ls->u64); 887 888 lio->linfo.link.u64 = ls->u64; 889 890 if ((lio->intf_open) && (changed)) { 891 print_link_info(netdev); 892 lio->link_changes++; 893 894 if (lio->linfo.link.s.link_up) { 895 netif_carrier_on(netdev); 896 txqs_wake(netdev); 897 } else { 898 netif_carrier_off(netdev); 899 stop_txq(netdev); 900 } 901 } 902 } 903 904 static struct octeon_device *get_other_octeon_device(struct octeon_device *oct) 905 { 906 struct octeon_device *other_oct; 907 908 other_oct = lio_get_device(oct->octeon_id + 1); 909 910 if (other_oct && other_oct->pci_dev) { 911 int oct_busnum, other_oct_busnum; 912 913 oct_busnum = oct->pci_dev->bus->number; 914 other_oct_busnum = other_oct->pci_dev->bus->number; 915 916 if (oct_busnum == other_oct_busnum) { 917 int oct_slot, other_oct_slot; 918 919 oct_slot = PCI_SLOT(oct->pci_dev->devfn); 920 other_oct_slot = PCI_SLOT(other_oct->pci_dev->devfn); 921 922 if (oct_slot == other_oct_slot) 923 return other_oct; 924 } 925 } 926 927 return NULL; 928 } 929 930 static void disable_all_vf_links(struct octeon_device *oct) 931 { 932 struct net_device *netdev; 933 int max_vfs, vf, i; 934 935 if (!oct) 936 return; 937 938 max_vfs = oct->sriov_info.max_vfs; 939 940 for (i = 0; i < oct->ifcount; i++) { 941 netdev = oct->props[i].netdev; 942 if (!netdev) 943 continue; 944 945 for (vf = 0; vf < max_vfs; vf++) 946 liquidio_set_vf_link_state(netdev, vf, 947 IFLA_VF_LINK_STATE_DISABLE); 948 } 949 } 950 951 static int liquidio_watchdog(void *param) 952 { 953 bool err_msg_was_printed[LIO_MAX_CORES]; 954 u16 mask_of_crashed_or_stuck_cores = 0; 955 bool all_vf_links_are_disabled = false; 956 struct octeon_device *oct = param; 957 struct octeon_device *other_oct; 958 #ifdef CONFIG_MODULE_UNLOAD 959 long refcount, vfs_referencing_pf; 960 u64 vfs_mask1, vfs_mask2; 961 #endif 962 int core; 963 964 memset(err_msg_was_printed, 0, sizeof(err_msg_was_printed)); 965 966 while (!kthread_should_stop()) { 967 /* sleep for a couple of seconds so that we don't hog the CPU */ 968 set_current_state(TASK_INTERRUPTIBLE); 969 schedule_timeout(msecs_to_jiffies(2000)); 970 971 mask_of_crashed_or_stuck_cores = 972 (u16)octeon_read_csr64(oct, CN23XX_SLI_SCRATCH2); 973 974 if (!mask_of_crashed_or_stuck_cores) 975 continue; 976 977 WRITE_ONCE(oct->cores_crashed, true); 978 other_oct = get_other_octeon_device(oct); 979 if (other_oct) 980 WRITE_ONCE(other_oct->cores_crashed, true); 981 982 for (core = 0; core < LIO_MAX_CORES; core++) { 983 bool core_crashed_or_got_stuck; 984 985 core_crashed_or_got_stuck = 986 (mask_of_crashed_or_stuck_cores 987 >> core) & 1; 988 989 if (core_crashed_or_got_stuck && 990 !err_msg_was_printed[core]) { 991 dev_err(&oct->pci_dev->dev, 992 "ERROR: Octeon core %d crashed or got stuck! See oct-fwdump for details.\n", 993 core); 994 err_msg_was_printed[core] = true; 995 } 996 } 997 998 if (all_vf_links_are_disabled) 999 continue; 1000 1001 disable_all_vf_links(oct); 1002 disable_all_vf_links(other_oct); 1003 all_vf_links_are_disabled = true; 1004 1005 #ifdef CONFIG_MODULE_UNLOAD 1006 vfs_mask1 = READ_ONCE(oct->sriov_info.vf_drv_loaded_mask); 1007 vfs_mask2 = READ_ONCE(other_oct->sriov_info.vf_drv_loaded_mask); 1008 1009 vfs_referencing_pf = hweight64(vfs_mask1); 1010 vfs_referencing_pf += hweight64(vfs_mask2); 1011 1012 refcount = module_refcount(THIS_MODULE); 1013 if (refcount >= vfs_referencing_pf) { 1014 while (vfs_referencing_pf) { 1015 module_put(THIS_MODULE); 1016 vfs_referencing_pf--; 1017 } 1018 } 1019 #endif 1020 } 1021 1022 return 0; 1023 } 1024 1025 /** 1026 * \brief PCI probe handler 1027 * @param pdev PCI device structure 1028 * @param ent unused 1029 */ 1030 static int 1031 liquidio_probe(struct pci_dev *pdev, 1032 const struct pci_device_id *ent __attribute__((unused))) 1033 { 1034 struct octeon_device *oct_dev = NULL; 1035 struct handshake *hs; 1036 1037 oct_dev = octeon_allocate_device(pdev->device, 1038 sizeof(struct octeon_device_priv)); 1039 if (!oct_dev) { 1040 dev_err(&pdev->dev, "Unable to allocate device\n"); 1041 return -ENOMEM; 1042 } 1043 1044 if (pdev->device == OCTEON_CN23XX_PF_VID) 1045 oct_dev->msix_on = LIO_FLAG_MSIX_ENABLED; 1046 1047 /* Enable PTP for 6XXX Device */ 1048 if (((pdev->device == OCTEON_CN66XX) || 1049 (pdev->device == OCTEON_CN68XX))) 1050 oct_dev->ptp_enable = true; 1051 else 1052 oct_dev->ptp_enable = false; 1053 1054 dev_info(&pdev->dev, "Initializing device %x:%x.\n", 1055 (u32)pdev->vendor, (u32)pdev->device); 1056 1057 /* Assign octeon_device for this device to the private data area. */ 1058 pci_set_drvdata(pdev, oct_dev); 1059 1060 /* set linux specific device pointer */ 1061 oct_dev->pci_dev = (void *)pdev; 1062 1063 hs = &handshake[oct_dev->octeon_id]; 1064 init_completion(&hs->init); 1065 init_completion(&hs->started); 1066 hs->pci_dev = pdev; 1067 1068 if (oct_dev->octeon_id == 0) 1069 /* first LiquidIO NIC is detected */ 1070 complete(&first_stage); 1071 1072 if (octeon_device_init(oct_dev)) { 1073 complete(&hs->init); 1074 liquidio_remove(pdev); 1075 return -ENOMEM; 1076 } 1077 1078 if (OCTEON_CN23XX_PF(oct_dev)) { 1079 u64 scratch1; 1080 u8 bus, device, function; 1081 1082 scratch1 = octeon_read_csr64(oct_dev, CN23XX_SLI_SCRATCH1); 1083 if (!(scratch1 & 4ULL)) { 1084 /* Bit 2 of SLI_SCRATCH_1 is a flag that indicates that 1085 * the lio watchdog kernel thread is running for this 1086 * NIC. Each NIC gets one watchdog kernel thread. 1087 */ 1088 scratch1 |= 4ULL; 1089 octeon_write_csr64(oct_dev, CN23XX_SLI_SCRATCH1, 1090 scratch1); 1091 1092 bus = pdev->bus->number; 1093 device = PCI_SLOT(pdev->devfn); 1094 function = PCI_FUNC(pdev->devfn); 1095 oct_dev->watchdog_task = kthread_create( 1096 liquidio_watchdog, oct_dev, 1097 "liowd/%02hhx:%02hhx.%hhx", bus, device, function); 1098 if (!IS_ERR(oct_dev->watchdog_task)) { 1099 wake_up_process(oct_dev->watchdog_task); 1100 } else { 1101 oct_dev->watchdog_task = NULL; 1102 dev_err(&oct_dev->pci_dev->dev, 1103 "failed to create kernel_thread\n"); 1104 liquidio_remove(pdev); 1105 return -1; 1106 } 1107 } 1108 } 1109 1110 oct_dev->rx_pause = 1; 1111 oct_dev->tx_pause = 1; 1112 1113 dev_dbg(&oct_dev->pci_dev->dev, "Device is ready\n"); 1114 1115 return 0; 1116 } 1117 1118 static bool fw_type_is_auto(void) 1119 { 1120 return strncmp(fw_type, LIO_FW_NAME_TYPE_AUTO, 1121 sizeof(LIO_FW_NAME_TYPE_AUTO)) == 0; 1122 } 1123 1124 /** 1125 * \brief PCI FLR for each Octeon device. 1126 * @param oct octeon device 1127 */ 1128 static void octeon_pci_flr(struct octeon_device *oct) 1129 { 1130 int rc; 1131 1132 pci_save_state(oct->pci_dev); 1133 1134 pci_cfg_access_lock(oct->pci_dev); 1135 1136 /* Quiesce the device completely */ 1137 pci_write_config_word(oct->pci_dev, PCI_COMMAND, 1138 PCI_COMMAND_INTX_DISABLE); 1139 1140 rc = __pci_reset_function_locked(oct->pci_dev); 1141 1142 if (rc != 0) 1143 dev_err(&oct->pci_dev->dev, "Error %d resetting PCI function %d\n", 1144 rc, oct->pf_num); 1145 1146 pci_cfg_access_unlock(oct->pci_dev); 1147 1148 pci_restore_state(oct->pci_dev); 1149 } 1150 1151 /** 1152 *\brief Destroy resources associated with octeon device 1153 * @param pdev PCI device structure 1154 * @param ent unused 1155 */ 1156 static void octeon_destroy_resources(struct octeon_device *oct) 1157 { 1158 int i, refcount; 1159 struct msix_entry *msix_entries; 1160 struct octeon_device_priv *oct_priv = 1161 (struct octeon_device_priv *)oct->priv; 1162 1163 struct handshake *hs; 1164 1165 switch (atomic_read(&oct->status)) { 1166 case OCT_DEV_RUNNING: 1167 case OCT_DEV_CORE_OK: 1168 1169 /* No more instructions will be forwarded. */ 1170 atomic_set(&oct->status, OCT_DEV_IN_RESET); 1171 1172 oct->app_mode = CVM_DRV_INVALID_APP; 1173 dev_dbg(&oct->pci_dev->dev, "Device state is now %s\n", 1174 lio_get_state_string(&oct->status)); 1175 1176 schedule_timeout_uninterruptible(HZ / 10); 1177 1178 /* fallthrough */ 1179 case OCT_DEV_HOST_OK: 1180 1181 /* fallthrough */ 1182 case OCT_DEV_CONSOLE_INIT_DONE: 1183 /* Remove any consoles */ 1184 octeon_remove_consoles(oct); 1185 1186 /* fallthrough */ 1187 case OCT_DEV_IO_QUEUES_DONE: 1188 if (wait_for_pending_requests(oct)) 1189 dev_err(&oct->pci_dev->dev, "There were pending requests\n"); 1190 1191 if (lio_wait_for_instr_fetch(oct)) 1192 dev_err(&oct->pci_dev->dev, "IQ had pending instructions\n"); 1193 1194 /* Disable the input and output queues now. No more packets will 1195 * arrive from Octeon, but we should wait for all packet 1196 * processing to finish. 1197 */ 1198 oct->fn_list.disable_io_queues(oct); 1199 1200 if (lio_wait_for_oq_pkts(oct)) 1201 dev_err(&oct->pci_dev->dev, "OQ had pending packets\n"); 1202 1203 /* fallthrough */ 1204 case OCT_DEV_INTR_SET_DONE: 1205 /* Disable interrupts */ 1206 oct->fn_list.disable_interrupt(oct, OCTEON_ALL_INTR); 1207 1208 if (oct->msix_on) { 1209 msix_entries = (struct msix_entry *)oct->msix_entries; 1210 for (i = 0; i < oct->num_msix_irqs - 1; i++) { 1211 if (oct->ioq_vector[i].vector) { 1212 /* clear the affinity_cpumask */ 1213 irq_set_affinity_hint( 1214 msix_entries[i].vector, 1215 NULL); 1216 free_irq(msix_entries[i].vector, 1217 &oct->ioq_vector[i]); 1218 oct->ioq_vector[i].vector = 0; 1219 } 1220 } 1221 /* non-iov vector's argument is oct struct */ 1222 free_irq(msix_entries[i].vector, oct); 1223 1224 pci_disable_msix(oct->pci_dev); 1225 kfree(oct->msix_entries); 1226 oct->msix_entries = NULL; 1227 } else { 1228 /* Release the interrupt line */ 1229 free_irq(oct->pci_dev->irq, oct); 1230 1231 if (oct->flags & LIO_FLAG_MSI_ENABLED) 1232 pci_disable_msi(oct->pci_dev); 1233 } 1234 1235 kfree(oct->irq_name_storage); 1236 oct->irq_name_storage = NULL; 1237 1238 /* fallthrough */ 1239 case OCT_DEV_MSIX_ALLOC_VECTOR_DONE: 1240 if (OCTEON_CN23XX_PF(oct)) 1241 octeon_free_ioq_vector(oct); 1242 1243 /* fallthrough */ 1244 case OCT_DEV_MBOX_SETUP_DONE: 1245 if (OCTEON_CN23XX_PF(oct)) 1246 oct->fn_list.free_mbox(oct); 1247 1248 /* fallthrough */ 1249 case OCT_DEV_IN_RESET: 1250 case OCT_DEV_DROQ_INIT_DONE: 1251 /* Wait for any pending operations */ 1252 mdelay(100); 1253 for (i = 0; i < MAX_OCTEON_OUTPUT_QUEUES(oct); i++) { 1254 if (!(oct->io_qmask.oq & BIT_ULL(i))) 1255 continue; 1256 octeon_delete_droq(oct, i); 1257 } 1258 1259 /* Force any pending handshakes to complete */ 1260 for (i = 0; i < MAX_OCTEON_DEVICES; i++) { 1261 hs = &handshake[i]; 1262 1263 if (hs->pci_dev) { 1264 handshake[oct->octeon_id].init_ok = 0; 1265 complete(&handshake[oct->octeon_id].init); 1266 handshake[oct->octeon_id].started_ok = 0; 1267 complete(&handshake[oct->octeon_id].started); 1268 } 1269 } 1270 1271 /* fallthrough */ 1272 case OCT_DEV_RESP_LIST_INIT_DONE: 1273 octeon_delete_response_list(oct); 1274 1275 /* fallthrough */ 1276 case OCT_DEV_INSTR_QUEUE_INIT_DONE: 1277 for (i = 0; i < MAX_OCTEON_INSTR_QUEUES(oct); i++) { 1278 if (!(oct->io_qmask.iq & BIT_ULL(i))) 1279 continue; 1280 octeon_delete_instr_queue(oct, i); 1281 } 1282 #ifdef CONFIG_PCI_IOV 1283 if (oct->sriov_info.sriov_enabled) 1284 pci_disable_sriov(oct->pci_dev); 1285 #endif 1286 /* fallthrough */ 1287 case OCT_DEV_SC_BUFF_POOL_INIT_DONE: 1288 octeon_free_sc_buffer_pool(oct); 1289 1290 /* fallthrough */ 1291 case OCT_DEV_DISPATCH_INIT_DONE: 1292 octeon_delete_dispatch_list(oct); 1293 cancel_delayed_work_sync(&oct->nic_poll_work.work); 1294 1295 /* fallthrough */ 1296 case OCT_DEV_PCI_MAP_DONE: 1297 refcount = octeon_deregister_device(oct); 1298 1299 /* Soft reset the octeon device before exiting. 1300 * However, if fw was loaded from card (i.e. autoboot), 1301 * perform an FLR instead. 1302 * Implementation note: only soft-reset the device 1303 * if it is a CN6XXX OR the LAST CN23XX device. 1304 */ 1305 if (atomic_read(oct->adapter_fw_state) == FW_IS_PRELOADED) 1306 octeon_pci_flr(oct); 1307 else if (OCTEON_CN6XXX(oct) || !refcount) 1308 oct->fn_list.soft_reset(oct); 1309 1310 octeon_unmap_pci_barx(oct, 0); 1311 octeon_unmap_pci_barx(oct, 1); 1312 1313 /* fallthrough */ 1314 case OCT_DEV_PCI_ENABLE_DONE: 1315 pci_clear_master(oct->pci_dev); 1316 /* Disable the device, releasing the PCI INT */ 1317 pci_disable_device(oct->pci_dev); 1318 1319 /* fallthrough */ 1320 case OCT_DEV_BEGIN_STATE: 1321 /* Nothing to be done here either */ 1322 break; 1323 } /* end switch (oct->status) */ 1324 1325 tasklet_kill(&oct_priv->droq_tasklet); 1326 } 1327 1328 /** 1329 * \brief Callback for rx ctrl 1330 * @param status status of request 1331 * @param buf pointer to resp structure 1332 */ 1333 static void rx_ctl_callback(struct octeon_device *oct, 1334 u32 status, 1335 void *buf) 1336 { 1337 struct octeon_soft_command *sc = (struct octeon_soft_command *)buf; 1338 struct liquidio_rx_ctl_context *ctx; 1339 1340 ctx = (struct liquidio_rx_ctl_context *)sc->ctxptr; 1341 1342 oct = lio_get_device(ctx->octeon_id); 1343 if (status) 1344 dev_err(&oct->pci_dev->dev, "rx ctl instruction failed. Status: %llx\n", 1345 CVM_CAST64(status)); 1346 WRITE_ONCE(ctx->cond, 1); 1347 1348 /* This barrier is required to be sure that the response has been 1349 * written fully before waking up the handler 1350 */ 1351 wmb(); 1352 1353 wake_up_interruptible(&ctx->wc); 1354 } 1355 1356 /** 1357 * \brief Send Rx control command 1358 * @param lio per-network private data 1359 * @param start_stop whether to start or stop 1360 */ 1361 static void send_rx_ctrl_cmd(struct lio *lio, int start_stop) 1362 { 1363 struct octeon_soft_command *sc; 1364 struct liquidio_rx_ctl_context *ctx; 1365 union octnet_cmd *ncmd; 1366 int ctx_size = sizeof(struct liquidio_rx_ctl_context); 1367 struct octeon_device *oct = (struct octeon_device *)lio->oct_dev; 1368 int retval; 1369 1370 if (oct->props[lio->ifidx].rx_on == start_stop) 1371 return; 1372 1373 sc = (struct octeon_soft_command *) 1374 octeon_alloc_soft_command(oct, OCTNET_CMD_SIZE, 1375 16, ctx_size); 1376 1377 ncmd = (union octnet_cmd *)sc->virtdptr; 1378 ctx = (struct liquidio_rx_ctl_context *)sc->ctxptr; 1379 1380 WRITE_ONCE(ctx->cond, 0); 1381 ctx->octeon_id = lio_get_device_id(oct); 1382 init_waitqueue_head(&ctx->wc); 1383 1384 ncmd->u64 = 0; 1385 ncmd->s.cmd = OCTNET_CMD_RX_CTL; 1386 ncmd->s.param1 = start_stop; 1387 1388 octeon_swap_8B_data((u64 *)ncmd, (OCTNET_CMD_SIZE >> 3)); 1389 1390 sc->iq_no = lio->linfo.txpciq[0].s.q_no; 1391 1392 octeon_prepare_soft_command(oct, sc, OPCODE_NIC, 1393 OPCODE_NIC_CMD, 0, 0, 0); 1394 1395 sc->callback = rx_ctl_callback; 1396 sc->callback_arg = sc; 1397 sc->wait_time = 5000; 1398 1399 retval = octeon_send_soft_command(oct, sc); 1400 if (retval == IQ_SEND_FAILED) { 1401 netif_info(lio, rx_err, lio->netdev, "Failed to send RX Control message\n"); 1402 } else { 1403 /* Sleep on a wait queue till the cond flag indicates that the 1404 * response arrived or timed-out. 1405 */ 1406 if (sleep_cond(&ctx->wc, &ctx->cond) == -EINTR) 1407 return; 1408 oct->props[lio->ifidx].rx_on = start_stop; 1409 } 1410 1411 octeon_free_soft_command(oct, sc); 1412 } 1413 1414 /** 1415 * \brief Destroy NIC device interface 1416 * @param oct octeon device 1417 * @param ifidx which interface to destroy 1418 * 1419 * Cleanup associated with each interface for an Octeon device when NIC 1420 * module is being unloaded or if initialization fails during load. 1421 */ 1422 static void liquidio_destroy_nic_device(struct octeon_device *oct, int ifidx) 1423 { 1424 struct net_device *netdev = oct->props[ifidx].netdev; 1425 struct lio *lio; 1426 struct napi_struct *napi, *n; 1427 1428 if (!netdev) { 1429 dev_err(&oct->pci_dev->dev, "%s No netdevice ptr for index %d\n", 1430 __func__, ifidx); 1431 return; 1432 } 1433 1434 lio = GET_LIO(netdev); 1435 1436 dev_dbg(&oct->pci_dev->dev, "NIC device cleanup\n"); 1437 1438 if (atomic_read(&lio->ifstate) & LIO_IFSTATE_RUNNING) 1439 liquidio_stop(netdev); 1440 1441 if (oct->props[lio->ifidx].napi_enabled == 1) { 1442 list_for_each_entry_safe(napi, n, &netdev->napi_list, dev_list) 1443 napi_disable(napi); 1444 1445 oct->props[lio->ifidx].napi_enabled = 0; 1446 1447 if (OCTEON_CN23XX_PF(oct)) 1448 oct->droq[0]->ops.poll_mode = 0; 1449 } 1450 1451 /* Delete NAPI */ 1452 list_for_each_entry_safe(napi, n, &netdev->napi_list, dev_list) 1453 netif_napi_del(napi); 1454 1455 if (atomic_read(&lio->ifstate) & LIO_IFSTATE_REGISTERED) 1456 unregister_netdev(netdev); 1457 1458 cleanup_link_status_change_wq(netdev); 1459 1460 cleanup_rx_oom_poll_fn(netdev); 1461 1462 delete_glists(lio); 1463 1464 free_netdev(netdev); 1465 1466 oct->props[ifidx].gmxport = -1; 1467 1468 oct->props[ifidx].netdev = NULL; 1469 } 1470 1471 /** 1472 * \brief Stop complete NIC functionality 1473 * @param oct octeon device 1474 */ 1475 static int liquidio_stop_nic_module(struct octeon_device *oct) 1476 { 1477 int i, j; 1478 struct lio *lio; 1479 1480 dev_dbg(&oct->pci_dev->dev, "Stopping network interfaces\n"); 1481 if (!oct->ifcount) { 1482 dev_err(&oct->pci_dev->dev, "Init for Octeon was not completed\n"); 1483 return 1; 1484 } 1485 1486 spin_lock_bh(&oct->cmd_resp_wqlock); 1487 oct->cmd_resp_state = OCT_DRV_OFFLINE; 1488 spin_unlock_bh(&oct->cmd_resp_wqlock); 1489 1490 for (i = 0; i < oct->ifcount; i++) { 1491 lio = GET_LIO(oct->props[i].netdev); 1492 for (j = 0; j < oct->num_oqs; j++) 1493 octeon_unregister_droq_ops(oct, 1494 lio->linfo.rxpciq[j].s.q_no); 1495 } 1496 1497 for (i = 0; i < oct->ifcount; i++) 1498 liquidio_destroy_nic_device(oct, i); 1499 1500 dev_dbg(&oct->pci_dev->dev, "Network interfaces stopped\n"); 1501 return 0; 1502 } 1503 1504 /** 1505 * \brief Cleans up resources at unload time 1506 * @param pdev PCI device structure 1507 */ 1508 static void liquidio_remove(struct pci_dev *pdev) 1509 { 1510 struct octeon_device *oct_dev = pci_get_drvdata(pdev); 1511 1512 dev_dbg(&oct_dev->pci_dev->dev, "Stopping device\n"); 1513 1514 if (oct_dev->watchdog_task) 1515 kthread_stop(oct_dev->watchdog_task); 1516 1517 if (oct_dev->app_mode && (oct_dev->app_mode == CVM_DRV_NIC_APP)) 1518 liquidio_stop_nic_module(oct_dev); 1519 1520 /* Reset the octeon device and cleanup all memory allocated for 1521 * the octeon device by driver. 1522 */ 1523 octeon_destroy_resources(oct_dev); 1524 1525 dev_info(&oct_dev->pci_dev->dev, "Device removed\n"); 1526 1527 /* This octeon device has been removed. Update the global 1528 * data structure to reflect this. Free the device structure. 1529 */ 1530 octeon_free_device_mem(oct_dev); 1531 } 1532 1533 /** 1534 * \brief Identify the Octeon device and to map the BAR address space 1535 * @param oct octeon device 1536 */ 1537 static int octeon_chip_specific_setup(struct octeon_device *oct) 1538 { 1539 u32 dev_id, rev_id; 1540 int ret = 1; 1541 char *s; 1542 1543 pci_read_config_dword(oct->pci_dev, 0, &dev_id); 1544 pci_read_config_dword(oct->pci_dev, 8, &rev_id); 1545 oct->rev_id = rev_id & 0xff; 1546 1547 switch (dev_id) { 1548 case OCTEON_CN68XX_PCIID: 1549 oct->chip_id = OCTEON_CN68XX; 1550 ret = lio_setup_cn68xx_octeon_device(oct); 1551 s = "CN68XX"; 1552 break; 1553 1554 case OCTEON_CN66XX_PCIID: 1555 oct->chip_id = OCTEON_CN66XX; 1556 ret = lio_setup_cn66xx_octeon_device(oct); 1557 s = "CN66XX"; 1558 break; 1559 1560 case OCTEON_CN23XX_PCIID_PF: 1561 oct->chip_id = OCTEON_CN23XX_PF_VID; 1562 ret = setup_cn23xx_octeon_pf_device(oct); 1563 if (ret) 1564 break; 1565 #ifdef CONFIG_PCI_IOV 1566 if (!ret) 1567 pci_sriov_set_totalvfs(oct->pci_dev, 1568 oct->sriov_info.max_vfs); 1569 #endif 1570 s = "CN23XX"; 1571 break; 1572 1573 default: 1574 s = "?"; 1575 dev_err(&oct->pci_dev->dev, "Unknown device found (dev_id: %x)\n", 1576 dev_id); 1577 } 1578 1579 if (!ret) 1580 dev_info(&oct->pci_dev->dev, "%s PASS%d.%d %s Version: %s\n", s, 1581 OCTEON_MAJOR_REV(oct), 1582 OCTEON_MINOR_REV(oct), 1583 octeon_get_conf(oct)->card_name, 1584 LIQUIDIO_VERSION); 1585 1586 return ret; 1587 } 1588 1589 /** 1590 * \brief PCI initialization for each Octeon device. 1591 * @param oct octeon device 1592 */ 1593 static int octeon_pci_os_setup(struct octeon_device *oct) 1594 { 1595 /* setup PCI stuff first */ 1596 if (pci_enable_device(oct->pci_dev)) { 1597 dev_err(&oct->pci_dev->dev, "pci_enable_device failed\n"); 1598 return 1; 1599 } 1600 1601 if (dma_set_mask_and_coherent(&oct->pci_dev->dev, DMA_BIT_MASK(64))) { 1602 dev_err(&oct->pci_dev->dev, "Unexpected DMA device capability\n"); 1603 pci_disable_device(oct->pci_dev); 1604 return 1; 1605 } 1606 1607 /* Enable PCI DMA Master. */ 1608 pci_set_master(oct->pci_dev); 1609 1610 return 0; 1611 } 1612 1613 static inline int skb_iq(struct lio *lio, struct sk_buff *skb) 1614 { 1615 int q = 0; 1616 1617 if (netif_is_multiqueue(lio->netdev)) 1618 q = skb->queue_mapping % lio->linfo.num_txpciq; 1619 1620 return q; 1621 } 1622 1623 /** 1624 * \brief Check Tx queue state for a given network buffer 1625 * @param lio per-network private data 1626 * @param skb network buffer 1627 */ 1628 static inline int check_txq_state(struct lio *lio, struct sk_buff *skb) 1629 { 1630 int q = 0, iq = 0; 1631 1632 if (netif_is_multiqueue(lio->netdev)) { 1633 q = skb->queue_mapping; 1634 iq = lio->linfo.txpciq[(q % lio->oct_dev->num_iqs)].s.q_no; 1635 } else { 1636 iq = lio->txq; 1637 q = iq; 1638 } 1639 1640 if (octnet_iq_is_full(lio->oct_dev, iq)) 1641 return 0; 1642 1643 if (__netif_subqueue_stopped(lio->netdev, q)) { 1644 INCR_INSTRQUEUE_PKT_COUNT(lio->oct_dev, iq, tx_restart, 1); 1645 wake_q(lio->netdev, q); 1646 } 1647 return 1; 1648 } 1649 1650 /** 1651 * \brief Unmap and free network buffer 1652 * @param buf buffer 1653 */ 1654 static void free_netbuf(void *buf) 1655 { 1656 struct sk_buff *skb; 1657 struct octnet_buf_free_info *finfo; 1658 struct lio *lio; 1659 1660 finfo = (struct octnet_buf_free_info *)buf; 1661 skb = finfo->skb; 1662 lio = finfo->lio; 1663 1664 dma_unmap_single(&lio->oct_dev->pci_dev->dev, finfo->dptr, skb->len, 1665 DMA_TO_DEVICE); 1666 1667 check_txq_state(lio, skb); 1668 1669 tx_buffer_free(skb); 1670 } 1671 1672 /** 1673 * \brief Unmap and free gather buffer 1674 * @param buf buffer 1675 */ 1676 static void free_netsgbuf(void *buf) 1677 { 1678 struct octnet_buf_free_info *finfo; 1679 struct sk_buff *skb; 1680 struct lio *lio; 1681 struct octnic_gather *g; 1682 int i, frags, iq; 1683 1684 finfo = (struct octnet_buf_free_info *)buf; 1685 skb = finfo->skb; 1686 lio = finfo->lio; 1687 g = finfo->g; 1688 frags = skb_shinfo(skb)->nr_frags; 1689 1690 dma_unmap_single(&lio->oct_dev->pci_dev->dev, 1691 g->sg[0].ptr[0], (skb->len - skb->data_len), 1692 DMA_TO_DEVICE); 1693 1694 i = 1; 1695 while (frags--) { 1696 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i - 1]; 1697 1698 pci_unmap_page((lio->oct_dev)->pci_dev, 1699 g->sg[(i >> 2)].ptr[(i & 3)], 1700 frag->size, DMA_TO_DEVICE); 1701 i++; 1702 } 1703 1704 iq = skb_iq(lio, skb); 1705 spin_lock(&lio->glist_lock[iq]); 1706 list_add_tail(&g->list, &lio->glist[iq]); 1707 spin_unlock(&lio->glist_lock[iq]); 1708 1709 check_txq_state(lio, skb); /* mq support: sub-queue state check */ 1710 1711 tx_buffer_free(skb); 1712 } 1713 1714 /** 1715 * \brief Unmap and free gather buffer with response 1716 * @param buf buffer 1717 */ 1718 static void free_netsgbuf_with_resp(void *buf) 1719 { 1720 struct octeon_soft_command *sc; 1721 struct octnet_buf_free_info *finfo; 1722 struct sk_buff *skb; 1723 struct lio *lio; 1724 struct octnic_gather *g; 1725 int i, frags, iq; 1726 1727 sc = (struct octeon_soft_command *)buf; 1728 skb = (struct sk_buff *)sc->callback_arg; 1729 finfo = (struct octnet_buf_free_info *)&skb->cb; 1730 1731 lio = finfo->lio; 1732 g = finfo->g; 1733 frags = skb_shinfo(skb)->nr_frags; 1734 1735 dma_unmap_single(&lio->oct_dev->pci_dev->dev, 1736 g->sg[0].ptr[0], (skb->len - skb->data_len), 1737 DMA_TO_DEVICE); 1738 1739 i = 1; 1740 while (frags--) { 1741 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i - 1]; 1742 1743 pci_unmap_page((lio->oct_dev)->pci_dev, 1744 g->sg[(i >> 2)].ptr[(i & 3)], 1745 frag->size, DMA_TO_DEVICE); 1746 i++; 1747 } 1748 1749 iq = skb_iq(lio, skb); 1750 1751 spin_lock(&lio->glist_lock[iq]); 1752 list_add_tail(&g->list, &lio->glist[iq]); 1753 spin_unlock(&lio->glist_lock[iq]); 1754 1755 /* Don't free the skb yet */ 1756 1757 check_txq_state(lio, skb); 1758 } 1759 1760 /** 1761 * \brief Adjust ptp frequency 1762 * @param ptp PTP clock info 1763 * @param ppb how much to adjust by, in parts-per-billion 1764 */ 1765 static int liquidio_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb) 1766 { 1767 struct lio *lio = container_of(ptp, struct lio, ptp_info); 1768 struct octeon_device *oct = (struct octeon_device *)lio->oct_dev; 1769 u64 comp, delta; 1770 unsigned long flags; 1771 bool neg_adj = false; 1772 1773 if (ppb < 0) { 1774 neg_adj = true; 1775 ppb = -ppb; 1776 } 1777 1778 /* The hardware adds the clock compensation value to the 1779 * PTP clock on every coprocessor clock cycle, so we 1780 * compute the delta in terms of coprocessor clocks. 1781 */ 1782 delta = (u64)ppb << 32; 1783 do_div(delta, oct->coproc_clock_rate); 1784 1785 spin_lock_irqsave(&lio->ptp_lock, flags); 1786 comp = lio_pci_readq(oct, CN6XXX_MIO_PTP_CLOCK_COMP); 1787 if (neg_adj) 1788 comp -= delta; 1789 else 1790 comp += delta; 1791 lio_pci_writeq(oct, comp, CN6XXX_MIO_PTP_CLOCK_COMP); 1792 spin_unlock_irqrestore(&lio->ptp_lock, flags); 1793 1794 return 0; 1795 } 1796 1797 /** 1798 * \brief Adjust ptp time 1799 * @param ptp PTP clock info 1800 * @param delta how much to adjust by, in nanosecs 1801 */ 1802 static int liquidio_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta) 1803 { 1804 unsigned long flags; 1805 struct lio *lio = container_of(ptp, struct lio, ptp_info); 1806 1807 spin_lock_irqsave(&lio->ptp_lock, flags); 1808 lio->ptp_adjust += delta; 1809 spin_unlock_irqrestore(&lio->ptp_lock, flags); 1810 1811 return 0; 1812 } 1813 1814 /** 1815 * \brief Get hardware clock time, including any adjustment 1816 * @param ptp PTP clock info 1817 * @param ts timespec 1818 */ 1819 static int liquidio_ptp_gettime(struct ptp_clock_info *ptp, 1820 struct timespec64 *ts) 1821 { 1822 u64 ns; 1823 unsigned long flags; 1824 struct lio *lio = container_of(ptp, struct lio, ptp_info); 1825 struct octeon_device *oct = (struct octeon_device *)lio->oct_dev; 1826 1827 spin_lock_irqsave(&lio->ptp_lock, flags); 1828 ns = lio_pci_readq(oct, CN6XXX_MIO_PTP_CLOCK_HI); 1829 ns += lio->ptp_adjust; 1830 spin_unlock_irqrestore(&lio->ptp_lock, flags); 1831 1832 *ts = ns_to_timespec64(ns); 1833 1834 return 0; 1835 } 1836 1837 /** 1838 * \brief Set hardware clock time. Reset adjustment 1839 * @param ptp PTP clock info 1840 * @param ts timespec 1841 */ 1842 static int liquidio_ptp_settime(struct ptp_clock_info *ptp, 1843 const struct timespec64 *ts) 1844 { 1845 u64 ns; 1846 unsigned long flags; 1847 struct lio *lio = container_of(ptp, struct lio, ptp_info); 1848 struct octeon_device *oct = (struct octeon_device *)lio->oct_dev; 1849 1850 ns = timespec_to_ns(ts); 1851 1852 spin_lock_irqsave(&lio->ptp_lock, flags); 1853 lio_pci_writeq(oct, ns, CN6XXX_MIO_PTP_CLOCK_HI); 1854 lio->ptp_adjust = 0; 1855 spin_unlock_irqrestore(&lio->ptp_lock, flags); 1856 1857 return 0; 1858 } 1859 1860 /** 1861 * \brief Check if PTP is enabled 1862 * @param ptp PTP clock info 1863 * @param rq request 1864 * @param on is it on 1865 */ 1866 static int 1867 liquidio_ptp_enable(struct ptp_clock_info *ptp __attribute__((unused)), 1868 struct ptp_clock_request *rq __attribute__((unused)), 1869 int on __attribute__((unused))) 1870 { 1871 return -EOPNOTSUPP; 1872 } 1873 1874 /** 1875 * \brief Open PTP clock source 1876 * @param netdev network device 1877 */ 1878 static void oct_ptp_open(struct net_device *netdev) 1879 { 1880 struct lio *lio = GET_LIO(netdev); 1881 struct octeon_device *oct = (struct octeon_device *)lio->oct_dev; 1882 1883 spin_lock_init(&lio->ptp_lock); 1884 1885 snprintf(lio->ptp_info.name, 16, "%s", netdev->name); 1886 lio->ptp_info.owner = THIS_MODULE; 1887 lio->ptp_info.max_adj = 250000000; 1888 lio->ptp_info.n_alarm = 0; 1889 lio->ptp_info.n_ext_ts = 0; 1890 lio->ptp_info.n_per_out = 0; 1891 lio->ptp_info.pps = 0; 1892 lio->ptp_info.adjfreq = liquidio_ptp_adjfreq; 1893 lio->ptp_info.adjtime = liquidio_ptp_adjtime; 1894 lio->ptp_info.gettime64 = liquidio_ptp_gettime; 1895 lio->ptp_info.settime64 = liquidio_ptp_settime; 1896 lio->ptp_info.enable = liquidio_ptp_enable; 1897 1898 lio->ptp_adjust = 0; 1899 1900 lio->ptp_clock = ptp_clock_register(&lio->ptp_info, 1901 &oct->pci_dev->dev); 1902 1903 if (IS_ERR(lio->ptp_clock)) 1904 lio->ptp_clock = NULL; 1905 } 1906 1907 /** 1908 * \brief Init PTP clock 1909 * @param oct octeon device 1910 */ 1911 static void liquidio_ptp_init(struct octeon_device *oct) 1912 { 1913 u64 clock_comp, cfg; 1914 1915 clock_comp = (u64)NSEC_PER_SEC << 32; 1916 do_div(clock_comp, oct->coproc_clock_rate); 1917 lio_pci_writeq(oct, clock_comp, CN6XXX_MIO_PTP_CLOCK_COMP); 1918 1919 /* Enable */ 1920 cfg = lio_pci_readq(oct, CN6XXX_MIO_PTP_CLOCK_CFG); 1921 lio_pci_writeq(oct, cfg | 0x01, CN6XXX_MIO_PTP_CLOCK_CFG); 1922 } 1923 1924 /** 1925 * \brief Load firmware to device 1926 * @param oct octeon device 1927 * 1928 * Maps device to firmware filename, requests firmware, and downloads it 1929 */ 1930 static int load_firmware(struct octeon_device *oct) 1931 { 1932 int ret = 0; 1933 const struct firmware *fw; 1934 char fw_name[LIO_MAX_FW_FILENAME_LEN]; 1935 char *tmp_fw_type; 1936 1937 if (fw_type_is_auto()) { 1938 tmp_fw_type = LIO_FW_NAME_TYPE_NIC; 1939 strncpy(fw_type, tmp_fw_type, sizeof(fw_type)); 1940 } else { 1941 tmp_fw_type = fw_type; 1942 } 1943 1944 sprintf(fw_name, "%s%s%s_%s%s", LIO_FW_DIR, LIO_FW_BASE_NAME, 1945 octeon_get_conf(oct)->card_name, tmp_fw_type, 1946 LIO_FW_NAME_SUFFIX); 1947 1948 ret = request_firmware(&fw, fw_name, &oct->pci_dev->dev); 1949 if (ret) { 1950 dev_err(&oct->pci_dev->dev, "Request firmware failed. Could not find file %s.\n.", 1951 fw_name); 1952 release_firmware(fw); 1953 return ret; 1954 } 1955 1956 ret = octeon_download_firmware(oct, fw->data, fw->size); 1957 1958 release_firmware(fw); 1959 1960 return ret; 1961 } 1962 1963 /** 1964 * \brief Callback for getting interface configuration 1965 * @param status status of request 1966 * @param buf pointer to resp structure 1967 */ 1968 static void if_cfg_callback(struct octeon_device *oct, 1969 u32 status __attribute__((unused)), 1970 void *buf) 1971 { 1972 struct octeon_soft_command *sc = (struct octeon_soft_command *)buf; 1973 struct liquidio_if_cfg_resp *resp; 1974 struct liquidio_if_cfg_context *ctx; 1975 1976 resp = (struct liquidio_if_cfg_resp *)sc->virtrptr; 1977 ctx = (struct liquidio_if_cfg_context *)sc->ctxptr; 1978 1979 oct = lio_get_device(ctx->octeon_id); 1980 if (resp->status) 1981 dev_err(&oct->pci_dev->dev, "nic if cfg instruction failed. Status: 0x%llx (0x%08x)\n", 1982 CVM_CAST64(resp->status), status); 1983 WRITE_ONCE(ctx->cond, 1); 1984 1985 snprintf(oct->fw_info.liquidio_firmware_version, 32, "%s", 1986 resp->cfg_info.liquidio_firmware_version); 1987 1988 /* This barrier is required to be sure that the response has been 1989 * written fully before waking up the handler 1990 */ 1991 wmb(); 1992 1993 wake_up_interruptible(&ctx->wc); 1994 } 1995 1996 /** 1997 * \brief Poll routine for checking transmit queue status 1998 * @param work work_struct data structure 1999 */ 2000 static void octnet_poll_check_txq_status(struct work_struct *work) 2001 { 2002 struct cavium_wk *wk = (struct cavium_wk *)work; 2003 struct lio *lio = (struct lio *)wk->ctxptr; 2004 2005 if (!ifstate_check(lio, LIO_IFSTATE_RUNNING)) 2006 return; 2007 2008 check_txq_status(lio); 2009 queue_delayed_work(lio->txq_status_wq.wq, 2010 &lio->txq_status_wq.wk.work, msecs_to_jiffies(1)); 2011 } 2012 2013 /** 2014 * \brief Sets up the txq poll check 2015 * @param netdev network device 2016 */ 2017 static inline int setup_tx_poll_fn(struct net_device *netdev) 2018 { 2019 struct lio *lio = GET_LIO(netdev); 2020 struct octeon_device *oct = lio->oct_dev; 2021 2022 lio->txq_status_wq.wq = alloc_workqueue("txq-status", 2023 WQ_MEM_RECLAIM, 0); 2024 if (!lio->txq_status_wq.wq) { 2025 dev_err(&oct->pci_dev->dev, "unable to create cavium txq status wq\n"); 2026 return -1; 2027 } 2028 INIT_DELAYED_WORK(&lio->txq_status_wq.wk.work, 2029 octnet_poll_check_txq_status); 2030 lio->txq_status_wq.wk.ctxptr = lio; 2031 queue_delayed_work(lio->txq_status_wq.wq, 2032 &lio->txq_status_wq.wk.work, msecs_to_jiffies(1)); 2033 return 0; 2034 } 2035 2036 static inline void cleanup_tx_poll_fn(struct net_device *netdev) 2037 { 2038 struct lio *lio = GET_LIO(netdev); 2039 2040 if (lio->txq_status_wq.wq) { 2041 cancel_delayed_work_sync(&lio->txq_status_wq.wk.work); 2042 destroy_workqueue(lio->txq_status_wq.wq); 2043 } 2044 } 2045 2046 /** 2047 * \brief Net device open for LiquidIO 2048 * @param netdev network device 2049 */ 2050 static int liquidio_open(struct net_device *netdev) 2051 { 2052 struct lio *lio = GET_LIO(netdev); 2053 struct octeon_device *oct = lio->oct_dev; 2054 struct napi_struct *napi, *n; 2055 2056 if (oct->props[lio->ifidx].napi_enabled == 0) { 2057 list_for_each_entry_safe(napi, n, &netdev->napi_list, dev_list) 2058 napi_enable(napi); 2059 2060 oct->props[lio->ifidx].napi_enabled = 1; 2061 2062 if (OCTEON_CN23XX_PF(oct)) 2063 oct->droq[0]->ops.poll_mode = 1; 2064 } 2065 2066 if (oct->ptp_enable) 2067 oct_ptp_open(netdev); 2068 2069 ifstate_set(lio, LIO_IFSTATE_RUNNING); 2070 2071 /* Ready for link status updates */ 2072 lio->intf_open = 1; 2073 2074 netif_info(lio, ifup, lio->netdev, "Interface Open, ready for traffic\n"); 2075 2076 if (OCTEON_CN23XX_PF(oct)) { 2077 if (!oct->msix_on) 2078 if (setup_tx_poll_fn(netdev)) 2079 return -1; 2080 } else { 2081 if (setup_tx_poll_fn(netdev)) 2082 return -1; 2083 } 2084 2085 start_txq(netdev); 2086 2087 /* tell Octeon to start forwarding packets to host */ 2088 send_rx_ctrl_cmd(lio, 1); 2089 2090 dev_info(&oct->pci_dev->dev, "%s interface is opened\n", 2091 netdev->name); 2092 2093 return 0; 2094 } 2095 2096 /** 2097 * \brief Net device stop for LiquidIO 2098 * @param netdev network device 2099 */ 2100 static int liquidio_stop(struct net_device *netdev) 2101 { 2102 struct lio *lio = GET_LIO(netdev); 2103 struct octeon_device *oct = lio->oct_dev; 2104 struct napi_struct *napi, *n; 2105 2106 if (oct->props[lio->ifidx].napi_enabled) { 2107 list_for_each_entry_safe(napi, n, &netdev->napi_list, dev_list) 2108 napi_disable(napi); 2109 2110 oct->props[lio->ifidx].napi_enabled = 0; 2111 2112 if (OCTEON_CN23XX_PF(oct)) 2113 oct->droq[0]->ops.poll_mode = 0; 2114 } 2115 2116 ifstate_reset(lio, LIO_IFSTATE_RUNNING); 2117 2118 netif_tx_disable(netdev); 2119 2120 /* Inform that netif carrier is down */ 2121 netif_carrier_off(netdev); 2122 lio->intf_open = 0; 2123 lio->linfo.link.s.link_up = 0; 2124 lio->link_changes++; 2125 2126 /* Tell Octeon that nic interface is down. */ 2127 send_rx_ctrl_cmd(lio, 0); 2128 2129 if (OCTEON_CN23XX_PF(oct)) { 2130 if (!oct->msix_on) 2131 cleanup_tx_poll_fn(netdev); 2132 } else { 2133 cleanup_tx_poll_fn(netdev); 2134 } 2135 2136 if (lio->ptp_clock) { 2137 ptp_clock_unregister(lio->ptp_clock); 2138 lio->ptp_clock = NULL; 2139 } 2140 2141 dev_info(&oct->pci_dev->dev, "%s interface is stopped\n", netdev->name); 2142 2143 return 0; 2144 } 2145 2146 /** 2147 * \brief Converts a mask based on net device flags 2148 * @param netdev network device 2149 * 2150 * This routine generates a octnet_ifflags mask from the net device flags 2151 * received from the OS. 2152 */ 2153 static inline enum octnet_ifflags get_new_flags(struct net_device *netdev) 2154 { 2155 enum octnet_ifflags f = OCTNET_IFFLAG_UNICAST; 2156 2157 if (netdev->flags & IFF_PROMISC) 2158 f |= OCTNET_IFFLAG_PROMISC; 2159 2160 if (netdev->flags & IFF_ALLMULTI) 2161 f |= OCTNET_IFFLAG_ALLMULTI; 2162 2163 if (netdev->flags & IFF_MULTICAST) { 2164 f |= OCTNET_IFFLAG_MULTICAST; 2165 2166 /* Accept all multicast addresses if there are more than we 2167 * can handle 2168 */ 2169 if (netdev_mc_count(netdev) > MAX_OCTEON_MULTICAST_ADDR) 2170 f |= OCTNET_IFFLAG_ALLMULTI; 2171 } 2172 2173 if (netdev->flags & IFF_BROADCAST) 2174 f |= OCTNET_IFFLAG_BROADCAST; 2175 2176 return f; 2177 } 2178 2179 /** 2180 * \brief Net device set_multicast_list 2181 * @param netdev network device 2182 */ 2183 static void liquidio_set_mcast_list(struct net_device *netdev) 2184 { 2185 struct lio *lio = GET_LIO(netdev); 2186 struct octeon_device *oct = lio->oct_dev; 2187 struct octnic_ctrl_pkt nctrl; 2188 struct netdev_hw_addr *ha; 2189 u64 *mc; 2190 int ret; 2191 int mc_count = min(netdev_mc_count(netdev), MAX_OCTEON_MULTICAST_ADDR); 2192 2193 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt)); 2194 2195 /* Create a ctrl pkt command to be sent to core app. */ 2196 nctrl.ncmd.u64 = 0; 2197 nctrl.ncmd.s.cmd = OCTNET_CMD_SET_MULTI_LIST; 2198 nctrl.ncmd.s.param1 = get_new_flags(netdev); 2199 nctrl.ncmd.s.param2 = mc_count; 2200 nctrl.ncmd.s.more = mc_count; 2201 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no; 2202 nctrl.netpndev = (u64)netdev; 2203 nctrl.cb_fn = liquidio_link_ctrl_cmd_completion; 2204 2205 /* copy all the addresses into the udd */ 2206 mc = &nctrl.udd[0]; 2207 netdev_for_each_mc_addr(ha, netdev) { 2208 *mc = 0; 2209 memcpy(((u8 *)mc) + 2, ha->addr, ETH_ALEN); 2210 /* no need to swap bytes */ 2211 2212 if (++mc > &nctrl.udd[mc_count]) 2213 break; 2214 } 2215 2216 /* Apparently, any activity in this call from the kernel has to 2217 * be atomic. So we won't wait for response. 2218 */ 2219 nctrl.wait_time = 0; 2220 2221 ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl); 2222 if (ret < 0) { 2223 dev_err(&oct->pci_dev->dev, "DEVFLAGS change failed in core (ret: 0x%x)\n", 2224 ret); 2225 } 2226 } 2227 2228 /** 2229 * \brief Net device set_mac_address 2230 * @param netdev network device 2231 */ 2232 static int liquidio_set_mac(struct net_device *netdev, void *p) 2233 { 2234 int ret = 0; 2235 struct lio *lio = GET_LIO(netdev); 2236 struct octeon_device *oct = lio->oct_dev; 2237 struct sockaddr *addr = (struct sockaddr *)p; 2238 struct octnic_ctrl_pkt nctrl; 2239 2240 if (!is_valid_ether_addr(addr->sa_data)) 2241 return -EADDRNOTAVAIL; 2242 2243 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt)); 2244 2245 nctrl.ncmd.u64 = 0; 2246 nctrl.ncmd.s.cmd = OCTNET_CMD_CHANGE_MACADDR; 2247 nctrl.ncmd.s.param1 = 0; 2248 nctrl.ncmd.s.more = 1; 2249 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no; 2250 nctrl.netpndev = (u64)netdev; 2251 nctrl.cb_fn = liquidio_link_ctrl_cmd_completion; 2252 nctrl.wait_time = 100; 2253 2254 nctrl.udd[0] = 0; 2255 /* The MAC Address is presented in network byte order. */ 2256 memcpy((u8 *)&nctrl.udd[0] + 2, addr->sa_data, ETH_ALEN); 2257 2258 ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl); 2259 if (ret < 0) { 2260 dev_err(&oct->pci_dev->dev, "MAC Address change failed\n"); 2261 return -ENOMEM; 2262 } 2263 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 2264 memcpy(((u8 *)&lio->linfo.hw_addr) + 2, addr->sa_data, ETH_ALEN); 2265 2266 return 0; 2267 } 2268 2269 /** 2270 * \brief Net device get_stats 2271 * @param netdev network device 2272 */ 2273 static struct net_device_stats *liquidio_get_stats(struct net_device *netdev) 2274 { 2275 struct lio *lio = GET_LIO(netdev); 2276 struct net_device_stats *stats = &netdev->stats; 2277 struct octeon_device *oct; 2278 u64 pkts = 0, drop = 0, bytes = 0; 2279 struct oct_droq_stats *oq_stats; 2280 struct oct_iq_stats *iq_stats; 2281 int i, iq_no, oq_no; 2282 2283 oct = lio->oct_dev; 2284 2285 if (ifstate_check(lio, LIO_IFSTATE_RESETTING)) 2286 return stats; 2287 2288 for (i = 0; i < oct->num_iqs; i++) { 2289 iq_no = lio->linfo.txpciq[i].s.q_no; 2290 iq_stats = &oct->instr_queue[iq_no]->stats; 2291 pkts += iq_stats->tx_done; 2292 drop += iq_stats->tx_dropped; 2293 bytes += iq_stats->tx_tot_bytes; 2294 } 2295 2296 stats->tx_packets = pkts; 2297 stats->tx_bytes = bytes; 2298 stats->tx_dropped = drop; 2299 2300 pkts = 0; 2301 drop = 0; 2302 bytes = 0; 2303 2304 for (i = 0; i < oct->num_oqs; i++) { 2305 oq_no = lio->linfo.rxpciq[i].s.q_no; 2306 oq_stats = &oct->droq[oq_no]->stats; 2307 pkts += oq_stats->rx_pkts_received; 2308 drop += (oq_stats->rx_dropped + 2309 oq_stats->dropped_nodispatch + 2310 oq_stats->dropped_toomany + 2311 oq_stats->dropped_nomem); 2312 bytes += oq_stats->rx_bytes_received; 2313 } 2314 2315 stats->rx_bytes = bytes; 2316 stats->rx_packets = pkts; 2317 stats->rx_dropped = drop; 2318 2319 return stats; 2320 } 2321 2322 /** 2323 * \brief Net device change_mtu 2324 * @param netdev network device 2325 */ 2326 static int liquidio_change_mtu(struct net_device *netdev, int new_mtu) 2327 { 2328 struct lio *lio = GET_LIO(netdev); 2329 struct octeon_device *oct = lio->oct_dev; 2330 struct octnic_ctrl_pkt nctrl; 2331 int ret = 0; 2332 2333 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt)); 2334 2335 nctrl.ncmd.u64 = 0; 2336 nctrl.ncmd.s.cmd = OCTNET_CMD_CHANGE_MTU; 2337 nctrl.ncmd.s.param1 = new_mtu; 2338 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no; 2339 nctrl.wait_time = 100; 2340 nctrl.netpndev = (u64)netdev; 2341 nctrl.cb_fn = liquidio_link_ctrl_cmd_completion; 2342 2343 ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl); 2344 if (ret < 0) { 2345 dev_err(&oct->pci_dev->dev, "Failed to set MTU\n"); 2346 return -1; 2347 } 2348 2349 lio->mtu = new_mtu; 2350 2351 return 0; 2352 } 2353 2354 /** 2355 * \brief Handler for SIOCSHWTSTAMP ioctl 2356 * @param netdev network device 2357 * @param ifr interface request 2358 * @param cmd command 2359 */ 2360 static int hwtstamp_ioctl(struct net_device *netdev, struct ifreq *ifr) 2361 { 2362 struct hwtstamp_config conf; 2363 struct lio *lio = GET_LIO(netdev); 2364 2365 if (copy_from_user(&conf, ifr->ifr_data, sizeof(conf))) 2366 return -EFAULT; 2367 2368 if (conf.flags) 2369 return -EINVAL; 2370 2371 switch (conf.tx_type) { 2372 case HWTSTAMP_TX_ON: 2373 case HWTSTAMP_TX_OFF: 2374 break; 2375 default: 2376 return -ERANGE; 2377 } 2378 2379 switch (conf.rx_filter) { 2380 case HWTSTAMP_FILTER_NONE: 2381 break; 2382 case HWTSTAMP_FILTER_ALL: 2383 case HWTSTAMP_FILTER_SOME: 2384 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 2385 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 2386 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 2387 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 2388 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 2389 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 2390 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 2391 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 2392 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 2393 case HWTSTAMP_FILTER_PTP_V2_EVENT: 2394 case HWTSTAMP_FILTER_PTP_V2_SYNC: 2395 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 2396 case HWTSTAMP_FILTER_NTP_ALL: 2397 conf.rx_filter = HWTSTAMP_FILTER_ALL; 2398 break; 2399 default: 2400 return -ERANGE; 2401 } 2402 2403 if (conf.rx_filter == HWTSTAMP_FILTER_ALL) 2404 ifstate_set(lio, LIO_IFSTATE_RX_TIMESTAMP_ENABLED); 2405 2406 else 2407 ifstate_reset(lio, LIO_IFSTATE_RX_TIMESTAMP_ENABLED); 2408 2409 return copy_to_user(ifr->ifr_data, &conf, sizeof(conf)) ? -EFAULT : 0; 2410 } 2411 2412 /** 2413 * \brief ioctl handler 2414 * @param netdev network device 2415 * @param ifr interface request 2416 * @param cmd command 2417 */ 2418 static int liquidio_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 2419 { 2420 struct lio *lio = GET_LIO(netdev); 2421 2422 switch (cmd) { 2423 case SIOCSHWTSTAMP: 2424 if (lio->oct_dev->ptp_enable) 2425 return hwtstamp_ioctl(netdev, ifr); 2426 default: 2427 return -EOPNOTSUPP; 2428 } 2429 } 2430 2431 /** 2432 * \brief handle a Tx timestamp response 2433 * @param status response status 2434 * @param buf pointer to skb 2435 */ 2436 static void handle_timestamp(struct octeon_device *oct, 2437 u32 status, 2438 void *buf) 2439 { 2440 struct octnet_buf_free_info *finfo; 2441 struct octeon_soft_command *sc; 2442 struct oct_timestamp_resp *resp; 2443 struct lio *lio; 2444 struct sk_buff *skb = (struct sk_buff *)buf; 2445 2446 finfo = (struct octnet_buf_free_info *)skb->cb; 2447 lio = finfo->lio; 2448 sc = finfo->sc; 2449 oct = lio->oct_dev; 2450 resp = (struct oct_timestamp_resp *)sc->virtrptr; 2451 2452 if (status != OCTEON_REQUEST_DONE) { 2453 dev_err(&oct->pci_dev->dev, "Tx timestamp instruction failed. Status: %llx\n", 2454 CVM_CAST64(status)); 2455 resp->timestamp = 0; 2456 } 2457 2458 octeon_swap_8B_data(&resp->timestamp, 1); 2459 2460 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) != 0)) { 2461 struct skb_shared_hwtstamps ts; 2462 u64 ns = resp->timestamp; 2463 2464 netif_info(lio, tx_done, lio->netdev, 2465 "Got resulting SKBTX_HW_TSTAMP skb=%p ns=%016llu\n", 2466 skb, (unsigned long long)ns); 2467 ts.hwtstamp = ns_to_ktime(ns + lio->ptp_adjust); 2468 skb_tstamp_tx(skb, &ts); 2469 } 2470 2471 octeon_free_soft_command(oct, sc); 2472 tx_buffer_free(skb); 2473 } 2474 2475 /* \brief Send a data packet that will be timestamped 2476 * @param oct octeon device 2477 * @param ndata pointer to network data 2478 * @param finfo pointer to private network data 2479 */ 2480 static inline int send_nic_timestamp_pkt(struct octeon_device *oct, 2481 struct octnic_data_pkt *ndata, 2482 struct octnet_buf_free_info *finfo) 2483 { 2484 int retval; 2485 struct octeon_soft_command *sc; 2486 struct lio *lio; 2487 int ring_doorbell; 2488 u32 len; 2489 2490 lio = finfo->lio; 2491 2492 sc = octeon_alloc_soft_command_resp(oct, &ndata->cmd, 2493 sizeof(struct oct_timestamp_resp)); 2494 finfo->sc = sc; 2495 2496 if (!sc) { 2497 dev_err(&oct->pci_dev->dev, "No memory for timestamped data packet\n"); 2498 return IQ_SEND_FAILED; 2499 } 2500 2501 if (ndata->reqtype == REQTYPE_NORESP_NET) 2502 ndata->reqtype = REQTYPE_RESP_NET; 2503 else if (ndata->reqtype == REQTYPE_NORESP_NET_SG) 2504 ndata->reqtype = REQTYPE_RESP_NET_SG; 2505 2506 sc->callback = handle_timestamp; 2507 sc->callback_arg = finfo->skb; 2508 sc->iq_no = ndata->q_no; 2509 2510 if (OCTEON_CN23XX_PF(oct)) 2511 len = (u32)((struct octeon_instr_ih3 *) 2512 (&sc->cmd.cmd3.ih3))->dlengsz; 2513 else 2514 len = (u32)((struct octeon_instr_ih2 *) 2515 (&sc->cmd.cmd2.ih2))->dlengsz; 2516 2517 ring_doorbell = 1; 2518 2519 retval = octeon_send_command(oct, sc->iq_no, ring_doorbell, &sc->cmd, 2520 sc, len, ndata->reqtype); 2521 2522 if (retval == IQ_SEND_FAILED) { 2523 dev_err(&oct->pci_dev->dev, "timestamp data packet failed status: %x\n", 2524 retval); 2525 octeon_free_soft_command(oct, sc); 2526 } else { 2527 netif_info(lio, tx_queued, lio->netdev, "Queued timestamp packet\n"); 2528 } 2529 2530 return retval; 2531 } 2532 2533 /** \brief Transmit networks packets to the Octeon interface 2534 * @param skbuff skbuff struct to be passed to network layer. 2535 * @param netdev pointer to network device 2536 * @returns whether the packet was transmitted to the device okay or not 2537 * (NETDEV_TX_OK or NETDEV_TX_BUSY) 2538 */ 2539 static int liquidio_xmit(struct sk_buff *skb, struct net_device *netdev) 2540 { 2541 struct lio *lio; 2542 struct octnet_buf_free_info *finfo; 2543 union octnic_cmd_setup cmdsetup; 2544 struct octnic_data_pkt ndata; 2545 struct octeon_device *oct; 2546 struct oct_iq_stats *stats; 2547 struct octeon_instr_irh *irh; 2548 union tx_info *tx_info; 2549 int status = 0; 2550 int q_idx = 0, iq_no = 0; 2551 int j; 2552 u64 dptr = 0; 2553 u32 tag = 0; 2554 2555 lio = GET_LIO(netdev); 2556 oct = lio->oct_dev; 2557 2558 if (netif_is_multiqueue(netdev)) { 2559 q_idx = skb->queue_mapping; 2560 q_idx = (q_idx % (lio->linfo.num_txpciq)); 2561 tag = q_idx; 2562 iq_no = lio->linfo.txpciq[q_idx].s.q_no; 2563 } else { 2564 iq_no = lio->txq; 2565 } 2566 2567 stats = &oct->instr_queue[iq_no]->stats; 2568 2569 /* Check for all conditions in which the current packet cannot be 2570 * transmitted. 2571 */ 2572 if (!(atomic_read(&lio->ifstate) & LIO_IFSTATE_RUNNING) || 2573 (!lio->linfo.link.s.link_up) || 2574 (skb->len <= 0)) { 2575 netif_info(lio, tx_err, lio->netdev, 2576 "Transmit failed link_status : %d\n", 2577 lio->linfo.link.s.link_up); 2578 goto lio_xmit_failed; 2579 } 2580 2581 /* Use space in skb->cb to store info used to unmap and 2582 * free the buffers. 2583 */ 2584 finfo = (struct octnet_buf_free_info *)skb->cb; 2585 finfo->lio = lio; 2586 finfo->skb = skb; 2587 finfo->sc = NULL; 2588 2589 /* Prepare the attributes for the data to be passed to OSI. */ 2590 memset(&ndata, 0, sizeof(struct octnic_data_pkt)); 2591 2592 ndata.buf = (void *)finfo; 2593 2594 ndata.q_no = iq_no; 2595 2596 if (netif_is_multiqueue(netdev)) { 2597 if (octnet_iq_is_full(oct, ndata.q_no)) { 2598 /* defer sending if queue is full */ 2599 netif_info(lio, tx_err, lio->netdev, "Transmit failed iq:%d full\n", 2600 ndata.q_no); 2601 stats->tx_iq_busy++; 2602 return NETDEV_TX_BUSY; 2603 } 2604 } else { 2605 if (octnet_iq_is_full(oct, lio->txq)) { 2606 /* defer sending if queue is full */ 2607 stats->tx_iq_busy++; 2608 netif_info(lio, tx_err, lio->netdev, "Transmit failed iq:%d full\n", 2609 lio->txq); 2610 return NETDEV_TX_BUSY; 2611 } 2612 } 2613 /* pr_info(" XMIT - valid Qs: %d, 1st Q no: %d, cpu: %d, q_no:%d\n", 2614 * lio->linfo.num_txpciq, lio->txq, cpu, ndata.q_no); 2615 */ 2616 2617 ndata.datasize = skb->len; 2618 2619 cmdsetup.u64 = 0; 2620 cmdsetup.s.iq_no = iq_no; 2621 2622 if (skb->ip_summed == CHECKSUM_PARTIAL) { 2623 if (skb->encapsulation) { 2624 cmdsetup.s.tnl_csum = 1; 2625 stats->tx_vxlan++; 2626 } else { 2627 cmdsetup.s.transport_csum = 1; 2628 } 2629 } 2630 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { 2631 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 2632 cmdsetup.s.timestamp = 1; 2633 } 2634 2635 if (skb_shinfo(skb)->nr_frags == 0) { 2636 cmdsetup.s.u.datasize = skb->len; 2637 octnet_prepare_pci_cmd(oct, &ndata.cmd, &cmdsetup, tag); 2638 2639 /* Offload checksum calculation for TCP/UDP packets */ 2640 dptr = dma_map_single(&oct->pci_dev->dev, 2641 skb->data, 2642 skb->len, 2643 DMA_TO_DEVICE); 2644 if (dma_mapping_error(&oct->pci_dev->dev, dptr)) { 2645 dev_err(&oct->pci_dev->dev, "%s DMA mapping error 1\n", 2646 __func__); 2647 return NETDEV_TX_BUSY; 2648 } 2649 2650 if (OCTEON_CN23XX_PF(oct)) 2651 ndata.cmd.cmd3.dptr = dptr; 2652 else 2653 ndata.cmd.cmd2.dptr = dptr; 2654 finfo->dptr = dptr; 2655 ndata.reqtype = REQTYPE_NORESP_NET; 2656 2657 } else { 2658 int i, frags; 2659 struct skb_frag_struct *frag; 2660 struct octnic_gather *g; 2661 2662 spin_lock(&lio->glist_lock[q_idx]); 2663 g = (struct octnic_gather *) 2664 list_delete_head(&lio->glist[q_idx]); 2665 spin_unlock(&lio->glist_lock[q_idx]); 2666 2667 if (!g) { 2668 netif_info(lio, tx_err, lio->netdev, 2669 "Transmit scatter gather: glist null!\n"); 2670 goto lio_xmit_failed; 2671 } 2672 2673 cmdsetup.s.gather = 1; 2674 cmdsetup.s.u.gatherptrs = (skb_shinfo(skb)->nr_frags + 1); 2675 octnet_prepare_pci_cmd(oct, &ndata.cmd, &cmdsetup, tag); 2676 2677 memset(g->sg, 0, g->sg_size); 2678 2679 g->sg[0].ptr[0] = dma_map_single(&oct->pci_dev->dev, 2680 skb->data, 2681 (skb->len - skb->data_len), 2682 DMA_TO_DEVICE); 2683 if (dma_mapping_error(&oct->pci_dev->dev, g->sg[0].ptr[0])) { 2684 dev_err(&oct->pci_dev->dev, "%s DMA mapping error 2\n", 2685 __func__); 2686 return NETDEV_TX_BUSY; 2687 } 2688 add_sg_size(&g->sg[0], (skb->len - skb->data_len), 0); 2689 2690 frags = skb_shinfo(skb)->nr_frags; 2691 i = 1; 2692 while (frags--) { 2693 frag = &skb_shinfo(skb)->frags[i - 1]; 2694 2695 g->sg[(i >> 2)].ptr[(i & 3)] = 2696 dma_map_page(&oct->pci_dev->dev, 2697 frag->page.p, 2698 frag->page_offset, 2699 frag->size, 2700 DMA_TO_DEVICE); 2701 2702 if (dma_mapping_error(&oct->pci_dev->dev, 2703 g->sg[i >> 2].ptr[i & 3])) { 2704 dma_unmap_single(&oct->pci_dev->dev, 2705 g->sg[0].ptr[0], 2706 skb->len - skb->data_len, 2707 DMA_TO_DEVICE); 2708 for (j = 1; j < i; j++) { 2709 frag = &skb_shinfo(skb)->frags[j - 1]; 2710 dma_unmap_page(&oct->pci_dev->dev, 2711 g->sg[j >> 2].ptr[j & 3], 2712 frag->size, 2713 DMA_TO_DEVICE); 2714 } 2715 dev_err(&oct->pci_dev->dev, "%s DMA mapping error 3\n", 2716 __func__); 2717 return NETDEV_TX_BUSY; 2718 } 2719 2720 add_sg_size(&g->sg[(i >> 2)], frag->size, (i & 3)); 2721 i++; 2722 } 2723 2724 dptr = g->sg_dma_ptr; 2725 2726 if (OCTEON_CN23XX_PF(oct)) 2727 ndata.cmd.cmd3.dptr = dptr; 2728 else 2729 ndata.cmd.cmd2.dptr = dptr; 2730 finfo->dptr = dptr; 2731 finfo->g = g; 2732 2733 ndata.reqtype = REQTYPE_NORESP_NET_SG; 2734 } 2735 2736 if (OCTEON_CN23XX_PF(oct)) { 2737 irh = (struct octeon_instr_irh *)&ndata.cmd.cmd3.irh; 2738 tx_info = (union tx_info *)&ndata.cmd.cmd3.ossp[0]; 2739 } else { 2740 irh = (struct octeon_instr_irh *)&ndata.cmd.cmd2.irh; 2741 tx_info = (union tx_info *)&ndata.cmd.cmd2.ossp[0]; 2742 } 2743 2744 if (skb_shinfo(skb)->gso_size) { 2745 tx_info->s.gso_size = skb_shinfo(skb)->gso_size; 2746 tx_info->s.gso_segs = skb_shinfo(skb)->gso_segs; 2747 stats->tx_gso++; 2748 } 2749 2750 /* HW insert VLAN tag */ 2751 if (skb_vlan_tag_present(skb)) { 2752 irh->priority = skb_vlan_tag_get(skb) >> 13; 2753 irh->vlan = skb_vlan_tag_get(skb) & 0xfff; 2754 } 2755 2756 if (unlikely(cmdsetup.s.timestamp)) 2757 status = send_nic_timestamp_pkt(oct, &ndata, finfo); 2758 else 2759 status = octnet_send_nic_data_pkt(oct, &ndata); 2760 if (status == IQ_SEND_FAILED) 2761 goto lio_xmit_failed; 2762 2763 netif_info(lio, tx_queued, lio->netdev, "Transmit queued successfully\n"); 2764 2765 if (status == IQ_SEND_STOP) 2766 stop_q(lio->netdev, q_idx); 2767 2768 netif_trans_update(netdev); 2769 2770 if (tx_info->s.gso_segs) 2771 stats->tx_done += tx_info->s.gso_segs; 2772 else 2773 stats->tx_done++; 2774 stats->tx_tot_bytes += ndata.datasize; 2775 2776 return NETDEV_TX_OK; 2777 2778 lio_xmit_failed: 2779 stats->tx_dropped++; 2780 netif_info(lio, tx_err, lio->netdev, "IQ%d Transmit dropped:%llu\n", 2781 iq_no, stats->tx_dropped); 2782 if (dptr) 2783 dma_unmap_single(&oct->pci_dev->dev, dptr, 2784 ndata.datasize, DMA_TO_DEVICE); 2785 tx_buffer_free(skb); 2786 return NETDEV_TX_OK; 2787 } 2788 2789 /** \brief Network device Tx timeout 2790 * @param netdev pointer to network device 2791 */ 2792 static void liquidio_tx_timeout(struct net_device *netdev) 2793 { 2794 struct lio *lio; 2795 2796 lio = GET_LIO(netdev); 2797 2798 netif_info(lio, tx_err, lio->netdev, 2799 "Transmit timeout tx_dropped:%ld, waking up queues now!!\n", 2800 netdev->stats.tx_dropped); 2801 netif_trans_update(netdev); 2802 txqs_wake(netdev); 2803 } 2804 2805 static int liquidio_vlan_rx_add_vid(struct net_device *netdev, 2806 __be16 proto __attribute__((unused)), 2807 u16 vid) 2808 { 2809 struct lio *lio = GET_LIO(netdev); 2810 struct octeon_device *oct = lio->oct_dev; 2811 struct octnic_ctrl_pkt nctrl; 2812 int ret = 0; 2813 2814 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt)); 2815 2816 nctrl.ncmd.u64 = 0; 2817 nctrl.ncmd.s.cmd = OCTNET_CMD_ADD_VLAN_FILTER; 2818 nctrl.ncmd.s.param1 = vid; 2819 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no; 2820 nctrl.wait_time = 100; 2821 nctrl.netpndev = (u64)netdev; 2822 nctrl.cb_fn = liquidio_link_ctrl_cmd_completion; 2823 2824 ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl); 2825 if (ret < 0) { 2826 dev_err(&oct->pci_dev->dev, "Add VLAN filter failed in core (ret: 0x%x)\n", 2827 ret); 2828 } 2829 2830 return ret; 2831 } 2832 2833 static int liquidio_vlan_rx_kill_vid(struct net_device *netdev, 2834 __be16 proto __attribute__((unused)), 2835 u16 vid) 2836 { 2837 struct lio *lio = GET_LIO(netdev); 2838 struct octeon_device *oct = lio->oct_dev; 2839 struct octnic_ctrl_pkt nctrl; 2840 int ret = 0; 2841 2842 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt)); 2843 2844 nctrl.ncmd.u64 = 0; 2845 nctrl.ncmd.s.cmd = OCTNET_CMD_DEL_VLAN_FILTER; 2846 nctrl.ncmd.s.param1 = vid; 2847 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no; 2848 nctrl.wait_time = 100; 2849 nctrl.netpndev = (u64)netdev; 2850 nctrl.cb_fn = liquidio_link_ctrl_cmd_completion; 2851 2852 ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl); 2853 if (ret < 0) { 2854 dev_err(&oct->pci_dev->dev, "Add VLAN filter failed in core (ret: 0x%x)\n", 2855 ret); 2856 } 2857 return ret; 2858 } 2859 2860 /** Sending command to enable/disable RX checksum offload 2861 * @param netdev pointer to network device 2862 * @param command OCTNET_CMD_TNL_RX_CSUM_CTL 2863 * @param rx_cmd_bit OCTNET_CMD_RXCSUM_ENABLE/ 2864 * OCTNET_CMD_RXCSUM_DISABLE 2865 * @returns SUCCESS or FAILURE 2866 */ 2867 static int liquidio_set_rxcsum_command(struct net_device *netdev, int command, 2868 u8 rx_cmd) 2869 { 2870 struct lio *lio = GET_LIO(netdev); 2871 struct octeon_device *oct = lio->oct_dev; 2872 struct octnic_ctrl_pkt nctrl; 2873 int ret = 0; 2874 2875 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt)); 2876 2877 nctrl.ncmd.u64 = 0; 2878 nctrl.ncmd.s.cmd = command; 2879 nctrl.ncmd.s.param1 = rx_cmd; 2880 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no; 2881 nctrl.wait_time = 100; 2882 nctrl.netpndev = (u64)netdev; 2883 nctrl.cb_fn = liquidio_link_ctrl_cmd_completion; 2884 2885 ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl); 2886 if (ret < 0) { 2887 dev_err(&oct->pci_dev->dev, 2888 "DEVFLAGS RXCSUM change failed in core(ret:0x%x)\n", 2889 ret); 2890 } 2891 return ret; 2892 } 2893 2894 /** Sending command to add/delete VxLAN UDP port to firmware 2895 * @param netdev pointer to network device 2896 * @param command OCTNET_CMD_VXLAN_PORT_CONFIG 2897 * @param vxlan_port VxLAN port to be added or deleted 2898 * @param vxlan_cmd_bit OCTNET_CMD_VXLAN_PORT_ADD, 2899 * OCTNET_CMD_VXLAN_PORT_DEL 2900 * @returns SUCCESS or FAILURE 2901 */ 2902 static int liquidio_vxlan_port_command(struct net_device *netdev, int command, 2903 u16 vxlan_port, u8 vxlan_cmd_bit) 2904 { 2905 struct lio *lio = GET_LIO(netdev); 2906 struct octeon_device *oct = lio->oct_dev; 2907 struct octnic_ctrl_pkt nctrl; 2908 int ret = 0; 2909 2910 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt)); 2911 2912 nctrl.ncmd.u64 = 0; 2913 nctrl.ncmd.s.cmd = command; 2914 nctrl.ncmd.s.more = vxlan_cmd_bit; 2915 nctrl.ncmd.s.param1 = vxlan_port; 2916 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no; 2917 nctrl.wait_time = 100; 2918 nctrl.netpndev = (u64)netdev; 2919 nctrl.cb_fn = liquidio_link_ctrl_cmd_completion; 2920 2921 ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl); 2922 if (ret < 0) { 2923 dev_err(&oct->pci_dev->dev, 2924 "VxLAN port add/delete failed in core (ret:0x%x)\n", 2925 ret); 2926 } 2927 return ret; 2928 } 2929 2930 /** \brief Net device fix features 2931 * @param netdev pointer to network device 2932 * @param request features requested 2933 * @returns updated features list 2934 */ 2935 static netdev_features_t liquidio_fix_features(struct net_device *netdev, 2936 netdev_features_t request) 2937 { 2938 struct lio *lio = netdev_priv(netdev); 2939 2940 if ((request & NETIF_F_RXCSUM) && 2941 !(lio->dev_capability & NETIF_F_RXCSUM)) 2942 request &= ~NETIF_F_RXCSUM; 2943 2944 if ((request & NETIF_F_HW_CSUM) && 2945 !(lio->dev_capability & NETIF_F_HW_CSUM)) 2946 request &= ~NETIF_F_HW_CSUM; 2947 2948 if ((request & NETIF_F_TSO) && !(lio->dev_capability & NETIF_F_TSO)) 2949 request &= ~NETIF_F_TSO; 2950 2951 if ((request & NETIF_F_TSO6) && !(lio->dev_capability & NETIF_F_TSO6)) 2952 request &= ~NETIF_F_TSO6; 2953 2954 if ((request & NETIF_F_LRO) && !(lio->dev_capability & NETIF_F_LRO)) 2955 request &= ~NETIF_F_LRO; 2956 2957 /*Disable LRO if RXCSUM is off */ 2958 if (!(request & NETIF_F_RXCSUM) && (netdev->features & NETIF_F_LRO) && 2959 (lio->dev_capability & NETIF_F_LRO)) 2960 request &= ~NETIF_F_LRO; 2961 2962 if ((request & NETIF_F_HW_VLAN_CTAG_FILTER) && 2963 !(lio->dev_capability & NETIF_F_HW_VLAN_CTAG_FILTER)) 2964 request &= ~NETIF_F_HW_VLAN_CTAG_FILTER; 2965 2966 return request; 2967 } 2968 2969 /** \brief Net device set features 2970 * @param netdev pointer to network device 2971 * @param features features to enable/disable 2972 */ 2973 static int liquidio_set_features(struct net_device *netdev, 2974 netdev_features_t features) 2975 { 2976 struct lio *lio = netdev_priv(netdev); 2977 2978 if ((features & NETIF_F_LRO) && 2979 (lio->dev_capability & NETIF_F_LRO) && 2980 !(netdev->features & NETIF_F_LRO)) 2981 liquidio_set_feature(netdev, OCTNET_CMD_LRO_ENABLE, 2982 OCTNIC_LROIPV4 | OCTNIC_LROIPV6); 2983 else if (!(features & NETIF_F_LRO) && 2984 (lio->dev_capability & NETIF_F_LRO) && 2985 (netdev->features & NETIF_F_LRO)) 2986 liquidio_set_feature(netdev, OCTNET_CMD_LRO_DISABLE, 2987 OCTNIC_LROIPV4 | OCTNIC_LROIPV6); 2988 2989 /* Sending command to firmware to enable/disable RX checksum 2990 * offload settings using ethtool 2991 */ 2992 if (!(netdev->features & NETIF_F_RXCSUM) && 2993 (lio->enc_dev_capability & NETIF_F_RXCSUM) && 2994 (features & NETIF_F_RXCSUM)) 2995 liquidio_set_rxcsum_command(netdev, 2996 OCTNET_CMD_TNL_RX_CSUM_CTL, 2997 OCTNET_CMD_RXCSUM_ENABLE); 2998 else if ((netdev->features & NETIF_F_RXCSUM) && 2999 (lio->enc_dev_capability & NETIF_F_RXCSUM) && 3000 !(features & NETIF_F_RXCSUM)) 3001 liquidio_set_rxcsum_command(netdev, OCTNET_CMD_TNL_RX_CSUM_CTL, 3002 OCTNET_CMD_RXCSUM_DISABLE); 3003 3004 if ((features & NETIF_F_HW_VLAN_CTAG_FILTER) && 3005 (lio->dev_capability & NETIF_F_HW_VLAN_CTAG_FILTER) && 3006 !(netdev->features & NETIF_F_HW_VLAN_CTAG_FILTER)) 3007 liquidio_set_feature(netdev, OCTNET_CMD_VLAN_FILTER_CTL, 3008 OCTNET_CMD_VLAN_FILTER_ENABLE); 3009 else if (!(features & NETIF_F_HW_VLAN_CTAG_FILTER) && 3010 (lio->dev_capability & NETIF_F_HW_VLAN_CTAG_FILTER) && 3011 (netdev->features & NETIF_F_HW_VLAN_CTAG_FILTER)) 3012 liquidio_set_feature(netdev, OCTNET_CMD_VLAN_FILTER_CTL, 3013 OCTNET_CMD_VLAN_FILTER_DISABLE); 3014 3015 return 0; 3016 } 3017 3018 static void liquidio_add_vxlan_port(struct net_device *netdev, 3019 struct udp_tunnel_info *ti) 3020 { 3021 if (ti->type != UDP_TUNNEL_TYPE_VXLAN) 3022 return; 3023 3024 liquidio_vxlan_port_command(netdev, 3025 OCTNET_CMD_VXLAN_PORT_CONFIG, 3026 htons(ti->port), 3027 OCTNET_CMD_VXLAN_PORT_ADD); 3028 } 3029 3030 static void liquidio_del_vxlan_port(struct net_device *netdev, 3031 struct udp_tunnel_info *ti) 3032 { 3033 if (ti->type != UDP_TUNNEL_TYPE_VXLAN) 3034 return; 3035 3036 liquidio_vxlan_port_command(netdev, 3037 OCTNET_CMD_VXLAN_PORT_CONFIG, 3038 htons(ti->port), 3039 OCTNET_CMD_VXLAN_PORT_DEL); 3040 } 3041 3042 static int __liquidio_set_vf_mac(struct net_device *netdev, int vfidx, 3043 u8 *mac, bool is_admin_assigned) 3044 { 3045 struct lio *lio = GET_LIO(netdev); 3046 struct octeon_device *oct = lio->oct_dev; 3047 struct octnic_ctrl_pkt nctrl; 3048 3049 if (!is_valid_ether_addr(mac)) 3050 return -EINVAL; 3051 3052 if (vfidx < 0 || vfidx >= oct->sriov_info.max_vfs) 3053 return -EINVAL; 3054 3055 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt)); 3056 3057 nctrl.ncmd.u64 = 0; 3058 nctrl.ncmd.s.cmd = OCTNET_CMD_CHANGE_MACADDR; 3059 /* vfidx is 0 based, but vf_num (param1) is 1 based */ 3060 nctrl.ncmd.s.param1 = vfidx + 1; 3061 nctrl.ncmd.s.param2 = (is_admin_assigned ? 1 : 0); 3062 nctrl.ncmd.s.more = 1; 3063 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no; 3064 nctrl.netpndev = (u64)netdev; 3065 nctrl.cb_fn = liquidio_link_ctrl_cmd_completion; 3066 nctrl.wait_time = LIO_CMD_WAIT_TM; 3067 3068 nctrl.udd[0] = 0; 3069 /* The MAC Address is presented in network byte order. */ 3070 ether_addr_copy((u8 *)&nctrl.udd[0] + 2, mac); 3071 3072 oct->sriov_info.vf_macaddr[vfidx] = nctrl.udd[0]; 3073 3074 octnet_send_nic_ctrl_pkt(oct, &nctrl); 3075 3076 return 0; 3077 } 3078 3079 static int liquidio_set_vf_mac(struct net_device *netdev, int vfidx, u8 *mac) 3080 { 3081 struct lio *lio = GET_LIO(netdev); 3082 struct octeon_device *oct = lio->oct_dev; 3083 int retval; 3084 3085 if (vfidx < 0 || vfidx >= oct->sriov_info.num_vfs_alloced) 3086 return -EINVAL; 3087 3088 retval = __liquidio_set_vf_mac(netdev, vfidx, mac, true); 3089 if (!retval) 3090 cn23xx_tell_vf_its_macaddr_changed(oct, vfidx, mac); 3091 3092 return retval; 3093 } 3094 3095 static int liquidio_set_vf_vlan(struct net_device *netdev, int vfidx, 3096 u16 vlan, u8 qos, __be16 vlan_proto) 3097 { 3098 struct lio *lio = GET_LIO(netdev); 3099 struct octeon_device *oct = lio->oct_dev; 3100 struct octnic_ctrl_pkt nctrl; 3101 u16 vlantci; 3102 3103 if (vfidx < 0 || vfidx >= oct->sriov_info.num_vfs_alloced) 3104 return -EINVAL; 3105 3106 if (vlan_proto != htons(ETH_P_8021Q)) 3107 return -EPROTONOSUPPORT; 3108 3109 if (vlan >= VLAN_N_VID || qos > 7) 3110 return -EINVAL; 3111 3112 if (vlan) 3113 vlantci = vlan | (u16)qos << VLAN_PRIO_SHIFT; 3114 else 3115 vlantci = 0; 3116 3117 if (oct->sriov_info.vf_vlantci[vfidx] == vlantci) 3118 return 0; 3119 3120 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt)); 3121 3122 if (vlan) 3123 nctrl.ncmd.s.cmd = OCTNET_CMD_ADD_VLAN_FILTER; 3124 else 3125 nctrl.ncmd.s.cmd = OCTNET_CMD_DEL_VLAN_FILTER; 3126 3127 nctrl.ncmd.s.param1 = vlantci; 3128 nctrl.ncmd.s.param2 = 3129 vfidx + 1; /* vfidx is 0 based, but vf_num (param2) is 1 based */ 3130 nctrl.ncmd.s.more = 0; 3131 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no; 3132 nctrl.cb_fn = 0; 3133 nctrl.wait_time = LIO_CMD_WAIT_TM; 3134 3135 octnet_send_nic_ctrl_pkt(oct, &nctrl); 3136 3137 oct->sriov_info.vf_vlantci[vfidx] = vlantci; 3138 3139 return 0; 3140 } 3141 3142 static int liquidio_get_vf_config(struct net_device *netdev, int vfidx, 3143 struct ifla_vf_info *ivi) 3144 { 3145 struct lio *lio = GET_LIO(netdev); 3146 struct octeon_device *oct = lio->oct_dev; 3147 u8 *macaddr; 3148 3149 if (vfidx < 0 || vfidx >= oct->sriov_info.num_vfs_alloced) 3150 return -EINVAL; 3151 3152 ivi->vf = vfidx; 3153 macaddr = 2 + (u8 *)&oct->sriov_info.vf_macaddr[vfidx]; 3154 ether_addr_copy(&ivi->mac[0], macaddr); 3155 ivi->vlan = oct->sriov_info.vf_vlantci[vfidx] & VLAN_VID_MASK; 3156 ivi->qos = oct->sriov_info.vf_vlantci[vfidx] >> VLAN_PRIO_SHIFT; 3157 ivi->linkstate = oct->sriov_info.vf_linkstate[vfidx]; 3158 return 0; 3159 } 3160 3161 static int liquidio_set_vf_link_state(struct net_device *netdev, int vfidx, 3162 int linkstate) 3163 { 3164 struct lio *lio = GET_LIO(netdev); 3165 struct octeon_device *oct = lio->oct_dev; 3166 struct octnic_ctrl_pkt nctrl; 3167 3168 if (vfidx < 0 || vfidx >= oct->sriov_info.num_vfs_alloced) 3169 return -EINVAL; 3170 3171 if (oct->sriov_info.vf_linkstate[vfidx] == linkstate) 3172 return 0; 3173 3174 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt)); 3175 nctrl.ncmd.s.cmd = OCTNET_CMD_SET_VF_LINKSTATE; 3176 nctrl.ncmd.s.param1 = 3177 vfidx + 1; /* vfidx is 0 based, but vf_num (param1) is 1 based */ 3178 nctrl.ncmd.s.param2 = linkstate; 3179 nctrl.ncmd.s.more = 0; 3180 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no; 3181 nctrl.cb_fn = 0; 3182 nctrl.wait_time = LIO_CMD_WAIT_TM; 3183 3184 octnet_send_nic_ctrl_pkt(oct, &nctrl); 3185 3186 oct->sriov_info.vf_linkstate[vfidx] = linkstate; 3187 3188 return 0; 3189 } 3190 3191 static const struct net_device_ops lionetdevops = { 3192 .ndo_open = liquidio_open, 3193 .ndo_stop = liquidio_stop, 3194 .ndo_start_xmit = liquidio_xmit, 3195 .ndo_get_stats = liquidio_get_stats, 3196 .ndo_set_mac_address = liquidio_set_mac, 3197 .ndo_set_rx_mode = liquidio_set_mcast_list, 3198 .ndo_tx_timeout = liquidio_tx_timeout, 3199 3200 .ndo_vlan_rx_add_vid = liquidio_vlan_rx_add_vid, 3201 .ndo_vlan_rx_kill_vid = liquidio_vlan_rx_kill_vid, 3202 .ndo_change_mtu = liquidio_change_mtu, 3203 .ndo_do_ioctl = liquidio_ioctl, 3204 .ndo_fix_features = liquidio_fix_features, 3205 .ndo_set_features = liquidio_set_features, 3206 .ndo_udp_tunnel_add = liquidio_add_vxlan_port, 3207 .ndo_udp_tunnel_del = liquidio_del_vxlan_port, 3208 .ndo_set_vf_mac = liquidio_set_vf_mac, 3209 .ndo_set_vf_vlan = liquidio_set_vf_vlan, 3210 .ndo_get_vf_config = liquidio_get_vf_config, 3211 .ndo_set_vf_link_state = liquidio_set_vf_link_state, 3212 }; 3213 3214 /** \brief Entry point for the liquidio module 3215 */ 3216 static int __init liquidio_init(void) 3217 { 3218 int i; 3219 struct handshake *hs; 3220 3221 init_completion(&first_stage); 3222 3223 octeon_init_device_list(OCTEON_CONFIG_TYPE_DEFAULT); 3224 3225 if (liquidio_init_pci()) 3226 return -EINVAL; 3227 3228 wait_for_completion_timeout(&first_stage, msecs_to_jiffies(1000)); 3229 3230 for (i = 0; i < MAX_OCTEON_DEVICES; i++) { 3231 hs = &handshake[i]; 3232 if (hs->pci_dev) { 3233 wait_for_completion(&hs->init); 3234 if (!hs->init_ok) { 3235 /* init handshake failed */ 3236 dev_err(&hs->pci_dev->dev, 3237 "Failed to init device\n"); 3238 liquidio_deinit_pci(); 3239 return -EIO; 3240 } 3241 } 3242 } 3243 3244 for (i = 0; i < MAX_OCTEON_DEVICES; i++) { 3245 hs = &handshake[i]; 3246 if (hs->pci_dev) { 3247 wait_for_completion_timeout(&hs->started, 3248 msecs_to_jiffies(30000)); 3249 if (!hs->started_ok) { 3250 /* starter handshake failed */ 3251 dev_err(&hs->pci_dev->dev, 3252 "Firmware failed to start\n"); 3253 liquidio_deinit_pci(); 3254 return -EIO; 3255 } 3256 } 3257 } 3258 3259 return 0; 3260 } 3261 3262 static int lio_nic_info(struct octeon_recv_info *recv_info, void *buf) 3263 { 3264 struct octeon_device *oct = (struct octeon_device *)buf; 3265 struct octeon_recv_pkt *recv_pkt = recv_info->recv_pkt; 3266 int gmxport = 0; 3267 union oct_link_status *ls; 3268 int i; 3269 3270 if (recv_pkt->buffer_size[0] != (sizeof(*ls) + OCT_DROQ_INFO_SIZE)) { 3271 dev_err(&oct->pci_dev->dev, "Malformed NIC_INFO, len=%d, ifidx=%d\n", 3272 recv_pkt->buffer_size[0], 3273 recv_pkt->rh.r_nic_info.gmxport); 3274 goto nic_info_err; 3275 } 3276 3277 gmxport = recv_pkt->rh.r_nic_info.gmxport; 3278 ls = (union oct_link_status *)(get_rbd(recv_pkt->buffer_ptr[0]) + 3279 OCT_DROQ_INFO_SIZE); 3280 3281 octeon_swap_8B_data((u64 *)ls, (sizeof(union oct_link_status)) >> 3); 3282 for (i = 0; i < oct->ifcount; i++) { 3283 if (oct->props[i].gmxport == gmxport) { 3284 update_link_status(oct->props[i].netdev, ls); 3285 break; 3286 } 3287 } 3288 3289 nic_info_err: 3290 for (i = 0; i < recv_pkt->buffer_count; i++) 3291 recv_buffer_free(recv_pkt->buffer_ptr[i]); 3292 octeon_free_recv_info(recv_info); 3293 return 0; 3294 } 3295 3296 /** 3297 * \brief Setup network interfaces 3298 * @param octeon_dev octeon device 3299 * 3300 * Called during init time for each device. It assumes the NIC 3301 * is already up and running. The link information for each 3302 * interface is passed in link_info. 3303 */ 3304 static int setup_nic_devices(struct octeon_device *octeon_dev) 3305 { 3306 struct lio *lio = NULL; 3307 struct net_device *netdev; 3308 u8 mac[6], i, j, *fw_ver; 3309 struct octeon_soft_command *sc; 3310 struct liquidio_if_cfg_context *ctx; 3311 struct liquidio_if_cfg_resp *resp; 3312 struct octdev_props *props; 3313 int retval, num_iqueues, num_oqueues; 3314 union oct_nic_if_cfg if_cfg; 3315 unsigned int base_queue; 3316 unsigned int gmx_port_id; 3317 u32 resp_size, ctx_size, data_size; 3318 u32 ifidx_or_pfnum; 3319 struct lio_version *vdata; 3320 3321 /* This is to handle link status changes */ 3322 octeon_register_dispatch_fn(octeon_dev, OPCODE_NIC, 3323 OPCODE_NIC_INFO, 3324 lio_nic_info, octeon_dev); 3325 3326 /* REQTYPE_RESP_NET and REQTYPE_SOFT_COMMAND do not have free functions. 3327 * They are handled directly. 3328 */ 3329 octeon_register_reqtype_free_fn(octeon_dev, REQTYPE_NORESP_NET, 3330 free_netbuf); 3331 3332 octeon_register_reqtype_free_fn(octeon_dev, REQTYPE_NORESP_NET_SG, 3333 free_netsgbuf); 3334 3335 octeon_register_reqtype_free_fn(octeon_dev, REQTYPE_RESP_NET_SG, 3336 free_netsgbuf_with_resp); 3337 3338 for (i = 0; i < octeon_dev->ifcount; i++) { 3339 resp_size = sizeof(struct liquidio_if_cfg_resp); 3340 ctx_size = sizeof(struct liquidio_if_cfg_context); 3341 data_size = sizeof(struct lio_version); 3342 sc = (struct octeon_soft_command *) 3343 octeon_alloc_soft_command(octeon_dev, data_size, 3344 resp_size, ctx_size); 3345 resp = (struct liquidio_if_cfg_resp *)sc->virtrptr; 3346 ctx = (struct liquidio_if_cfg_context *)sc->ctxptr; 3347 vdata = (struct lio_version *)sc->virtdptr; 3348 3349 *((u64 *)vdata) = 0; 3350 vdata->major = cpu_to_be16(LIQUIDIO_BASE_MAJOR_VERSION); 3351 vdata->minor = cpu_to_be16(LIQUIDIO_BASE_MINOR_VERSION); 3352 vdata->micro = cpu_to_be16(LIQUIDIO_BASE_MICRO_VERSION); 3353 3354 if (OCTEON_CN23XX_PF(octeon_dev)) { 3355 num_iqueues = octeon_dev->sriov_info.num_pf_rings; 3356 num_oqueues = octeon_dev->sriov_info.num_pf_rings; 3357 base_queue = octeon_dev->sriov_info.pf_srn; 3358 3359 gmx_port_id = octeon_dev->pf_num; 3360 ifidx_or_pfnum = octeon_dev->pf_num; 3361 } else { 3362 num_iqueues = CFG_GET_NUM_TXQS_NIC_IF( 3363 octeon_get_conf(octeon_dev), i); 3364 num_oqueues = CFG_GET_NUM_RXQS_NIC_IF( 3365 octeon_get_conf(octeon_dev), i); 3366 base_queue = CFG_GET_BASE_QUE_NIC_IF( 3367 octeon_get_conf(octeon_dev), i); 3368 gmx_port_id = CFG_GET_GMXID_NIC_IF( 3369 octeon_get_conf(octeon_dev), i); 3370 ifidx_or_pfnum = i; 3371 } 3372 3373 dev_dbg(&octeon_dev->pci_dev->dev, 3374 "requesting config for interface %d, iqs %d, oqs %d\n", 3375 ifidx_or_pfnum, num_iqueues, num_oqueues); 3376 WRITE_ONCE(ctx->cond, 0); 3377 ctx->octeon_id = lio_get_device_id(octeon_dev); 3378 init_waitqueue_head(&ctx->wc); 3379 3380 if_cfg.u64 = 0; 3381 if_cfg.s.num_iqueues = num_iqueues; 3382 if_cfg.s.num_oqueues = num_oqueues; 3383 if_cfg.s.base_queue = base_queue; 3384 if_cfg.s.gmx_port_id = gmx_port_id; 3385 3386 sc->iq_no = 0; 3387 3388 octeon_prepare_soft_command(octeon_dev, sc, OPCODE_NIC, 3389 OPCODE_NIC_IF_CFG, 0, 3390 if_cfg.u64, 0); 3391 3392 sc->callback = if_cfg_callback; 3393 sc->callback_arg = sc; 3394 sc->wait_time = 3000; 3395 3396 retval = octeon_send_soft_command(octeon_dev, sc); 3397 if (retval == IQ_SEND_FAILED) { 3398 dev_err(&octeon_dev->pci_dev->dev, 3399 "iq/oq config failed status: %x\n", 3400 retval); 3401 /* Soft instr is freed by driver in case of failure. */ 3402 goto setup_nic_dev_fail; 3403 } 3404 3405 /* Sleep on a wait queue till the cond flag indicates that the 3406 * response arrived or timed-out. 3407 */ 3408 if (sleep_cond(&ctx->wc, &ctx->cond) == -EINTR) { 3409 dev_err(&octeon_dev->pci_dev->dev, "Wait interrupted\n"); 3410 goto setup_nic_wait_intr; 3411 } 3412 3413 retval = resp->status; 3414 if (retval) { 3415 dev_err(&octeon_dev->pci_dev->dev, "iq/oq config failed\n"); 3416 goto setup_nic_dev_fail; 3417 } 3418 3419 /* Verify f/w version (in case of 'auto' loading from flash) */ 3420 fw_ver = octeon_dev->fw_info.liquidio_firmware_version; 3421 if (memcmp(LIQUIDIO_BASE_VERSION, 3422 fw_ver, 3423 strlen(LIQUIDIO_BASE_VERSION))) { 3424 dev_err(&octeon_dev->pci_dev->dev, 3425 "Unmatched firmware version. Expected %s.x, got %s.\n", 3426 LIQUIDIO_BASE_VERSION, fw_ver); 3427 goto setup_nic_dev_fail; 3428 } else if (atomic_read(octeon_dev->adapter_fw_state) == 3429 FW_IS_PRELOADED) { 3430 dev_info(&octeon_dev->pci_dev->dev, 3431 "Using auto-loaded firmware version %s.\n", 3432 fw_ver); 3433 } 3434 3435 octeon_swap_8B_data((u64 *)(&resp->cfg_info), 3436 (sizeof(struct liquidio_if_cfg_info)) >> 3); 3437 3438 num_iqueues = hweight64(resp->cfg_info.iqmask); 3439 num_oqueues = hweight64(resp->cfg_info.oqmask); 3440 3441 if (!(num_iqueues) || !(num_oqueues)) { 3442 dev_err(&octeon_dev->pci_dev->dev, 3443 "Got bad iqueues (%016llx) or oqueues (%016llx) from firmware.\n", 3444 resp->cfg_info.iqmask, 3445 resp->cfg_info.oqmask); 3446 goto setup_nic_dev_fail; 3447 } 3448 dev_dbg(&octeon_dev->pci_dev->dev, 3449 "interface %d, iqmask %016llx, oqmask %016llx, numiqueues %d, numoqueues %d\n", 3450 i, resp->cfg_info.iqmask, resp->cfg_info.oqmask, 3451 num_iqueues, num_oqueues); 3452 netdev = alloc_etherdev_mq(LIO_SIZE, num_iqueues); 3453 3454 if (!netdev) { 3455 dev_err(&octeon_dev->pci_dev->dev, "Device allocation failed\n"); 3456 goto setup_nic_dev_fail; 3457 } 3458 3459 SET_NETDEV_DEV(netdev, &octeon_dev->pci_dev->dev); 3460 3461 /* Associate the routines that will handle different 3462 * netdev tasks. 3463 */ 3464 netdev->netdev_ops = &lionetdevops; 3465 3466 lio = GET_LIO(netdev); 3467 3468 memset(lio, 0, sizeof(struct lio)); 3469 3470 lio->ifidx = ifidx_or_pfnum; 3471 3472 props = &octeon_dev->props[i]; 3473 props->gmxport = resp->cfg_info.linfo.gmxport; 3474 props->netdev = netdev; 3475 3476 lio->linfo.num_rxpciq = num_oqueues; 3477 lio->linfo.num_txpciq = num_iqueues; 3478 for (j = 0; j < num_oqueues; j++) { 3479 lio->linfo.rxpciq[j].u64 = 3480 resp->cfg_info.linfo.rxpciq[j].u64; 3481 } 3482 for (j = 0; j < num_iqueues; j++) { 3483 lio->linfo.txpciq[j].u64 = 3484 resp->cfg_info.linfo.txpciq[j].u64; 3485 } 3486 lio->linfo.hw_addr = resp->cfg_info.linfo.hw_addr; 3487 lio->linfo.gmxport = resp->cfg_info.linfo.gmxport; 3488 lio->linfo.link.u64 = resp->cfg_info.linfo.link.u64; 3489 3490 lio->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 3491 3492 if (OCTEON_CN23XX_PF(octeon_dev) || 3493 OCTEON_CN6XXX(octeon_dev)) { 3494 lio->dev_capability = NETIF_F_HIGHDMA 3495 | NETIF_F_IP_CSUM 3496 | NETIF_F_IPV6_CSUM 3497 | NETIF_F_SG | NETIF_F_RXCSUM 3498 | NETIF_F_GRO 3499 | NETIF_F_TSO | NETIF_F_TSO6 3500 | NETIF_F_LRO; 3501 } 3502 netif_set_gso_max_size(netdev, OCTNIC_GSO_MAX_SIZE); 3503 3504 /* Copy of transmit encapsulation capabilities: 3505 * TSO, TSO6, Checksums for this device 3506 */ 3507 lio->enc_dev_capability = NETIF_F_IP_CSUM 3508 | NETIF_F_IPV6_CSUM 3509 | NETIF_F_GSO_UDP_TUNNEL 3510 | NETIF_F_HW_CSUM | NETIF_F_SG 3511 | NETIF_F_RXCSUM 3512 | NETIF_F_TSO | NETIF_F_TSO6 3513 | NETIF_F_LRO; 3514 3515 netdev->hw_enc_features = (lio->enc_dev_capability & 3516 ~NETIF_F_LRO); 3517 3518 lio->dev_capability |= NETIF_F_GSO_UDP_TUNNEL; 3519 3520 netdev->vlan_features = lio->dev_capability; 3521 /* Add any unchangeable hw features */ 3522 lio->dev_capability |= NETIF_F_HW_VLAN_CTAG_FILTER | 3523 NETIF_F_HW_VLAN_CTAG_RX | 3524 NETIF_F_HW_VLAN_CTAG_TX; 3525 3526 netdev->features = (lio->dev_capability & ~NETIF_F_LRO); 3527 3528 netdev->hw_features = lio->dev_capability; 3529 /*HW_VLAN_RX and HW_VLAN_FILTER is always on*/ 3530 netdev->hw_features = netdev->hw_features & 3531 ~NETIF_F_HW_VLAN_CTAG_RX; 3532 3533 /* MTU range: 68 - 16000 */ 3534 netdev->min_mtu = LIO_MIN_MTU_SIZE; 3535 netdev->max_mtu = LIO_MAX_MTU_SIZE; 3536 3537 /* Point to the properties for octeon device to which this 3538 * interface belongs. 3539 */ 3540 lio->oct_dev = octeon_dev; 3541 lio->octprops = props; 3542 lio->netdev = netdev; 3543 3544 dev_dbg(&octeon_dev->pci_dev->dev, 3545 "if%d gmx: %d hw_addr: 0x%llx\n", i, 3546 lio->linfo.gmxport, CVM_CAST64(lio->linfo.hw_addr)); 3547 3548 for (j = 0; j < octeon_dev->sriov_info.max_vfs; j++) { 3549 u8 vfmac[ETH_ALEN]; 3550 3551 random_ether_addr(&vfmac[0]); 3552 if (__liquidio_set_vf_mac(netdev, j, 3553 &vfmac[0], false)) { 3554 dev_err(&octeon_dev->pci_dev->dev, 3555 "Error setting VF%d MAC address\n", 3556 j); 3557 goto setup_nic_dev_fail; 3558 } 3559 } 3560 3561 /* 64-bit swap required on LE machines */ 3562 octeon_swap_8B_data(&lio->linfo.hw_addr, 1); 3563 for (j = 0; j < 6; j++) 3564 mac[j] = *((u8 *)(((u8 *)&lio->linfo.hw_addr) + 2 + j)); 3565 3566 /* Copy MAC Address to OS network device structure */ 3567 3568 ether_addr_copy(netdev->dev_addr, mac); 3569 3570 /* By default all interfaces on a single Octeon uses the same 3571 * tx and rx queues 3572 */ 3573 lio->txq = lio->linfo.txpciq[0].s.q_no; 3574 lio->rxq = lio->linfo.rxpciq[0].s.q_no; 3575 if (liquidio_setup_io_queues(octeon_dev, i, 3576 lio->linfo.num_txpciq, 3577 lio->linfo.num_rxpciq)) { 3578 dev_err(&octeon_dev->pci_dev->dev, "I/O queues creation failed\n"); 3579 goto setup_nic_dev_fail; 3580 } 3581 3582 ifstate_set(lio, LIO_IFSTATE_DROQ_OPS); 3583 3584 lio->tx_qsize = octeon_get_tx_qsize(octeon_dev, lio->txq); 3585 lio->rx_qsize = octeon_get_rx_qsize(octeon_dev, lio->rxq); 3586 3587 if (setup_glists(octeon_dev, lio, num_iqueues)) { 3588 dev_err(&octeon_dev->pci_dev->dev, 3589 "Gather list allocation failed\n"); 3590 goto setup_nic_dev_fail; 3591 } 3592 3593 /* Register ethtool support */ 3594 liquidio_set_ethtool_ops(netdev); 3595 if (lio->oct_dev->chip_id == OCTEON_CN23XX_PF_VID) 3596 octeon_dev->priv_flags = OCT_PRIV_FLAG_DEFAULT; 3597 else 3598 octeon_dev->priv_flags = 0x0; 3599 3600 if (netdev->features & NETIF_F_LRO) 3601 liquidio_set_feature(netdev, OCTNET_CMD_LRO_ENABLE, 3602 OCTNIC_LROIPV4 | OCTNIC_LROIPV6); 3603 3604 liquidio_set_feature(netdev, OCTNET_CMD_VLAN_FILTER_CTL, 3605 OCTNET_CMD_VLAN_FILTER_ENABLE); 3606 3607 if ((debug != -1) && (debug & NETIF_MSG_HW)) 3608 liquidio_set_feature(netdev, 3609 OCTNET_CMD_VERBOSE_ENABLE, 0); 3610 3611 if (setup_link_status_change_wq(netdev)) 3612 goto setup_nic_dev_fail; 3613 3614 if (setup_rx_oom_poll_fn(netdev)) 3615 goto setup_nic_dev_fail; 3616 3617 /* Register the network device with the OS */ 3618 if (register_netdev(netdev)) { 3619 dev_err(&octeon_dev->pci_dev->dev, "Device registration failed\n"); 3620 goto setup_nic_dev_fail; 3621 } 3622 3623 dev_dbg(&octeon_dev->pci_dev->dev, 3624 "Setup NIC ifidx:%d mac:%02x%02x%02x%02x%02x%02x\n", 3625 i, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); 3626 netif_carrier_off(netdev); 3627 lio->link_changes++; 3628 3629 ifstate_set(lio, LIO_IFSTATE_REGISTERED); 3630 3631 /* Sending command to firmware to enable Rx checksum offload 3632 * by default at the time of setup of Liquidio driver for 3633 * this device 3634 */ 3635 liquidio_set_rxcsum_command(netdev, OCTNET_CMD_TNL_RX_CSUM_CTL, 3636 OCTNET_CMD_RXCSUM_ENABLE); 3637 liquidio_set_feature(netdev, OCTNET_CMD_TNL_TX_CSUM_CTL, 3638 OCTNET_CMD_TXCSUM_ENABLE); 3639 3640 dev_dbg(&octeon_dev->pci_dev->dev, 3641 "NIC ifidx:%d Setup successful\n", i); 3642 3643 octeon_free_soft_command(octeon_dev, sc); 3644 } 3645 3646 return 0; 3647 3648 setup_nic_dev_fail: 3649 3650 octeon_free_soft_command(octeon_dev, sc); 3651 3652 setup_nic_wait_intr: 3653 3654 while (i--) { 3655 dev_err(&octeon_dev->pci_dev->dev, 3656 "NIC ifidx:%d Setup failed\n", i); 3657 liquidio_destroy_nic_device(octeon_dev, i); 3658 } 3659 return -ENODEV; 3660 } 3661 3662 #ifdef CONFIG_PCI_IOV 3663 static int octeon_enable_sriov(struct octeon_device *oct) 3664 { 3665 unsigned int num_vfs_alloced = oct->sriov_info.num_vfs_alloced; 3666 struct pci_dev *vfdev; 3667 int err; 3668 u32 u; 3669 3670 if (OCTEON_CN23XX_PF(oct) && num_vfs_alloced) { 3671 err = pci_enable_sriov(oct->pci_dev, 3672 oct->sriov_info.num_vfs_alloced); 3673 if (err) { 3674 dev_err(&oct->pci_dev->dev, 3675 "OCTEON: Failed to enable PCI sriov: %d\n", 3676 err); 3677 oct->sriov_info.num_vfs_alloced = 0; 3678 return err; 3679 } 3680 oct->sriov_info.sriov_enabled = 1; 3681 3682 /* init lookup table that maps DPI ring number to VF pci_dev 3683 * struct pointer 3684 */ 3685 u = 0; 3686 vfdev = pci_get_device(PCI_VENDOR_ID_CAVIUM, 3687 OCTEON_CN23XX_VF_VID, NULL); 3688 while (vfdev) { 3689 if (vfdev->is_virtfn && 3690 (vfdev->physfn == oct->pci_dev)) { 3691 oct->sriov_info.dpiring_to_vfpcidev_lut[u] = 3692 vfdev; 3693 u += oct->sriov_info.rings_per_vf; 3694 } 3695 vfdev = pci_get_device(PCI_VENDOR_ID_CAVIUM, 3696 OCTEON_CN23XX_VF_VID, vfdev); 3697 } 3698 } 3699 3700 return num_vfs_alloced; 3701 } 3702 3703 static int lio_pci_sriov_disable(struct octeon_device *oct) 3704 { 3705 int u; 3706 3707 if (pci_vfs_assigned(oct->pci_dev)) { 3708 dev_err(&oct->pci_dev->dev, "VFs are still assigned to VMs.\n"); 3709 return -EPERM; 3710 } 3711 3712 pci_disable_sriov(oct->pci_dev); 3713 3714 u = 0; 3715 while (u < MAX_POSSIBLE_VFS) { 3716 oct->sriov_info.dpiring_to_vfpcidev_lut[u] = NULL; 3717 u += oct->sriov_info.rings_per_vf; 3718 } 3719 3720 oct->sriov_info.num_vfs_alloced = 0; 3721 dev_info(&oct->pci_dev->dev, "oct->pf_num:%d disabled VFs\n", 3722 oct->pf_num); 3723 3724 return 0; 3725 } 3726 3727 static int liquidio_enable_sriov(struct pci_dev *dev, int num_vfs) 3728 { 3729 struct octeon_device *oct = pci_get_drvdata(dev); 3730 int ret = 0; 3731 3732 if ((num_vfs == oct->sriov_info.num_vfs_alloced) && 3733 (oct->sriov_info.sriov_enabled)) { 3734 dev_info(&oct->pci_dev->dev, "oct->pf_num:%d already enabled num_vfs:%d\n", 3735 oct->pf_num, num_vfs); 3736 return 0; 3737 } 3738 3739 if (!num_vfs) { 3740 ret = lio_pci_sriov_disable(oct); 3741 } else if (num_vfs > oct->sriov_info.max_vfs) { 3742 dev_err(&oct->pci_dev->dev, 3743 "OCTEON: Max allowed VFs:%d user requested:%d", 3744 oct->sriov_info.max_vfs, num_vfs); 3745 ret = -EPERM; 3746 } else { 3747 oct->sriov_info.num_vfs_alloced = num_vfs; 3748 ret = octeon_enable_sriov(oct); 3749 dev_info(&oct->pci_dev->dev, "oct->pf_num:%d num_vfs:%d\n", 3750 oct->pf_num, num_vfs); 3751 } 3752 3753 return ret; 3754 } 3755 #endif 3756 3757 /** 3758 * \brief initialize the NIC 3759 * @param oct octeon device 3760 * 3761 * This initialization routine is called once the Octeon device application is 3762 * up and running 3763 */ 3764 static int liquidio_init_nic_module(struct octeon_device *oct) 3765 { 3766 int i, retval = 0; 3767 int num_nic_ports = CFG_GET_NUM_NIC_PORTS(octeon_get_conf(oct)); 3768 3769 dev_dbg(&oct->pci_dev->dev, "Initializing network interfaces\n"); 3770 3771 /* only default iq and oq were initialized 3772 * initialize the rest as well 3773 */ 3774 /* run port_config command for each port */ 3775 oct->ifcount = num_nic_ports; 3776 3777 memset(oct->props, 0, sizeof(struct octdev_props) * num_nic_ports); 3778 3779 for (i = 0; i < MAX_OCTEON_LINKS; i++) 3780 oct->props[i].gmxport = -1; 3781 3782 retval = setup_nic_devices(oct); 3783 if (retval) { 3784 dev_err(&oct->pci_dev->dev, "Setup NIC devices failed\n"); 3785 goto octnet_init_failure; 3786 } 3787 3788 liquidio_ptp_init(oct); 3789 3790 dev_dbg(&oct->pci_dev->dev, "Network interfaces ready\n"); 3791 3792 return retval; 3793 3794 octnet_init_failure: 3795 3796 oct->ifcount = 0; 3797 3798 return retval; 3799 } 3800 3801 /** 3802 * \brief starter callback that invokes the remaining initialization work after 3803 * the NIC is up and running. 3804 * @param octptr work struct work_struct 3805 */ 3806 static void nic_starter(struct work_struct *work) 3807 { 3808 struct octeon_device *oct; 3809 struct cavium_wk *wk = (struct cavium_wk *)work; 3810 3811 oct = (struct octeon_device *)wk->ctxptr; 3812 3813 if (atomic_read(&oct->status) == OCT_DEV_RUNNING) 3814 return; 3815 3816 /* If the status of the device is CORE_OK, the core 3817 * application has reported its application type. Call 3818 * any registered handlers now and move to the RUNNING 3819 * state. 3820 */ 3821 if (atomic_read(&oct->status) != OCT_DEV_CORE_OK) { 3822 schedule_delayed_work(&oct->nic_poll_work.work, 3823 LIQUIDIO_STARTER_POLL_INTERVAL_MS); 3824 return; 3825 } 3826 3827 atomic_set(&oct->status, OCT_DEV_RUNNING); 3828 3829 if (oct->app_mode && oct->app_mode == CVM_DRV_NIC_APP) { 3830 dev_dbg(&oct->pci_dev->dev, "Starting NIC module\n"); 3831 3832 if (liquidio_init_nic_module(oct)) 3833 dev_err(&oct->pci_dev->dev, "NIC initialization failed\n"); 3834 else 3835 handshake[oct->octeon_id].started_ok = 1; 3836 } else { 3837 dev_err(&oct->pci_dev->dev, 3838 "Unexpected application running on NIC (%d). Check firmware.\n", 3839 oct->app_mode); 3840 } 3841 3842 complete(&handshake[oct->octeon_id].started); 3843 } 3844 3845 static int 3846 octeon_recv_vf_drv_notice(struct octeon_recv_info *recv_info, void *buf) 3847 { 3848 struct octeon_device *oct = (struct octeon_device *)buf; 3849 struct octeon_recv_pkt *recv_pkt = recv_info->recv_pkt; 3850 int i, notice, vf_idx; 3851 bool cores_crashed; 3852 u64 *data, vf_num; 3853 3854 notice = recv_pkt->rh.r.ossp; 3855 data = (u64 *)(get_rbd(recv_pkt->buffer_ptr[0]) + OCT_DROQ_INFO_SIZE); 3856 3857 /* the first 64-bit word of data is the vf_num */ 3858 vf_num = data[0]; 3859 octeon_swap_8B_data(&vf_num, 1); 3860 vf_idx = (int)vf_num - 1; 3861 3862 cores_crashed = READ_ONCE(oct->cores_crashed); 3863 3864 if (notice == VF_DRV_LOADED) { 3865 if (!(oct->sriov_info.vf_drv_loaded_mask & BIT_ULL(vf_idx))) { 3866 oct->sriov_info.vf_drv_loaded_mask |= BIT_ULL(vf_idx); 3867 dev_info(&oct->pci_dev->dev, 3868 "driver for VF%d was loaded\n", vf_idx); 3869 if (!cores_crashed) 3870 try_module_get(THIS_MODULE); 3871 } 3872 } else if (notice == VF_DRV_REMOVED) { 3873 if (oct->sriov_info.vf_drv_loaded_mask & BIT_ULL(vf_idx)) { 3874 oct->sriov_info.vf_drv_loaded_mask &= ~BIT_ULL(vf_idx); 3875 dev_info(&oct->pci_dev->dev, 3876 "driver for VF%d was removed\n", vf_idx); 3877 if (!cores_crashed) 3878 module_put(THIS_MODULE); 3879 } 3880 } else if (notice == VF_DRV_MACADDR_CHANGED) { 3881 u8 *b = (u8 *)&data[1]; 3882 3883 oct->sriov_info.vf_macaddr[vf_idx] = data[1]; 3884 dev_info(&oct->pci_dev->dev, 3885 "VF driver changed VF%d's MAC address to %pM\n", 3886 vf_idx, b + 2); 3887 } 3888 3889 for (i = 0; i < recv_pkt->buffer_count; i++) 3890 recv_buffer_free(recv_pkt->buffer_ptr[i]); 3891 octeon_free_recv_info(recv_info); 3892 3893 return 0; 3894 } 3895 3896 /** 3897 * \brief Device initialization for each Octeon device that is probed 3898 * @param octeon_dev octeon device 3899 */ 3900 static int octeon_device_init(struct octeon_device *octeon_dev) 3901 { 3902 int j, ret; 3903 char bootcmd[] = "\n"; 3904 char *dbg_enb = NULL; 3905 enum lio_fw_state fw_state; 3906 struct octeon_device_priv *oct_priv = 3907 (struct octeon_device_priv *)octeon_dev->priv; 3908 atomic_set(&octeon_dev->status, OCT_DEV_BEGIN_STATE); 3909 3910 /* Enable access to the octeon device and make its DMA capability 3911 * known to the OS. 3912 */ 3913 if (octeon_pci_os_setup(octeon_dev)) 3914 return 1; 3915 3916 atomic_set(&octeon_dev->status, OCT_DEV_PCI_ENABLE_DONE); 3917 3918 /* Identify the Octeon type and map the BAR address space. */ 3919 if (octeon_chip_specific_setup(octeon_dev)) { 3920 dev_err(&octeon_dev->pci_dev->dev, "Chip specific setup failed\n"); 3921 return 1; 3922 } 3923 3924 atomic_set(&octeon_dev->status, OCT_DEV_PCI_MAP_DONE); 3925 3926 /* Only add a reference after setting status 'OCT_DEV_PCI_MAP_DONE', 3927 * since that is what is required for the reference to be removed 3928 * during de-initialization (see 'octeon_destroy_resources'). 3929 */ 3930 octeon_register_device(octeon_dev, octeon_dev->pci_dev->bus->number, 3931 PCI_SLOT(octeon_dev->pci_dev->devfn), 3932 PCI_FUNC(octeon_dev->pci_dev->devfn), 3933 true); 3934 3935 octeon_dev->app_mode = CVM_DRV_INVALID_APP; 3936 3937 /* CN23XX supports preloaded firmware if the following is true: 3938 * 3939 * The adapter indicates that firmware is currently running AND 3940 * 'fw_type' is 'auto'. 3941 * 3942 * (default state is NEEDS_TO_BE_LOADED, override it if appropriate). 3943 */ 3944 if (OCTEON_CN23XX_PF(octeon_dev) && 3945 cn23xx_fw_loaded(octeon_dev) && fw_type_is_auto()) { 3946 atomic_cmpxchg(octeon_dev->adapter_fw_state, 3947 FW_NEEDS_TO_BE_LOADED, FW_IS_PRELOADED); 3948 } 3949 3950 /* If loading firmware, only first device of adapter needs to do so. */ 3951 fw_state = atomic_cmpxchg(octeon_dev->adapter_fw_state, 3952 FW_NEEDS_TO_BE_LOADED, 3953 FW_IS_BEING_LOADED); 3954 3955 /* Here, [local variable] 'fw_state' is set to one of: 3956 * 3957 * FW_IS_PRELOADED: No firmware is to be loaded (see above) 3958 * FW_NEEDS_TO_BE_LOADED: The driver's first instance will load 3959 * firmware to the adapter. 3960 * FW_IS_BEING_LOADED: The driver's second instance will not load 3961 * firmware to the adapter. 3962 */ 3963 3964 /* Prior to f/w load, perform a soft reset of the Octeon device; 3965 * if error resetting, return w/error. 3966 */ 3967 if (fw_state == FW_NEEDS_TO_BE_LOADED) 3968 if (octeon_dev->fn_list.soft_reset(octeon_dev)) 3969 return 1; 3970 3971 /* Initialize the dispatch mechanism used to push packets arriving on 3972 * Octeon Output queues. 3973 */ 3974 if (octeon_init_dispatch_list(octeon_dev)) 3975 return 1; 3976 3977 octeon_register_dispatch_fn(octeon_dev, OPCODE_NIC, 3978 OPCODE_NIC_CORE_DRV_ACTIVE, 3979 octeon_core_drv_init, 3980 octeon_dev); 3981 3982 octeon_register_dispatch_fn(octeon_dev, OPCODE_NIC, 3983 OPCODE_NIC_VF_DRV_NOTICE, 3984 octeon_recv_vf_drv_notice, octeon_dev); 3985 INIT_DELAYED_WORK(&octeon_dev->nic_poll_work.work, nic_starter); 3986 octeon_dev->nic_poll_work.ctxptr = (void *)octeon_dev; 3987 schedule_delayed_work(&octeon_dev->nic_poll_work.work, 3988 LIQUIDIO_STARTER_POLL_INTERVAL_MS); 3989 3990 atomic_set(&octeon_dev->status, OCT_DEV_DISPATCH_INIT_DONE); 3991 3992 if (octeon_set_io_queues_off(octeon_dev)) { 3993 dev_err(&octeon_dev->pci_dev->dev, "setting io queues off failed\n"); 3994 return 1; 3995 } 3996 3997 if (OCTEON_CN23XX_PF(octeon_dev)) { 3998 ret = octeon_dev->fn_list.setup_device_regs(octeon_dev); 3999 if (ret) { 4000 dev_err(&octeon_dev->pci_dev->dev, "OCTEON: Failed to configure device registers\n"); 4001 return ret; 4002 } 4003 } 4004 4005 /* Initialize soft command buffer pool 4006 */ 4007 if (octeon_setup_sc_buffer_pool(octeon_dev)) { 4008 dev_err(&octeon_dev->pci_dev->dev, "sc buffer pool allocation failed\n"); 4009 return 1; 4010 } 4011 atomic_set(&octeon_dev->status, OCT_DEV_SC_BUFF_POOL_INIT_DONE); 4012 4013 /* Setup the data structures that manage this Octeon's Input queues. */ 4014 if (octeon_setup_instr_queues(octeon_dev)) { 4015 dev_err(&octeon_dev->pci_dev->dev, 4016 "instruction queue initialization failed\n"); 4017 return 1; 4018 } 4019 atomic_set(&octeon_dev->status, OCT_DEV_INSTR_QUEUE_INIT_DONE); 4020 4021 /* Initialize lists to manage the requests of different types that 4022 * arrive from user & kernel applications for this octeon device. 4023 */ 4024 if (octeon_setup_response_list(octeon_dev)) { 4025 dev_err(&octeon_dev->pci_dev->dev, "Response list allocation failed\n"); 4026 return 1; 4027 } 4028 atomic_set(&octeon_dev->status, OCT_DEV_RESP_LIST_INIT_DONE); 4029 4030 if (octeon_setup_output_queues(octeon_dev)) { 4031 dev_err(&octeon_dev->pci_dev->dev, "Output queue initialization failed\n"); 4032 return 1; 4033 } 4034 4035 atomic_set(&octeon_dev->status, OCT_DEV_DROQ_INIT_DONE); 4036 4037 if (OCTEON_CN23XX_PF(octeon_dev)) { 4038 if (octeon_dev->fn_list.setup_mbox(octeon_dev)) { 4039 dev_err(&octeon_dev->pci_dev->dev, "OCTEON: Mailbox setup failed\n"); 4040 return 1; 4041 } 4042 atomic_set(&octeon_dev->status, OCT_DEV_MBOX_SETUP_DONE); 4043 4044 if (octeon_allocate_ioq_vector(octeon_dev)) { 4045 dev_err(&octeon_dev->pci_dev->dev, "OCTEON: ioq vector allocation failed\n"); 4046 return 1; 4047 } 4048 atomic_set(&octeon_dev->status, OCT_DEV_MSIX_ALLOC_VECTOR_DONE); 4049 4050 } else { 4051 /* The input and output queue registers were setup earlier (the 4052 * queues were not enabled). Any additional registers 4053 * that need to be programmed should be done now. 4054 */ 4055 ret = octeon_dev->fn_list.setup_device_regs(octeon_dev); 4056 if (ret) { 4057 dev_err(&octeon_dev->pci_dev->dev, 4058 "Failed to configure device registers\n"); 4059 return ret; 4060 } 4061 } 4062 4063 /* Initialize the tasklet that handles output queue packet processing.*/ 4064 dev_dbg(&octeon_dev->pci_dev->dev, "Initializing droq tasklet\n"); 4065 tasklet_init(&oct_priv->droq_tasklet, octeon_droq_bh, 4066 (unsigned long)octeon_dev); 4067 4068 /* Setup the interrupt handler and record the INT SUM register address 4069 */ 4070 if (octeon_setup_interrupt(octeon_dev, 4071 octeon_dev->sriov_info.num_pf_rings)) 4072 return 1; 4073 4074 /* Enable Octeon device interrupts */ 4075 octeon_dev->fn_list.enable_interrupt(octeon_dev, OCTEON_ALL_INTR); 4076 4077 atomic_set(&octeon_dev->status, OCT_DEV_INTR_SET_DONE); 4078 4079 /* Send Credit for Octeon Output queues. Credits are always sent BEFORE 4080 * the output queue is enabled. 4081 * This ensures that we'll receive the f/w CORE DRV_ACTIVE message in 4082 * case we've configured CN23XX_SLI_GBL_CONTROL[NOPTR_D] = 0. 4083 * Otherwise, it is possible that the DRV_ACTIVE message will be sent 4084 * before any credits have been issued, causing the ring to be reset 4085 * (and the f/w appear to never have started). 4086 */ 4087 for (j = 0; j < octeon_dev->num_oqs; j++) 4088 writel(octeon_dev->droq[j]->max_count, 4089 octeon_dev->droq[j]->pkts_credit_reg); 4090 4091 /* Enable the input and output queues for this Octeon device */ 4092 ret = octeon_dev->fn_list.enable_io_queues(octeon_dev); 4093 if (ret) { 4094 dev_err(&octeon_dev->pci_dev->dev, "Failed to enable input/output queues"); 4095 return ret; 4096 } 4097 4098 atomic_set(&octeon_dev->status, OCT_DEV_IO_QUEUES_DONE); 4099 4100 if (fw_state == FW_NEEDS_TO_BE_LOADED) { 4101 dev_dbg(&octeon_dev->pci_dev->dev, "Waiting for DDR initialization...\n"); 4102 if (!ddr_timeout) { 4103 dev_info(&octeon_dev->pci_dev->dev, 4104 "WAITING. Set ddr_timeout to non-zero value to proceed with initialization.\n"); 4105 } 4106 4107 schedule_timeout_uninterruptible(HZ * LIO_RESET_SECS); 4108 4109 /* Wait for the octeon to initialize DDR after the soft-reset.*/ 4110 while (!ddr_timeout) { 4111 set_current_state(TASK_INTERRUPTIBLE); 4112 if (schedule_timeout(HZ / 10)) { 4113 /* user probably pressed Control-C */ 4114 return 1; 4115 } 4116 } 4117 ret = octeon_wait_for_ddr_init(octeon_dev, &ddr_timeout); 4118 if (ret) { 4119 dev_err(&octeon_dev->pci_dev->dev, 4120 "DDR not initialized. Please confirm that board is configured to boot from Flash, ret: %d\n", 4121 ret); 4122 return 1; 4123 } 4124 4125 if (octeon_wait_for_bootloader(octeon_dev, 1000)) { 4126 dev_err(&octeon_dev->pci_dev->dev, "Board not responding\n"); 4127 return 1; 4128 } 4129 4130 /* Divert uboot to take commands from host instead. */ 4131 ret = octeon_console_send_cmd(octeon_dev, bootcmd, 50); 4132 4133 dev_dbg(&octeon_dev->pci_dev->dev, "Initializing consoles\n"); 4134 ret = octeon_init_consoles(octeon_dev); 4135 if (ret) { 4136 dev_err(&octeon_dev->pci_dev->dev, "Could not access board consoles\n"); 4137 return 1; 4138 } 4139 /* If console debug enabled, specify empty string to use default 4140 * enablement ELSE specify NULL string for 'disabled'. 4141 */ 4142 dbg_enb = octeon_console_debug_enabled(0) ? "" : NULL; 4143 ret = octeon_add_console(octeon_dev, 0, dbg_enb); 4144 if (ret) { 4145 dev_err(&octeon_dev->pci_dev->dev, "Could not access board console\n"); 4146 return 1; 4147 } else if (octeon_console_debug_enabled(0)) { 4148 /* If console was added AND we're logging console output 4149 * then set our console print function. 4150 */ 4151 octeon_dev->console[0].print = octeon_dbg_console_print; 4152 } 4153 4154 atomic_set(&octeon_dev->status, OCT_DEV_CONSOLE_INIT_DONE); 4155 4156 dev_dbg(&octeon_dev->pci_dev->dev, "Loading firmware\n"); 4157 ret = load_firmware(octeon_dev); 4158 if (ret) { 4159 dev_err(&octeon_dev->pci_dev->dev, "Could not load firmware to board\n"); 4160 return 1; 4161 } 4162 4163 atomic_set(octeon_dev->adapter_fw_state, FW_HAS_BEEN_LOADED); 4164 } 4165 4166 handshake[octeon_dev->octeon_id].init_ok = 1; 4167 complete(&handshake[octeon_dev->octeon_id].init); 4168 4169 atomic_set(&octeon_dev->status, OCT_DEV_HOST_OK); 4170 4171 return 0; 4172 } 4173 4174 /** 4175 * \brief Debug console print function 4176 * @param octeon_dev octeon device 4177 * @param console_num console number 4178 * @param prefix first portion of line to display 4179 * @param suffix second portion of line to display 4180 * 4181 * The OCTEON debug console outputs entire lines (excluding '\n'). 4182 * Normally, the line will be passed in the 'prefix' parameter. 4183 * However, due to buffering, it is possible for a line to be split into two 4184 * parts, in which case they will be passed as the 'prefix' parameter and 4185 * 'suffix' parameter. 4186 */ 4187 static int octeon_dbg_console_print(struct octeon_device *oct, u32 console_num, 4188 char *prefix, char *suffix) 4189 { 4190 if (prefix && suffix) 4191 dev_info(&oct->pci_dev->dev, "%u: %s%s\n", console_num, prefix, 4192 suffix); 4193 else if (prefix) 4194 dev_info(&oct->pci_dev->dev, "%u: %s\n", console_num, prefix); 4195 else if (suffix) 4196 dev_info(&oct->pci_dev->dev, "%u: %s\n", console_num, suffix); 4197 4198 return 0; 4199 } 4200 4201 /** 4202 * \brief Exits the module 4203 */ 4204 static void __exit liquidio_exit(void) 4205 { 4206 liquidio_deinit_pci(); 4207 4208 pr_info("LiquidIO network module is now unloaded\n"); 4209 } 4210 4211 module_init(liquidio_init); 4212 module_exit(liquidio_exit); 4213