1 /********************************************************************** 2 * Author: Cavium, Inc. 3 * 4 * Contact: support@cavium.com 5 * Please include "LiquidIO" in the subject. 6 * 7 * Copyright (c) 2003-2016 Cavium, Inc. 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more details. 17 ***********************************************************************/ 18 #include <linux/pci.h> 19 #include <linux/firmware.h> 20 #include <net/vxlan.h> 21 #include <linux/kthread.h> 22 #include "liquidio_common.h" 23 #include "octeon_droq.h" 24 #include "octeon_iq.h" 25 #include "response_manager.h" 26 #include "octeon_device.h" 27 #include "octeon_nic.h" 28 #include "octeon_main.h" 29 #include "octeon_network.h" 30 #include "cn66xx_regs.h" 31 #include "cn66xx_device.h" 32 #include "cn68xx_device.h" 33 #include "cn23xx_pf_device.h" 34 #include "liquidio_image.h" 35 36 MODULE_AUTHOR("Cavium Networks, <support@cavium.com>"); 37 MODULE_DESCRIPTION("Cavium LiquidIO Intelligent Server Adapter Driver"); 38 MODULE_LICENSE("GPL"); 39 MODULE_VERSION(LIQUIDIO_VERSION); 40 MODULE_FIRMWARE(LIO_FW_DIR LIO_FW_BASE_NAME LIO_210SV_NAME LIO_FW_NAME_SUFFIX); 41 MODULE_FIRMWARE(LIO_FW_DIR LIO_FW_BASE_NAME LIO_210NV_NAME LIO_FW_NAME_SUFFIX); 42 MODULE_FIRMWARE(LIO_FW_DIR LIO_FW_BASE_NAME LIO_410NV_NAME LIO_FW_NAME_SUFFIX); 43 44 static int ddr_timeout = 10000; 45 module_param(ddr_timeout, int, 0644); 46 MODULE_PARM_DESC(ddr_timeout, 47 "Number of milliseconds to wait for DDR initialization. 0 waits for ddr_timeout to be set to non-zero value before starting to check"); 48 49 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK) 50 51 static int debug = -1; 52 module_param(debug, int, 0644); 53 MODULE_PARM_DESC(debug, "NETIF_MSG debug bits"); 54 55 static char fw_type[LIO_MAX_FW_TYPE_LEN]; 56 module_param_string(fw_type, fw_type, sizeof(fw_type), 0000); 57 MODULE_PARM_DESC(fw_type, "Type of firmware to be loaded. Default \"nic\""); 58 59 static int ptp_enable = 1; 60 61 /* Bit mask values for lio->ifstate */ 62 #define LIO_IFSTATE_DROQ_OPS 0x01 63 #define LIO_IFSTATE_REGISTERED 0x02 64 #define LIO_IFSTATE_RUNNING 0x04 65 #define LIO_IFSTATE_RX_TIMESTAMP_ENABLED 0x08 66 67 /* Polling interval for determining when NIC application is alive */ 68 #define LIQUIDIO_STARTER_POLL_INTERVAL_MS 100 69 70 /* runtime link query interval */ 71 #define LIQUIDIO_LINK_QUERY_INTERVAL_MS 1000 72 73 struct liquidio_if_cfg_context { 74 int octeon_id; 75 76 wait_queue_head_t wc; 77 78 int cond; 79 }; 80 81 struct liquidio_if_cfg_resp { 82 u64 rh; 83 struct liquidio_if_cfg_info cfg_info; 84 u64 status; 85 }; 86 87 struct liquidio_rx_ctl_context { 88 int octeon_id; 89 90 wait_queue_head_t wc; 91 92 int cond; 93 }; 94 95 struct oct_link_status_resp { 96 u64 rh; 97 struct oct_link_info link_info; 98 u64 status; 99 }; 100 101 struct oct_timestamp_resp { 102 u64 rh; 103 u64 timestamp; 104 u64 status; 105 }; 106 107 #define OCT_TIMESTAMP_RESP_SIZE (sizeof(struct oct_timestamp_resp)) 108 109 union tx_info { 110 u64 u64; 111 struct { 112 #ifdef __BIG_ENDIAN_BITFIELD 113 u16 gso_size; 114 u16 gso_segs; 115 u32 reserved; 116 #else 117 u32 reserved; 118 u16 gso_segs; 119 u16 gso_size; 120 #endif 121 } s; 122 }; 123 124 /** Octeon device properties to be used by the NIC module. 125 * Each octeon device in the system will be represented 126 * by this structure in the NIC module. 127 */ 128 129 #define OCTNIC_MAX_SG (MAX_SKB_FRAGS) 130 131 #define OCTNIC_GSO_MAX_HEADER_SIZE 128 132 #define OCTNIC_GSO_MAX_SIZE \ 133 (CN23XX_DEFAULT_INPUT_JABBER - OCTNIC_GSO_MAX_HEADER_SIZE) 134 135 /** Structure of a node in list of gather components maintained by 136 * NIC driver for each network device. 137 */ 138 struct octnic_gather { 139 /** List manipulation. Next and prev pointers. */ 140 struct list_head list; 141 142 /** Size of the gather component at sg in bytes. */ 143 int sg_size; 144 145 /** Number of bytes that sg was adjusted to make it 8B-aligned. */ 146 int adjust; 147 148 /** Gather component that can accommodate max sized fragment list 149 * received from the IP layer. 150 */ 151 struct octeon_sg_entry *sg; 152 153 u64 sg_dma_ptr; 154 }; 155 156 struct handshake { 157 struct completion init; 158 struct completion started; 159 struct pci_dev *pci_dev; 160 int init_ok; 161 int started_ok; 162 }; 163 164 struct octeon_device_priv { 165 /** Tasklet structures for this device. */ 166 struct tasklet_struct droq_tasklet; 167 unsigned long napi_mask; 168 }; 169 170 #ifdef CONFIG_PCI_IOV 171 static int liquidio_enable_sriov(struct pci_dev *dev, int num_vfs); 172 #endif 173 174 static int octeon_device_init(struct octeon_device *); 175 static int liquidio_stop(struct net_device *netdev); 176 static void liquidio_remove(struct pci_dev *pdev); 177 static int liquidio_probe(struct pci_dev *pdev, 178 const struct pci_device_id *ent); 179 180 static struct handshake handshake[MAX_OCTEON_DEVICES]; 181 static struct completion first_stage; 182 183 static void octeon_droq_bh(unsigned long pdev) 184 { 185 int q_no; 186 int reschedule = 0; 187 struct octeon_device *oct = (struct octeon_device *)pdev; 188 struct octeon_device_priv *oct_priv = 189 (struct octeon_device_priv *)oct->priv; 190 191 for (q_no = 0; q_no < MAX_OCTEON_OUTPUT_QUEUES(oct); q_no++) { 192 if (!(oct->io_qmask.oq & BIT_ULL(q_no))) 193 continue; 194 reschedule |= octeon_droq_process_packets(oct, oct->droq[q_no], 195 MAX_PACKET_BUDGET); 196 lio_enable_irq(oct->droq[q_no], NULL); 197 198 if (OCTEON_CN23XX_PF(oct) && oct->msix_on) { 199 /* set time and cnt interrupt thresholds for this DROQ 200 * for NAPI 201 */ 202 int adjusted_q_no = q_no + oct->sriov_info.pf_srn; 203 204 octeon_write_csr64( 205 oct, CN23XX_SLI_OQ_PKT_INT_LEVELS(adjusted_q_no), 206 0x5700000040ULL); 207 octeon_write_csr64( 208 oct, CN23XX_SLI_OQ_PKTS_SENT(adjusted_q_no), 0); 209 } 210 } 211 212 if (reschedule) 213 tasklet_schedule(&oct_priv->droq_tasklet); 214 } 215 216 static int lio_wait_for_oq_pkts(struct octeon_device *oct) 217 { 218 struct octeon_device_priv *oct_priv = 219 (struct octeon_device_priv *)oct->priv; 220 int retry = 100, pkt_cnt = 0, pending_pkts = 0; 221 int i; 222 223 do { 224 pending_pkts = 0; 225 226 for (i = 0; i < MAX_OCTEON_OUTPUT_QUEUES(oct); i++) { 227 if (!(oct->io_qmask.oq & BIT_ULL(i))) 228 continue; 229 pkt_cnt += octeon_droq_check_hw_for_pkts(oct->droq[i]); 230 } 231 if (pkt_cnt > 0) { 232 pending_pkts += pkt_cnt; 233 tasklet_schedule(&oct_priv->droq_tasklet); 234 } 235 pkt_cnt = 0; 236 schedule_timeout_uninterruptible(1); 237 238 } while (retry-- && pending_pkts); 239 240 return pkt_cnt; 241 } 242 243 /** 244 * \brief Forces all IO queues off on a given device 245 * @param oct Pointer to Octeon device 246 */ 247 static void force_io_queues_off(struct octeon_device *oct) 248 { 249 if ((oct->chip_id == OCTEON_CN66XX) || 250 (oct->chip_id == OCTEON_CN68XX)) { 251 /* Reset the Enable bits for Input Queues. */ 252 octeon_write_csr(oct, CN6XXX_SLI_PKT_INSTR_ENB, 0); 253 254 /* Reset the Enable bits for Output Queues. */ 255 octeon_write_csr(oct, CN6XXX_SLI_PKT_OUT_ENB, 0); 256 } 257 } 258 259 /** 260 * \brief wait for all pending requests to complete 261 * @param oct Pointer to Octeon device 262 * 263 * Called during shutdown sequence 264 */ 265 static int wait_for_pending_requests(struct octeon_device *oct) 266 { 267 int i, pcount = 0; 268 269 for (i = 0; i < 100; i++) { 270 pcount = 271 atomic_read(&oct->response_list 272 [OCTEON_ORDERED_SC_LIST].pending_req_count); 273 if (pcount) 274 schedule_timeout_uninterruptible(HZ / 10); 275 else 276 break; 277 } 278 279 if (pcount) 280 return 1; 281 282 return 0; 283 } 284 285 /** 286 * \brief Cause device to go quiet so it can be safely removed/reset/etc 287 * @param oct Pointer to Octeon device 288 */ 289 static inline void pcierror_quiesce_device(struct octeon_device *oct) 290 { 291 int i; 292 293 /* Disable the input and output queues now. No more packets will 294 * arrive from Octeon, but we should wait for all packet processing 295 * to finish. 296 */ 297 force_io_queues_off(oct); 298 299 /* To allow for in-flight requests */ 300 schedule_timeout_uninterruptible(100); 301 302 if (wait_for_pending_requests(oct)) 303 dev_err(&oct->pci_dev->dev, "There were pending requests\n"); 304 305 /* Force all requests waiting to be fetched by OCTEON to complete. */ 306 for (i = 0; i < MAX_OCTEON_INSTR_QUEUES(oct); i++) { 307 struct octeon_instr_queue *iq; 308 309 if (!(oct->io_qmask.iq & BIT_ULL(i))) 310 continue; 311 iq = oct->instr_queue[i]; 312 313 if (atomic_read(&iq->instr_pending)) { 314 spin_lock_bh(&iq->lock); 315 iq->fill_cnt = 0; 316 iq->octeon_read_index = iq->host_write_index; 317 iq->stats.instr_processed += 318 atomic_read(&iq->instr_pending); 319 lio_process_iq_request_list(oct, iq, 0); 320 spin_unlock_bh(&iq->lock); 321 } 322 } 323 324 /* Force all pending ordered list requests to time out. */ 325 lio_process_ordered_list(oct, 1); 326 327 /* We do not need to wait for output queue packets to be processed. */ 328 } 329 330 /** 331 * \brief Cleanup PCI AER uncorrectable error status 332 * @param dev Pointer to PCI device 333 */ 334 static void cleanup_aer_uncorrect_error_status(struct pci_dev *dev) 335 { 336 int pos = 0x100; 337 u32 status, mask; 338 339 pr_info("%s :\n", __func__); 340 341 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, &status); 342 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, &mask); 343 if (dev->error_state == pci_channel_io_normal) 344 status &= ~mask; /* Clear corresponding nonfatal bits */ 345 else 346 status &= mask; /* Clear corresponding fatal bits */ 347 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, status); 348 } 349 350 /** 351 * \brief Stop all PCI IO to a given device 352 * @param dev Pointer to Octeon device 353 */ 354 static void stop_pci_io(struct octeon_device *oct) 355 { 356 /* No more instructions will be forwarded. */ 357 atomic_set(&oct->status, OCT_DEV_IN_RESET); 358 359 pci_disable_device(oct->pci_dev); 360 361 /* Disable interrupts */ 362 oct->fn_list.disable_interrupt(oct, OCTEON_ALL_INTR); 363 364 pcierror_quiesce_device(oct); 365 366 /* Release the interrupt line */ 367 free_irq(oct->pci_dev->irq, oct); 368 369 if (oct->flags & LIO_FLAG_MSI_ENABLED) 370 pci_disable_msi(oct->pci_dev); 371 372 dev_dbg(&oct->pci_dev->dev, "Device state is now %s\n", 373 lio_get_state_string(&oct->status)); 374 375 /* making it a common function for all OCTEON models */ 376 cleanup_aer_uncorrect_error_status(oct->pci_dev); 377 } 378 379 /** 380 * \brief called when PCI error is detected 381 * @param pdev Pointer to PCI device 382 * @param state The current pci connection state 383 * 384 * This function is called after a PCI bus error affecting 385 * this device has been detected. 386 */ 387 static pci_ers_result_t liquidio_pcie_error_detected(struct pci_dev *pdev, 388 pci_channel_state_t state) 389 { 390 struct octeon_device *oct = pci_get_drvdata(pdev); 391 392 /* Non-correctable Non-fatal errors */ 393 if (state == pci_channel_io_normal) { 394 dev_err(&oct->pci_dev->dev, "Non-correctable non-fatal error reported:\n"); 395 cleanup_aer_uncorrect_error_status(oct->pci_dev); 396 return PCI_ERS_RESULT_CAN_RECOVER; 397 } 398 399 /* Non-correctable Fatal errors */ 400 dev_err(&oct->pci_dev->dev, "Non-correctable FATAL reported by PCI AER driver\n"); 401 stop_pci_io(oct); 402 403 /* Always return a DISCONNECT. There is no support for recovery but only 404 * for a clean shutdown. 405 */ 406 return PCI_ERS_RESULT_DISCONNECT; 407 } 408 409 /** 410 * \brief mmio handler 411 * @param pdev Pointer to PCI device 412 */ 413 static pci_ers_result_t liquidio_pcie_mmio_enabled( 414 struct pci_dev *pdev __attribute__((unused))) 415 { 416 /* We should never hit this since we never ask for a reset for a Fatal 417 * Error. We always return DISCONNECT in io_error above. 418 * But play safe and return RECOVERED for now. 419 */ 420 return PCI_ERS_RESULT_RECOVERED; 421 } 422 423 /** 424 * \brief called after the pci bus has been reset. 425 * @param pdev Pointer to PCI device 426 * 427 * Restart the card from scratch, as if from a cold-boot. Implementation 428 * resembles the first-half of the octeon_resume routine. 429 */ 430 static pci_ers_result_t liquidio_pcie_slot_reset( 431 struct pci_dev *pdev __attribute__((unused))) 432 { 433 /* We should never hit this since we never ask for a reset for a Fatal 434 * Error. We always return DISCONNECT in io_error above. 435 * But play safe and return RECOVERED for now. 436 */ 437 return PCI_ERS_RESULT_RECOVERED; 438 } 439 440 /** 441 * \brief called when traffic can start flowing again. 442 * @param pdev Pointer to PCI device 443 * 444 * This callback is called when the error recovery driver tells us that 445 * its OK to resume normal operation. Implementation resembles the 446 * second-half of the octeon_resume routine. 447 */ 448 static void liquidio_pcie_resume(struct pci_dev *pdev __attribute__((unused))) 449 { 450 /* Nothing to be done here. */ 451 } 452 453 #ifdef CONFIG_PM 454 /** 455 * \brief called when suspending 456 * @param pdev Pointer to PCI device 457 * @param state state to suspend to 458 */ 459 static int liquidio_suspend(struct pci_dev *pdev __attribute__((unused)), 460 pm_message_t state __attribute__((unused))) 461 { 462 return 0; 463 } 464 465 /** 466 * \brief called when resuming 467 * @param pdev Pointer to PCI device 468 */ 469 static int liquidio_resume(struct pci_dev *pdev __attribute__((unused))) 470 { 471 return 0; 472 } 473 #endif 474 475 /* For PCI-E Advanced Error Recovery (AER) Interface */ 476 static const struct pci_error_handlers liquidio_err_handler = { 477 .error_detected = liquidio_pcie_error_detected, 478 .mmio_enabled = liquidio_pcie_mmio_enabled, 479 .slot_reset = liquidio_pcie_slot_reset, 480 .resume = liquidio_pcie_resume, 481 }; 482 483 static const struct pci_device_id liquidio_pci_tbl[] = { 484 { /* 68xx */ 485 PCI_VENDOR_ID_CAVIUM, 0x91, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 486 }, 487 { /* 66xx */ 488 PCI_VENDOR_ID_CAVIUM, 0x92, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 489 }, 490 { /* 23xx pf */ 491 PCI_VENDOR_ID_CAVIUM, 0x9702, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 492 }, 493 { 494 0, 0, 0, 0, 0, 0, 0 495 } 496 }; 497 MODULE_DEVICE_TABLE(pci, liquidio_pci_tbl); 498 499 static struct pci_driver liquidio_pci_driver = { 500 .name = "LiquidIO", 501 .id_table = liquidio_pci_tbl, 502 .probe = liquidio_probe, 503 .remove = liquidio_remove, 504 .err_handler = &liquidio_err_handler, /* For AER */ 505 506 #ifdef CONFIG_PM 507 .suspend = liquidio_suspend, 508 .resume = liquidio_resume, 509 #endif 510 #ifdef CONFIG_PCI_IOV 511 .sriov_configure = liquidio_enable_sriov, 512 #endif 513 }; 514 515 /** 516 * \brief register PCI driver 517 */ 518 static int liquidio_init_pci(void) 519 { 520 return pci_register_driver(&liquidio_pci_driver); 521 } 522 523 /** 524 * \brief unregister PCI driver 525 */ 526 static void liquidio_deinit_pci(void) 527 { 528 pci_unregister_driver(&liquidio_pci_driver); 529 } 530 531 /** 532 * \brief check interface state 533 * @param lio per-network private data 534 * @param state_flag flag state to check 535 */ 536 static inline int ifstate_check(struct lio *lio, int state_flag) 537 { 538 return atomic_read(&lio->ifstate) & state_flag; 539 } 540 541 /** 542 * \brief set interface state 543 * @param lio per-network private data 544 * @param state_flag flag state to set 545 */ 546 static inline void ifstate_set(struct lio *lio, int state_flag) 547 { 548 atomic_set(&lio->ifstate, (atomic_read(&lio->ifstate) | state_flag)); 549 } 550 551 /** 552 * \brief clear interface state 553 * @param lio per-network private data 554 * @param state_flag flag state to clear 555 */ 556 static inline void ifstate_reset(struct lio *lio, int state_flag) 557 { 558 atomic_set(&lio->ifstate, (atomic_read(&lio->ifstate) & ~(state_flag))); 559 } 560 561 /** 562 * \brief Stop Tx queues 563 * @param netdev network device 564 */ 565 static inline void txqs_stop(struct net_device *netdev) 566 { 567 if (netif_is_multiqueue(netdev)) { 568 int i; 569 570 for (i = 0; i < netdev->num_tx_queues; i++) 571 netif_stop_subqueue(netdev, i); 572 } else { 573 netif_stop_queue(netdev); 574 } 575 } 576 577 /** 578 * \brief Start Tx queues 579 * @param netdev network device 580 */ 581 static inline void txqs_start(struct net_device *netdev) 582 { 583 if (netif_is_multiqueue(netdev)) { 584 int i; 585 586 for (i = 0; i < netdev->num_tx_queues; i++) 587 netif_start_subqueue(netdev, i); 588 } else { 589 netif_start_queue(netdev); 590 } 591 } 592 593 /** 594 * \brief Wake Tx queues 595 * @param netdev network device 596 */ 597 static inline void txqs_wake(struct net_device *netdev) 598 { 599 struct lio *lio = GET_LIO(netdev); 600 601 if (netif_is_multiqueue(netdev)) { 602 int i; 603 604 for (i = 0; i < netdev->num_tx_queues; i++) { 605 int qno = lio->linfo.txpciq[i % 606 (lio->linfo.num_txpciq)].s.q_no; 607 608 if (__netif_subqueue_stopped(netdev, i)) { 609 INCR_INSTRQUEUE_PKT_COUNT(lio->oct_dev, qno, 610 tx_restart, 1); 611 netif_wake_subqueue(netdev, i); 612 } 613 } 614 } else { 615 INCR_INSTRQUEUE_PKT_COUNT(lio->oct_dev, lio->txq, 616 tx_restart, 1); 617 netif_wake_queue(netdev); 618 } 619 } 620 621 /** 622 * \brief Stop Tx queue 623 * @param netdev network device 624 */ 625 static void stop_txq(struct net_device *netdev) 626 { 627 txqs_stop(netdev); 628 } 629 630 /** 631 * \brief Start Tx queue 632 * @param netdev network device 633 */ 634 static void start_txq(struct net_device *netdev) 635 { 636 struct lio *lio = GET_LIO(netdev); 637 638 if (lio->linfo.link.s.link_up) { 639 txqs_start(netdev); 640 return; 641 } 642 } 643 644 /** 645 * \brief Wake a queue 646 * @param netdev network device 647 * @param q which queue to wake 648 */ 649 static inline void wake_q(struct net_device *netdev, int q) 650 { 651 if (netif_is_multiqueue(netdev)) 652 netif_wake_subqueue(netdev, q); 653 else 654 netif_wake_queue(netdev); 655 } 656 657 /** 658 * \brief Stop a queue 659 * @param netdev network device 660 * @param q which queue to stop 661 */ 662 static inline void stop_q(struct net_device *netdev, int q) 663 { 664 if (netif_is_multiqueue(netdev)) 665 netif_stop_subqueue(netdev, q); 666 else 667 netif_stop_queue(netdev); 668 } 669 670 /** 671 * \brief Check Tx queue status, and take appropriate action 672 * @param lio per-network private data 673 * @returns 0 if full, number of queues woken up otherwise 674 */ 675 static inline int check_txq_status(struct lio *lio) 676 { 677 int ret_val = 0; 678 679 if (netif_is_multiqueue(lio->netdev)) { 680 int numqs = lio->netdev->num_tx_queues; 681 int q, iq = 0; 682 683 /* check each sub-queue state */ 684 for (q = 0; q < numqs; q++) { 685 iq = lio->linfo.txpciq[q % 686 (lio->linfo.num_txpciq)].s.q_no; 687 if (octnet_iq_is_full(lio->oct_dev, iq)) 688 continue; 689 if (__netif_subqueue_stopped(lio->netdev, q)) { 690 wake_q(lio->netdev, q); 691 INCR_INSTRQUEUE_PKT_COUNT(lio->oct_dev, iq, 692 tx_restart, 1); 693 ret_val++; 694 } 695 } 696 } else { 697 if (octnet_iq_is_full(lio->oct_dev, lio->txq)) 698 return 0; 699 wake_q(lio->netdev, lio->txq); 700 INCR_INSTRQUEUE_PKT_COUNT(lio->oct_dev, lio->txq, 701 tx_restart, 1); 702 ret_val = 1; 703 } 704 return ret_val; 705 } 706 707 /** 708 * Remove the node at the head of the list. The list would be empty at 709 * the end of this call if there are no more nodes in the list. 710 */ 711 static inline struct list_head *list_delete_head(struct list_head *root) 712 { 713 struct list_head *node; 714 715 if ((root->prev == root) && (root->next == root)) 716 node = NULL; 717 else 718 node = root->next; 719 720 if (node) 721 list_del(node); 722 723 return node; 724 } 725 726 /** 727 * \brief Delete gather lists 728 * @param lio per-network private data 729 */ 730 static void delete_glists(struct lio *lio) 731 { 732 struct octnic_gather *g; 733 int i; 734 735 if (!lio->glist) 736 return; 737 738 for (i = 0; i < lio->linfo.num_txpciq; i++) { 739 do { 740 g = (struct octnic_gather *) 741 list_delete_head(&lio->glist[i]); 742 if (g) { 743 if (g->sg) { 744 dma_unmap_single(&lio->oct_dev-> 745 pci_dev->dev, 746 g->sg_dma_ptr, 747 g->sg_size, 748 DMA_TO_DEVICE); 749 kfree((void *)((unsigned long)g->sg - 750 g->adjust)); 751 } 752 kfree(g); 753 } 754 } while (g); 755 } 756 757 kfree((void *)lio->glist); 758 kfree((void *)lio->glist_lock); 759 } 760 761 /** 762 * \brief Setup gather lists 763 * @param lio per-network private data 764 */ 765 static int setup_glists(struct octeon_device *oct, struct lio *lio, int num_iqs) 766 { 767 int i, j; 768 struct octnic_gather *g; 769 770 lio->glist_lock = kcalloc(num_iqs, sizeof(*lio->glist_lock), 771 GFP_KERNEL); 772 if (!lio->glist_lock) 773 return 1; 774 775 lio->glist = kcalloc(num_iqs, sizeof(*lio->glist), 776 GFP_KERNEL); 777 if (!lio->glist) { 778 kfree((void *)lio->glist_lock); 779 return 1; 780 } 781 782 for (i = 0; i < num_iqs; i++) { 783 int numa_node = cpu_to_node(i % num_online_cpus()); 784 785 spin_lock_init(&lio->glist_lock[i]); 786 787 INIT_LIST_HEAD(&lio->glist[i]); 788 789 for (j = 0; j < lio->tx_qsize; j++) { 790 g = kzalloc_node(sizeof(*g), GFP_KERNEL, 791 numa_node); 792 if (!g) 793 g = kzalloc(sizeof(*g), GFP_KERNEL); 794 if (!g) 795 break; 796 797 g->sg_size = ((ROUNDUP4(OCTNIC_MAX_SG) >> 2) * 798 OCT_SG_ENTRY_SIZE); 799 800 g->sg = kmalloc_node(g->sg_size + 8, 801 GFP_KERNEL, numa_node); 802 if (!g->sg) 803 g->sg = kmalloc(g->sg_size + 8, GFP_KERNEL); 804 if (!g->sg) { 805 kfree(g); 806 break; 807 } 808 809 /* The gather component should be aligned on 64-bit 810 * boundary 811 */ 812 if (((unsigned long)g->sg) & 7) { 813 g->adjust = 8 - (((unsigned long)g->sg) & 7); 814 g->sg = (struct octeon_sg_entry *) 815 ((unsigned long)g->sg + g->adjust); 816 } 817 g->sg_dma_ptr = dma_map_single(&oct->pci_dev->dev, 818 g->sg, g->sg_size, 819 DMA_TO_DEVICE); 820 if (dma_mapping_error(&oct->pci_dev->dev, 821 g->sg_dma_ptr)) { 822 kfree((void *)((unsigned long)g->sg - 823 g->adjust)); 824 kfree(g); 825 break; 826 } 827 828 list_add_tail(&g->list, &lio->glist[i]); 829 } 830 831 if (j != lio->tx_qsize) { 832 delete_glists(lio); 833 return 1; 834 } 835 } 836 837 return 0; 838 } 839 840 /** 841 * \brief Print link information 842 * @param netdev network device 843 */ 844 static void print_link_info(struct net_device *netdev) 845 { 846 struct lio *lio = GET_LIO(netdev); 847 848 if (atomic_read(&lio->ifstate) & LIO_IFSTATE_REGISTERED) { 849 struct oct_link_info *linfo = &lio->linfo; 850 851 if (linfo->link.s.link_up) { 852 netif_info(lio, link, lio->netdev, "%d Mbps %s Duplex UP\n", 853 linfo->link.s.speed, 854 (linfo->link.s.duplex) ? "Full" : "Half"); 855 } else { 856 netif_info(lio, link, lio->netdev, "Link Down\n"); 857 } 858 } 859 } 860 861 /** 862 * \brief Routine to notify MTU change 863 * @param work work_struct data structure 864 */ 865 static void octnet_link_status_change(struct work_struct *work) 866 { 867 struct cavium_wk *wk = (struct cavium_wk *)work; 868 struct lio *lio = (struct lio *)wk->ctxptr; 869 870 rtnl_lock(); 871 call_netdevice_notifiers(NETDEV_CHANGEMTU, lio->netdev); 872 rtnl_unlock(); 873 } 874 875 /** 876 * \brief Sets up the mtu status change work 877 * @param netdev network device 878 */ 879 static inline int setup_link_status_change_wq(struct net_device *netdev) 880 { 881 struct lio *lio = GET_LIO(netdev); 882 struct octeon_device *oct = lio->oct_dev; 883 884 lio->link_status_wq.wq = alloc_workqueue("link-status", 885 WQ_MEM_RECLAIM, 0); 886 if (!lio->link_status_wq.wq) { 887 dev_err(&oct->pci_dev->dev, "unable to create cavium link status wq\n"); 888 return -1; 889 } 890 INIT_DELAYED_WORK(&lio->link_status_wq.wk.work, 891 octnet_link_status_change); 892 lio->link_status_wq.wk.ctxptr = lio; 893 894 return 0; 895 } 896 897 static inline void cleanup_link_status_change_wq(struct net_device *netdev) 898 { 899 struct lio *lio = GET_LIO(netdev); 900 901 if (lio->link_status_wq.wq) { 902 cancel_delayed_work_sync(&lio->link_status_wq.wk.work); 903 destroy_workqueue(lio->link_status_wq.wq); 904 } 905 } 906 907 /** 908 * \brief Update link status 909 * @param netdev network device 910 * @param ls link status structure 911 * 912 * Called on receipt of a link status response from the core application to 913 * update each interface's link status. 914 */ 915 static inline void update_link_status(struct net_device *netdev, 916 union oct_link_status *ls) 917 { 918 struct lio *lio = GET_LIO(netdev); 919 int changed = (lio->linfo.link.u64 != ls->u64); 920 921 lio->linfo.link.u64 = ls->u64; 922 923 if ((lio->intf_open) && (changed)) { 924 print_link_info(netdev); 925 lio->link_changes++; 926 927 if (lio->linfo.link.s.link_up) { 928 netif_carrier_on(netdev); 929 txqs_wake(netdev); 930 } else { 931 netif_carrier_off(netdev); 932 stop_txq(netdev); 933 } 934 } 935 } 936 937 /* Runs in interrupt context. */ 938 static void update_txq_status(struct octeon_device *oct, int iq_num) 939 { 940 struct net_device *netdev; 941 struct lio *lio; 942 struct octeon_instr_queue *iq = oct->instr_queue[iq_num]; 943 944 netdev = oct->props[iq->ifidx].netdev; 945 946 /* This is needed because the first IQ does not have 947 * a netdev associated with it. 948 */ 949 if (!netdev) 950 return; 951 952 lio = GET_LIO(netdev); 953 if (netif_is_multiqueue(netdev)) { 954 if (__netif_subqueue_stopped(netdev, iq->q_index) && 955 lio->linfo.link.s.link_up && 956 (!octnet_iq_is_full(oct, iq_num))) { 957 INCR_INSTRQUEUE_PKT_COUNT(lio->oct_dev, iq_num, 958 tx_restart, 1); 959 netif_wake_subqueue(netdev, iq->q_index); 960 } else { 961 if (!octnet_iq_is_full(oct, lio->txq)) { 962 INCR_INSTRQUEUE_PKT_COUNT(lio->oct_dev, 963 lio->txq, 964 tx_restart, 1); 965 wake_q(netdev, lio->txq); 966 } 967 } 968 } 969 } 970 971 static 972 int liquidio_schedule_msix_droq_pkt_handler(struct octeon_droq *droq, u64 ret) 973 { 974 struct octeon_device *oct = droq->oct_dev; 975 struct octeon_device_priv *oct_priv = 976 (struct octeon_device_priv *)oct->priv; 977 978 if (droq->ops.poll_mode) { 979 droq->ops.napi_fn(droq); 980 } else { 981 if (ret & MSIX_PO_INT) { 982 tasklet_schedule(&oct_priv->droq_tasklet); 983 return 1; 984 } 985 /* this will be flushed periodically by check iq db */ 986 if (ret & MSIX_PI_INT) 987 return 0; 988 } 989 return 0; 990 } 991 992 /** 993 * \brief Droq packet processor sceduler 994 * @param oct octeon device 995 */ 996 static void liquidio_schedule_droq_pkt_handlers(struct octeon_device *oct) 997 { 998 struct octeon_device_priv *oct_priv = 999 (struct octeon_device_priv *)oct->priv; 1000 u64 oq_no; 1001 struct octeon_droq *droq; 1002 1003 if (oct->int_status & OCT_DEV_INTR_PKT_DATA) { 1004 for (oq_no = 0; oq_no < MAX_OCTEON_OUTPUT_QUEUES(oct); 1005 oq_no++) { 1006 if (!(oct->droq_intr & BIT_ULL(oq_no))) 1007 continue; 1008 1009 droq = oct->droq[oq_no]; 1010 1011 if (droq->ops.poll_mode) { 1012 droq->ops.napi_fn(droq); 1013 oct_priv->napi_mask |= (1 << oq_no); 1014 } else { 1015 tasklet_schedule(&oct_priv->droq_tasklet); 1016 } 1017 } 1018 } 1019 } 1020 1021 static irqreturn_t 1022 liquidio_msix_intr_handler(int irq __attribute__((unused)), void *dev) 1023 { 1024 u64 ret; 1025 struct octeon_ioq_vector *ioq_vector = (struct octeon_ioq_vector *)dev; 1026 struct octeon_device *oct = ioq_vector->oct_dev; 1027 struct octeon_droq *droq = oct->droq[ioq_vector->droq_index]; 1028 1029 ret = oct->fn_list.msix_interrupt_handler(ioq_vector); 1030 1031 if ((ret & MSIX_PO_INT) || (ret & MSIX_PI_INT)) 1032 liquidio_schedule_msix_droq_pkt_handler(droq, ret); 1033 1034 return IRQ_HANDLED; 1035 } 1036 1037 /** 1038 * \brief Interrupt handler for octeon 1039 * @param irq unused 1040 * @param dev octeon device 1041 */ 1042 static 1043 irqreturn_t liquidio_legacy_intr_handler(int irq __attribute__((unused)), 1044 void *dev) 1045 { 1046 struct octeon_device *oct = (struct octeon_device *)dev; 1047 irqreturn_t ret; 1048 1049 /* Disable our interrupts for the duration of ISR */ 1050 oct->fn_list.disable_interrupt(oct, OCTEON_ALL_INTR); 1051 1052 ret = oct->fn_list.process_interrupt_regs(oct); 1053 1054 if (ret == IRQ_HANDLED) 1055 liquidio_schedule_droq_pkt_handlers(oct); 1056 1057 /* Re-enable our interrupts */ 1058 if (!(atomic_read(&oct->status) == OCT_DEV_IN_RESET)) 1059 oct->fn_list.enable_interrupt(oct, OCTEON_ALL_INTR); 1060 1061 return ret; 1062 } 1063 1064 /** 1065 * \brief Setup interrupt for octeon device 1066 * @param oct octeon device 1067 * 1068 * Enable interrupt in Octeon device as given in the PCI interrupt mask. 1069 */ 1070 static int octeon_setup_interrupt(struct octeon_device *oct) 1071 { 1072 int irqret, err; 1073 struct msix_entry *msix_entries; 1074 int i; 1075 int num_ioq_vectors; 1076 int num_alloc_ioq_vectors; 1077 1078 if (OCTEON_CN23XX_PF(oct) && oct->msix_on) { 1079 oct->num_msix_irqs = oct->sriov_info.num_pf_rings; 1080 /* one non ioq interrupt for handling sli_mac_pf_int_sum */ 1081 oct->num_msix_irqs += 1; 1082 1083 oct->msix_entries = kcalloc( 1084 oct->num_msix_irqs, sizeof(struct msix_entry), GFP_KERNEL); 1085 if (!oct->msix_entries) 1086 return 1; 1087 1088 msix_entries = (struct msix_entry *)oct->msix_entries; 1089 /*Assumption is that pf msix vectors start from pf srn to pf to 1090 * trs and not from 0. if not change this code 1091 */ 1092 for (i = 0; i < oct->num_msix_irqs - 1; i++) 1093 msix_entries[i].entry = oct->sriov_info.pf_srn + i; 1094 msix_entries[oct->num_msix_irqs - 1].entry = 1095 oct->sriov_info.trs; 1096 num_alloc_ioq_vectors = pci_enable_msix_range( 1097 oct->pci_dev, msix_entries, 1098 oct->num_msix_irqs, 1099 oct->num_msix_irqs); 1100 if (num_alloc_ioq_vectors < 0) { 1101 dev_err(&oct->pci_dev->dev, "unable to Allocate MSI-X interrupts\n"); 1102 kfree(oct->msix_entries); 1103 oct->msix_entries = NULL; 1104 return 1; 1105 } 1106 dev_dbg(&oct->pci_dev->dev, "OCTEON: Enough MSI-X interrupts are allocated...\n"); 1107 1108 num_ioq_vectors = oct->num_msix_irqs; 1109 1110 /** For PF, there is one non-ioq interrupt handler */ 1111 num_ioq_vectors -= 1; 1112 irqret = request_irq(msix_entries[num_ioq_vectors].vector, 1113 liquidio_legacy_intr_handler, 0, "octeon", 1114 oct); 1115 if (irqret) { 1116 dev_err(&oct->pci_dev->dev, 1117 "OCTEON: Request_irq failed for MSIX interrupt Error: %d\n", 1118 irqret); 1119 pci_disable_msix(oct->pci_dev); 1120 kfree(oct->msix_entries); 1121 oct->msix_entries = NULL; 1122 return 1; 1123 } 1124 1125 for (i = 0; i < num_ioq_vectors; i++) { 1126 irqret = request_irq(msix_entries[i].vector, 1127 liquidio_msix_intr_handler, 0, 1128 "octeon", &oct->ioq_vector[i]); 1129 if (irqret) { 1130 dev_err(&oct->pci_dev->dev, 1131 "OCTEON: Request_irq failed for MSIX interrupt Error: %d\n", 1132 irqret); 1133 /** Freeing the non-ioq irq vector here . */ 1134 free_irq(msix_entries[num_ioq_vectors].vector, 1135 oct); 1136 1137 while (i) { 1138 i--; 1139 /** clearing affinity mask. */ 1140 irq_set_affinity_hint( 1141 msix_entries[i].vector, NULL); 1142 free_irq(msix_entries[i].vector, 1143 &oct->ioq_vector[i]); 1144 } 1145 pci_disable_msix(oct->pci_dev); 1146 kfree(oct->msix_entries); 1147 oct->msix_entries = NULL; 1148 return 1; 1149 } 1150 oct->ioq_vector[i].vector = msix_entries[i].vector; 1151 /* assign the cpu mask for this msix interrupt vector */ 1152 irq_set_affinity_hint( 1153 msix_entries[i].vector, 1154 (&oct->ioq_vector[i].affinity_mask)); 1155 } 1156 dev_dbg(&oct->pci_dev->dev, "OCTEON[%d]: MSI-X enabled\n", 1157 oct->octeon_id); 1158 } else { 1159 err = pci_enable_msi(oct->pci_dev); 1160 if (err) 1161 dev_warn(&oct->pci_dev->dev, "Reverting to legacy interrupts. Error: %d\n", 1162 err); 1163 else 1164 oct->flags |= LIO_FLAG_MSI_ENABLED; 1165 1166 irqret = request_irq(oct->pci_dev->irq, 1167 liquidio_legacy_intr_handler, IRQF_SHARED, 1168 "octeon", oct); 1169 if (irqret) { 1170 if (oct->flags & LIO_FLAG_MSI_ENABLED) 1171 pci_disable_msi(oct->pci_dev); 1172 dev_err(&oct->pci_dev->dev, "Request IRQ failed with code: %d\n", 1173 irqret); 1174 return 1; 1175 } 1176 } 1177 return 0; 1178 } 1179 1180 static int liquidio_watchdog(void *param) 1181 { 1182 u64 wdog; 1183 u16 mask_of_stuck_cores = 0; 1184 u16 mask_of_crashed_cores = 0; 1185 int core_num; 1186 u8 core_is_stuck[LIO_MAX_CORES]; 1187 u8 core_crashed[LIO_MAX_CORES]; 1188 struct octeon_device *oct = param; 1189 1190 memset(core_is_stuck, 0, sizeof(core_is_stuck)); 1191 memset(core_crashed, 0, sizeof(core_crashed)); 1192 1193 while (!kthread_should_stop()) { 1194 mask_of_crashed_cores = 1195 (u16)octeon_read_csr64(oct, CN23XX_SLI_SCRATCH2); 1196 1197 for (core_num = 0; core_num < LIO_MAX_CORES; core_num++) { 1198 if (!core_is_stuck[core_num]) { 1199 wdog = lio_pci_readq(oct, CIU3_WDOG(core_num)); 1200 1201 /* look at watchdog state field */ 1202 wdog &= CIU3_WDOG_MASK; 1203 if (wdog) { 1204 /* this watchdog timer has expired */ 1205 core_is_stuck[core_num] = 1206 LIO_MONITOR_WDOG_EXPIRE; 1207 mask_of_stuck_cores |= (1 << core_num); 1208 } 1209 } 1210 1211 if (!core_crashed[core_num]) 1212 core_crashed[core_num] = 1213 (mask_of_crashed_cores >> core_num) & 1; 1214 } 1215 1216 if (mask_of_stuck_cores) { 1217 for (core_num = 0; core_num < LIO_MAX_CORES; 1218 core_num++) { 1219 if (core_is_stuck[core_num] == 1) { 1220 dev_err(&oct->pci_dev->dev, 1221 "ERROR: Octeon core %d is stuck!\n", 1222 core_num); 1223 /* 2 means we have printk'd an error 1224 * so no need to repeat the same printk 1225 */ 1226 core_is_stuck[core_num] = 1227 LIO_MONITOR_CORE_STUCK_MSGD; 1228 } 1229 } 1230 } 1231 1232 if (mask_of_crashed_cores) { 1233 for (core_num = 0; core_num < LIO_MAX_CORES; 1234 core_num++) { 1235 if (core_crashed[core_num] == 1) { 1236 dev_err(&oct->pci_dev->dev, 1237 "ERROR: Octeon core %d crashed! See oct-fwdump for details.\n", 1238 core_num); 1239 /* 2 means we have printk'd an error 1240 * so no need to repeat the same printk 1241 */ 1242 core_crashed[core_num] = 1243 LIO_MONITOR_CORE_STUCK_MSGD; 1244 } 1245 } 1246 } 1247 #ifdef CONFIG_MODULE_UNLOAD 1248 if (mask_of_stuck_cores || mask_of_crashed_cores) { 1249 /* make module refcount=0 so that rmmod will work */ 1250 long refcount; 1251 1252 refcount = module_refcount(THIS_MODULE); 1253 1254 while (refcount > 0) { 1255 module_put(THIS_MODULE); 1256 refcount = module_refcount(THIS_MODULE); 1257 } 1258 1259 /* compensate for and withstand an unlikely (but still 1260 * possible) race condition 1261 */ 1262 while (refcount < 0) { 1263 try_module_get(THIS_MODULE); 1264 refcount = module_refcount(THIS_MODULE); 1265 } 1266 } 1267 #endif 1268 /* sleep for two seconds */ 1269 set_current_state(TASK_INTERRUPTIBLE); 1270 schedule_timeout(2 * HZ); 1271 } 1272 1273 return 0; 1274 } 1275 1276 /** 1277 * \brief PCI probe handler 1278 * @param pdev PCI device structure 1279 * @param ent unused 1280 */ 1281 static int 1282 liquidio_probe(struct pci_dev *pdev, 1283 const struct pci_device_id *ent __attribute__((unused))) 1284 { 1285 struct octeon_device *oct_dev = NULL; 1286 struct handshake *hs; 1287 1288 oct_dev = octeon_allocate_device(pdev->device, 1289 sizeof(struct octeon_device_priv)); 1290 if (!oct_dev) { 1291 dev_err(&pdev->dev, "Unable to allocate device\n"); 1292 return -ENOMEM; 1293 } 1294 1295 if (pdev->device == OCTEON_CN23XX_PF_VID) 1296 oct_dev->msix_on = LIO_FLAG_MSIX_ENABLED; 1297 1298 dev_info(&pdev->dev, "Initializing device %x:%x.\n", 1299 (u32)pdev->vendor, (u32)pdev->device); 1300 1301 /* Assign octeon_device for this device to the private data area. */ 1302 pci_set_drvdata(pdev, oct_dev); 1303 1304 /* set linux specific device pointer */ 1305 oct_dev->pci_dev = (void *)pdev; 1306 1307 hs = &handshake[oct_dev->octeon_id]; 1308 init_completion(&hs->init); 1309 init_completion(&hs->started); 1310 hs->pci_dev = pdev; 1311 1312 if (oct_dev->octeon_id == 0) 1313 /* first LiquidIO NIC is detected */ 1314 complete(&first_stage); 1315 1316 if (octeon_device_init(oct_dev)) { 1317 complete(&hs->init); 1318 liquidio_remove(pdev); 1319 return -ENOMEM; 1320 } 1321 1322 if (OCTEON_CN23XX_PF(oct_dev)) { 1323 u64 scratch1; 1324 u8 bus, device, function; 1325 1326 scratch1 = octeon_read_csr64(oct_dev, CN23XX_SLI_SCRATCH1); 1327 if (!(scratch1 & 4ULL)) { 1328 /* Bit 2 of SLI_SCRATCH_1 is a flag that indicates that 1329 * the lio watchdog kernel thread is running for this 1330 * NIC. Each NIC gets one watchdog kernel thread. 1331 */ 1332 scratch1 |= 4ULL; 1333 octeon_write_csr64(oct_dev, CN23XX_SLI_SCRATCH1, 1334 scratch1); 1335 1336 bus = pdev->bus->number; 1337 device = PCI_SLOT(pdev->devfn); 1338 function = PCI_FUNC(pdev->devfn); 1339 oct_dev->watchdog_task = kthread_create( 1340 liquidio_watchdog, oct_dev, 1341 "liowd/%02hhx:%02hhx.%hhx", bus, device, function); 1342 if (!IS_ERR(oct_dev->watchdog_task)) { 1343 wake_up_process(oct_dev->watchdog_task); 1344 } else { 1345 oct_dev->watchdog_task = NULL; 1346 dev_err(&oct_dev->pci_dev->dev, 1347 "failed to create kernel_thread\n"); 1348 liquidio_remove(pdev); 1349 return -1; 1350 } 1351 } 1352 } 1353 1354 oct_dev->rx_pause = 1; 1355 oct_dev->tx_pause = 1; 1356 1357 dev_dbg(&oct_dev->pci_dev->dev, "Device is ready\n"); 1358 1359 return 0; 1360 } 1361 1362 /** 1363 *\brief Destroy resources associated with octeon device 1364 * @param pdev PCI device structure 1365 * @param ent unused 1366 */ 1367 static void octeon_destroy_resources(struct octeon_device *oct) 1368 { 1369 int i; 1370 struct msix_entry *msix_entries; 1371 struct octeon_device_priv *oct_priv = 1372 (struct octeon_device_priv *)oct->priv; 1373 1374 struct handshake *hs; 1375 1376 switch (atomic_read(&oct->status)) { 1377 case OCT_DEV_RUNNING: 1378 case OCT_DEV_CORE_OK: 1379 1380 /* No more instructions will be forwarded. */ 1381 atomic_set(&oct->status, OCT_DEV_IN_RESET); 1382 1383 oct->app_mode = CVM_DRV_INVALID_APP; 1384 dev_dbg(&oct->pci_dev->dev, "Device state is now %s\n", 1385 lio_get_state_string(&oct->status)); 1386 1387 schedule_timeout_uninterruptible(HZ / 10); 1388 1389 /* fallthrough */ 1390 case OCT_DEV_HOST_OK: 1391 1392 /* fallthrough */ 1393 case OCT_DEV_CONSOLE_INIT_DONE: 1394 /* Remove any consoles */ 1395 octeon_remove_consoles(oct); 1396 1397 /* fallthrough */ 1398 case OCT_DEV_IO_QUEUES_DONE: 1399 if (wait_for_pending_requests(oct)) 1400 dev_err(&oct->pci_dev->dev, "There were pending requests\n"); 1401 1402 if (lio_wait_for_instr_fetch(oct)) 1403 dev_err(&oct->pci_dev->dev, "IQ had pending instructions\n"); 1404 1405 /* Disable the input and output queues now. No more packets will 1406 * arrive from Octeon, but we should wait for all packet 1407 * processing to finish. 1408 */ 1409 oct->fn_list.disable_io_queues(oct); 1410 1411 if (lio_wait_for_oq_pkts(oct)) 1412 dev_err(&oct->pci_dev->dev, "OQ had pending packets\n"); 1413 1414 /* fallthrough */ 1415 case OCT_DEV_INTR_SET_DONE: 1416 /* Disable interrupts */ 1417 oct->fn_list.disable_interrupt(oct, OCTEON_ALL_INTR); 1418 1419 if (oct->msix_on) { 1420 msix_entries = (struct msix_entry *)oct->msix_entries; 1421 for (i = 0; i < oct->num_msix_irqs - 1; i++) { 1422 /* clear the affinity_cpumask */ 1423 irq_set_affinity_hint(msix_entries[i].vector, 1424 NULL); 1425 free_irq(msix_entries[i].vector, 1426 &oct->ioq_vector[i]); 1427 } 1428 /* non-iov vector's argument is oct struct */ 1429 free_irq(msix_entries[i].vector, oct); 1430 1431 pci_disable_msix(oct->pci_dev); 1432 kfree(oct->msix_entries); 1433 oct->msix_entries = NULL; 1434 } else { 1435 /* Release the interrupt line */ 1436 free_irq(oct->pci_dev->irq, oct); 1437 1438 if (oct->flags & LIO_FLAG_MSI_ENABLED) 1439 pci_disable_msi(oct->pci_dev); 1440 } 1441 1442 /* fallthrough */ 1443 case OCT_DEV_MSIX_ALLOC_VECTOR_DONE: 1444 if (OCTEON_CN23XX_PF(oct)) 1445 octeon_free_ioq_vector(oct); 1446 1447 /* fallthrough */ 1448 case OCT_DEV_MBOX_SETUP_DONE: 1449 if (OCTEON_CN23XX_PF(oct)) 1450 oct->fn_list.free_mbox(oct); 1451 1452 /* fallthrough */ 1453 case OCT_DEV_IN_RESET: 1454 case OCT_DEV_DROQ_INIT_DONE: 1455 /* Wait for any pending operations */ 1456 mdelay(100); 1457 for (i = 0; i < MAX_OCTEON_OUTPUT_QUEUES(oct); i++) { 1458 if (!(oct->io_qmask.oq & BIT_ULL(i))) 1459 continue; 1460 octeon_delete_droq(oct, i); 1461 } 1462 1463 /* Force any pending handshakes to complete */ 1464 for (i = 0; i < MAX_OCTEON_DEVICES; i++) { 1465 hs = &handshake[i]; 1466 1467 if (hs->pci_dev) { 1468 handshake[oct->octeon_id].init_ok = 0; 1469 complete(&handshake[oct->octeon_id].init); 1470 handshake[oct->octeon_id].started_ok = 0; 1471 complete(&handshake[oct->octeon_id].started); 1472 } 1473 } 1474 1475 /* fallthrough */ 1476 case OCT_DEV_RESP_LIST_INIT_DONE: 1477 octeon_delete_response_list(oct); 1478 1479 /* fallthrough */ 1480 case OCT_DEV_INSTR_QUEUE_INIT_DONE: 1481 for (i = 0; i < MAX_OCTEON_INSTR_QUEUES(oct); i++) { 1482 if (!(oct->io_qmask.iq & BIT_ULL(i))) 1483 continue; 1484 octeon_delete_instr_queue(oct, i); 1485 } 1486 #ifdef CONFIG_PCI_IOV 1487 if (oct->sriov_info.sriov_enabled) 1488 pci_disable_sriov(oct->pci_dev); 1489 #endif 1490 /* fallthrough */ 1491 case OCT_DEV_SC_BUFF_POOL_INIT_DONE: 1492 octeon_free_sc_buffer_pool(oct); 1493 1494 /* fallthrough */ 1495 case OCT_DEV_DISPATCH_INIT_DONE: 1496 octeon_delete_dispatch_list(oct); 1497 cancel_delayed_work_sync(&oct->nic_poll_work.work); 1498 1499 /* fallthrough */ 1500 case OCT_DEV_PCI_MAP_DONE: 1501 /* Soft reset the octeon device before exiting */ 1502 if ((!OCTEON_CN23XX_PF(oct)) || !oct->octeon_id) 1503 oct->fn_list.soft_reset(oct); 1504 1505 octeon_unmap_pci_barx(oct, 0); 1506 octeon_unmap_pci_barx(oct, 1); 1507 1508 /* fallthrough */ 1509 case OCT_DEV_PCI_ENABLE_DONE: 1510 pci_clear_master(oct->pci_dev); 1511 /* Disable the device, releasing the PCI INT */ 1512 pci_disable_device(oct->pci_dev); 1513 1514 /* fallthrough */ 1515 case OCT_DEV_BEGIN_STATE: 1516 /* Nothing to be done here either */ 1517 break; 1518 } /* end switch (oct->status) */ 1519 1520 tasklet_kill(&oct_priv->droq_tasklet); 1521 } 1522 1523 /** 1524 * \brief Callback for rx ctrl 1525 * @param status status of request 1526 * @param buf pointer to resp structure 1527 */ 1528 static void rx_ctl_callback(struct octeon_device *oct, 1529 u32 status, 1530 void *buf) 1531 { 1532 struct octeon_soft_command *sc = (struct octeon_soft_command *)buf; 1533 struct liquidio_rx_ctl_context *ctx; 1534 1535 ctx = (struct liquidio_rx_ctl_context *)sc->ctxptr; 1536 1537 oct = lio_get_device(ctx->octeon_id); 1538 if (status) 1539 dev_err(&oct->pci_dev->dev, "rx ctl instruction failed. Status: %llx\n", 1540 CVM_CAST64(status)); 1541 WRITE_ONCE(ctx->cond, 1); 1542 1543 /* This barrier is required to be sure that the response has been 1544 * written fully before waking up the handler 1545 */ 1546 wmb(); 1547 1548 wake_up_interruptible(&ctx->wc); 1549 } 1550 1551 /** 1552 * \brief Send Rx control command 1553 * @param lio per-network private data 1554 * @param start_stop whether to start or stop 1555 */ 1556 static void send_rx_ctrl_cmd(struct lio *lio, int start_stop) 1557 { 1558 struct octeon_soft_command *sc; 1559 struct liquidio_rx_ctl_context *ctx; 1560 union octnet_cmd *ncmd; 1561 int ctx_size = sizeof(struct liquidio_rx_ctl_context); 1562 struct octeon_device *oct = (struct octeon_device *)lio->oct_dev; 1563 int retval; 1564 1565 if (oct->props[lio->ifidx].rx_on == start_stop) 1566 return; 1567 1568 sc = (struct octeon_soft_command *) 1569 octeon_alloc_soft_command(oct, OCTNET_CMD_SIZE, 1570 16, ctx_size); 1571 1572 ncmd = (union octnet_cmd *)sc->virtdptr; 1573 ctx = (struct liquidio_rx_ctl_context *)sc->ctxptr; 1574 1575 WRITE_ONCE(ctx->cond, 0); 1576 ctx->octeon_id = lio_get_device_id(oct); 1577 init_waitqueue_head(&ctx->wc); 1578 1579 ncmd->u64 = 0; 1580 ncmd->s.cmd = OCTNET_CMD_RX_CTL; 1581 ncmd->s.param1 = start_stop; 1582 1583 octeon_swap_8B_data((u64 *)ncmd, (OCTNET_CMD_SIZE >> 3)); 1584 1585 sc->iq_no = lio->linfo.txpciq[0].s.q_no; 1586 1587 octeon_prepare_soft_command(oct, sc, OPCODE_NIC, 1588 OPCODE_NIC_CMD, 0, 0, 0); 1589 1590 sc->callback = rx_ctl_callback; 1591 sc->callback_arg = sc; 1592 sc->wait_time = 5000; 1593 1594 retval = octeon_send_soft_command(oct, sc); 1595 if (retval == IQ_SEND_FAILED) { 1596 netif_info(lio, rx_err, lio->netdev, "Failed to send RX Control message\n"); 1597 } else { 1598 /* Sleep on a wait queue till the cond flag indicates that the 1599 * response arrived or timed-out. 1600 */ 1601 if (sleep_cond(&ctx->wc, &ctx->cond) == -EINTR) 1602 return; 1603 oct->props[lio->ifidx].rx_on = start_stop; 1604 } 1605 1606 octeon_free_soft_command(oct, sc); 1607 } 1608 1609 /** 1610 * \brief Destroy NIC device interface 1611 * @param oct octeon device 1612 * @param ifidx which interface to destroy 1613 * 1614 * Cleanup associated with each interface for an Octeon device when NIC 1615 * module is being unloaded or if initialization fails during load. 1616 */ 1617 static void liquidio_destroy_nic_device(struct octeon_device *oct, int ifidx) 1618 { 1619 struct net_device *netdev = oct->props[ifidx].netdev; 1620 struct lio *lio; 1621 struct napi_struct *napi, *n; 1622 1623 if (!netdev) { 1624 dev_err(&oct->pci_dev->dev, "%s No netdevice ptr for index %d\n", 1625 __func__, ifidx); 1626 return; 1627 } 1628 1629 lio = GET_LIO(netdev); 1630 1631 dev_dbg(&oct->pci_dev->dev, "NIC device cleanup\n"); 1632 1633 if (atomic_read(&lio->ifstate) & LIO_IFSTATE_RUNNING) 1634 liquidio_stop(netdev); 1635 1636 if (oct->props[lio->ifidx].napi_enabled == 1) { 1637 list_for_each_entry_safe(napi, n, &netdev->napi_list, dev_list) 1638 napi_disable(napi); 1639 1640 oct->props[lio->ifidx].napi_enabled = 0; 1641 1642 if (OCTEON_CN23XX_PF(oct)) 1643 oct->droq[0]->ops.poll_mode = 0; 1644 } 1645 1646 if (atomic_read(&lio->ifstate) & LIO_IFSTATE_REGISTERED) 1647 unregister_netdev(netdev); 1648 1649 cleanup_link_status_change_wq(netdev); 1650 1651 delete_glists(lio); 1652 1653 free_netdev(netdev); 1654 1655 oct->props[ifidx].gmxport = -1; 1656 1657 oct->props[ifidx].netdev = NULL; 1658 } 1659 1660 /** 1661 * \brief Stop complete NIC functionality 1662 * @param oct octeon device 1663 */ 1664 static int liquidio_stop_nic_module(struct octeon_device *oct) 1665 { 1666 int i, j; 1667 struct lio *lio; 1668 1669 dev_dbg(&oct->pci_dev->dev, "Stopping network interfaces\n"); 1670 if (!oct->ifcount) { 1671 dev_err(&oct->pci_dev->dev, "Init for Octeon was not completed\n"); 1672 return 1; 1673 } 1674 1675 spin_lock_bh(&oct->cmd_resp_wqlock); 1676 oct->cmd_resp_state = OCT_DRV_OFFLINE; 1677 spin_unlock_bh(&oct->cmd_resp_wqlock); 1678 1679 for (i = 0; i < oct->ifcount; i++) { 1680 lio = GET_LIO(oct->props[i].netdev); 1681 for (j = 0; j < lio->linfo.num_rxpciq; j++) 1682 octeon_unregister_droq_ops(oct, 1683 lio->linfo.rxpciq[j].s.q_no); 1684 } 1685 1686 for (i = 0; i < oct->ifcount; i++) 1687 liquidio_destroy_nic_device(oct, i); 1688 1689 dev_dbg(&oct->pci_dev->dev, "Network interfaces stopped\n"); 1690 return 0; 1691 } 1692 1693 /** 1694 * \brief Cleans up resources at unload time 1695 * @param pdev PCI device structure 1696 */ 1697 static void liquidio_remove(struct pci_dev *pdev) 1698 { 1699 struct octeon_device *oct_dev = pci_get_drvdata(pdev); 1700 1701 dev_dbg(&oct_dev->pci_dev->dev, "Stopping device\n"); 1702 1703 if (oct_dev->watchdog_task) 1704 kthread_stop(oct_dev->watchdog_task); 1705 1706 if (oct_dev->app_mode && (oct_dev->app_mode == CVM_DRV_NIC_APP)) 1707 liquidio_stop_nic_module(oct_dev); 1708 1709 /* Reset the octeon device and cleanup all memory allocated for 1710 * the octeon device by driver. 1711 */ 1712 octeon_destroy_resources(oct_dev); 1713 1714 dev_info(&oct_dev->pci_dev->dev, "Device removed\n"); 1715 1716 /* This octeon device has been removed. Update the global 1717 * data structure to reflect this. Free the device structure. 1718 */ 1719 octeon_free_device_mem(oct_dev); 1720 } 1721 1722 /** 1723 * \brief Identify the Octeon device and to map the BAR address space 1724 * @param oct octeon device 1725 */ 1726 static int octeon_chip_specific_setup(struct octeon_device *oct) 1727 { 1728 u32 dev_id, rev_id; 1729 int ret = 1; 1730 char *s; 1731 1732 pci_read_config_dword(oct->pci_dev, 0, &dev_id); 1733 pci_read_config_dword(oct->pci_dev, 8, &rev_id); 1734 oct->rev_id = rev_id & 0xff; 1735 1736 switch (dev_id) { 1737 case OCTEON_CN68XX_PCIID: 1738 oct->chip_id = OCTEON_CN68XX; 1739 ret = lio_setup_cn68xx_octeon_device(oct); 1740 s = "CN68XX"; 1741 break; 1742 1743 case OCTEON_CN66XX_PCIID: 1744 oct->chip_id = OCTEON_CN66XX; 1745 ret = lio_setup_cn66xx_octeon_device(oct); 1746 s = "CN66XX"; 1747 break; 1748 1749 case OCTEON_CN23XX_PCIID_PF: 1750 oct->chip_id = OCTEON_CN23XX_PF_VID; 1751 ret = setup_cn23xx_octeon_pf_device(oct); 1752 s = "CN23XX"; 1753 break; 1754 1755 default: 1756 s = "?"; 1757 dev_err(&oct->pci_dev->dev, "Unknown device found (dev_id: %x)\n", 1758 dev_id); 1759 } 1760 1761 if (!ret) 1762 dev_info(&oct->pci_dev->dev, "%s PASS%d.%d %s Version: %s\n", s, 1763 OCTEON_MAJOR_REV(oct), 1764 OCTEON_MINOR_REV(oct), 1765 octeon_get_conf(oct)->card_name, 1766 LIQUIDIO_VERSION); 1767 1768 return ret; 1769 } 1770 1771 /** 1772 * \brief PCI initialization for each Octeon device. 1773 * @param oct octeon device 1774 */ 1775 static int octeon_pci_os_setup(struct octeon_device *oct) 1776 { 1777 /* setup PCI stuff first */ 1778 if (pci_enable_device(oct->pci_dev)) { 1779 dev_err(&oct->pci_dev->dev, "pci_enable_device failed\n"); 1780 return 1; 1781 } 1782 1783 if (dma_set_mask_and_coherent(&oct->pci_dev->dev, DMA_BIT_MASK(64))) { 1784 dev_err(&oct->pci_dev->dev, "Unexpected DMA device capability\n"); 1785 pci_disable_device(oct->pci_dev); 1786 return 1; 1787 } 1788 1789 /* Enable PCI DMA Master. */ 1790 pci_set_master(oct->pci_dev); 1791 1792 return 0; 1793 } 1794 1795 static inline int skb_iq(struct lio *lio, struct sk_buff *skb) 1796 { 1797 int q = 0; 1798 1799 if (netif_is_multiqueue(lio->netdev)) 1800 q = skb->queue_mapping % lio->linfo.num_txpciq; 1801 1802 return q; 1803 } 1804 1805 /** 1806 * \brief Check Tx queue state for a given network buffer 1807 * @param lio per-network private data 1808 * @param skb network buffer 1809 */ 1810 static inline int check_txq_state(struct lio *lio, struct sk_buff *skb) 1811 { 1812 int q = 0, iq = 0; 1813 1814 if (netif_is_multiqueue(lio->netdev)) { 1815 q = skb->queue_mapping; 1816 iq = lio->linfo.txpciq[(q % (lio->linfo.num_txpciq))].s.q_no; 1817 } else { 1818 iq = lio->txq; 1819 q = iq; 1820 } 1821 1822 if (octnet_iq_is_full(lio->oct_dev, iq)) 1823 return 0; 1824 1825 if (__netif_subqueue_stopped(lio->netdev, q)) { 1826 INCR_INSTRQUEUE_PKT_COUNT(lio->oct_dev, iq, tx_restart, 1); 1827 wake_q(lio->netdev, q); 1828 } 1829 return 1; 1830 } 1831 1832 /** 1833 * \brief Unmap and free network buffer 1834 * @param buf buffer 1835 */ 1836 static void free_netbuf(void *buf) 1837 { 1838 struct sk_buff *skb; 1839 struct octnet_buf_free_info *finfo; 1840 struct lio *lio; 1841 1842 finfo = (struct octnet_buf_free_info *)buf; 1843 skb = finfo->skb; 1844 lio = finfo->lio; 1845 1846 dma_unmap_single(&lio->oct_dev->pci_dev->dev, finfo->dptr, skb->len, 1847 DMA_TO_DEVICE); 1848 1849 check_txq_state(lio, skb); 1850 1851 tx_buffer_free(skb); 1852 } 1853 1854 /** 1855 * \brief Unmap and free gather buffer 1856 * @param buf buffer 1857 */ 1858 static void free_netsgbuf(void *buf) 1859 { 1860 struct octnet_buf_free_info *finfo; 1861 struct sk_buff *skb; 1862 struct lio *lio; 1863 struct octnic_gather *g; 1864 int i, frags, iq; 1865 1866 finfo = (struct octnet_buf_free_info *)buf; 1867 skb = finfo->skb; 1868 lio = finfo->lio; 1869 g = finfo->g; 1870 frags = skb_shinfo(skb)->nr_frags; 1871 1872 dma_unmap_single(&lio->oct_dev->pci_dev->dev, 1873 g->sg[0].ptr[0], (skb->len - skb->data_len), 1874 DMA_TO_DEVICE); 1875 1876 i = 1; 1877 while (frags--) { 1878 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i - 1]; 1879 1880 pci_unmap_page((lio->oct_dev)->pci_dev, 1881 g->sg[(i >> 2)].ptr[(i & 3)], 1882 frag->size, DMA_TO_DEVICE); 1883 i++; 1884 } 1885 1886 dma_sync_single_for_cpu(&lio->oct_dev->pci_dev->dev, 1887 g->sg_dma_ptr, g->sg_size, DMA_TO_DEVICE); 1888 1889 iq = skb_iq(lio, skb); 1890 spin_lock(&lio->glist_lock[iq]); 1891 list_add_tail(&g->list, &lio->glist[iq]); 1892 spin_unlock(&lio->glist_lock[iq]); 1893 1894 check_txq_state(lio, skb); /* mq support: sub-queue state check */ 1895 1896 tx_buffer_free(skb); 1897 } 1898 1899 /** 1900 * \brief Unmap and free gather buffer with response 1901 * @param buf buffer 1902 */ 1903 static void free_netsgbuf_with_resp(void *buf) 1904 { 1905 struct octeon_soft_command *sc; 1906 struct octnet_buf_free_info *finfo; 1907 struct sk_buff *skb; 1908 struct lio *lio; 1909 struct octnic_gather *g; 1910 int i, frags, iq; 1911 1912 sc = (struct octeon_soft_command *)buf; 1913 skb = (struct sk_buff *)sc->callback_arg; 1914 finfo = (struct octnet_buf_free_info *)&skb->cb; 1915 1916 lio = finfo->lio; 1917 g = finfo->g; 1918 frags = skb_shinfo(skb)->nr_frags; 1919 1920 dma_unmap_single(&lio->oct_dev->pci_dev->dev, 1921 g->sg[0].ptr[0], (skb->len - skb->data_len), 1922 DMA_TO_DEVICE); 1923 1924 i = 1; 1925 while (frags--) { 1926 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i - 1]; 1927 1928 pci_unmap_page((lio->oct_dev)->pci_dev, 1929 g->sg[(i >> 2)].ptr[(i & 3)], 1930 frag->size, DMA_TO_DEVICE); 1931 i++; 1932 } 1933 1934 dma_sync_single_for_cpu(&lio->oct_dev->pci_dev->dev, 1935 g->sg_dma_ptr, g->sg_size, DMA_TO_DEVICE); 1936 1937 iq = skb_iq(lio, skb); 1938 1939 spin_lock(&lio->glist_lock[iq]); 1940 list_add_tail(&g->list, &lio->glist[iq]); 1941 spin_unlock(&lio->glist_lock[iq]); 1942 1943 /* Don't free the skb yet */ 1944 1945 check_txq_state(lio, skb); 1946 } 1947 1948 /** 1949 * \brief Adjust ptp frequency 1950 * @param ptp PTP clock info 1951 * @param ppb how much to adjust by, in parts-per-billion 1952 */ 1953 static int liquidio_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb) 1954 { 1955 struct lio *lio = container_of(ptp, struct lio, ptp_info); 1956 struct octeon_device *oct = (struct octeon_device *)lio->oct_dev; 1957 u64 comp, delta; 1958 unsigned long flags; 1959 bool neg_adj = false; 1960 1961 if (ppb < 0) { 1962 neg_adj = true; 1963 ppb = -ppb; 1964 } 1965 1966 /* The hardware adds the clock compensation value to the 1967 * PTP clock on every coprocessor clock cycle, so we 1968 * compute the delta in terms of coprocessor clocks. 1969 */ 1970 delta = (u64)ppb << 32; 1971 do_div(delta, oct->coproc_clock_rate); 1972 1973 spin_lock_irqsave(&lio->ptp_lock, flags); 1974 comp = lio_pci_readq(oct, CN6XXX_MIO_PTP_CLOCK_COMP); 1975 if (neg_adj) 1976 comp -= delta; 1977 else 1978 comp += delta; 1979 lio_pci_writeq(oct, comp, CN6XXX_MIO_PTP_CLOCK_COMP); 1980 spin_unlock_irqrestore(&lio->ptp_lock, flags); 1981 1982 return 0; 1983 } 1984 1985 /** 1986 * \brief Adjust ptp time 1987 * @param ptp PTP clock info 1988 * @param delta how much to adjust by, in nanosecs 1989 */ 1990 static int liquidio_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta) 1991 { 1992 unsigned long flags; 1993 struct lio *lio = container_of(ptp, struct lio, ptp_info); 1994 1995 spin_lock_irqsave(&lio->ptp_lock, flags); 1996 lio->ptp_adjust += delta; 1997 spin_unlock_irqrestore(&lio->ptp_lock, flags); 1998 1999 return 0; 2000 } 2001 2002 /** 2003 * \brief Get hardware clock time, including any adjustment 2004 * @param ptp PTP clock info 2005 * @param ts timespec 2006 */ 2007 static int liquidio_ptp_gettime(struct ptp_clock_info *ptp, 2008 struct timespec64 *ts) 2009 { 2010 u64 ns; 2011 unsigned long flags; 2012 struct lio *lio = container_of(ptp, struct lio, ptp_info); 2013 struct octeon_device *oct = (struct octeon_device *)lio->oct_dev; 2014 2015 spin_lock_irqsave(&lio->ptp_lock, flags); 2016 ns = lio_pci_readq(oct, CN6XXX_MIO_PTP_CLOCK_HI); 2017 ns += lio->ptp_adjust; 2018 spin_unlock_irqrestore(&lio->ptp_lock, flags); 2019 2020 *ts = ns_to_timespec64(ns); 2021 2022 return 0; 2023 } 2024 2025 /** 2026 * \brief Set hardware clock time. Reset adjustment 2027 * @param ptp PTP clock info 2028 * @param ts timespec 2029 */ 2030 static int liquidio_ptp_settime(struct ptp_clock_info *ptp, 2031 const struct timespec64 *ts) 2032 { 2033 u64 ns; 2034 unsigned long flags; 2035 struct lio *lio = container_of(ptp, struct lio, ptp_info); 2036 struct octeon_device *oct = (struct octeon_device *)lio->oct_dev; 2037 2038 ns = timespec_to_ns(ts); 2039 2040 spin_lock_irqsave(&lio->ptp_lock, flags); 2041 lio_pci_writeq(oct, ns, CN6XXX_MIO_PTP_CLOCK_HI); 2042 lio->ptp_adjust = 0; 2043 spin_unlock_irqrestore(&lio->ptp_lock, flags); 2044 2045 return 0; 2046 } 2047 2048 /** 2049 * \brief Check if PTP is enabled 2050 * @param ptp PTP clock info 2051 * @param rq request 2052 * @param on is it on 2053 */ 2054 static int 2055 liquidio_ptp_enable(struct ptp_clock_info *ptp __attribute__((unused)), 2056 struct ptp_clock_request *rq __attribute__((unused)), 2057 int on __attribute__((unused))) 2058 { 2059 return -EOPNOTSUPP; 2060 } 2061 2062 /** 2063 * \brief Open PTP clock source 2064 * @param netdev network device 2065 */ 2066 static void oct_ptp_open(struct net_device *netdev) 2067 { 2068 struct lio *lio = GET_LIO(netdev); 2069 struct octeon_device *oct = (struct octeon_device *)lio->oct_dev; 2070 2071 spin_lock_init(&lio->ptp_lock); 2072 2073 snprintf(lio->ptp_info.name, 16, "%s", netdev->name); 2074 lio->ptp_info.owner = THIS_MODULE; 2075 lio->ptp_info.max_adj = 250000000; 2076 lio->ptp_info.n_alarm = 0; 2077 lio->ptp_info.n_ext_ts = 0; 2078 lio->ptp_info.n_per_out = 0; 2079 lio->ptp_info.pps = 0; 2080 lio->ptp_info.adjfreq = liquidio_ptp_adjfreq; 2081 lio->ptp_info.adjtime = liquidio_ptp_adjtime; 2082 lio->ptp_info.gettime64 = liquidio_ptp_gettime; 2083 lio->ptp_info.settime64 = liquidio_ptp_settime; 2084 lio->ptp_info.enable = liquidio_ptp_enable; 2085 2086 lio->ptp_adjust = 0; 2087 2088 lio->ptp_clock = ptp_clock_register(&lio->ptp_info, 2089 &oct->pci_dev->dev); 2090 2091 if (IS_ERR(lio->ptp_clock)) 2092 lio->ptp_clock = NULL; 2093 } 2094 2095 /** 2096 * \brief Init PTP clock 2097 * @param oct octeon device 2098 */ 2099 static void liquidio_ptp_init(struct octeon_device *oct) 2100 { 2101 u64 clock_comp, cfg; 2102 2103 clock_comp = (u64)NSEC_PER_SEC << 32; 2104 do_div(clock_comp, oct->coproc_clock_rate); 2105 lio_pci_writeq(oct, clock_comp, CN6XXX_MIO_PTP_CLOCK_COMP); 2106 2107 /* Enable */ 2108 cfg = lio_pci_readq(oct, CN6XXX_MIO_PTP_CLOCK_CFG); 2109 lio_pci_writeq(oct, cfg | 0x01, CN6XXX_MIO_PTP_CLOCK_CFG); 2110 } 2111 2112 /** 2113 * \brief Load firmware to device 2114 * @param oct octeon device 2115 * 2116 * Maps device to firmware filename, requests firmware, and downloads it 2117 */ 2118 static int load_firmware(struct octeon_device *oct) 2119 { 2120 int ret = 0; 2121 const struct firmware *fw; 2122 char fw_name[LIO_MAX_FW_FILENAME_LEN]; 2123 char *tmp_fw_type; 2124 2125 if (strncmp(fw_type, LIO_FW_NAME_TYPE_NONE, 2126 sizeof(LIO_FW_NAME_TYPE_NONE)) == 0) { 2127 dev_info(&oct->pci_dev->dev, "Skipping firmware load\n"); 2128 return ret; 2129 } 2130 2131 if (fw_type[0] == '\0') 2132 tmp_fw_type = LIO_FW_NAME_TYPE_NIC; 2133 else 2134 tmp_fw_type = fw_type; 2135 2136 sprintf(fw_name, "%s%s%s_%s%s", LIO_FW_DIR, LIO_FW_BASE_NAME, 2137 octeon_get_conf(oct)->card_name, tmp_fw_type, 2138 LIO_FW_NAME_SUFFIX); 2139 2140 ret = request_firmware(&fw, fw_name, &oct->pci_dev->dev); 2141 if (ret) { 2142 dev_err(&oct->pci_dev->dev, "Request firmware failed. Could not find file %s.\n.", 2143 fw_name); 2144 release_firmware(fw); 2145 return ret; 2146 } 2147 2148 ret = octeon_download_firmware(oct, fw->data, fw->size); 2149 2150 release_firmware(fw); 2151 2152 return ret; 2153 } 2154 2155 /** 2156 * \brief Setup output queue 2157 * @param oct octeon device 2158 * @param q_no which queue 2159 * @param num_descs how many descriptors 2160 * @param desc_size size of each descriptor 2161 * @param app_ctx application context 2162 */ 2163 static int octeon_setup_droq(struct octeon_device *oct, int q_no, int num_descs, 2164 int desc_size, void *app_ctx) 2165 { 2166 int ret_val = 0; 2167 2168 dev_dbg(&oct->pci_dev->dev, "Creating Droq: %d\n", q_no); 2169 /* droq creation and local register settings. */ 2170 ret_val = octeon_create_droq(oct, q_no, num_descs, desc_size, app_ctx); 2171 if (ret_val < 0) 2172 return ret_val; 2173 2174 if (ret_val == 1) { 2175 dev_dbg(&oct->pci_dev->dev, "Using default droq %d\n", q_no); 2176 return 0; 2177 } 2178 /* tasklet creation for the droq */ 2179 2180 /* Enable the droq queues */ 2181 octeon_set_droq_pkt_op(oct, q_no, 1); 2182 2183 /* Send Credit for Octeon Output queues. Credits are always 2184 * sent after the output queue is enabled. 2185 */ 2186 writel(oct->droq[q_no]->max_count, 2187 oct->droq[q_no]->pkts_credit_reg); 2188 2189 return ret_val; 2190 } 2191 2192 /** 2193 * \brief Callback for getting interface configuration 2194 * @param status status of request 2195 * @param buf pointer to resp structure 2196 */ 2197 static void if_cfg_callback(struct octeon_device *oct, 2198 u32 status __attribute__((unused)), 2199 void *buf) 2200 { 2201 struct octeon_soft_command *sc = (struct octeon_soft_command *)buf; 2202 struct liquidio_if_cfg_resp *resp; 2203 struct liquidio_if_cfg_context *ctx; 2204 2205 resp = (struct liquidio_if_cfg_resp *)sc->virtrptr; 2206 ctx = (struct liquidio_if_cfg_context *)sc->ctxptr; 2207 2208 oct = lio_get_device(ctx->octeon_id); 2209 if (resp->status) 2210 dev_err(&oct->pci_dev->dev, "nic if cfg instruction failed. Status: %llx\n", 2211 CVM_CAST64(resp->status)); 2212 WRITE_ONCE(ctx->cond, 1); 2213 2214 snprintf(oct->fw_info.liquidio_firmware_version, 32, "%s", 2215 resp->cfg_info.liquidio_firmware_version); 2216 2217 /* This barrier is required to be sure that the response has been 2218 * written fully before waking up the handler 2219 */ 2220 wmb(); 2221 2222 wake_up_interruptible(&ctx->wc); 2223 } 2224 2225 /** 2226 * \brief Select queue based on hash 2227 * @param dev Net device 2228 * @param skb sk_buff structure 2229 * @returns selected queue number 2230 */ 2231 static u16 select_q(struct net_device *dev, struct sk_buff *skb, 2232 void *accel_priv __attribute__((unused)), 2233 select_queue_fallback_t fallback __attribute__((unused))) 2234 { 2235 u32 qindex = 0; 2236 struct lio *lio; 2237 2238 lio = GET_LIO(dev); 2239 qindex = skb_tx_hash(dev, skb); 2240 2241 return (u16)(qindex % (lio->linfo.num_txpciq)); 2242 } 2243 2244 /** Routine to push packets arriving on Octeon interface upto network layer. 2245 * @param oct_id - octeon device id. 2246 * @param skbuff - skbuff struct to be passed to network layer. 2247 * @param len - size of total data received. 2248 * @param rh - Control header associated with the packet 2249 * @param param - additional control data with the packet 2250 * @param arg - farg registered in droq_ops 2251 */ 2252 static void 2253 liquidio_push_packet(u32 octeon_id __attribute__((unused)), 2254 void *skbuff, 2255 u32 len, 2256 union octeon_rh *rh, 2257 void *param, 2258 void *arg) 2259 { 2260 struct napi_struct *napi = param; 2261 struct sk_buff *skb = (struct sk_buff *)skbuff; 2262 struct skb_shared_hwtstamps *shhwtstamps; 2263 u64 ns; 2264 u16 vtag = 0; 2265 struct net_device *netdev = (struct net_device *)arg; 2266 struct octeon_droq *droq = container_of(param, struct octeon_droq, 2267 napi); 2268 if (netdev) { 2269 int packet_was_received; 2270 struct lio *lio = GET_LIO(netdev); 2271 struct octeon_device *oct = lio->oct_dev; 2272 2273 /* Do not proceed if the interface is not in RUNNING state. */ 2274 if (!ifstate_check(lio, LIO_IFSTATE_RUNNING)) { 2275 recv_buffer_free(skb); 2276 droq->stats.rx_dropped++; 2277 return; 2278 } 2279 2280 skb->dev = netdev; 2281 2282 skb_record_rx_queue(skb, droq->q_no); 2283 if (likely(len > MIN_SKB_SIZE)) { 2284 struct octeon_skb_page_info *pg_info; 2285 unsigned char *va; 2286 2287 pg_info = ((struct octeon_skb_page_info *)(skb->cb)); 2288 if (pg_info->page) { 2289 /* For Paged allocation use the frags */ 2290 va = page_address(pg_info->page) + 2291 pg_info->page_offset; 2292 memcpy(skb->data, va, MIN_SKB_SIZE); 2293 skb_put(skb, MIN_SKB_SIZE); 2294 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 2295 pg_info->page, 2296 pg_info->page_offset + 2297 MIN_SKB_SIZE, 2298 len - MIN_SKB_SIZE, 2299 LIO_RXBUFFER_SZ); 2300 } 2301 } else { 2302 struct octeon_skb_page_info *pg_info = 2303 ((struct octeon_skb_page_info *)(skb->cb)); 2304 skb_copy_to_linear_data(skb, page_address(pg_info->page) 2305 + pg_info->page_offset, len); 2306 skb_put(skb, len); 2307 put_page(pg_info->page); 2308 } 2309 2310 if (((oct->chip_id == OCTEON_CN66XX) || 2311 (oct->chip_id == OCTEON_CN68XX)) && 2312 ptp_enable) { 2313 if (rh->r_dh.has_hwtstamp) { 2314 /* timestamp is included from the hardware at 2315 * the beginning of the packet. 2316 */ 2317 if (ifstate_check 2318 (lio, LIO_IFSTATE_RX_TIMESTAMP_ENABLED)) { 2319 /* Nanoseconds are in the first 64-bits 2320 * of the packet. 2321 */ 2322 memcpy(&ns, (skb->data), sizeof(ns)); 2323 shhwtstamps = skb_hwtstamps(skb); 2324 shhwtstamps->hwtstamp = 2325 ns_to_ktime(ns + 2326 lio->ptp_adjust); 2327 } 2328 skb_pull(skb, sizeof(ns)); 2329 } 2330 } 2331 2332 skb->protocol = eth_type_trans(skb, skb->dev); 2333 if ((netdev->features & NETIF_F_RXCSUM) && 2334 (((rh->r_dh.encap_on) && 2335 (rh->r_dh.csum_verified & CNNIC_TUN_CSUM_VERIFIED)) || 2336 (!(rh->r_dh.encap_on) && 2337 (rh->r_dh.csum_verified & CNNIC_CSUM_VERIFIED)))) 2338 /* checksum has already been verified */ 2339 skb->ip_summed = CHECKSUM_UNNECESSARY; 2340 else 2341 skb->ip_summed = CHECKSUM_NONE; 2342 2343 /* Setting Encapsulation field on basis of status received 2344 * from the firmware 2345 */ 2346 if (rh->r_dh.encap_on) { 2347 skb->encapsulation = 1; 2348 skb->csum_level = 1; 2349 droq->stats.rx_vxlan++; 2350 } 2351 2352 /* inbound VLAN tag */ 2353 if ((netdev->features & NETIF_F_HW_VLAN_CTAG_RX) && 2354 (rh->r_dh.vlan != 0)) { 2355 u16 vid = rh->r_dh.vlan; 2356 u16 priority = rh->r_dh.priority; 2357 2358 vtag = priority << 13 | vid; 2359 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vtag); 2360 } 2361 2362 packet_was_received = napi_gro_receive(napi, skb) != GRO_DROP; 2363 2364 if (packet_was_received) { 2365 droq->stats.rx_bytes_received += len; 2366 droq->stats.rx_pkts_received++; 2367 netdev->last_rx = jiffies; 2368 } else { 2369 droq->stats.rx_dropped++; 2370 netif_info(lio, rx_err, lio->netdev, 2371 "droq:%d error rx_dropped:%llu\n", 2372 droq->q_no, droq->stats.rx_dropped); 2373 } 2374 2375 } else { 2376 recv_buffer_free(skb); 2377 } 2378 } 2379 2380 /** 2381 * \brief wrapper for calling napi_schedule 2382 * @param param parameters to pass to napi_schedule 2383 * 2384 * Used when scheduling on different CPUs 2385 */ 2386 static void napi_schedule_wrapper(void *param) 2387 { 2388 struct napi_struct *napi = param; 2389 2390 napi_schedule(napi); 2391 } 2392 2393 /** 2394 * \brief callback when receive interrupt occurs and we are in NAPI mode 2395 * @param arg pointer to octeon output queue 2396 */ 2397 static void liquidio_napi_drv_callback(void *arg) 2398 { 2399 struct octeon_device *oct; 2400 struct octeon_droq *droq = arg; 2401 int this_cpu = smp_processor_id(); 2402 2403 oct = droq->oct_dev; 2404 2405 if (OCTEON_CN23XX_PF(oct) || droq->cpu_id == this_cpu) { 2406 napi_schedule_irqoff(&droq->napi); 2407 } else { 2408 struct call_single_data *csd = &droq->csd; 2409 2410 csd->func = napi_schedule_wrapper; 2411 csd->info = &droq->napi; 2412 csd->flags = 0; 2413 2414 smp_call_function_single_async(droq->cpu_id, csd); 2415 } 2416 } 2417 2418 /** 2419 * \brief Entry point for NAPI polling 2420 * @param napi NAPI structure 2421 * @param budget maximum number of items to process 2422 */ 2423 static int liquidio_napi_poll(struct napi_struct *napi, int budget) 2424 { 2425 struct octeon_droq *droq; 2426 int work_done; 2427 int tx_done = 0, iq_no; 2428 struct octeon_instr_queue *iq; 2429 struct octeon_device *oct; 2430 2431 droq = container_of(napi, struct octeon_droq, napi); 2432 oct = droq->oct_dev; 2433 iq_no = droq->q_no; 2434 /* Handle Droq descriptors */ 2435 work_done = octeon_process_droq_poll_cmd(oct, droq->q_no, 2436 POLL_EVENT_PROCESS_PKTS, 2437 budget); 2438 2439 /* Flush the instruction queue */ 2440 iq = oct->instr_queue[iq_no]; 2441 if (iq) { 2442 /* Process iq buffers with in the budget limits */ 2443 tx_done = octeon_flush_iq(oct, iq, 1, budget); 2444 /* Update iq read-index rather than waiting for next interrupt. 2445 * Return back if tx_done is false. 2446 */ 2447 update_txq_status(oct, iq_no); 2448 } else { 2449 dev_err(&oct->pci_dev->dev, "%s: iq (%d) num invalid\n", 2450 __func__, iq_no); 2451 } 2452 2453 if ((work_done < budget) && (tx_done)) { 2454 napi_complete(napi); 2455 octeon_process_droq_poll_cmd(droq->oct_dev, droq->q_no, 2456 POLL_EVENT_ENABLE_INTR, 0); 2457 return 0; 2458 } 2459 2460 return (!tx_done) ? (budget) : (work_done); 2461 } 2462 2463 /** 2464 * \brief Setup input and output queues 2465 * @param octeon_dev octeon device 2466 * @param ifidx Interface Index 2467 * 2468 * Note: Queues are with respect to the octeon device. Thus 2469 * an input queue is for egress packets, and output queues 2470 * are for ingress packets. 2471 */ 2472 static inline int setup_io_queues(struct octeon_device *octeon_dev, 2473 int ifidx) 2474 { 2475 struct octeon_droq_ops droq_ops; 2476 struct net_device *netdev; 2477 static int cpu_id; 2478 static int cpu_id_modulus; 2479 struct octeon_droq *droq; 2480 struct napi_struct *napi; 2481 int q, q_no, retval = 0; 2482 struct lio *lio; 2483 int num_tx_descs; 2484 2485 netdev = octeon_dev->props[ifidx].netdev; 2486 2487 lio = GET_LIO(netdev); 2488 2489 memset(&droq_ops, 0, sizeof(struct octeon_droq_ops)); 2490 2491 droq_ops.fptr = liquidio_push_packet; 2492 droq_ops.farg = (void *)netdev; 2493 2494 droq_ops.poll_mode = 1; 2495 droq_ops.napi_fn = liquidio_napi_drv_callback; 2496 cpu_id = 0; 2497 cpu_id_modulus = num_present_cpus(); 2498 2499 /* set up DROQs. */ 2500 for (q = 0; q < lio->linfo.num_rxpciq; q++) { 2501 q_no = lio->linfo.rxpciq[q].s.q_no; 2502 dev_dbg(&octeon_dev->pci_dev->dev, 2503 "setup_io_queues index:%d linfo.rxpciq.s.q_no:%d\n", 2504 q, q_no); 2505 retval = octeon_setup_droq(octeon_dev, q_no, 2506 CFG_GET_NUM_RX_DESCS_NIC_IF 2507 (octeon_get_conf(octeon_dev), 2508 lio->ifidx), 2509 CFG_GET_NUM_RX_BUF_SIZE_NIC_IF 2510 (octeon_get_conf(octeon_dev), 2511 lio->ifidx), NULL); 2512 if (retval) { 2513 dev_err(&octeon_dev->pci_dev->dev, 2514 "%s : Runtime DROQ(RxQ) creation failed.\n", 2515 __func__); 2516 return 1; 2517 } 2518 2519 droq = octeon_dev->droq[q_no]; 2520 napi = &droq->napi; 2521 dev_dbg(&octeon_dev->pci_dev->dev, "netif_napi_add netdev:%llx oct:%llx pf_num:%d\n", 2522 (u64)netdev, (u64)octeon_dev, octeon_dev->pf_num); 2523 netif_napi_add(netdev, napi, liquidio_napi_poll, 64); 2524 2525 /* designate a CPU for this droq */ 2526 droq->cpu_id = cpu_id; 2527 cpu_id++; 2528 if (cpu_id >= cpu_id_modulus) 2529 cpu_id = 0; 2530 2531 octeon_register_droq_ops(octeon_dev, q_no, &droq_ops); 2532 } 2533 2534 if (OCTEON_CN23XX_PF(octeon_dev)) { 2535 /* 23XX PF can receive control messages (via the first PF-owned 2536 * droq) from the firmware even if the ethX interface is down, 2537 * so that's why poll_mode must be off for the first droq. 2538 */ 2539 octeon_dev->droq[0]->ops.poll_mode = 0; 2540 } 2541 2542 /* set up IQs. */ 2543 for (q = 0; q < lio->linfo.num_txpciq; q++) { 2544 num_tx_descs = CFG_GET_NUM_TX_DESCS_NIC_IF(octeon_get_conf 2545 (octeon_dev), 2546 lio->ifidx); 2547 retval = octeon_setup_iq(octeon_dev, ifidx, q, 2548 lio->linfo.txpciq[q], num_tx_descs, 2549 netdev_get_tx_queue(netdev, q)); 2550 if (retval) { 2551 dev_err(&octeon_dev->pci_dev->dev, 2552 " %s : Runtime IQ(TxQ) creation failed.\n", 2553 __func__); 2554 return 1; 2555 } 2556 } 2557 2558 return 0; 2559 } 2560 2561 /** 2562 * \brief Poll routine for checking transmit queue status 2563 * @param work work_struct data structure 2564 */ 2565 static void octnet_poll_check_txq_status(struct work_struct *work) 2566 { 2567 struct cavium_wk *wk = (struct cavium_wk *)work; 2568 struct lio *lio = (struct lio *)wk->ctxptr; 2569 2570 if (!ifstate_check(lio, LIO_IFSTATE_RUNNING)) 2571 return; 2572 2573 check_txq_status(lio); 2574 queue_delayed_work(lio->txq_status_wq.wq, 2575 &lio->txq_status_wq.wk.work, msecs_to_jiffies(1)); 2576 } 2577 2578 /** 2579 * \brief Sets up the txq poll check 2580 * @param netdev network device 2581 */ 2582 static inline int setup_tx_poll_fn(struct net_device *netdev) 2583 { 2584 struct lio *lio = GET_LIO(netdev); 2585 struct octeon_device *oct = lio->oct_dev; 2586 2587 lio->txq_status_wq.wq = alloc_workqueue("txq-status", 2588 WQ_MEM_RECLAIM, 0); 2589 if (!lio->txq_status_wq.wq) { 2590 dev_err(&oct->pci_dev->dev, "unable to create cavium txq status wq\n"); 2591 return -1; 2592 } 2593 INIT_DELAYED_WORK(&lio->txq_status_wq.wk.work, 2594 octnet_poll_check_txq_status); 2595 lio->txq_status_wq.wk.ctxptr = lio; 2596 queue_delayed_work(lio->txq_status_wq.wq, 2597 &lio->txq_status_wq.wk.work, msecs_to_jiffies(1)); 2598 return 0; 2599 } 2600 2601 static inline void cleanup_tx_poll_fn(struct net_device *netdev) 2602 { 2603 struct lio *lio = GET_LIO(netdev); 2604 2605 if (lio->txq_status_wq.wq) { 2606 cancel_delayed_work_sync(&lio->txq_status_wq.wk.work); 2607 destroy_workqueue(lio->txq_status_wq.wq); 2608 } 2609 } 2610 2611 /** 2612 * \brief Net device open for LiquidIO 2613 * @param netdev network device 2614 */ 2615 static int liquidio_open(struct net_device *netdev) 2616 { 2617 struct lio *lio = GET_LIO(netdev); 2618 struct octeon_device *oct = lio->oct_dev; 2619 struct napi_struct *napi, *n; 2620 2621 if (oct->props[lio->ifidx].napi_enabled == 0) { 2622 list_for_each_entry_safe(napi, n, &netdev->napi_list, dev_list) 2623 napi_enable(napi); 2624 2625 oct->props[lio->ifidx].napi_enabled = 1; 2626 2627 if (OCTEON_CN23XX_PF(oct)) 2628 oct->droq[0]->ops.poll_mode = 1; 2629 } 2630 2631 oct_ptp_open(netdev); 2632 2633 ifstate_set(lio, LIO_IFSTATE_RUNNING); 2634 2635 /* Ready for link status updates */ 2636 lio->intf_open = 1; 2637 2638 netif_info(lio, ifup, lio->netdev, "Interface Open, ready for traffic\n"); 2639 2640 if (OCTEON_CN23XX_PF(oct)) { 2641 if (!oct->msix_on) 2642 if (setup_tx_poll_fn(netdev)) 2643 return -1; 2644 } else { 2645 if (setup_tx_poll_fn(netdev)) 2646 return -1; 2647 } 2648 2649 start_txq(netdev); 2650 2651 /* tell Octeon to start forwarding packets to host */ 2652 send_rx_ctrl_cmd(lio, 1); 2653 2654 dev_info(&oct->pci_dev->dev, "%s interface is opened\n", 2655 netdev->name); 2656 2657 return 0; 2658 } 2659 2660 /** 2661 * \brief Net device stop for LiquidIO 2662 * @param netdev network device 2663 */ 2664 static int liquidio_stop(struct net_device *netdev) 2665 { 2666 struct lio *lio = GET_LIO(netdev); 2667 struct octeon_device *oct = lio->oct_dev; 2668 2669 ifstate_reset(lio, LIO_IFSTATE_RUNNING); 2670 2671 netif_tx_disable(netdev); 2672 2673 /* Inform that netif carrier is down */ 2674 netif_carrier_off(netdev); 2675 lio->intf_open = 0; 2676 lio->linfo.link.s.link_up = 0; 2677 lio->link_changes++; 2678 2679 /* Pause for a moment and wait for Octeon to flush out (to the wire) any 2680 * egress packets that are in-flight. 2681 */ 2682 set_current_state(TASK_INTERRUPTIBLE); 2683 schedule_timeout(msecs_to_jiffies(100)); 2684 2685 /* Now it should be safe to tell Octeon that nic interface is down. */ 2686 send_rx_ctrl_cmd(lio, 0); 2687 2688 if (OCTEON_CN23XX_PF(oct)) { 2689 if (!oct->msix_on) 2690 cleanup_tx_poll_fn(netdev); 2691 } else { 2692 cleanup_tx_poll_fn(netdev); 2693 } 2694 2695 if (lio->ptp_clock) { 2696 ptp_clock_unregister(lio->ptp_clock); 2697 lio->ptp_clock = NULL; 2698 } 2699 2700 dev_info(&oct->pci_dev->dev, "%s interface is stopped\n", netdev->name); 2701 2702 return 0; 2703 } 2704 2705 /** 2706 * \brief Converts a mask based on net device flags 2707 * @param netdev network device 2708 * 2709 * This routine generates a octnet_ifflags mask from the net device flags 2710 * received from the OS. 2711 */ 2712 static inline enum octnet_ifflags get_new_flags(struct net_device *netdev) 2713 { 2714 enum octnet_ifflags f = OCTNET_IFFLAG_UNICAST; 2715 2716 if (netdev->flags & IFF_PROMISC) 2717 f |= OCTNET_IFFLAG_PROMISC; 2718 2719 if (netdev->flags & IFF_ALLMULTI) 2720 f |= OCTNET_IFFLAG_ALLMULTI; 2721 2722 if (netdev->flags & IFF_MULTICAST) { 2723 f |= OCTNET_IFFLAG_MULTICAST; 2724 2725 /* Accept all multicast addresses if there are more than we 2726 * can handle 2727 */ 2728 if (netdev_mc_count(netdev) > MAX_OCTEON_MULTICAST_ADDR) 2729 f |= OCTNET_IFFLAG_ALLMULTI; 2730 } 2731 2732 if (netdev->flags & IFF_BROADCAST) 2733 f |= OCTNET_IFFLAG_BROADCAST; 2734 2735 return f; 2736 } 2737 2738 /** 2739 * \brief Net device set_multicast_list 2740 * @param netdev network device 2741 */ 2742 static void liquidio_set_mcast_list(struct net_device *netdev) 2743 { 2744 struct lio *lio = GET_LIO(netdev); 2745 struct octeon_device *oct = lio->oct_dev; 2746 struct octnic_ctrl_pkt nctrl; 2747 struct netdev_hw_addr *ha; 2748 u64 *mc; 2749 int ret; 2750 int mc_count = min(netdev_mc_count(netdev), MAX_OCTEON_MULTICAST_ADDR); 2751 2752 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt)); 2753 2754 /* Create a ctrl pkt command to be sent to core app. */ 2755 nctrl.ncmd.u64 = 0; 2756 nctrl.ncmd.s.cmd = OCTNET_CMD_SET_MULTI_LIST; 2757 nctrl.ncmd.s.param1 = get_new_flags(netdev); 2758 nctrl.ncmd.s.param2 = mc_count; 2759 nctrl.ncmd.s.more = mc_count; 2760 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no; 2761 nctrl.netpndev = (u64)netdev; 2762 nctrl.cb_fn = liquidio_link_ctrl_cmd_completion; 2763 2764 /* copy all the addresses into the udd */ 2765 mc = &nctrl.udd[0]; 2766 netdev_for_each_mc_addr(ha, netdev) { 2767 *mc = 0; 2768 memcpy(((u8 *)mc) + 2, ha->addr, ETH_ALEN); 2769 /* no need to swap bytes */ 2770 2771 if (++mc > &nctrl.udd[mc_count]) 2772 break; 2773 } 2774 2775 /* Apparently, any activity in this call from the kernel has to 2776 * be atomic. So we won't wait for response. 2777 */ 2778 nctrl.wait_time = 0; 2779 2780 ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl); 2781 if (ret < 0) { 2782 dev_err(&oct->pci_dev->dev, "DEVFLAGS change failed in core (ret: 0x%x)\n", 2783 ret); 2784 } 2785 } 2786 2787 /** 2788 * \brief Net device set_mac_address 2789 * @param netdev network device 2790 */ 2791 static int liquidio_set_mac(struct net_device *netdev, void *p) 2792 { 2793 int ret = 0; 2794 struct lio *lio = GET_LIO(netdev); 2795 struct octeon_device *oct = lio->oct_dev; 2796 struct sockaddr *addr = (struct sockaddr *)p; 2797 struct octnic_ctrl_pkt nctrl; 2798 2799 if (!is_valid_ether_addr(addr->sa_data)) 2800 return -EADDRNOTAVAIL; 2801 2802 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt)); 2803 2804 nctrl.ncmd.u64 = 0; 2805 nctrl.ncmd.s.cmd = OCTNET_CMD_CHANGE_MACADDR; 2806 nctrl.ncmd.s.param1 = 0; 2807 nctrl.ncmd.s.more = 1; 2808 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no; 2809 nctrl.netpndev = (u64)netdev; 2810 nctrl.cb_fn = liquidio_link_ctrl_cmd_completion; 2811 nctrl.wait_time = 100; 2812 2813 nctrl.udd[0] = 0; 2814 /* The MAC Address is presented in network byte order. */ 2815 memcpy((u8 *)&nctrl.udd[0] + 2, addr->sa_data, ETH_ALEN); 2816 2817 ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl); 2818 if (ret < 0) { 2819 dev_err(&oct->pci_dev->dev, "MAC Address change failed\n"); 2820 return -ENOMEM; 2821 } 2822 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 2823 memcpy(((u8 *)&lio->linfo.hw_addr) + 2, addr->sa_data, ETH_ALEN); 2824 2825 return 0; 2826 } 2827 2828 /** 2829 * \brief Net device get_stats 2830 * @param netdev network device 2831 */ 2832 static struct net_device_stats *liquidio_get_stats(struct net_device *netdev) 2833 { 2834 struct lio *lio = GET_LIO(netdev); 2835 struct net_device_stats *stats = &netdev->stats; 2836 struct octeon_device *oct; 2837 u64 pkts = 0, drop = 0, bytes = 0; 2838 struct oct_droq_stats *oq_stats; 2839 struct oct_iq_stats *iq_stats; 2840 int i, iq_no, oq_no; 2841 2842 oct = lio->oct_dev; 2843 2844 for (i = 0; i < lio->linfo.num_txpciq; i++) { 2845 iq_no = lio->linfo.txpciq[i].s.q_no; 2846 iq_stats = &oct->instr_queue[iq_no]->stats; 2847 pkts += iq_stats->tx_done; 2848 drop += iq_stats->tx_dropped; 2849 bytes += iq_stats->tx_tot_bytes; 2850 } 2851 2852 stats->tx_packets = pkts; 2853 stats->tx_bytes = bytes; 2854 stats->tx_dropped = drop; 2855 2856 pkts = 0; 2857 drop = 0; 2858 bytes = 0; 2859 2860 for (i = 0; i < lio->linfo.num_rxpciq; i++) { 2861 oq_no = lio->linfo.rxpciq[i].s.q_no; 2862 oq_stats = &oct->droq[oq_no]->stats; 2863 pkts += oq_stats->rx_pkts_received; 2864 drop += (oq_stats->rx_dropped + 2865 oq_stats->dropped_nodispatch + 2866 oq_stats->dropped_toomany + 2867 oq_stats->dropped_nomem); 2868 bytes += oq_stats->rx_bytes_received; 2869 } 2870 2871 stats->rx_bytes = bytes; 2872 stats->rx_packets = pkts; 2873 stats->rx_dropped = drop; 2874 2875 return stats; 2876 } 2877 2878 /** 2879 * \brief Net device change_mtu 2880 * @param netdev network device 2881 */ 2882 static int liquidio_change_mtu(struct net_device *netdev, int new_mtu) 2883 { 2884 struct lio *lio = GET_LIO(netdev); 2885 struct octeon_device *oct = lio->oct_dev; 2886 struct octnic_ctrl_pkt nctrl; 2887 int ret = 0; 2888 2889 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt)); 2890 2891 nctrl.ncmd.u64 = 0; 2892 nctrl.ncmd.s.cmd = OCTNET_CMD_CHANGE_MTU; 2893 nctrl.ncmd.s.param1 = new_mtu; 2894 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no; 2895 nctrl.wait_time = 100; 2896 nctrl.netpndev = (u64)netdev; 2897 nctrl.cb_fn = liquidio_link_ctrl_cmd_completion; 2898 2899 ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl); 2900 if (ret < 0) { 2901 dev_err(&oct->pci_dev->dev, "Failed to set MTU\n"); 2902 return -1; 2903 } 2904 2905 lio->mtu = new_mtu; 2906 2907 return 0; 2908 } 2909 2910 /** 2911 * \brief Handler for SIOCSHWTSTAMP ioctl 2912 * @param netdev network device 2913 * @param ifr interface request 2914 * @param cmd command 2915 */ 2916 static int hwtstamp_ioctl(struct net_device *netdev, struct ifreq *ifr) 2917 { 2918 struct hwtstamp_config conf; 2919 struct lio *lio = GET_LIO(netdev); 2920 2921 if (copy_from_user(&conf, ifr->ifr_data, sizeof(conf))) 2922 return -EFAULT; 2923 2924 if (conf.flags) 2925 return -EINVAL; 2926 2927 switch (conf.tx_type) { 2928 case HWTSTAMP_TX_ON: 2929 case HWTSTAMP_TX_OFF: 2930 break; 2931 default: 2932 return -ERANGE; 2933 } 2934 2935 switch (conf.rx_filter) { 2936 case HWTSTAMP_FILTER_NONE: 2937 break; 2938 case HWTSTAMP_FILTER_ALL: 2939 case HWTSTAMP_FILTER_SOME: 2940 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 2941 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 2942 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 2943 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 2944 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 2945 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 2946 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 2947 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 2948 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 2949 case HWTSTAMP_FILTER_PTP_V2_EVENT: 2950 case HWTSTAMP_FILTER_PTP_V2_SYNC: 2951 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 2952 conf.rx_filter = HWTSTAMP_FILTER_ALL; 2953 break; 2954 default: 2955 return -ERANGE; 2956 } 2957 2958 if (conf.rx_filter == HWTSTAMP_FILTER_ALL) 2959 ifstate_set(lio, LIO_IFSTATE_RX_TIMESTAMP_ENABLED); 2960 2961 else 2962 ifstate_reset(lio, LIO_IFSTATE_RX_TIMESTAMP_ENABLED); 2963 2964 return copy_to_user(ifr->ifr_data, &conf, sizeof(conf)) ? -EFAULT : 0; 2965 } 2966 2967 /** 2968 * \brief ioctl handler 2969 * @param netdev network device 2970 * @param ifr interface request 2971 * @param cmd command 2972 */ 2973 static int liquidio_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 2974 { 2975 switch (cmd) { 2976 case SIOCSHWTSTAMP: 2977 return hwtstamp_ioctl(netdev, ifr); 2978 default: 2979 return -EOPNOTSUPP; 2980 } 2981 } 2982 2983 /** 2984 * \brief handle a Tx timestamp response 2985 * @param status response status 2986 * @param buf pointer to skb 2987 */ 2988 static void handle_timestamp(struct octeon_device *oct, 2989 u32 status, 2990 void *buf) 2991 { 2992 struct octnet_buf_free_info *finfo; 2993 struct octeon_soft_command *sc; 2994 struct oct_timestamp_resp *resp; 2995 struct lio *lio; 2996 struct sk_buff *skb = (struct sk_buff *)buf; 2997 2998 finfo = (struct octnet_buf_free_info *)skb->cb; 2999 lio = finfo->lio; 3000 sc = finfo->sc; 3001 oct = lio->oct_dev; 3002 resp = (struct oct_timestamp_resp *)sc->virtrptr; 3003 3004 if (status != OCTEON_REQUEST_DONE) { 3005 dev_err(&oct->pci_dev->dev, "Tx timestamp instruction failed. Status: %llx\n", 3006 CVM_CAST64(status)); 3007 resp->timestamp = 0; 3008 } 3009 3010 octeon_swap_8B_data(&resp->timestamp, 1); 3011 3012 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) != 0)) { 3013 struct skb_shared_hwtstamps ts; 3014 u64 ns = resp->timestamp; 3015 3016 netif_info(lio, tx_done, lio->netdev, 3017 "Got resulting SKBTX_HW_TSTAMP skb=%p ns=%016llu\n", 3018 skb, (unsigned long long)ns); 3019 ts.hwtstamp = ns_to_ktime(ns + lio->ptp_adjust); 3020 skb_tstamp_tx(skb, &ts); 3021 } 3022 3023 octeon_free_soft_command(oct, sc); 3024 tx_buffer_free(skb); 3025 } 3026 3027 /* \brief Send a data packet that will be timestamped 3028 * @param oct octeon device 3029 * @param ndata pointer to network data 3030 * @param finfo pointer to private network data 3031 */ 3032 static inline int send_nic_timestamp_pkt(struct octeon_device *oct, 3033 struct octnic_data_pkt *ndata, 3034 struct octnet_buf_free_info *finfo) 3035 { 3036 int retval; 3037 struct octeon_soft_command *sc; 3038 struct lio *lio; 3039 int ring_doorbell; 3040 u32 len; 3041 3042 lio = finfo->lio; 3043 3044 sc = octeon_alloc_soft_command_resp(oct, &ndata->cmd, 3045 sizeof(struct oct_timestamp_resp)); 3046 finfo->sc = sc; 3047 3048 if (!sc) { 3049 dev_err(&oct->pci_dev->dev, "No memory for timestamped data packet\n"); 3050 return IQ_SEND_FAILED; 3051 } 3052 3053 if (ndata->reqtype == REQTYPE_NORESP_NET) 3054 ndata->reqtype = REQTYPE_RESP_NET; 3055 else if (ndata->reqtype == REQTYPE_NORESP_NET_SG) 3056 ndata->reqtype = REQTYPE_RESP_NET_SG; 3057 3058 sc->callback = handle_timestamp; 3059 sc->callback_arg = finfo->skb; 3060 sc->iq_no = ndata->q_no; 3061 3062 if (OCTEON_CN23XX_PF(oct)) 3063 len = (u32)((struct octeon_instr_ih3 *) 3064 (&sc->cmd.cmd3.ih3))->dlengsz; 3065 else 3066 len = (u32)((struct octeon_instr_ih2 *) 3067 (&sc->cmd.cmd2.ih2))->dlengsz; 3068 3069 ring_doorbell = 1; 3070 3071 retval = octeon_send_command(oct, sc->iq_no, ring_doorbell, &sc->cmd, 3072 sc, len, ndata->reqtype); 3073 3074 if (retval == IQ_SEND_FAILED) { 3075 dev_err(&oct->pci_dev->dev, "timestamp data packet failed status: %x\n", 3076 retval); 3077 octeon_free_soft_command(oct, sc); 3078 } else { 3079 netif_info(lio, tx_queued, lio->netdev, "Queued timestamp packet\n"); 3080 } 3081 3082 return retval; 3083 } 3084 3085 /** \brief Transmit networks packets to the Octeon interface 3086 * @param skbuff skbuff struct to be passed to network layer. 3087 * @param netdev pointer to network device 3088 * @returns whether the packet was transmitted to the device okay or not 3089 * (NETDEV_TX_OK or NETDEV_TX_BUSY) 3090 */ 3091 static int liquidio_xmit(struct sk_buff *skb, struct net_device *netdev) 3092 { 3093 struct lio *lio; 3094 struct octnet_buf_free_info *finfo; 3095 union octnic_cmd_setup cmdsetup; 3096 struct octnic_data_pkt ndata; 3097 struct octeon_device *oct; 3098 struct oct_iq_stats *stats; 3099 struct octeon_instr_irh *irh; 3100 union tx_info *tx_info; 3101 int status = 0; 3102 int q_idx = 0, iq_no = 0; 3103 int j; 3104 u64 dptr = 0; 3105 u32 tag = 0; 3106 3107 lio = GET_LIO(netdev); 3108 oct = lio->oct_dev; 3109 3110 if (netif_is_multiqueue(netdev)) { 3111 q_idx = skb->queue_mapping; 3112 q_idx = (q_idx % (lio->linfo.num_txpciq)); 3113 tag = q_idx; 3114 iq_no = lio->linfo.txpciq[q_idx].s.q_no; 3115 } else { 3116 iq_no = lio->txq; 3117 } 3118 3119 stats = &oct->instr_queue[iq_no]->stats; 3120 3121 /* Check for all conditions in which the current packet cannot be 3122 * transmitted. 3123 */ 3124 if (!(atomic_read(&lio->ifstate) & LIO_IFSTATE_RUNNING) || 3125 (!lio->linfo.link.s.link_up) || 3126 (skb->len <= 0)) { 3127 netif_info(lio, tx_err, lio->netdev, 3128 "Transmit failed link_status : %d\n", 3129 lio->linfo.link.s.link_up); 3130 goto lio_xmit_failed; 3131 } 3132 3133 /* Use space in skb->cb to store info used to unmap and 3134 * free the buffers. 3135 */ 3136 finfo = (struct octnet_buf_free_info *)skb->cb; 3137 finfo->lio = lio; 3138 finfo->skb = skb; 3139 finfo->sc = NULL; 3140 3141 /* Prepare the attributes for the data to be passed to OSI. */ 3142 memset(&ndata, 0, sizeof(struct octnic_data_pkt)); 3143 3144 ndata.buf = (void *)finfo; 3145 3146 ndata.q_no = iq_no; 3147 3148 if (netif_is_multiqueue(netdev)) { 3149 if (octnet_iq_is_full(oct, ndata.q_no)) { 3150 /* defer sending if queue is full */ 3151 netif_info(lio, tx_err, lio->netdev, "Transmit failed iq:%d full\n", 3152 ndata.q_no); 3153 stats->tx_iq_busy++; 3154 return NETDEV_TX_BUSY; 3155 } 3156 } else { 3157 if (octnet_iq_is_full(oct, lio->txq)) { 3158 /* defer sending if queue is full */ 3159 stats->tx_iq_busy++; 3160 netif_info(lio, tx_err, lio->netdev, "Transmit failed iq:%d full\n", 3161 lio->txq); 3162 return NETDEV_TX_BUSY; 3163 } 3164 } 3165 /* pr_info(" XMIT - valid Qs: %d, 1st Q no: %d, cpu: %d, q_no:%d\n", 3166 * lio->linfo.num_txpciq, lio->txq, cpu, ndata.q_no); 3167 */ 3168 3169 ndata.datasize = skb->len; 3170 3171 cmdsetup.u64 = 0; 3172 cmdsetup.s.iq_no = iq_no; 3173 3174 if (skb->ip_summed == CHECKSUM_PARTIAL) { 3175 if (skb->encapsulation) { 3176 cmdsetup.s.tnl_csum = 1; 3177 stats->tx_vxlan++; 3178 } else { 3179 cmdsetup.s.transport_csum = 1; 3180 } 3181 } 3182 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { 3183 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 3184 cmdsetup.s.timestamp = 1; 3185 } 3186 3187 if (skb_shinfo(skb)->nr_frags == 0) { 3188 cmdsetup.s.u.datasize = skb->len; 3189 octnet_prepare_pci_cmd(oct, &ndata.cmd, &cmdsetup, tag); 3190 3191 /* Offload checksum calculation for TCP/UDP packets */ 3192 dptr = dma_map_single(&oct->pci_dev->dev, 3193 skb->data, 3194 skb->len, 3195 DMA_TO_DEVICE); 3196 if (dma_mapping_error(&oct->pci_dev->dev, dptr)) { 3197 dev_err(&oct->pci_dev->dev, "%s DMA mapping error 1\n", 3198 __func__); 3199 return NETDEV_TX_BUSY; 3200 } 3201 3202 if (OCTEON_CN23XX_PF(oct)) 3203 ndata.cmd.cmd3.dptr = dptr; 3204 else 3205 ndata.cmd.cmd2.dptr = dptr; 3206 finfo->dptr = dptr; 3207 ndata.reqtype = REQTYPE_NORESP_NET; 3208 3209 } else { 3210 int i, frags; 3211 struct skb_frag_struct *frag; 3212 struct octnic_gather *g; 3213 3214 spin_lock(&lio->glist_lock[q_idx]); 3215 g = (struct octnic_gather *) 3216 list_delete_head(&lio->glist[q_idx]); 3217 spin_unlock(&lio->glist_lock[q_idx]); 3218 3219 if (!g) { 3220 netif_info(lio, tx_err, lio->netdev, 3221 "Transmit scatter gather: glist null!\n"); 3222 goto lio_xmit_failed; 3223 } 3224 3225 cmdsetup.s.gather = 1; 3226 cmdsetup.s.u.gatherptrs = (skb_shinfo(skb)->nr_frags + 1); 3227 octnet_prepare_pci_cmd(oct, &ndata.cmd, &cmdsetup, tag); 3228 3229 memset(g->sg, 0, g->sg_size); 3230 3231 g->sg[0].ptr[0] = dma_map_single(&oct->pci_dev->dev, 3232 skb->data, 3233 (skb->len - skb->data_len), 3234 DMA_TO_DEVICE); 3235 if (dma_mapping_error(&oct->pci_dev->dev, g->sg[0].ptr[0])) { 3236 dev_err(&oct->pci_dev->dev, "%s DMA mapping error 2\n", 3237 __func__); 3238 return NETDEV_TX_BUSY; 3239 } 3240 add_sg_size(&g->sg[0], (skb->len - skb->data_len), 0); 3241 3242 frags = skb_shinfo(skb)->nr_frags; 3243 i = 1; 3244 while (frags--) { 3245 frag = &skb_shinfo(skb)->frags[i - 1]; 3246 3247 g->sg[(i >> 2)].ptr[(i & 3)] = 3248 dma_map_page(&oct->pci_dev->dev, 3249 frag->page.p, 3250 frag->page_offset, 3251 frag->size, 3252 DMA_TO_DEVICE); 3253 3254 if (dma_mapping_error(&oct->pci_dev->dev, 3255 g->sg[i >> 2].ptr[i & 3])) { 3256 dma_unmap_single(&oct->pci_dev->dev, 3257 g->sg[0].ptr[0], 3258 skb->len - skb->data_len, 3259 DMA_TO_DEVICE); 3260 for (j = 1; j < i; j++) { 3261 frag = &skb_shinfo(skb)->frags[j - 1]; 3262 dma_unmap_page(&oct->pci_dev->dev, 3263 g->sg[j >> 2].ptr[j & 3], 3264 frag->size, 3265 DMA_TO_DEVICE); 3266 } 3267 dev_err(&oct->pci_dev->dev, "%s DMA mapping error 3\n", 3268 __func__); 3269 return NETDEV_TX_BUSY; 3270 } 3271 3272 add_sg_size(&g->sg[(i >> 2)], frag->size, (i & 3)); 3273 i++; 3274 } 3275 3276 dma_sync_single_for_device(&oct->pci_dev->dev, g->sg_dma_ptr, 3277 g->sg_size, DMA_TO_DEVICE); 3278 dptr = g->sg_dma_ptr; 3279 3280 if (OCTEON_CN23XX_PF(oct)) 3281 ndata.cmd.cmd3.dptr = dptr; 3282 else 3283 ndata.cmd.cmd2.dptr = dptr; 3284 finfo->dptr = dptr; 3285 finfo->g = g; 3286 3287 ndata.reqtype = REQTYPE_NORESP_NET_SG; 3288 } 3289 3290 if (OCTEON_CN23XX_PF(oct)) { 3291 irh = (struct octeon_instr_irh *)&ndata.cmd.cmd3.irh; 3292 tx_info = (union tx_info *)&ndata.cmd.cmd3.ossp[0]; 3293 } else { 3294 irh = (struct octeon_instr_irh *)&ndata.cmd.cmd2.irh; 3295 tx_info = (union tx_info *)&ndata.cmd.cmd2.ossp[0]; 3296 } 3297 3298 if (skb_shinfo(skb)->gso_size) { 3299 tx_info->s.gso_size = skb_shinfo(skb)->gso_size; 3300 tx_info->s.gso_segs = skb_shinfo(skb)->gso_segs; 3301 stats->tx_gso++; 3302 } 3303 3304 /* HW insert VLAN tag */ 3305 if (skb_vlan_tag_present(skb)) { 3306 irh->priority = skb_vlan_tag_get(skb) >> 13; 3307 irh->vlan = skb_vlan_tag_get(skb) & 0xfff; 3308 } 3309 3310 if (unlikely(cmdsetup.s.timestamp)) 3311 status = send_nic_timestamp_pkt(oct, &ndata, finfo); 3312 else 3313 status = octnet_send_nic_data_pkt(oct, &ndata); 3314 if (status == IQ_SEND_FAILED) 3315 goto lio_xmit_failed; 3316 3317 netif_info(lio, tx_queued, lio->netdev, "Transmit queued successfully\n"); 3318 3319 if (status == IQ_SEND_STOP) 3320 stop_q(lio->netdev, q_idx); 3321 3322 netif_trans_update(netdev); 3323 3324 if (skb_shinfo(skb)->gso_size) 3325 stats->tx_done += skb_shinfo(skb)->gso_segs; 3326 else 3327 stats->tx_done++; 3328 stats->tx_tot_bytes += skb->len; 3329 3330 return NETDEV_TX_OK; 3331 3332 lio_xmit_failed: 3333 stats->tx_dropped++; 3334 netif_info(lio, tx_err, lio->netdev, "IQ%d Transmit dropped:%llu\n", 3335 iq_no, stats->tx_dropped); 3336 if (dptr) 3337 dma_unmap_single(&oct->pci_dev->dev, dptr, 3338 ndata.datasize, DMA_TO_DEVICE); 3339 tx_buffer_free(skb); 3340 return NETDEV_TX_OK; 3341 } 3342 3343 /** \brief Network device Tx timeout 3344 * @param netdev pointer to network device 3345 */ 3346 static void liquidio_tx_timeout(struct net_device *netdev) 3347 { 3348 struct lio *lio; 3349 3350 lio = GET_LIO(netdev); 3351 3352 netif_info(lio, tx_err, lio->netdev, 3353 "Transmit timeout tx_dropped:%ld, waking up queues now!!\n", 3354 netdev->stats.tx_dropped); 3355 netif_trans_update(netdev); 3356 txqs_wake(netdev); 3357 } 3358 3359 static int liquidio_vlan_rx_add_vid(struct net_device *netdev, 3360 __be16 proto __attribute__((unused)), 3361 u16 vid) 3362 { 3363 struct lio *lio = GET_LIO(netdev); 3364 struct octeon_device *oct = lio->oct_dev; 3365 struct octnic_ctrl_pkt nctrl; 3366 int ret = 0; 3367 3368 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt)); 3369 3370 nctrl.ncmd.u64 = 0; 3371 nctrl.ncmd.s.cmd = OCTNET_CMD_ADD_VLAN_FILTER; 3372 nctrl.ncmd.s.param1 = vid; 3373 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no; 3374 nctrl.wait_time = 100; 3375 nctrl.netpndev = (u64)netdev; 3376 nctrl.cb_fn = liquidio_link_ctrl_cmd_completion; 3377 3378 ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl); 3379 if (ret < 0) { 3380 dev_err(&oct->pci_dev->dev, "Add VLAN filter failed in core (ret: 0x%x)\n", 3381 ret); 3382 } 3383 3384 return ret; 3385 } 3386 3387 static int liquidio_vlan_rx_kill_vid(struct net_device *netdev, 3388 __be16 proto __attribute__((unused)), 3389 u16 vid) 3390 { 3391 struct lio *lio = GET_LIO(netdev); 3392 struct octeon_device *oct = lio->oct_dev; 3393 struct octnic_ctrl_pkt nctrl; 3394 int ret = 0; 3395 3396 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt)); 3397 3398 nctrl.ncmd.u64 = 0; 3399 nctrl.ncmd.s.cmd = OCTNET_CMD_DEL_VLAN_FILTER; 3400 nctrl.ncmd.s.param1 = vid; 3401 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no; 3402 nctrl.wait_time = 100; 3403 nctrl.netpndev = (u64)netdev; 3404 nctrl.cb_fn = liquidio_link_ctrl_cmd_completion; 3405 3406 ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl); 3407 if (ret < 0) { 3408 dev_err(&oct->pci_dev->dev, "Add VLAN filter failed in core (ret: 0x%x)\n", 3409 ret); 3410 } 3411 return ret; 3412 } 3413 3414 /** Sending command to enable/disable RX checksum offload 3415 * @param netdev pointer to network device 3416 * @param command OCTNET_CMD_TNL_RX_CSUM_CTL 3417 * @param rx_cmd_bit OCTNET_CMD_RXCSUM_ENABLE/ 3418 * OCTNET_CMD_RXCSUM_DISABLE 3419 * @returns SUCCESS or FAILURE 3420 */ 3421 static int liquidio_set_rxcsum_command(struct net_device *netdev, int command, 3422 u8 rx_cmd) 3423 { 3424 struct lio *lio = GET_LIO(netdev); 3425 struct octeon_device *oct = lio->oct_dev; 3426 struct octnic_ctrl_pkt nctrl; 3427 int ret = 0; 3428 3429 nctrl.ncmd.u64 = 0; 3430 nctrl.ncmd.s.cmd = command; 3431 nctrl.ncmd.s.param1 = rx_cmd; 3432 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no; 3433 nctrl.wait_time = 100; 3434 nctrl.netpndev = (u64)netdev; 3435 nctrl.cb_fn = liquidio_link_ctrl_cmd_completion; 3436 3437 ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl); 3438 if (ret < 0) { 3439 dev_err(&oct->pci_dev->dev, 3440 "DEVFLAGS RXCSUM change failed in core(ret:0x%x)\n", 3441 ret); 3442 } 3443 return ret; 3444 } 3445 3446 /** Sending command to add/delete VxLAN UDP port to firmware 3447 * @param netdev pointer to network device 3448 * @param command OCTNET_CMD_VXLAN_PORT_CONFIG 3449 * @param vxlan_port VxLAN port to be added or deleted 3450 * @param vxlan_cmd_bit OCTNET_CMD_VXLAN_PORT_ADD, 3451 * OCTNET_CMD_VXLAN_PORT_DEL 3452 * @returns SUCCESS or FAILURE 3453 */ 3454 static int liquidio_vxlan_port_command(struct net_device *netdev, int command, 3455 u16 vxlan_port, u8 vxlan_cmd_bit) 3456 { 3457 struct lio *lio = GET_LIO(netdev); 3458 struct octeon_device *oct = lio->oct_dev; 3459 struct octnic_ctrl_pkt nctrl; 3460 int ret = 0; 3461 3462 nctrl.ncmd.u64 = 0; 3463 nctrl.ncmd.s.cmd = command; 3464 nctrl.ncmd.s.more = vxlan_cmd_bit; 3465 nctrl.ncmd.s.param1 = vxlan_port; 3466 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no; 3467 nctrl.wait_time = 100; 3468 nctrl.netpndev = (u64)netdev; 3469 nctrl.cb_fn = liquidio_link_ctrl_cmd_completion; 3470 3471 ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl); 3472 if (ret < 0) { 3473 dev_err(&oct->pci_dev->dev, 3474 "VxLAN port add/delete failed in core (ret:0x%x)\n", 3475 ret); 3476 } 3477 return ret; 3478 } 3479 3480 /** \brief Net device fix features 3481 * @param netdev pointer to network device 3482 * @param request features requested 3483 * @returns updated features list 3484 */ 3485 static netdev_features_t liquidio_fix_features(struct net_device *netdev, 3486 netdev_features_t request) 3487 { 3488 struct lio *lio = netdev_priv(netdev); 3489 3490 if ((request & NETIF_F_RXCSUM) && 3491 !(lio->dev_capability & NETIF_F_RXCSUM)) 3492 request &= ~NETIF_F_RXCSUM; 3493 3494 if ((request & NETIF_F_HW_CSUM) && 3495 !(lio->dev_capability & NETIF_F_HW_CSUM)) 3496 request &= ~NETIF_F_HW_CSUM; 3497 3498 if ((request & NETIF_F_TSO) && !(lio->dev_capability & NETIF_F_TSO)) 3499 request &= ~NETIF_F_TSO; 3500 3501 if ((request & NETIF_F_TSO6) && !(lio->dev_capability & NETIF_F_TSO6)) 3502 request &= ~NETIF_F_TSO6; 3503 3504 if ((request & NETIF_F_LRO) && !(lio->dev_capability & NETIF_F_LRO)) 3505 request &= ~NETIF_F_LRO; 3506 3507 /*Disable LRO if RXCSUM is off */ 3508 if (!(request & NETIF_F_RXCSUM) && (netdev->features & NETIF_F_LRO) && 3509 (lio->dev_capability & NETIF_F_LRO)) 3510 request &= ~NETIF_F_LRO; 3511 3512 return request; 3513 } 3514 3515 /** \brief Net device set features 3516 * @param netdev pointer to network device 3517 * @param features features to enable/disable 3518 */ 3519 static int liquidio_set_features(struct net_device *netdev, 3520 netdev_features_t features) 3521 { 3522 struct lio *lio = netdev_priv(netdev); 3523 3524 if (!((netdev->features ^ features) & NETIF_F_LRO)) 3525 return 0; 3526 3527 if ((features & NETIF_F_LRO) && (lio->dev_capability & NETIF_F_LRO)) 3528 liquidio_set_feature(netdev, OCTNET_CMD_LRO_ENABLE, 3529 OCTNIC_LROIPV4 | OCTNIC_LROIPV6); 3530 else if (!(features & NETIF_F_LRO) && 3531 (lio->dev_capability & NETIF_F_LRO)) 3532 liquidio_set_feature(netdev, OCTNET_CMD_LRO_DISABLE, 3533 OCTNIC_LROIPV4 | OCTNIC_LROIPV6); 3534 3535 /* Sending command to firmware to enable/disable RX checksum 3536 * offload settings using ethtool 3537 */ 3538 if (!(netdev->features & NETIF_F_RXCSUM) && 3539 (lio->enc_dev_capability & NETIF_F_RXCSUM) && 3540 (features & NETIF_F_RXCSUM)) 3541 liquidio_set_rxcsum_command(netdev, 3542 OCTNET_CMD_TNL_RX_CSUM_CTL, 3543 OCTNET_CMD_RXCSUM_ENABLE); 3544 else if ((netdev->features & NETIF_F_RXCSUM) && 3545 (lio->enc_dev_capability & NETIF_F_RXCSUM) && 3546 !(features & NETIF_F_RXCSUM)) 3547 liquidio_set_rxcsum_command(netdev, OCTNET_CMD_TNL_RX_CSUM_CTL, 3548 OCTNET_CMD_RXCSUM_DISABLE); 3549 3550 return 0; 3551 } 3552 3553 static void liquidio_add_vxlan_port(struct net_device *netdev, 3554 struct udp_tunnel_info *ti) 3555 { 3556 if (ti->type != UDP_TUNNEL_TYPE_VXLAN) 3557 return; 3558 3559 liquidio_vxlan_port_command(netdev, 3560 OCTNET_CMD_VXLAN_PORT_CONFIG, 3561 htons(ti->port), 3562 OCTNET_CMD_VXLAN_PORT_ADD); 3563 } 3564 3565 static void liquidio_del_vxlan_port(struct net_device *netdev, 3566 struct udp_tunnel_info *ti) 3567 { 3568 if (ti->type != UDP_TUNNEL_TYPE_VXLAN) 3569 return; 3570 3571 liquidio_vxlan_port_command(netdev, 3572 OCTNET_CMD_VXLAN_PORT_CONFIG, 3573 htons(ti->port), 3574 OCTNET_CMD_VXLAN_PORT_DEL); 3575 } 3576 3577 static int __liquidio_set_vf_mac(struct net_device *netdev, int vfidx, 3578 u8 *mac, bool is_admin_assigned) 3579 { 3580 struct lio *lio = GET_LIO(netdev); 3581 struct octeon_device *oct = lio->oct_dev; 3582 struct octnic_ctrl_pkt nctrl; 3583 3584 if (!is_valid_ether_addr(mac)) 3585 return -EINVAL; 3586 3587 if (vfidx < 0 || vfidx >= oct->sriov_info.max_vfs) 3588 return -EINVAL; 3589 3590 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt)); 3591 3592 nctrl.ncmd.u64 = 0; 3593 nctrl.ncmd.s.cmd = OCTNET_CMD_CHANGE_MACADDR; 3594 /* vfidx is 0 based, but vf_num (param1) is 1 based */ 3595 nctrl.ncmd.s.param1 = vfidx + 1; 3596 nctrl.ncmd.s.param2 = (is_admin_assigned ? 1 : 0); 3597 nctrl.ncmd.s.more = 1; 3598 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no; 3599 nctrl.cb_fn = 0; 3600 nctrl.wait_time = LIO_CMD_WAIT_TM; 3601 3602 nctrl.udd[0] = 0; 3603 /* The MAC Address is presented in network byte order. */ 3604 ether_addr_copy((u8 *)&nctrl.udd[0] + 2, mac); 3605 3606 oct->sriov_info.vf_macaddr[vfidx] = nctrl.udd[0]; 3607 3608 octnet_send_nic_ctrl_pkt(oct, &nctrl); 3609 3610 return 0; 3611 } 3612 3613 static int liquidio_set_vf_mac(struct net_device *netdev, int vfidx, u8 *mac) 3614 { 3615 struct lio *lio = GET_LIO(netdev); 3616 struct octeon_device *oct = lio->oct_dev; 3617 int retval; 3618 3619 retval = __liquidio_set_vf_mac(netdev, vfidx, mac, true); 3620 if (!retval) 3621 cn23xx_tell_vf_its_macaddr_changed(oct, vfidx, mac); 3622 3623 return retval; 3624 } 3625 3626 static int liquidio_set_vf_vlan(struct net_device *netdev, int vfidx, 3627 u16 vlan, u8 qos, __be16 vlan_proto) 3628 { 3629 struct lio *lio = GET_LIO(netdev); 3630 struct octeon_device *oct = lio->oct_dev; 3631 struct octnic_ctrl_pkt nctrl; 3632 u16 vlantci; 3633 3634 if (vfidx < 0 || vfidx >= oct->sriov_info.num_vfs_alloced) 3635 return -EINVAL; 3636 3637 if (vlan_proto != htons(ETH_P_8021Q)) 3638 return -EPROTONOSUPPORT; 3639 3640 if (vlan >= VLAN_N_VID || qos > 7) 3641 return -EINVAL; 3642 3643 if (vlan) 3644 vlantci = vlan | (u16)qos << VLAN_PRIO_SHIFT; 3645 else 3646 vlantci = 0; 3647 3648 if (oct->sriov_info.vf_vlantci[vfidx] == vlantci) 3649 return 0; 3650 3651 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt)); 3652 3653 if (vlan) 3654 nctrl.ncmd.s.cmd = OCTNET_CMD_ADD_VLAN_FILTER; 3655 else 3656 nctrl.ncmd.s.cmd = OCTNET_CMD_DEL_VLAN_FILTER; 3657 3658 nctrl.ncmd.s.param1 = vlantci; 3659 nctrl.ncmd.s.param2 = 3660 vfidx + 1; /* vfidx is 0 based, but vf_num (param2) is 1 based */ 3661 nctrl.ncmd.s.more = 0; 3662 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no; 3663 nctrl.cb_fn = 0; 3664 nctrl.wait_time = LIO_CMD_WAIT_TM; 3665 3666 octnet_send_nic_ctrl_pkt(oct, &nctrl); 3667 3668 oct->sriov_info.vf_vlantci[vfidx] = vlantci; 3669 3670 return 0; 3671 } 3672 3673 static int liquidio_get_vf_config(struct net_device *netdev, int vfidx, 3674 struct ifla_vf_info *ivi) 3675 { 3676 struct lio *lio = GET_LIO(netdev); 3677 struct octeon_device *oct = lio->oct_dev; 3678 u8 *macaddr; 3679 3680 if (vfidx < 0 || vfidx >= oct->sriov_info.num_vfs_alloced) 3681 return -EINVAL; 3682 3683 ivi->vf = vfidx; 3684 macaddr = 2 + (u8 *)&oct->sriov_info.vf_macaddr[vfidx]; 3685 ether_addr_copy(&ivi->mac[0], macaddr); 3686 ivi->vlan = oct->sriov_info.vf_vlantci[vfidx] & VLAN_VID_MASK; 3687 ivi->qos = oct->sriov_info.vf_vlantci[vfidx] >> VLAN_PRIO_SHIFT; 3688 ivi->linkstate = oct->sriov_info.vf_linkstate[vfidx]; 3689 return 0; 3690 } 3691 3692 static int liquidio_set_vf_link_state(struct net_device *netdev, int vfidx, 3693 int linkstate) 3694 { 3695 struct lio *lio = GET_LIO(netdev); 3696 struct octeon_device *oct = lio->oct_dev; 3697 struct octnic_ctrl_pkt nctrl; 3698 3699 if (vfidx < 0 || vfidx >= oct->sriov_info.num_vfs_alloced) 3700 return -EINVAL; 3701 3702 if (oct->sriov_info.vf_linkstate[vfidx] == linkstate) 3703 return 0; 3704 3705 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt)); 3706 nctrl.ncmd.s.cmd = OCTNET_CMD_SET_VF_LINKSTATE; 3707 nctrl.ncmd.s.param1 = 3708 vfidx + 1; /* vfidx is 0 based, but vf_num (param1) is 1 based */ 3709 nctrl.ncmd.s.param2 = linkstate; 3710 nctrl.ncmd.s.more = 0; 3711 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no; 3712 nctrl.cb_fn = 0; 3713 nctrl.wait_time = LIO_CMD_WAIT_TM; 3714 3715 octnet_send_nic_ctrl_pkt(oct, &nctrl); 3716 3717 oct->sriov_info.vf_linkstate[vfidx] = linkstate; 3718 3719 return 0; 3720 } 3721 3722 static const struct net_device_ops lionetdevops = { 3723 .ndo_open = liquidio_open, 3724 .ndo_stop = liquidio_stop, 3725 .ndo_start_xmit = liquidio_xmit, 3726 .ndo_get_stats = liquidio_get_stats, 3727 .ndo_set_mac_address = liquidio_set_mac, 3728 .ndo_set_rx_mode = liquidio_set_mcast_list, 3729 .ndo_tx_timeout = liquidio_tx_timeout, 3730 3731 .ndo_vlan_rx_add_vid = liquidio_vlan_rx_add_vid, 3732 .ndo_vlan_rx_kill_vid = liquidio_vlan_rx_kill_vid, 3733 .ndo_change_mtu = liquidio_change_mtu, 3734 .ndo_do_ioctl = liquidio_ioctl, 3735 .ndo_fix_features = liquidio_fix_features, 3736 .ndo_set_features = liquidio_set_features, 3737 .ndo_udp_tunnel_add = liquidio_add_vxlan_port, 3738 .ndo_udp_tunnel_del = liquidio_del_vxlan_port, 3739 .ndo_set_vf_mac = liquidio_set_vf_mac, 3740 .ndo_set_vf_vlan = liquidio_set_vf_vlan, 3741 .ndo_get_vf_config = liquidio_get_vf_config, 3742 .ndo_set_vf_link_state = liquidio_set_vf_link_state, 3743 .ndo_select_queue = select_q 3744 }; 3745 3746 /** \brief Entry point for the liquidio module 3747 */ 3748 static int __init liquidio_init(void) 3749 { 3750 int i; 3751 struct handshake *hs; 3752 3753 init_completion(&first_stage); 3754 3755 octeon_init_device_list(OCTEON_CONFIG_TYPE_DEFAULT); 3756 3757 if (liquidio_init_pci()) 3758 return -EINVAL; 3759 3760 wait_for_completion_timeout(&first_stage, msecs_to_jiffies(1000)); 3761 3762 for (i = 0; i < MAX_OCTEON_DEVICES; i++) { 3763 hs = &handshake[i]; 3764 if (hs->pci_dev) { 3765 wait_for_completion(&hs->init); 3766 if (!hs->init_ok) { 3767 /* init handshake failed */ 3768 dev_err(&hs->pci_dev->dev, 3769 "Failed to init device\n"); 3770 liquidio_deinit_pci(); 3771 return -EIO; 3772 } 3773 } 3774 } 3775 3776 for (i = 0; i < MAX_OCTEON_DEVICES; i++) { 3777 hs = &handshake[i]; 3778 if (hs->pci_dev) { 3779 wait_for_completion_timeout(&hs->started, 3780 msecs_to_jiffies(30000)); 3781 if (!hs->started_ok) { 3782 /* starter handshake failed */ 3783 dev_err(&hs->pci_dev->dev, 3784 "Firmware failed to start\n"); 3785 liquidio_deinit_pci(); 3786 return -EIO; 3787 } 3788 } 3789 } 3790 3791 return 0; 3792 } 3793 3794 static int lio_nic_info(struct octeon_recv_info *recv_info, void *buf) 3795 { 3796 struct octeon_device *oct = (struct octeon_device *)buf; 3797 struct octeon_recv_pkt *recv_pkt = recv_info->recv_pkt; 3798 int gmxport = 0; 3799 union oct_link_status *ls; 3800 int i; 3801 3802 if (recv_pkt->buffer_size[0] != sizeof(*ls)) { 3803 dev_err(&oct->pci_dev->dev, "Malformed NIC_INFO, len=%d, ifidx=%d\n", 3804 recv_pkt->buffer_size[0], 3805 recv_pkt->rh.r_nic_info.gmxport); 3806 goto nic_info_err; 3807 } 3808 3809 gmxport = recv_pkt->rh.r_nic_info.gmxport; 3810 ls = (union oct_link_status *)get_rbd(recv_pkt->buffer_ptr[0]); 3811 3812 octeon_swap_8B_data((u64 *)ls, (sizeof(union oct_link_status)) >> 3); 3813 for (i = 0; i < oct->ifcount; i++) { 3814 if (oct->props[i].gmxport == gmxport) { 3815 update_link_status(oct->props[i].netdev, ls); 3816 break; 3817 } 3818 } 3819 3820 nic_info_err: 3821 for (i = 0; i < recv_pkt->buffer_count; i++) 3822 recv_buffer_free(recv_pkt->buffer_ptr[i]); 3823 octeon_free_recv_info(recv_info); 3824 return 0; 3825 } 3826 3827 /** 3828 * \brief Setup network interfaces 3829 * @param octeon_dev octeon device 3830 * 3831 * Called during init time for each device. It assumes the NIC 3832 * is already up and running. The link information for each 3833 * interface is passed in link_info. 3834 */ 3835 static int setup_nic_devices(struct octeon_device *octeon_dev) 3836 { 3837 struct lio *lio = NULL; 3838 struct net_device *netdev; 3839 u8 mac[6], i, j; 3840 struct octeon_soft_command *sc; 3841 struct liquidio_if_cfg_context *ctx; 3842 struct liquidio_if_cfg_resp *resp; 3843 struct octdev_props *props; 3844 int retval, num_iqueues, num_oqueues; 3845 union oct_nic_if_cfg if_cfg; 3846 unsigned int base_queue; 3847 unsigned int gmx_port_id; 3848 u32 resp_size, ctx_size, data_size; 3849 u32 ifidx_or_pfnum; 3850 struct lio_version *vdata; 3851 3852 /* This is to handle link status changes */ 3853 octeon_register_dispatch_fn(octeon_dev, OPCODE_NIC, 3854 OPCODE_NIC_INFO, 3855 lio_nic_info, octeon_dev); 3856 3857 /* REQTYPE_RESP_NET and REQTYPE_SOFT_COMMAND do not have free functions. 3858 * They are handled directly. 3859 */ 3860 octeon_register_reqtype_free_fn(octeon_dev, REQTYPE_NORESP_NET, 3861 free_netbuf); 3862 3863 octeon_register_reqtype_free_fn(octeon_dev, REQTYPE_NORESP_NET_SG, 3864 free_netsgbuf); 3865 3866 octeon_register_reqtype_free_fn(octeon_dev, REQTYPE_RESP_NET_SG, 3867 free_netsgbuf_with_resp); 3868 3869 for (i = 0; i < octeon_dev->ifcount; i++) { 3870 resp_size = sizeof(struct liquidio_if_cfg_resp); 3871 ctx_size = sizeof(struct liquidio_if_cfg_context); 3872 data_size = sizeof(struct lio_version); 3873 sc = (struct octeon_soft_command *) 3874 octeon_alloc_soft_command(octeon_dev, data_size, 3875 resp_size, ctx_size); 3876 resp = (struct liquidio_if_cfg_resp *)sc->virtrptr; 3877 ctx = (struct liquidio_if_cfg_context *)sc->ctxptr; 3878 vdata = (struct lio_version *)sc->virtdptr; 3879 3880 *((u64 *)vdata) = 0; 3881 vdata->major = cpu_to_be16(LIQUIDIO_BASE_MAJOR_VERSION); 3882 vdata->minor = cpu_to_be16(LIQUIDIO_BASE_MINOR_VERSION); 3883 vdata->micro = cpu_to_be16(LIQUIDIO_BASE_MICRO_VERSION); 3884 3885 if (OCTEON_CN23XX_PF(octeon_dev)) { 3886 num_iqueues = octeon_dev->sriov_info.num_pf_rings; 3887 num_oqueues = octeon_dev->sriov_info.num_pf_rings; 3888 base_queue = octeon_dev->sriov_info.pf_srn; 3889 3890 gmx_port_id = octeon_dev->pf_num; 3891 ifidx_or_pfnum = octeon_dev->pf_num; 3892 } else { 3893 num_iqueues = CFG_GET_NUM_TXQS_NIC_IF( 3894 octeon_get_conf(octeon_dev), i); 3895 num_oqueues = CFG_GET_NUM_RXQS_NIC_IF( 3896 octeon_get_conf(octeon_dev), i); 3897 base_queue = CFG_GET_BASE_QUE_NIC_IF( 3898 octeon_get_conf(octeon_dev), i); 3899 gmx_port_id = CFG_GET_GMXID_NIC_IF( 3900 octeon_get_conf(octeon_dev), i); 3901 ifidx_or_pfnum = i; 3902 } 3903 3904 dev_dbg(&octeon_dev->pci_dev->dev, 3905 "requesting config for interface %d, iqs %d, oqs %d\n", 3906 ifidx_or_pfnum, num_iqueues, num_oqueues); 3907 WRITE_ONCE(ctx->cond, 0); 3908 ctx->octeon_id = lio_get_device_id(octeon_dev); 3909 init_waitqueue_head(&ctx->wc); 3910 3911 if_cfg.u64 = 0; 3912 if_cfg.s.num_iqueues = num_iqueues; 3913 if_cfg.s.num_oqueues = num_oqueues; 3914 if_cfg.s.base_queue = base_queue; 3915 if_cfg.s.gmx_port_id = gmx_port_id; 3916 3917 sc->iq_no = 0; 3918 3919 octeon_prepare_soft_command(octeon_dev, sc, OPCODE_NIC, 3920 OPCODE_NIC_IF_CFG, 0, 3921 if_cfg.u64, 0); 3922 3923 sc->callback = if_cfg_callback; 3924 sc->callback_arg = sc; 3925 sc->wait_time = 3000; 3926 3927 retval = octeon_send_soft_command(octeon_dev, sc); 3928 if (retval == IQ_SEND_FAILED) { 3929 dev_err(&octeon_dev->pci_dev->dev, 3930 "iq/oq config failed status: %x\n", 3931 retval); 3932 /* Soft instr is freed by driver in case of failure. */ 3933 goto setup_nic_dev_fail; 3934 } 3935 3936 /* Sleep on a wait queue till the cond flag indicates that the 3937 * response arrived or timed-out. 3938 */ 3939 if (sleep_cond(&ctx->wc, &ctx->cond) == -EINTR) { 3940 dev_err(&octeon_dev->pci_dev->dev, "Wait interrupted\n"); 3941 goto setup_nic_wait_intr; 3942 } 3943 3944 retval = resp->status; 3945 if (retval) { 3946 dev_err(&octeon_dev->pci_dev->dev, "iq/oq config failed\n"); 3947 goto setup_nic_dev_fail; 3948 } 3949 3950 octeon_swap_8B_data((u64 *)(&resp->cfg_info), 3951 (sizeof(struct liquidio_if_cfg_info)) >> 3); 3952 3953 num_iqueues = hweight64(resp->cfg_info.iqmask); 3954 num_oqueues = hweight64(resp->cfg_info.oqmask); 3955 3956 if (!(num_iqueues) || !(num_oqueues)) { 3957 dev_err(&octeon_dev->pci_dev->dev, 3958 "Got bad iqueues (%016llx) or oqueues (%016llx) from firmware.\n", 3959 resp->cfg_info.iqmask, 3960 resp->cfg_info.oqmask); 3961 goto setup_nic_dev_fail; 3962 } 3963 dev_dbg(&octeon_dev->pci_dev->dev, 3964 "interface %d, iqmask %016llx, oqmask %016llx, numiqueues %d, numoqueues %d\n", 3965 i, resp->cfg_info.iqmask, resp->cfg_info.oqmask, 3966 num_iqueues, num_oqueues); 3967 netdev = alloc_etherdev_mq(LIO_SIZE, num_iqueues); 3968 3969 if (!netdev) { 3970 dev_err(&octeon_dev->pci_dev->dev, "Device allocation failed\n"); 3971 goto setup_nic_dev_fail; 3972 } 3973 3974 SET_NETDEV_DEV(netdev, &octeon_dev->pci_dev->dev); 3975 3976 /* Associate the routines that will handle different 3977 * netdev tasks. 3978 */ 3979 netdev->netdev_ops = &lionetdevops; 3980 3981 lio = GET_LIO(netdev); 3982 3983 memset(lio, 0, sizeof(struct lio)); 3984 3985 lio->ifidx = ifidx_or_pfnum; 3986 3987 props = &octeon_dev->props[i]; 3988 props->gmxport = resp->cfg_info.linfo.gmxport; 3989 props->netdev = netdev; 3990 3991 lio->linfo.num_rxpciq = num_oqueues; 3992 lio->linfo.num_txpciq = num_iqueues; 3993 for (j = 0; j < num_oqueues; j++) { 3994 lio->linfo.rxpciq[j].u64 = 3995 resp->cfg_info.linfo.rxpciq[j].u64; 3996 } 3997 for (j = 0; j < num_iqueues; j++) { 3998 lio->linfo.txpciq[j].u64 = 3999 resp->cfg_info.linfo.txpciq[j].u64; 4000 } 4001 lio->linfo.hw_addr = resp->cfg_info.linfo.hw_addr; 4002 lio->linfo.gmxport = resp->cfg_info.linfo.gmxport; 4003 lio->linfo.link.u64 = resp->cfg_info.linfo.link.u64; 4004 4005 lio->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 4006 4007 if (OCTEON_CN23XX_PF(octeon_dev) || 4008 OCTEON_CN6XXX(octeon_dev)) { 4009 lio->dev_capability = NETIF_F_HIGHDMA 4010 | NETIF_F_IP_CSUM 4011 | NETIF_F_IPV6_CSUM 4012 | NETIF_F_SG | NETIF_F_RXCSUM 4013 | NETIF_F_GRO 4014 | NETIF_F_TSO | NETIF_F_TSO6 4015 | NETIF_F_LRO; 4016 } 4017 netif_set_gso_max_size(netdev, OCTNIC_GSO_MAX_SIZE); 4018 4019 /* Copy of transmit encapsulation capabilities: 4020 * TSO, TSO6, Checksums for this device 4021 */ 4022 lio->enc_dev_capability = NETIF_F_IP_CSUM 4023 | NETIF_F_IPV6_CSUM 4024 | NETIF_F_GSO_UDP_TUNNEL 4025 | NETIF_F_HW_CSUM | NETIF_F_SG 4026 | NETIF_F_RXCSUM 4027 | NETIF_F_TSO | NETIF_F_TSO6 4028 | NETIF_F_LRO; 4029 4030 netdev->hw_enc_features = (lio->enc_dev_capability & 4031 ~NETIF_F_LRO); 4032 4033 lio->dev_capability |= NETIF_F_GSO_UDP_TUNNEL; 4034 4035 netdev->vlan_features = lio->dev_capability; 4036 /* Add any unchangeable hw features */ 4037 lio->dev_capability |= NETIF_F_HW_VLAN_CTAG_FILTER | 4038 NETIF_F_HW_VLAN_CTAG_RX | 4039 NETIF_F_HW_VLAN_CTAG_TX; 4040 4041 netdev->features = (lio->dev_capability & ~NETIF_F_LRO); 4042 4043 netdev->hw_features = lio->dev_capability; 4044 /*HW_VLAN_RX and HW_VLAN_FILTER is always on*/ 4045 netdev->hw_features = netdev->hw_features & 4046 ~NETIF_F_HW_VLAN_CTAG_RX; 4047 4048 /* MTU range: 68 - 16000 */ 4049 netdev->min_mtu = LIO_MIN_MTU_SIZE; 4050 netdev->max_mtu = LIO_MAX_MTU_SIZE; 4051 4052 /* Point to the properties for octeon device to which this 4053 * interface belongs. 4054 */ 4055 lio->oct_dev = octeon_dev; 4056 lio->octprops = props; 4057 lio->netdev = netdev; 4058 4059 dev_dbg(&octeon_dev->pci_dev->dev, 4060 "if%d gmx: %d hw_addr: 0x%llx\n", i, 4061 lio->linfo.gmxport, CVM_CAST64(lio->linfo.hw_addr)); 4062 4063 for (j = 0; j < octeon_dev->sriov_info.max_vfs; j++) { 4064 u8 vfmac[ETH_ALEN]; 4065 4066 random_ether_addr(&vfmac[0]); 4067 if (__liquidio_set_vf_mac(netdev, j, 4068 &vfmac[0], false)) { 4069 dev_err(&octeon_dev->pci_dev->dev, 4070 "Error setting VF%d MAC address\n", 4071 j); 4072 goto setup_nic_dev_fail; 4073 } 4074 } 4075 4076 /* 64-bit swap required on LE machines */ 4077 octeon_swap_8B_data(&lio->linfo.hw_addr, 1); 4078 for (j = 0; j < 6; j++) 4079 mac[j] = *((u8 *)(((u8 *)&lio->linfo.hw_addr) + 2 + j)); 4080 4081 /* Copy MAC Address to OS network device structure */ 4082 4083 ether_addr_copy(netdev->dev_addr, mac); 4084 4085 /* By default all interfaces on a single Octeon uses the same 4086 * tx and rx queues 4087 */ 4088 lio->txq = lio->linfo.txpciq[0].s.q_no; 4089 lio->rxq = lio->linfo.rxpciq[0].s.q_no; 4090 if (setup_io_queues(octeon_dev, i)) { 4091 dev_err(&octeon_dev->pci_dev->dev, "I/O queues creation failed\n"); 4092 goto setup_nic_dev_fail; 4093 } 4094 4095 ifstate_set(lio, LIO_IFSTATE_DROQ_OPS); 4096 4097 lio->tx_qsize = octeon_get_tx_qsize(octeon_dev, lio->txq); 4098 lio->rx_qsize = octeon_get_rx_qsize(octeon_dev, lio->rxq); 4099 4100 if (setup_glists(octeon_dev, lio, num_iqueues)) { 4101 dev_err(&octeon_dev->pci_dev->dev, 4102 "Gather list allocation failed\n"); 4103 goto setup_nic_dev_fail; 4104 } 4105 4106 /* Register ethtool support */ 4107 liquidio_set_ethtool_ops(netdev); 4108 if (lio->oct_dev->chip_id == OCTEON_CN23XX_PF_VID) 4109 octeon_dev->priv_flags = OCT_PRIV_FLAG_DEFAULT; 4110 else 4111 octeon_dev->priv_flags = 0x0; 4112 4113 if (netdev->features & NETIF_F_LRO) 4114 liquidio_set_feature(netdev, OCTNET_CMD_LRO_ENABLE, 4115 OCTNIC_LROIPV4 | OCTNIC_LROIPV6); 4116 4117 liquidio_set_feature(netdev, OCTNET_CMD_ENABLE_VLAN_FILTER, 0); 4118 4119 if ((debug != -1) && (debug & NETIF_MSG_HW)) 4120 liquidio_set_feature(netdev, 4121 OCTNET_CMD_VERBOSE_ENABLE, 0); 4122 4123 if (setup_link_status_change_wq(netdev)) 4124 goto setup_nic_dev_fail; 4125 4126 /* Register the network device with the OS */ 4127 if (register_netdev(netdev)) { 4128 dev_err(&octeon_dev->pci_dev->dev, "Device registration failed\n"); 4129 goto setup_nic_dev_fail; 4130 } 4131 4132 dev_dbg(&octeon_dev->pci_dev->dev, 4133 "Setup NIC ifidx:%d mac:%02x%02x%02x%02x%02x%02x\n", 4134 i, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); 4135 netif_carrier_off(netdev); 4136 lio->link_changes++; 4137 4138 ifstate_set(lio, LIO_IFSTATE_REGISTERED); 4139 4140 /* Sending command to firmware to enable Rx checksum offload 4141 * by default at the time of setup of Liquidio driver for 4142 * this device 4143 */ 4144 liquidio_set_rxcsum_command(netdev, OCTNET_CMD_TNL_RX_CSUM_CTL, 4145 OCTNET_CMD_RXCSUM_ENABLE); 4146 liquidio_set_feature(netdev, OCTNET_CMD_TNL_TX_CSUM_CTL, 4147 OCTNET_CMD_TXCSUM_ENABLE); 4148 4149 dev_dbg(&octeon_dev->pci_dev->dev, 4150 "NIC ifidx:%d Setup successful\n", i); 4151 4152 octeon_free_soft_command(octeon_dev, sc); 4153 } 4154 4155 return 0; 4156 4157 setup_nic_dev_fail: 4158 4159 octeon_free_soft_command(octeon_dev, sc); 4160 4161 setup_nic_wait_intr: 4162 4163 while (i--) { 4164 dev_err(&octeon_dev->pci_dev->dev, 4165 "NIC ifidx:%d Setup failed\n", i); 4166 liquidio_destroy_nic_device(octeon_dev, i); 4167 } 4168 return -ENODEV; 4169 } 4170 4171 #ifdef CONFIG_PCI_IOV 4172 static int octeon_enable_sriov(struct octeon_device *oct) 4173 { 4174 unsigned int num_vfs_alloced = oct->sriov_info.num_vfs_alloced; 4175 struct pci_dev *vfdev; 4176 int err; 4177 u32 u; 4178 4179 if (OCTEON_CN23XX_PF(oct) && num_vfs_alloced) { 4180 err = pci_enable_sriov(oct->pci_dev, 4181 oct->sriov_info.num_vfs_alloced); 4182 if (err) { 4183 dev_err(&oct->pci_dev->dev, 4184 "OCTEON: Failed to enable PCI sriov: %d\n", 4185 err); 4186 oct->sriov_info.num_vfs_alloced = 0; 4187 return err; 4188 } 4189 oct->sriov_info.sriov_enabled = 1; 4190 4191 /* init lookup table that maps DPI ring number to VF pci_dev 4192 * struct pointer 4193 */ 4194 u = 0; 4195 vfdev = pci_get_device(PCI_VENDOR_ID_CAVIUM, 4196 OCTEON_CN23XX_VF_VID, NULL); 4197 while (vfdev) { 4198 if (vfdev->is_virtfn && 4199 (vfdev->physfn == oct->pci_dev)) { 4200 oct->sriov_info.dpiring_to_vfpcidev_lut[u] = 4201 vfdev; 4202 u += oct->sriov_info.rings_per_vf; 4203 } 4204 vfdev = pci_get_device(PCI_VENDOR_ID_CAVIUM, 4205 OCTEON_CN23XX_VF_VID, vfdev); 4206 } 4207 } 4208 4209 return num_vfs_alloced; 4210 } 4211 4212 static int lio_pci_sriov_disable(struct octeon_device *oct) 4213 { 4214 int u; 4215 4216 if (pci_vfs_assigned(oct->pci_dev)) { 4217 dev_err(&oct->pci_dev->dev, "VFs are still assigned to VMs.\n"); 4218 return -EPERM; 4219 } 4220 4221 pci_disable_sriov(oct->pci_dev); 4222 4223 u = 0; 4224 while (u < MAX_POSSIBLE_VFS) { 4225 oct->sriov_info.dpiring_to_vfpcidev_lut[u] = NULL; 4226 u += oct->sriov_info.rings_per_vf; 4227 } 4228 4229 oct->sriov_info.num_vfs_alloced = 0; 4230 dev_info(&oct->pci_dev->dev, "oct->pf_num:%d disabled VFs\n", 4231 oct->pf_num); 4232 4233 return 0; 4234 } 4235 4236 static int liquidio_enable_sriov(struct pci_dev *dev, int num_vfs) 4237 { 4238 struct octeon_device *oct = pci_get_drvdata(dev); 4239 int ret = 0; 4240 4241 if ((num_vfs == oct->sriov_info.num_vfs_alloced) && 4242 (oct->sriov_info.sriov_enabled)) { 4243 dev_info(&oct->pci_dev->dev, "oct->pf_num:%d already enabled num_vfs:%d\n", 4244 oct->pf_num, num_vfs); 4245 return 0; 4246 } 4247 4248 if (!num_vfs) { 4249 ret = lio_pci_sriov_disable(oct); 4250 } else if (num_vfs > oct->sriov_info.max_vfs) { 4251 dev_err(&oct->pci_dev->dev, 4252 "OCTEON: Max allowed VFs:%d user requested:%d", 4253 oct->sriov_info.max_vfs, num_vfs); 4254 ret = -EPERM; 4255 } else { 4256 oct->sriov_info.num_vfs_alloced = num_vfs; 4257 ret = octeon_enable_sriov(oct); 4258 dev_info(&oct->pci_dev->dev, "oct->pf_num:%d num_vfs:%d\n", 4259 oct->pf_num, num_vfs); 4260 } 4261 4262 return ret; 4263 } 4264 #endif 4265 4266 /** 4267 * \brief initialize the NIC 4268 * @param oct octeon device 4269 * 4270 * This initialization routine is called once the Octeon device application is 4271 * up and running 4272 */ 4273 static int liquidio_init_nic_module(struct octeon_device *oct) 4274 { 4275 struct oct_intrmod_cfg *intrmod_cfg; 4276 int i, retval = 0; 4277 int num_nic_ports = CFG_GET_NUM_NIC_PORTS(octeon_get_conf(oct)); 4278 4279 dev_dbg(&oct->pci_dev->dev, "Initializing network interfaces\n"); 4280 4281 /* only default iq and oq were initialized 4282 * initialize the rest as well 4283 */ 4284 /* run port_config command for each port */ 4285 oct->ifcount = num_nic_ports; 4286 4287 memset(oct->props, 0, sizeof(struct octdev_props) * num_nic_ports); 4288 4289 for (i = 0; i < MAX_OCTEON_LINKS; i++) 4290 oct->props[i].gmxport = -1; 4291 4292 retval = setup_nic_devices(oct); 4293 if (retval) { 4294 dev_err(&oct->pci_dev->dev, "Setup NIC devices failed\n"); 4295 goto octnet_init_failure; 4296 } 4297 4298 liquidio_ptp_init(oct); 4299 4300 /* Initialize interrupt moderation params */ 4301 intrmod_cfg = &((struct octeon_device *)oct)->intrmod; 4302 intrmod_cfg->rx_enable = 1; 4303 intrmod_cfg->check_intrvl = LIO_INTRMOD_CHECK_INTERVAL; 4304 intrmod_cfg->maxpkt_ratethr = LIO_INTRMOD_MAXPKT_RATETHR; 4305 intrmod_cfg->minpkt_ratethr = LIO_INTRMOD_MINPKT_RATETHR; 4306 intrmod_cfg->rx_maxcnt_trigger = LIO_INTRMOD_RXMAXCNT_TRIGGER; 4307 intrmod_cfg->rx_maxtmr_trigger = LIO_INTRMOD_RXMAXTMR_TRIGGER; 4308 intrmod_cfg->rx_mintmr_trigger = LIO_INTRMOD_RXMINTMR_TRIGGER; 4309 intrmod_cfg->rx_mincnt_trigger = LIO_INTRMOD_RXMINCNT_TRIGGER; 4310 intrmod_cfg->tx_enable = 1; 4311 intrmod_cfg->tx_maxcnt_trigger = LIO_INTRMOD_TXMAXCNT_TRIGGER; 4312 intrmod_cfg->tx_mincnt_trigger = LIO_INTRMOD_TXMINCNT_TRIGGER; 4313 intrmod_cfg->rx_frames = CFG_GET_OQ_INTR_PKT(octeon_get_conf(oct)); 4314 intrmod_cfg->rx_usecs = CFG_GET_OQ_INTR_TIME(octeon_get_conf(oct)); 4315 intrmod_cfg->tx_frames = CFG_GET_IQ_INTR_PKT(octeon_get_conf(oct)); 4316 dev_dbg(&oct->pci_dev->dev, "Network interfaces ready\n"); 4317 4318 return retval; 4319 4320 octnet_init_failure: 4321 4322 oct->ifcount = 0; 4323 4324 return retval; 4325 } 4326 4327 /** 4328 * \brief starter callback that invokes the remaining initialization work after 4329 * the NIC is up and running. 4330 * @param octptr work struct work_struct 4331 */ 4332 static void nic_starter(struct work_struct *work) 4333 { 4334 struct octeon_device *oct; 4335 struct cavium_wk *wk = (struct cavium_wk *)work; 4336 4337 oct = (struct octeon_device *)wk->ctxptr; 4338 4339 if (atomic_read(&oct->status) == OCT_DEV_RUNNING) 4340 return; 4341 4342 /* If the status of the device is CORE_OK, the core 4343 * application has reported its application type. Call 4344 * any registered handlers now and move to the RUNNING 4345 * state. 4346 */ 4347 if (atomic_read(&oct->status) != OCT_DEV_CORE_OK) { 4348 schedule_delayed_work(&oct->nic_poll_work.work, 4349 LIQUIDIO_STARTER_POLL_INTERVAL_MS); 4350 return; 4351 } 4352 4353 atomic_set(&oct->status, OCT_DEV_RUNNING); 4354 4355 if (oct->app_mode && oct->app_mode == CVM_DRV_NIC_APP) { 4356 dev_dbg(&oct->pci_dev->dev, "Starting NIC module\n"); 4357 4358 if (liquidio_init_nic_module(oct)) 4359 dev_err(&oct->pci_dev->dev, "NIC initialization failed\n"); 4360 else 4361 handshake[oct->octeon_id].started_ok = 1; 4362 } else { 4363 dev_err(&oct->pci_dev->dev, 4364 "Unexpected application running on NIC (%d). Check firmware.\n", 4365 oct->app_mode); 4366 } 4367 4368 complete(&handshake[oct->octeon_id].started); 4369 } 4370 4371 static int 4372 octeon_recv_vf_drv_notice(struct octeon_recv_info *recv_info, void *buf) 4373 { 4374 struct octeon_device *oct = (struct octeon_device *)buf; 4375 struct octeon_recv_pkt *recv_pkt = recv_info->recv_pkt; 4376 int i, notice, vf_idx; 4377 u64 *data, vf_num; 4378 4379 notice = recv_pkt->rh.r.ossp; 4380 data = (u64 *)get_rbd(recv_pkt->buffer_ptr[0]); 4381 4382 /* the first 64-bit word of data is the vf_num */ 4383 vf_num = data[0]; 4384 octeon_swap_8B_data(&vf_num, 1); 4385 vf_idx = (int)vf_num - 1; 4386 4387 if (notice == VF_DRV_LOADED) { 4388 if (!(oct->sriov_info.vf_drv_loaded_mask & BIT_ULL(vf_idx))) { 4389 oct->sriov_info.vf_drv_loaded_mask |= BIT_ULL(vf_idx); 4390 dev_info(&oct->pci_dev->dev, 4391 "driver for VF%d was loaded\n", vf_idx); 4392 try_module_get(THIS_MODULE); 4393 } 4394 } else if (notice == VF_DRV_REMOVED) { 4395 if (oct->sriov_info.vf_drv_loaded_mask & BIT_ULL(vf_idx)) { 4396 oct->sriov_info.vf_drv_loaded_mask &= ~BIT_ULL(vf_idx); 4397 dev_info(&oct->pci_dev->dev, 4398 "driver for VF%d was removed\n", vf_idx); 4399 module_put(THIS_MODULE); 4400 } 4401 } else if (notice == VF_DRV_MACADDR_CHANGED) { 4402 u8 *b = (u8 *)&data[1]; 4403 4404 oct->sriov_info.vf_macaddr[vf_idx] = data[1]; 4405 dev_info(&oct->pci_dev->dev, 4406 "VF driver changed VF%d's MAC address to %pM\n", 4407 vf_idx, b + 2); 4408 } 4409 4410 for (i = 0; i < recv_pkt->buffer_count; i++) 4411 recv_buffer_free(recv_pkt->buffer_ptr[i]); 4412 octeon_free_recv_info(recv_info); 4413 4414 return 0; 4415 } 4416 4417 /** 4418 * \brief Device initialization for each Octeon device that is probed 4419 * @param octeon_dev octeon device 4420 */ 4421 static int octeon_device_init(struct octeon_device *octeon_dev) 4422 { 4423 int j, ret; 4424 int fw_loaded = 0; 4425 char bootcmd[] = "\n"; 4426 struct octeon_device_priv *oct_priv = 4427 (struct octeon_device_priv *)octeon_dev->priv; 4428 atomic_set(&octeon_dev->status, OCT_DEV_BEGIN_STATE); 4429 4430 /* Enable access to the octeon device and make its DMA capability 4431 * known to the OS. 4432 */ 4433 if (octeon_pci_os_setup(octeon_dev)) 4434 return 1; 4435 4436 atomic_set(&octeon_dev->status, OCT_DEV_PCI_ENABLE_DONE); 4437 4438 /* Identify the Octeon type and map the BAR address space. */ 4439 if (octeon_chip_specific_setup(octeon_dev)) { 4440 dev_err(&octeon_dev->pci_dev->dev, "Chip specific setup failed\n"); 4441 return 1; 4442 } 4443 4444 atomic_set(&octeon_dev->status, OCT_DEV_PCI_MAP_DONE); 4445 4446 octeon_dev->app_mode = CVM_DRV_INVALID_APP; 4447 4448 if (OCTEON_CN23XX_PF(octeon_dev)) { 4449 if (!cn23xx_fw_loaded(octeon_dev)) { 4450 fw_loaded = 0; 4451 /* Do a soft reset of the Octeon device. */ 4452 if (octeon_dev->fn_list.soft_reset(octeon_dev)) 4453 return 1; 4454 /* things might have changed */ 4455 if (!cn23xx_fw_loaded(octeon_dev)) 4456 fw_loaded = 0; 4457 else 4458 fw_loaded = 1; 4459 } else { 4460 fw_loaded = 1; 4461 } 4462 } else if (octeon_dev->fn_list.soft_reset(octeon_dev)) { 4463 return 1; 4464 } 4465 4466 /* Initialize the dispatch mechanism used to push packets arriving on 4467 * Octeon Output queues. 4468 */ 4469 if (octeon_init_dispatch_list(octeon_dev)) 4470 return 1; 4471 4472 octeon_register_dispatch_fn(octeon_dev, OPCODE_NIC, 4473 OPCODE_NIC_CORE_DRV_ACTIVE, 4474 octeon_core_drv_init, 4475 octeon_dev); 4476 4477 octeon_register_dispatch_fn(octeon_dev, OPCODE_NIC, 4478 OPCODE_NIC_VF_DRV_NOTICE, 4479 octeon_recv_vf_drv_notice, octeon_dev); 4480 INIT_DELAYED_WORK(&octeon_dev->nic_poll_work.work, nic_starter); 4481 octeon_dev->nic_poll_work.ctxptr = (void *)octeon_dev; 4482 schedule_delayed_work(&octeon_dev->nic_poll_work.work, 4483 LIQUIDIO_STARTER_POLL_INTERVAL_MS); 4484 4485 atomic_set(&octeon_dev->status, OCT_DEV_DISPATCH_INIT_DONE); 4486 4487 octeon_set_io_queues_off(octeon_dev); 4488 4489 if (OCTEON_CN23XX_PF(octeon_dev)) { 4490 ret = octeon_dev->fn_list.setup_device_regs(octeon_dev); 4491 if (ret) { 4492 dev_err(&octeon_dev->pci_dev->dev, "OCTEON: Failed to configure device registers\n"); 4493 return ret; 4494 } 4495 } 4496 4497 /* Initialize soft command buffer pool 4498 */ 4499 if (octeon_setup_sc_buffer_pool(octeon_dev)) { 4500 dev_err(&octeon_dev->pci_dev->dev, "sc buffer pool allocation failed\n"); 4501 return 1; 4502 } 4503 atomic_set(&octeon_dev->status, OCT_DEV_SC_BUFF_POOL_INIT_DONE); 4504 4505 /* Setup the data structures that manage this Octeon's Input queues. */ 4506 if (octeon_setup_instr_queues(octeon_dev)) { 4507 dev_err(&octeon_dev->pci_dev->dev, 4508 "instruction queue initialization failed\n"); 4509 return 1; 4510 } 4511 atomic_set(&octeon_dev->status, OCT_DEV_INSTR_QUEUE_INIT_DONE); 4512 4513 /* Initialize lists to manage the requests of different types that 4514 * arrive from user & kernel applications for this octeon device. 4515 */ 4516 if (octeon_setup_response_list(octeon_dev)) { 4517 dev_err(&octeon_dev->pci_dev->dev, "Response list allocation failed\n"); 4518 return 1; 4519 } 4520 atomic_set(&octeon_dev->status, OCT_DEV_RESP_LIST_INIT_DONE); 4521 4522 if (octeon_setup_output_queues(octeon_dev)) { 4523 dev_err(&octeon_dev->pci_dev->dev, "Output queue initialization failed\n"); 4524 return 1; 4525 } 4526 4527 atomic_set(&octeon_dev->status, OCT_DEV_DROQ_INIT_DONE); 4528 4529 if (OCTEON_CN23XX_PF(octeon_dev)) { 4530 if (octeon_dev->fn_list.setup_mbox(octeon_dev)) { 4531 dev_err(&octeon_dev->pci_dev->dev, "OCTEON: Mailbox setup failed\n"); 4532 return 1; 4533 } 4534 atomic_set(&octeon_dev->status, OCT_DEV_MBOX_SETUP_DONE); 4535 4536 if (octeon_allocate_ioq_vector(octeon_dev)) { 4537 dev_err(&octeon_dev->pci_dev->dev, "OCTEON: ioq vector allocation failed\n"); 4538 return 1; 4539 } 4540 atomic_set(&octeon_dev->status, OCT_DEV_MSIX_ALLOC_VECTOR_DONE); 4541 4542 } else { 4543 /* The input and output queue registers were setup earlier (the 4544 * queues were not enabled). Any additional registers 4545 * that need to be programmed should be done now. 4546 */ 4547 ret = octeon_dev->fn_list.setup_device_regs(octeon_dev); 4548 if (ret) { 4549 dev_err(&octeon_dev->pci_dev->dev, 4550 "Failed to configure device registers\n"); 4551 return ret; 4552 } 4553 } 4554 4555 /* Initialize the tasklet that handles output queue packet processing.*/ 4556 dev_dbg(&octeon_dev->pci_dev->dev, "Initializing droq tasklet\n"); 4557 tasklet_init(&oct_priv->droq_tasklet, octeon_droq_bh, 4558 (unsigned long)octeon_dev); 4559 4560 /* Setup the interrupt handler and record the INT SUM register address 4561 */ 4562 if (octeon_setup_interrupt(octeon_dev)) 4563 return 1; 4564 4565 /* Enable Octeon device interrupts */ 4566 octeon_dev->fn_list.enable_interrupt(octeon_dev, OCTEON_ALL_INTR); 4567 4568 atomic_set(&octeon_dev->status, OCT_DEV_INTR_SET_DONE); 4569 4570 /* Enable the input and output queues for this Octeon device */ 4571 ret = octeon_dev->fn_list.enable_io_queues(octeon_dev); 4572 if (ret) { 4573 dev_err(&octeon_dev->pci_dev->dev, "Failed to enable input/output queues"); 4574 return ret; 4575 } 4576 4577 atomic_set(&octeon_dev->status, OCT_DEV_IO_QUEUES_DONE); 4578 4579 if ((!OCTEON_CN23XX_PF(octeon_dev)) || !fw_loaded) { 4580 dev_dbg(&octeon_dev->pci_dev->dev, "Waiting for DDR initialization...\n"); 4581 if (!ddr_timeout) { 4582 dev_info(&octeon_dev->pci_dev->dev, 4583 "WAITING. Set ddr_timeout to non-zero value to proceed with initialization.\n"); 4584 } 4585 4586 schedule_timeout_uninterruptible(HZ * LIO_RESET_SECS); 4587 4588 /* Wait for the octeon to initialize DDR after the soft-reset.*/ 4589 while (!ddr_timeout) { 4590 set_current_state(TASK_INTERRUPTIBLE); 4591 if (schedule_timeout(HZ / 10)) { 4592 /* user probably pressed Control-C */ 4593 return 1; 4594 } 4595 } 4596 ret = octeon_wait_for_ddr_init(octeon_dev, &ddr_timeout); 4597 if (ret) { 4598 dev_err(&octeon_dev->pci_dev->dev, 4599 "DDR not initialized. Please confirm that board is configured to boot from Flash, ret: %d\n", 4600 ret); 4601 return 1; 4602 } 4603 4604 if (octeon_wait_for_bootloader(octeon_dev, 1000)) { 4605 dev_err(&octeon_dev->pci_dev->dev, "Board not responding\n"); 4606 return 1; 4607 } 4608 4609 /* Divert uboot to take commands from host instead. */ 4610 ret = octeon_console_send_cmd(octeon_dev, bootcmd, 50); 4611 4612 dev_dbg(&octeon_dev->pci_dev->dev, "Initializing consoles\n"); 4613 ret = octeon_init_consoles(octeon_dev); 4614 if (ret) { 4615 dev_err(&octeon_dev->pci_dev->dev, "Could not access board consoles\n"); 4616 return 1; 4617 } 4618 ret = octeon_add_console(octeon_dev, 0); 4619 if (ret) { 4620 dev_err(&octeon_dev->pci_dev->dev, "Could not access board console\n"); 4621 return 1; 4622 } 4623 4624 atomic_set(&octeon_dev->status, OCT_DEV_CONSOLE_INIT_DONE); 4625 4626 dev_dbg(&octeon_dev->pci_dev->dev, "Loading firmware\n"); 4627 ret = load_firmware(octeon_dev); 4628 if (ret) { 4629 dev_err(&octeon_dev->pci_dev->dev, "Could not load firmware to board\n"); 4630 return 1; 4631 } 4632 /* set bit 1 of SLI_SCRATCH_1 to indicate that firmware is 4633 * loaded 4634 */ 4635 if (OCTEON_CN23XX_PF(octeon_dev)) 4636 octeon_write_csr64(octeon_dev, CN23XX_SLI_SCRATCH1, 4637 2ULL); 4638 } 4639 4640 handshake[octeon_dev->octeon_id].init_ok = 1; 4641 complete(&handshake[octeon_dev->octeon_id].init); 4642 4643 atomic_set(&octeon_dev->status, OCT_DEV_HOST_OK); 4644 4645 /* Send Credit for Octeon Output queues. Credits are always sent after 4646 * the output queue is enabled. 4647 */ 4648 for (j = 0; j < octeon_dev->num_oqs; j++) 4649 writel(octeon_dev->droq[j]->max_count, 4650 octeon_dev->droq[j]->pkts_credit_reg); 4651 4652 /* Packets can start arriving on the output queues from this point. */ 4653 return 0; 4654 } 4655 4656 /** 4657 * \brief Exits the module 4658 */ 4659 static void __exit liquidio_exit(void) 4660 { 4661 liquidio_deinit_pci(); 4662 4663 pr_info("LiquidIO network module is now unloaded\n"); 4664 } 4665 4666 module_init(liquidio_init); 4667 module_exit(liquidio_exit); 4668